2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/rockchip.h>
18 #include <dt-bindings/clock/rk3188-cru.h>
19 #include "rk3xxx.dtsi"
22 compatible = "rockchip,rk3188";
27 enable-method = "rockchip,rk3066-smp";
31 compatible = "arm,cortex-a9";
32 next-level-cache = <&L2>;
45 clock-latency = <40000>;
46 clocks = <&cru ARMCLK>;
50 compatible = "arm,cortex-a9";
51 next-level-cache = <&L2>;
56 compatible = "arm,cortex-a9";
57 next-level-cache = <&L2>;
62 compatible = "arm,cortex-a9";
63 next-level-cache = <&L2>;
69 compatible = "mmio-sram";
70 reg = <0x10080000 0x8000>;
73 ranges = <0 0x10080000 0x8000>;
76 compatible = "rockchip,rk3066-smp-sram";
82 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
83 reg = <0x1011a000 0x2000>;
84 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
87 pinctrl-names = "default";
88 pinctrl-0 = <&i2s0_bus>;
89 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
90 dma-names = "tx", "rx";
91 clock-names = "i2s_hclk", "i2s_clk";
92 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
96 cru: clock-controller@20000000 {
97 compatible = "rockchip,rk3188-cru";
98 reg = <0x20000000 0x1000>;
99 rockchip,grf = <&grf>;
106 compatible = "rockchip,rk3188-pinctrl";
107 rockchip,grf = <&grf>;
108 rockchip,pmu = <&pmu>;
110 #address-cells = <1>;
114 gpio0: gpio0@0x2000a000 {
115 compatible = "rockchip,rk3188-gpio-bank0";
116 reg = <0x2000a000 0x100>;
117 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
118 clocks = <&cru PCLK_GPIO0>;
123 interrupt-controller;
124 #interrupt-cells = <2>;
127 gpio1: gpio1@0x2003c000 {
128 compatible = "rockchip,gpio-bank";
129 reg = <0x2003c000 0x100>;
130 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
131 clocks = <&cru PCLK_GPIO1>;
136 interrupt-controller;
137 #interrupt-cells = <2>;
140 gpio2: gpio2@2003e000 {
141 compatible = "rockchip,gpio-bank";
142 reg = <0x2003e000 0x100>;
143 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
144 clocks = <&cru PCLK_GPIO2>;
149 interrupt-controller;
150 #interrupt-cells = <2>;
153 gpio3: gpio3@20080000 {
154 compatible = "rockchip,gpio-bank";
155 reg = <0x20080000 0x100>;
156 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
157 clocks = <&cru PCLK_GPIO3>;
162 interrupt-controller;
163 #interrupt-cells = <2>;
166 pcfg_pull_up: pcfg_pull_up {
170 pcfg_pull_down: pcfg_pull_down {
174 pcfg_pull_none: pcfg_pull_none {
180 rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
184 rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
188 rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
192 * The data pins are shared between nandc and emmc and
193 * not accessible through pinctrl. Also they should've
194 * been already set correctly by firmware, as
195 * flash/emmc is the boot-device.
200 emac_xfer: emac-xfer {
201 rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
202 <RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
203 <RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
204 <RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
205 <RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
206 <RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
207 <RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
208 <RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
211 emac_mdio: emac-mdio {
212 rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
213 <RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
218 i2c0_xfer: i2c0-xfer {
219 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
220 <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
225 i2c1_xfer: i2c1-xfer {
226 rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
227 <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
232 i2c2_xfer: i2c2-xfer {
233 rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
234 <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
239 i2c3_xfer: i2c3-xfer {
240 rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
241 <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
246 i2c4_xfer: i2c4-xfer {
247 rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
248 <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
254 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
260 rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
266 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
272 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
278 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
281 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
284 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
287 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
290 rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
296 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
299 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
302 rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
305 rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
308 rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
313 uart0_xfer: uart0-xfer {
314 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
315 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
318 uart0_cts: uart0-cts {
319 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
322 uart0_rts: uart0-rts {
323 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
328 uart1_xfer: uart1-xfer {
329 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
330 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
333 uart1_cts: uart1-cts {
334 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
337 uart1_rts: uart1-rts {
338 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
343 uart2_xfer: uart2-xfer {
344 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
345 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
347 /* no rts / cts for uart2 */
351 uart3_xfer: uart3-xfer {
352 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
353 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
356 uart3_cts: uart3-cts {
357 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
360 uart3_rts: uart3-rts {
361 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
367 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
371 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
375 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
379 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
383 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
386 sd0_bus1: sd0-bus-width1 {
387 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
390 sd0_bus4: sd0-bus-width4 {
391 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
392 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
393 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
394 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
400 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
404 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
408 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
412 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
415 sd1_bus1: sd1-bus-width1 {
416 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
419 sd1_bus4: sd1-bus-width4 {
420 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
421 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
422 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
423 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
429 rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
430 <RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
431 <RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
432 <RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
433 <RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
434 <RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
441 compatible = "rockchip,rk3188-emac";
445 interrupts = <GIC_PPI 11 0xf04>;
449 interrupts = <GIC_PPI 13 0xf04>;
453 compatible = "rockchip,rk3188-i2c";
454 pinctrl-names = "default";
455 pinctrl-0 = <&i2c0_xfer>;
459 compatible = "rockchip,rk3188-i2c";
460 pinctrl-names = "default";
461 pinctrl-0 = <&i2c1_xfer>;
465 compatible = "rockchip,rk3188-i2c";
466 pinctrl-names = "default";
467 pinctrl-0 = <&i2c2_xfer>;
471 compatible = "rockchip,rk3188-i2c";
472 pinctrl-names = "default";
473 pinctrl-0 = <&i2c3_xfer>;
477 compatible = "rockchip,rk3188-i2c";
478 pinctrl-names = "default";
479 pinctrl-0 = <&i2c4_xfer>;
483 pinctrl-names = "default";
484 pinctrl-0 = <&pwm0_out>;
488 pinctrl-names = "default";
489 pinctrl-0 = <&pwm1_out>;
493 pinctrl-names = "default";
494 pinctrl-0 = <&pwm2_out>;
498 pinctrl-names = "default";
499 pinctrl-0 = <&pwm3_out>;
503 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
504 pinctrl-names = "default";
505 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
509 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
510 pinctrl-names = "default";
511 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
515 pinctrl-names = "default";
516 pinctrl-0 = <&uart0_xfer>;
520 pinctrl-names = "default";
521 pinctrl-0 = <&uart1_xfer>;
525 pinctrl-names = "default";
526 pinctrl-0 = <&uart2_xfer>;
530 pinctrl-names = "default";
531 pinctrl-0 = <&uart3_xfer>;
535 compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";