2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2010 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mii.h>
36 #include <linux/phy.h>
37 #include <linux/brcmphy.h>
38 #include <linux/if_vlan.h>
40 #include <linux/tcp.h>
41 #include <linux/workqueue.h>
42 #include <linux/prefetch.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/firmware.h>
46 #include <net/checksum.h>
49 #include <asm/system.h>
51 #include <asm/byteorder.h>
52 #include <asm/uaccess.h>
55 #include <asm/idprom.h>
62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
63 #define TG3_VLAN_TAG_USED 1
65 #define TG3_VLAN_TAG_USED 0
70 #define DRV_MODULE_NAME "tg3"
72 #define TG3_MIN_NUM 113
73 #define DRV_MODULE_VERSION \
74 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
75 #define DRV_MODULE_RELDATE "August 2, 2010"
77 #define TG3_DEF_MAC_MODE 0
78 #define TG3_DEF_RX_MODE 0
79 #define TG3_DEF_TX_MODE 0
80 #define TG3_DEF_MSG_ENABLE \
90 /* length of time before we decide the hardware is borked,
91 * and dev->tx_timeout() should be called to fix the problem
93 #define TG3_TX_TIMEOUT (5 * HZ)
95 /* hardware minimum and maximum for a single frame's data payload */
96 #define TG3_MIN_MTU 60
97 #define TG3_MAX_MTU(tp) \
98 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
100 /* These numbers seem to be hard coded in the NIC firmware somehow.
101 * You can't change the ring sizes, but you can change where you place
102 * them in the NIC onboard memory.
104 #define TG3_RX_RING_SIZE 512
105 #define TG3_DEF_RX_RING_PENDING 200
106 #define TG3_RX_JUMBO_RING_SIZE 256
107 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
108 #define TG3_RSS_INDIR_TBL_SIZE 128
110 /* Do not place this n-ring entries value into the tp struct itself,
111 * we really want to expose these constants to GCC so that modulo et
112 * al. operations are done with shifts and masks instead of with
113 * hw multiply/modulo instructions. Another solution would be to
114 * replace things like '% foo' with '& (foo - 1)'.
116 #define TG3_RX_RCB_RING_SIZE(tp) \
117 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
118 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
120 #define TG3_TX_RING_SIZE 512
121 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
123 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
125 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
126 TG3_RX_JUMBO_RING_SIZE)
127 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
128 TG3_RX_RCB_RING_SIZE(tp))
129 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
131 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
133 #define TG3_RX_DMA_ALIGN 16
134 #define TG3_RX_HEADROOM ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
136 #define TG3_DMA_BYTE_ENAB 64
138 #define TG3_RX_STD_DMA_SZ 1536
139 #define TG3_RX_JMB_DMA_SZ 9046
141 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
143 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
144 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
146 #define TG3_RX_STD_BUFF_RING_SIZE \
147 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
149 #define TG3_RX_JMB_BUFF_RING_SIZE \
150 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
152 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
153 * that are at least dword aligned when used in PCIX mode. The driver
154 * works around this bug by double copying the packet. This workaround
155 * is built into the normal double copy length check for efficiency.
157 * However, the double copy is only necessary on those architectures
158 * where unaligned memory accesses are inefficient. For those architectures
159 * where unaligned memory accesses incur little penalty, we can reintegrate
160 * the 5701 in the normal rx path. Doing so saves a device structure
161 * dereference by hardcoding the double copy threshold in place.
163 #define TG3_RX_COPY_THRESHOLD 256
164 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
165 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
167 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
170 /* minimum number of free TX descriptors required to wake up TX process */
171 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
173 #define TG3_RAW_IP_ALIGN 2
175 /* number of ETHTOOL_GSTATS u64's */
176 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
178 #define TG3_NUM_TEST 6
180 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
182 #define FIRMWARE_TG3 "tigon/tg3.bin"
183 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
184 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
186 static char version
[] __devinitdata
=
187 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")";
189 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
190 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
191 MODULE_LICENSE("GPL");
192 MODULE_VERSION(DRV_MODULE_VERSION
);
193 MODULE_FIRMWARE(FIRMWARE_TG3
);
194 MODULE_FIRMWARE(FIRMWARE_TG3TSO
);
195 MODULE_FIRMWARE(FIRMWARE_TG3TSO5
);
197 static int tg3_debug
= -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
198 module_param(tg3_debug
, int, 0);
199 MODULE_PARM_DESC(tg3_debug
, "Tigon3 bitmapped debugging message enable value");
201 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl
) = {
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5700
)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5701
)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702
)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703
)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704
)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702FE
)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705
)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705_2
)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M
)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M_2
)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702X
)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703X
)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S
)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702A3
)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703A3
)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5782
)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5788
)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5789
)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901
)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901_2
)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S_2
)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705F
)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5721
)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5722
)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751
)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751M
)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751F
)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752
)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752M
)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753
)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753M
)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753F
)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754
)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754M
)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755
)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755M
)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5756
)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5786
)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787
)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787M
)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787F
)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714
)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714S
)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715
)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715S
)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780
)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780S
)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5781
)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906
)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906M
)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5784
)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5764
)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5723
)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761
)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761E
)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761S
)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761SE
)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5785_G
)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5785_F
)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57780
)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57760
)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57790
)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57788
)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5717
)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5718
)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5724
)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57781
)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57785
)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57761
)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57765
)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57791
)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57795
)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5719
)},
275 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9DXX
)},
276 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9MXX
)},
277 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1000
)},
278 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1001
)},
279 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1003
)},
280 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC9100
)},
281 {PCI_DEVICE(PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_TIGON3
)},
285 MODULE_DEVICE_TABLE(pci
, tg3_pci_tbl
);
287 static const struct {
288 const char string
[ETH_GSTRING_LEN
];
289 } ethtool_stats_keys
[TG3_NUM_STATS
] = {
292 { "rx_ucast_packets" },
293 { "rx_mcast_packets" },
294 { "rx_bcast_packets" },
296 { "rx_align_errors" },
297 { "rx_xon_pause_rcvd" },
298 { "rx_xoff_pause_rcvd" },
299 { "rx_mac_ctrl_rcvd" },
300 { "rx_xoff_entered" },
301 { "rx_frame_too_long_errors" },
303 { "rx_undersize_packets" },
304 { "rx_in_length_errors" },
305 { "rx_out_length_errors" },
306 { "rx_64_or_less_octet_packets" },
307 { "rx_65_to_127_octet_packets" },
308 { "rx_128_to_255_octet_packets" },
309 { "rx_256_to_511_octet_packets" },
310 { "rx_512_to_1023_octet_packets" },
311 { "rx_1024_to_1522_octet_packets" },
312 { "rx_1523_to_2047_octet_packets" },
313 { "rx_2048_to_4095_octet_packets" },
314 { "rx_4096_to_8191_octet_packets" },
315 { "rx_8192_to_9022_octet_packets" },
322 { "tx_flow_control" },
324 { "tx_single_collisions" },
325 { "tx_mult_collisions" },
327 { "tx_excessive_collisions" },
328 { "tx_late_collisions" },
329 { "tx_collide_2times" },
330 { "tx_collide_3times" },
331 { "tx_collide_4times" },
332 { "tx_collide_5times" },
333 { "tx_collide_6times" },
334 { "tx_collide_7times" },
335 { "tx_collide_8times" },
336 { "tx_collide_9times" },
337 { "tx_collide_10times" },
338 { "tx_collide_11times" },
339 { "tx_collide_12times" },
340 { "tx_collide_13times" },
341 { "tx_collide_14times" },
342 { "tx_collide_15times" },
343 { "tx_ucast_packets" },
344 { "tx_mcast_packets" },
345 { "tx_bcast_packets" },
346 { "tx_carrier_sense_errors" },
350 { "dma_writeq_full" },
351 { "dma_write_prioq_full" },
355 { "rx_threshold_hit" },
357 { "dma_readq_full" },
358 { "dma_read_prioq_full" },
359 { "tx_comp_queue_full" },
361 { "ring_set_send_prod_index" },
362 { "ring_status_update" },
364 { "nic_avoided_irqs" },
365 { "nic_tx_threshold_hit" }
368 static const struct {
369 const char string
[ETH_GSTRING_LEN
];
370 } ethtool_test_keys
[TG3_NUM_TEST
] = {
371 { "nvram test (online) " },
372 { "link test (online) " },
373 { "register test (offline)" },
374 { "memory test (offline)" },
375 { "loopback test (offline)" },
376 { "interrupt test (offline)" },
379 static void tg3_write32(struct tg3
*tp
, u32 off
, u32 val
)
381 writel(val
, tp
->regs
+ off
);
384 static u32
tg3_read32(struct tg3
*tp
, u32 off
)
386 return readl(tp
->regs
+ off
);
389 static void tg3_ape_write32(struct tg3
*tp
, u32 off
, u32 val
)
391 writel(val
, tp
->aperegs
+ off
);
394 static u32
tg3_ape_read32(struct tg3
*tp
, u32 off
)
396 return readl(tp
->aperegs
+ off
);
399 static void tg3_write_indirect_reg32(struct tg3
*tp
, u32 off
, u32 val
)
403 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
404 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
405 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
406 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
409 static void tg3_write_flush_reg32(struct tg3
*tp
, u32 off
, u32 val
)
411 writel(val
, tp
->regs
+ off
);
412 readl(tp
->regs
+ off
);
415 static u32
tg3_read_indirect_reg32(struct tg3
*tp
, u32 off
)
420 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
421 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
422 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
423 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
427 static void tg3_write_indirect_mbox(struct tg3
*tp
, u32 off
, u32 val
)
431 if (off
== (MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
)) {
432 pci_write_config_dword(tp
->pdev
, TG3PCI_RCV_RET_RING_CON_IDX
+
433 TG3_64BIT_REG_LOW
, val
);
436 if (off
== TG3_RX_STD_PROD_IDX_REG
) {
437 pci_write_config_dword(tp
->pdev
, TG3PCI_STD_RING_PROD_IDX
+
438 TG3_64BIT_REG_LOW
, val
);
442 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
443 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
444 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
445 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
447 /* In indirect mode when disabling interrupts, we also need
448 * to clear the interrupt bit in the GRC local ctrl register.
450 if ((off
== (MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
)) &&
452 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_LOCAL_CTRL
,
453 tp
->grc_local_ctrl
|GRC_LCLCTRL_CLEARINT
);
457 static u32
tg3_read_indirect_mbox(struct tg3
*tp
, u32 off
)
462 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
463 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
464 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
465 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
469 /* usec_wait specifies the wait time in usec when writing to certain registers
470 * where it is unsafe to read back the register without some delay.
471 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
472 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
474 static void _tw32_flush(struct tg3
*tp
, u32 off
, u32 val
, u32 usec_wait
)
476 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) ||
477 (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
478 /* Non-posted methods */
479 tp
->write32(tp
, off
, val
);
482 tg3_write32(tp
, off
, val
);
487 /* Wait again after the read for the posted method to guarantee that
488 * the wait time is met.
494 static inline void tw32_mailbox_flush(struct tg3
*tp
, u32 off
, u32 val
)
496 tp
->write32_mbox(tp
, off
, val
);
497 if (!(tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) &&
498 !(tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
499 tp
->read32_mbox(tp
, off
);
502 static void tg3_write32_tx_mbox(struct tg3
*tp
, u32 off
, u32 val
)
504 void __iomem
*mbox
= tp
->regs
+ off
;
506 if (tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
)
508 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
512 static u32
tg3_read32_mbox_5906(struct tg3
*tp
, u32 off
)
514 return readl(tp
->regs
+ off
+ GRCMBOX_BASE
);
517 static void tg3_write32_mbox_5906(struct tg3
*tp
, u32 off
, u32 val
)
519 writel(val
, tp
->regs
+ off
+ GRCMBOX_BASE
);
522 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
523 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
524 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
525 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
526 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
528 #define tw32(reg, val) tp->write32(tp, reg, val)
529 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
530 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
531 #define tr32(reg) tp->read32(tp, reg)
533 static void tg3_write_mem(struct tg3
*tp
, u32 off
, u32 val
)
537 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
538 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
))
541 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
542 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
543 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
544 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
546 /* Always leave this as zero. */
547 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
549 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
550 tw32_f(TG3PCI_MEM_WIN_DATA
, val
);
552 /* Always leave this as zero. */
553 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
555 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
558 static void tg3_read_mem(struct tg3
*tp
, u32 off
, u32
*val
)
562 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
563 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
)) {
568 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
569 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
570 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
571 pci_read_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
573 /* Always leave this as zero. */
574 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
576 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
577 *val
= tr32(TG3PCI_MEM_WIN_DATA
);
579 /* Always leave this as zero. */
580 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
582 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
585 static void tg3_ape_lock_init(struct tg3
*tp
)
590 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
591 regbase
= TG3_APE_LOCK_GRANT
;
593 regbase
= TG3_APE_PER_LOCK_GRANT
;
595 /* Make sure the driver hasn't any stale locks. */
596 for (i
= 0; i
< 8; i
++)
597 tg3_ape_write32(tp
, regbase
+ 4 * i
, APE_LOCK_GRANT_DRIVER
);
600 static int tg3_ape_lock(struct tg3
*tp
, int locknum
)
604 u32 status
, req
, gnt
;
606 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
610 case TG3_APE_LOCK_GRC
:
611 case TG3_APE_LOCK_MEM
:
617 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
) {
618 req
= TG3_APE_LOCK_REQ
;
619 gnt
= TG3_APE_LOCK_GRANT
;
621 req
= TG3_APE_PER_LOCK_REQ
;
622 gnt
= TG3_APE_PER_LOCK_GRANT
;
627 tg3_ape_write32(tp
, req
+ off
, APE_LOCK_REQ_DRIVER
);
629 /* Wait for up to 1 millisecond to acquire lock. */
630 for (i
= 0; i
< 100; i
++) {
631 status
= tg3_ape_read32(tp
, gnt
+ off
);
632 if (status
== APE_LOCK_GRANT_DRIVER
)
637 if (status
!= APE_LOCK_GRANT_DRIVER
) {
638 /* Revoke the lock request. */
639 tg3_ape_write32(tp
, gnt
+ off
,
640 APE_LOCK_GRANT_DRIVER
);
648 static void tg3_ape_unlock(struct tg3
*tp
, int locknum
)
652 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
656 case TG3_APE_LOCK_GRC
:
657 case TG3_APE_LOCK_MEM
:
663 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
664 gnt
= TG3_APE_LOCK_GRANT
;
666 gnt
= TG3_APE_PER_LOCK_GRANT
;
668 tg3_ape_write32(tp
, gnt
+ 4 * locknum
, APE_LOCK_GRANT_DRIVER
);
671 static void tg3_disable_ints(struct tg3
*tp
)
675 tw32(TG3PCI_MISC_HOST_CTRL
,
676 (tp
->misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
));
677 for (i
= 0; i
< tp
->irq_max
; i
++)
678 tw32_mailbox_f(tp
->napi
[i
].int_mbox
, 0x00000001);
681 static void tg3_enable_ints(struct tg3
*tp
)
688 tw32(TG3PCI_MISC_HOST_CTRL
,
689 (tp
->misc_host_ctrl
& ~MISC_HOST_CTRL_MASK_PCI_INT
));
691 tp
->coal_now
= tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
;
692 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
693 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
695 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
696 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
697 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
699 tp
->coal_now
|= tnapi
->coal_now
;
702 /* Force an initial interrupt */
703 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
704 (tp
->napi
[0].hw_status
->status
& SD_STATUS_UPDATED
))
705 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
707 tw32(HOSTCC_MODE
, tp
->coal_now
);
709 tp
->coal_now
&= ~(tp
->napi
[0].coal_now
| tp
->napi
[1].coal_now
);
712 static inline unsigned int tg3_has_work(struct tg3_napi
*tnapi
)
714 struct tg3
*tp
= tnapi
->tp
;
715 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
716 unsigned int work_exists
= 0;
718 /* check for phy events */
719 if (!(tp
->tg3_flags
&
720 (TG3_FLAG_USE_LINKCHG_REG
|
721 TG3_FLAG_POLL_SERDES
))) {
722 if (sblk
->status
& SD_STATUS_LINK_CHG
)
725 /* check for RX/TX work to do */
726 if (sblk
->idx
[0].tx_consumer
!= tnapi
->tx_cons
||
727 *(tnapi
->rx_rcb_prod_idx
) != tnapi
->rx_rcb_ptr
)
734 * similar to tg3_enable_ints, but it accurately determines whether there
735 * is new work pending and can return without flushing the PIO write
736 * which reenables interrupts
738 static void tg3_int_reenable(struct tg3_napi
*tnapi
)
740 struct tg3
*tp
= tnapi
->tp
;
742 tw32_mailbox(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
745 /* When doing tagged status, this work check is unnecessary.
746 * The last_tag we write above tells the chip which piece of
747 * work we've completed.
749 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
751 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
752 HOSTCC_MODE_ENABLE
| tnapi
->coal_now
);
755 static void tg3_napi_disable(struct tg3
*tp
)
759 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--)
760 napi_disable(&tp
->napi
[i
].napi
);
763 static void tg3_napi_enable(struct tg3
*tp
)
767 for (i
= 0; i
< tp
->irq_cnt
; i
++)
768 napi_enable(&tp
->napi
[i
].napi
);
771 static inline void tg3_netif_stop(struct tg3
*tp
)
773 tp
->dev
->trans_start
= jiffies
; /* prevent tx timeout */
774 tg3_napi_disable(tp
);
775 netif_tx_disable(tp
->dev
);
778 static inline void tg3_netif_start(struct tg3
*tp
)
780 /* NOTE: unconditional netif_tx_wake_all_queues is only
781 * appropriate so long as all callers are assured to
782 * have free tx slots (such as after tg3_init_hw)
784 netif_tx_wake_all_queues(tp
->dev
);
787 tp
->napi
[0].hw_status
->status
|= SD_STATUS_UPDATED
;
791 static void tg3_switch_clocks(struct tg3
*tp
)
796 if ((tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
797 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
800 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
);
802 orig_clock_ctrl
= clock_ctrl
;
803 clock_ctrl
&= (CLOCK_CTRL_FORCE_CLKRUN
|
804 CLOCK_CTRL_CLKRUN_OENABLE
|
806 tp
->pci_clock_ctrl
= clock_ctrl
;
808 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
809 if (orig_clock_ctrl
& CLOCK_CTRL_625_CORE
) {
810 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
811 clock_ctrl
| CLOCK_CTRL_625_CORE
, 40);
813 } else if ((orig_clock_ctrl
& CLOCK_CTRL_44MHZ_CORE
) != 0) {
814 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
816 (CLOCK_CTRL_44MHZ_CORE
| CLOCK_CTRL_ALTCLK
),
818 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
819 clock_ctrl
| (CLOCK_CTRL_ALTCLK
),
822 tw32_wait_f(TG3PCI_CLOCK_CTRL
, clock_ctrl
, 40);
825 #define PHY_BUSY_LOOPS 5000
827 static int tg3_readphy(struct tg3
*tp
, int reg
, u32
*val
)
833 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
835 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
841 frame_val
= ((tp
->phy_addr
<< MI_COM_PHY_ADDR_SHIFT
) &
842 MI_COM_PHY_ADDR_MASK
);
843 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
844 MI_COM_REG_ADDR_MASK
);
845 frame_val
|= (MI_COM_CMD_READ
| MI_COM_START
);
847 tw32_f(MAC_MI_COM
, frame_val
);
849 loops
= PHY_BUSY_LOOPS
;
852 frame_val
= tr32(MAC_MI_COM
);
854 if ((frame_val
& MI_COM_BUSY
) == 0) {
856 frame_val
= tr32(MAC_MI_COM
);
864 *val
= frame_val
& MI_COM_DATA_MASK
;
868 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
869 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
876 static int tg3_writephy(struct tg3
*tp
, int reg
, u32 val
)
882 if ((tp
->phy_flags
& TG3_PHYFLG_IS_FET
) &&
883 (reg
== MII_TG3_CTRL
|| reg
== MII_TG3_AUX_CTRL
))
886 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
888 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
892 frame_val
= ((tp
->phy_addr
<< MI_COM_PHY_ADDR_SHIFT
) &
893 MI_COM_PHY_ADDR_MASK
);
894 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
895 MI_COM_REG_ADDR_MASK
);
896 frame_val
|= (val
& MI_COM_DATA_MASK
);
897 frame_val
|= (MI_COM_CMD_WRITE
| MI_COM_START
);
899 tw32_f(MAC_MI_COM
, frame_val
);
901 loops
= PHY_BUSY_LOOPS
;
904 frame_val
= tr32(MAC_MI_COM
);
905 if ((frame_val
& MI_COM_BUSY
) == 0) {
907 frame_val
= tr32(MAC_MI_COM
);
917 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
918 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
925 static int tg3_bmcr_reset(struct tg3
*tp
)
930 /* OK, reset it, and poll the BMCR_RESET bit until it
931 * clears or we time out.
933 phy_control
= BMCR_RESET
;
934 err
= tg3_writephy(tp
, MII_BMCR
, phy_control
);
940 err
= tg3_readphy(tp
, MII_BMCR
, &phy_control
);
944 if ((phy_control
& BMCR_RESET
) == 0) {
956 static int tg3_mdio_read(struct mii_bus
*bp
, int mii_id
, int reg
)
958 struct tg3
*tp
= bp
->priv
;
961 spin_lock_bh(&tp
->lock
);
963 if (tg3_readphy(tp
, reg
, &val
))
966 spin_unlock_bh(&tp
->lock
);
971 static int tg3_mdio_write(struct mii_bus
*bp
, int mii_id
, int reg
, u16 val
)
973 struct tg3
*tp
= bp
->priv
;
976 spin_lock_bh(&tp
->lock
);
978 if (tg3_writephy(tp
, reg
, val
))
981 spin_unlock_bh(&tp
->lock
);
986 static int tg3_mdio_reset(struct mii_bus
*bp
)
991 static void tg3_mdio_config_5785(struct tg3
*tp
)
994 struct phy_device
*phydev
;
996 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
997 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
998 case PHY_ID_BCM50610
:
999 case PHY_ID_BCM50610M
:
1000 val
= MAC_PHYCFG2_50610_LED_MODES
;
1002 case PHY_ID_BCMAC131
:
1003 val
= MAC_PHYCFG2_AC131_LED_MODES
;
1005 case PHY_ID_RTL8211C
:
1006 val
= MAC_PHYCFG2_RTL8211C_LED_MODES
;
1008 case PHY_ID_RTL8201E
:
1009 val
= MAC_PHYCFG2_RTL8201E_LED_MODES
;
1015 if (phydev
->interface
!= PHY_INTERFACE_MODE_RGMII
) {
1016 tw32(MAC_PHYCFG2
, val
);
1018 val
= tr32(MAC_PHYCFG1
);
1019 val
&= ~(MAC_PHYCFG1_RGMII_INT
|
1020 MAC_PHYCFG1_RXCLK_TO_MASK
| MAC_PHYCFG1_TXCLK_TO_MASK
);
1021 val
|= MAC_PHYCFG1_RXCLK_TIMEOUT
| MAC_PHYCFG1_TXCLK_TIMEOUT
;
1022 tw32(MAC_PHYCFG1
, val
);
1027 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
))
1028 val
|= MAC_PHYCFG2_EMODE_MASK_MASK
|
1029 MAC_PHYCFG2_FMODE_MASK_MASK
|
1030 MAC_PHYCFG2_GMODE_MASK_MASK
|
1031 MAC_PHYCFG2_ACT_MASK_MASK
|
1032 MAC_PHYCFG2_QUAL_MASK_MASK
|
1033 MAC_PHYCFG2_INBAND_ENABLE
;
1035 tw32(MAC_PHYCFG2
, val
);
1037 val
= tr32(MAC_PHYCFG1
);
1038 val
&= ~(MAC_PHYCFG1_RXCLK_TO_MASK
| MAC_PHYCFG1_TXCLK_TO_MASK
|
1039 MAC_PHYCFG1_RGMII_EXT_RX_DEC
| MAC_PHYCFG1_RGMII_SND_STAT_EN
);
1040 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
)) {
1041 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1042 val
|= MAC_PHYCFG1_RGMII_EXT_RX_DEC
;
1043 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1044 val
|= MAC_PHYCFG1_RGMII_SND_STAT_EN
;
1046 val
|= MAC_PHYCFG1_RXCLK_TIMEOUT
| MAC_PHYCFG1_TXCLK_TIMEOUT
|
1047 MAC_PHYCFG1_RGMII_INT
| MAC_PHYCFG1_TXC_DRV
;
1048 tw32(MAC_PHYCFG1
, val
);
1050 val
= tr32(MAC_EXT_RGMII_MODE
);
1051 val
&= ~(MAC_RGMII_MODE_RX_INT_B
|
1052 MAC_RGMII_MODE_RX_QUALITY
|
1053 MAC_RGMII_MODE_RX_ACTIVITY
|
1054 MAC_RGMII_MODE_RX_ENG_DET
|
1055 MAC_RGMII_MODE_TX_ENABLE
|
1056 MAC_RGMII_MODE_TX_LOWPWR
|
1057 MAC_RGMII_MODE_TX_RESET
);
1058 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
)) {
1059 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1060 val
|= MAC_RGMII_MODE_RX_INT_B
|
1061 MAC_RGMII_MODE_RX_QUALITY
|
1062 MAC_RGMII_MODE_RX_ACTIVITY
|
1063 MAC_RGMII_MODE_RX_ENG_DET
;
1064 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1065 val
|= MAC_RGMII_MODE_TX_ENABLE
|
1066 MAC_RGMII_MODE_TX_LOWPWR
|
1067 MAC_RGMII_MODE_TX_RESET
;
1069 tw32(MAC_EXT_RGMII_MODE
, val
);
1072 static void tg3_mdio_start(struct tg3
*tp
)
1074 tp
->mi_mode
&= ~MAC_MI_MODE_AUTO_POLL
;
1075 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
1078 if ((tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) &&
1079 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
1080 tg3_mdio_config_5785(tp
);
1083 static int tg3_mdio_init(struct tg3
*tp
)
1087 struct phy_device
*phydev
;
1089 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
1090 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
) {
1093 tp
->phy_addr
= PCI_FUNC(tp
->pdev
->devfn
) + 1;
1095 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5717_A0
)
1096 is_serdes
= tr32(SG_DIG_STATUS
) & SG_DIG_IS_SERDES
;
1098 is_serdes
= tr32(TG3_CPMU_PHY_STRAP
) &
1099 TG3_CPMU_PHY_STRAP_IS_SERDES
;
1103 tp
->phy_addr
= TG3_PHY_MII_ADDR
;
1107 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) ||
1108 (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
))
1111 tp
->mdio_bus
= mdiobus_alloc();
1112 if (tp
->mdio_bus
== NULL
)
1115 tp
->mdio_bus
->name
= "tg3 mdio bus";
1116 snprintf(tp
->mdio_bus
->id
, MII_BUS_ID_SIZE
, "%x",
1117 (tp
->pdev
->bus
->number
<< 8) | tp
->pdev
->devfn
);
1118 tp
->mdio_bus
->priv
= tp
;
1119 tp
->mdio_bus
->parent
= &tp
->pdev
->dev
;
1120 tp
->mdio_bus
->read
= &tg3_mdio_read
;
1121 tp
->mdio_bus
->write
= &tg3_mdio_write
;
1122 tp
->mdio_bus
->reset
= &tg3_mdio_reset
;
1123 tp
->mdio_bus
->phy_mask
= ~(1 << TG3_PHY_MII_ADDR
);
1124 tp
->mdio_bus
->irq
= &tp
->mdio_irq
[0];
1126 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1127 tp
->mdio_bus
->irq
[i
] = PHY_POLL
;
1129 /* The bus registration will look for all the PHYs on the mdio bus.
1130 * Unfortunately, it does not ensure the PHY is powered up before
1131 * accessing the PHY ID registers. A chip reset is the
1132 * quickest way to bring the device back to an operational state..
1134 if (tg3_readphy(tp
, MII_BMCR
, ®
) || (reg
& BMCR_PDOWN
))
1137 i
= mdiobus_register(tp
->mdio_bus
);
1139 dev_warn(&tp
->pdev
->dev
, "mdiobus_reg failed (0x%x)\n", i
);
1140 mdiobus_free(tp
->mdio_bus
);
1144 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1146 if (!phydev
|| !phydev
->drv
) {
1147 dev_warn(&tp
->pdev
->dev
, "No PHY devices\n");
1148 mdiobus_unregister(tp
->mdio_bus
);
1149 mdiobus_free(tp
->mdio_bus
);
1153 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
1154 case PHY_ID_BCM57780
:
1155 phydev
->interface
= PHY_INTERFACE_MODE_GMII
;
1156 phydev
->dev_flags
|= PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1158 case PHY_ID_BCM50610
:
1159 case PHY_ID_BCM50610M
:
1160 phydev
->dev_flags
|= PHY_BRCM_CLEAR_RGMII_MODE
|
1161 PHY_BRCM_RX_REFCLK_UNUSED
|
1162 PHY_BRCM_DIS_TXCRXC_NOENRGY
|
1163 PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1164 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
)
1165 phydev
->dev_flags
|= PHY_BRCM_STD_IBND_DISABLE
;
1166 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1167 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_RX_ENABLE
;
1168 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1169 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_TX_ENABLE
;
1171 case PHY_ID_RTL8211C
:
1172 phydev
->interface
= PHY_INTERFACE_MODE_RGMII
;
1174 case PHY_ID_RTL8201E
:
1175 case PHY_ID_BCMAC131
:
1176 phydev
->interface
= PHY_INTERFACE_MODE_MII
;
1177 phydev
->dev_flags
|= PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1178 tp
->phy_flags
|= TG3_PHYFLG_IS_FET
;
1182 tp
->tg3_flags3
|= TG3_FLG3_MDIOBUS_INITED
;
1184 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
1185 tg3_mdio_config_5785(tp
);
1190 static void tg3_mdio_fini(struct tg3
*tp
)
1192 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) {
1193 tp
->tg3_flags3
&= ~TG3_FLG3_MDIOBUS_INITED
;
1194 mdiobus_unregister(tp
->mdio_bus
);
1195 mdiobus_free(tp
->mdio_bus
);
1199 /* tp->lock is held. */
1200 static inline void tg3_generate_fw_event(struct tg3
*tp
)
1204 val
= tr32(GRC_RX_CPU_EVENT
);
1205 val
|= GRC_RX_CPU_DRIVER_EVENT
;
1206 tw32_f(GRC_RX_CPU_EVENT
, val
);
1208 tp
->last_event_jiffies
= jiffies
;
1211 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1213 /* tp->lock is held. */
1214 static void tg3_wait_for_event_ack(struct tg3
*tp
)
1217 unsigned int delay_cnt
;
1220 /* If enough time has passed, no wait is necessary. */
1221 time_remain
= (long)(tp
->last_event_jiffies
+ 1 +
1222 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC
)) -
1224 if (time_remain
< 0)
1227 /* Check if we can shorten the wait time. */
1228 delay_cnt
= jiffies_to_usecs(time_remain
);
1229 if (delay_cnt
> TG3_FW_EVENT_TIMEOUT_USEC
)
1230 delay_cnt
= TG3_FW_EVENT_TIMEOUT_USEC
;
1231 delay_cnt
= (delay_cnt
>> 3) + 1;
1233 for (i
= 0; i
< delay_cnt
; i
++) {
1234 if (!(tr32(GRC_RX_CPU_EVENT
) & GRC_RX_CPU_DRIVER_EVENT
))
1240 /* tp->lock is held. */
1241 static void tg3_ump_link_report(struct tg3
*tp
)
1246 if (!(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
1247 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
1250 tg3_wait_for_event_ack(tp
);
1252 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_LINK_UPDATE
);
1254 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 14);
1257 if (!tg3_readphy(tp
, MII_BMCR
, ®
))
1259 if (!tg3_readphy(tp
, MII_BMSR
, ®
))
1260 val
|= (reg
& 0xffff);
1261 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
, val
);
1264 if (!tg3_readphy(tp
, MII_ADVERTISE
, ®
))
1266 if (!tg3_readphy(tp
, MII_LPA
, ®
))
1267 val
|= (reg
& 0xffff);
1268 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 4, val
);
1271 if (!(tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)) {
1272 if (!tg3_readphy(tp
, MII_CTRL1000
, ®
))
1274 if (!tg3_readphy(tp
, MII_STAT1000
, ®
))
1275 val
|= (reg
& 0xffff);
1277 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 8, val
);
1279 if (!tg3_readphy(tp
, MII_PHYADDR
, ®
))
1283 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 12, val
);
1285 tg3_generate_fw_event(tp
);
1288 static void tg3_link_report(struct tg3
*tp
)
1290 if (!netif_carrier_ok(tp
->dev
)) {
1291 netif_info(tp
, link
, tp
->dev
, "Link is down\n");
1292 tg3_ump_link_report(tp
);
1293 } else if (netif_msg_link(tp
)) {
1294 netdev_info(tp
->dev
, "Link is up at %d Mbps, %s duplex\n",
1295 (tp
->link_config
.active_speed
== SPEED_1000
?
1297 (tp
->link_config
.active_speed
== SPEED_100
?
1299 (tp
->link_config
.active_duplex
== DUPLEX_FULL
?
1302 netdev_info(tp
->dev
, "Flow control is %s for TX and %s for RX\n",
1303 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
) ?
1305 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
) ?
1307 tg3_ump_link_report(tp
);
1311 static u16
tg3_advert_flowctrl_1000T(u8 flow_ctrl
)
1315 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1316 miireg
= ADVERTISE_PAUSE_CAP
;
1317 else if (flow_ctrl
& FLOW_CTRL_TX
)
1318 miireg
= ADVERTISE_PAUSE_ASYM
;
1319 else if (flow_ctrl
& FLOW_CTRL_RX
)
1320 miireg
= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1327 static u16
tg3_advert_flowctrl_1000X(u8 flow_ctrl
)
1331 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1332 miireg
= ADVERTISE_1000XPAUSE
;
1333 else if (flow_ctrl
& FLOW_CTRL_TX
)
1334 miireg
= ADVERTISE_1000XPSE_ASYM
;
1335 else if (flow_ctrl
& FLOW_CTRL_RX
)
1336 miireg
= ADVERTISE_1000XPAUSE
| ADVERTISE_1000XPSE_ASYM
;
1343 static u8
tg3_resolve_flowctrl_1000X(u16 lcladv
, u16 rmtadv
)
1347 if (lcladv
& ADVERTISE_1000XPAUSE
) {
1348 if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1349 if (rmtadv
& LPA_1000XPAUSE
)
1350 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1351 else if (rmtadv
& LPA_1000XPAUSE_ASYM
)
1354 if (rmtadv
& LPA_1000XPAUSE
)
1355 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1357 } else if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1358 if ((rmtadv
& LPA_1000XPAUSE
) && (rmtadv
& LPA_1000XPAUSE_ASYM
))
1365 static void tg3_setup_flow_control(struct tg3
*tp
, u32 lcladv
, u32 rmtadv
)
1369 u32 old_rx_mode
= tp
->rx_mode
;
1370 u32 old_tx_mode
= tp
->tx_mode
;
1372 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
1373 autoneg
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]->autoneg
;
1375 autoneg
= tp
->link_config
.autoneg
;
1377 if (autoneg
== AUTONEG_ENABLE
&&
1378 (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)) {
1379 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
1380 flowctrl
= tg3_resolve_flowctrl_1000X(lcladv
, rmtadv
);
1382 flowctrl
= mii_resolve_flowctrl_fdx(lcladv
, rmtadv
);
1384 flowctrl
= tp
->link_config
.flowctrl
;
1386 tp
->link_config
.active_flowctrl
= flowctrl
;
1388 if (flowctrl
& FLOW_CTRL_RX
)
1389 tp
->rx_mode
|= RX_MODE_FLOW_CTRL_ENABLE
;
1391 tp
->rx_mode
&= ~RX_MODE_FLOW_CTRL_ENABLE
;
1393 if (old_rx_mode
!= tp
->rx_mode
)
1394 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
1396 if (flowctrl
& FLOW_CTRL_TX
)
1397 tp
->tx_mode
|= TX_MODE_FLOW_CTRL_ENABLE
;
1399 tp
->tx_mode
&= ~TX_MODE_FLOW_CTRL_ENABLE
;
1401 if (old_tx_mode
!= tp
->tx_mode
)
1402 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
1405 static void tg3_adjust_link(struct net_device
*dev
)
1407 u8 oldflowctrl
, linkmesg
= 0;
1408 u32 mac_mode
, lcl_adv
, rmt_adv
;
1409 struct tg3
*tp
= netdev_priv(dev
);
1410 struct phy_device
*phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1412 spin_lock_bh(&tp
->lock
);
1414 mac_mode
= tp
->mac_mode
& ~(MAC_MODE_PORT_MODE_MASK
|
1415 MAC_MODE_HALF_DUPLEX
);
1417 oldflowctrl
= tp
->link_config
.active_flowctrl
;
1423 if (phydev
->speed
== SPEED_100
|| phydev
->speed
== SPEED_10
)
1424 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
1425 else if (phydev
->speed
== SPEED_1000
||
1426 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
)
1427 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1429 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
1431 if (phydev
->duplex
== DUPLEX_HALF
)
1432 mac_mode
|= MAC_MODE_HALF_DUPLEX
;
1434 lcl_adv
= tg3_advert_flowctrl_1000T(
1435 tp
->link_config
.flowctrl
);
1438 rmt_adv
= LPA_PAUSE_CAP
;
1439 if (phydev
->asym_pause
)
1440 rmt_adv
|= LPA_PAUSE_ASYM
;
1443 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
1445 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1447 if (mac_mode
!= tp
->mac_mode
) {
1448 tp
->mac_mode
= mac_mode
;
1449 tw32_f(MAC_MODE
, tp
->mac_mode
);
1453 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
1454 if (phydev
->speed
== SPEED_10
)
1456 MAC_MI_STAT_10MBPS_MODE
|
1457 MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1459 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1462 if (phydev
->speed
== SPEED_1000
&& phydev
->duplex
== DUPLEX_HALF
)
1463 tw32(MAC_TX_LENGTHS
,
1464 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1465 (6 << TX_LENGTHS_IPG_SHIFT
) |
1466 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1468 tw32(MAC_TX_LENGTHS
,
1469 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1470 (6 << TX_LENGTHS_IPG_SHIFT
) |
1471 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1473 if ((phydev
->link
&& tp
->link_config
.active_speed
== SPEED_INVALID
) ||
1474 (!phydev
->link
&& tp
->link_config
.active_speed
!= SPEED_INVALID
) ||
1475 phydev
->speed
!= tp
->link_config
.active_speed
||
1476 phydev
->duplex
!= tp
->link_config
.active_duplex
||
1477 oldflowctrl
!= tp
->link_config
.active_flowctrl
)
1480 tp
->link_config
.active_speed
= phydev
->speed
;
1481 tp
->link_config
.active_duplex
= phydev
->duplex
;
1483 spin_unlock_bh(&tp
->lock
);
1486 tg3_link_report(tp
);
1489 static int tg3_phy_init(struct tg3
*tp
)
1491 struct phy_device
*phydev
;
1493 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
)
1496 /* Bring the PHY back to a known state. */
1499 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1501 /* Attach the MAC to the PHY. */
1502 phydev
= phy_connect(tp
->dev
, dev_name(&phydev
->dev
), tg3_adjust_link
,
1503 phydev
->dev_flags
, phydev
->interface
);
1504 if (IS_ERR(phydev
)) {
1505 dev_err(&tp
->pdev
->dev
, "Could not attach to PHY\n");
1506 return PTR_ERR(phydev
);
1509 /* Mask with MAC supported features. */
1510 switch (phydev
->interface
) {
1511 case PHY_INTERFACE_MODE_GMII
:
1512 case PHY_INTERFACE_MODE_RGMII
:
1513 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
1514 phydev
->supported
&= (PHY_GBIT_FEATURES
|
1516 SUPPORTED_Asym_Pause
);
1520 case PHY_INTERFACE_MODE_MII
:
1521 phydev
->supported
&= (PHY_BASIC_FEATURES
|
1523 SUPPORTED_Asym_Pause
);
1526 phy_disconnect(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1530 tp
->phy_flags
|= TG3_PHYFLG_IS_CONNECTED
;
1532 phydev
->advertising
= phydev
->supported
;
1537 static void tg3_phy_start(struct tg3
*tp
)
1539 struct phy_device
*phydev
;
1541 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
1544 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1546 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
) {
1547 tp
->phy_flags
&= ~TG3_PHYFLG_IS_LOW_POWER
;
1548 phydev
->speed
= tp
->link_config
.orig_speed
;
1549 phydev
->duplex
= tp
->link_config
.orig_duplex
;
1550 phydev
->autoneg
= tp
->link_config
.orig_autoneg
;
1551 phydev
->advertising
= tp
->link_config
.orig_advertising
;
1556 phy_start_aneg(phydev
);
1559 static void tg3_phy_stop(struct tg3
*tp
)
1561 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
1564 phy_stop(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1567 static void tg3_phy_fini(struct tg3
*tp
)
1569 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) {
1570 phy_disconnect(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1571 tp
->phy_flags
&= ~TG3_PHYFLG_IS_CONNECTED
;
1575 static int tg3_phydsp_write(struct tg3
*tp
, u32 reg
, u32 val
)
1579 err
= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, reg
);
1581 err
= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, val
);
1586 static void tg3_phy_fet_toggle_apd(struct tg3
*tp
, bool enable
)
1590 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &phytest
)) {
1593 tg3_writephy(tp
, MII_TG3_FET_TEST
,
1594 phytest
| MII_TG3_FET_SHADOW_EN
);
1595 if (!tg3_readphy(tp
, MII_TG3_FET_SHDW_AUXSTAT2
, &phy
)) {
1597 phy
|= MII_TG3_FET_SHDW_AUXSTAT2_APD
;
1599 phy
&= ~MII_TG3_FET_SHDW_AUXSTAT2_APD
;
1600 tg3_writephy(tp
, MII_TG3_FET_SHDW_AUXSTAT2
, phy
);
1602 tg3_writephy(tp
, MII_TG3_FET_TEST
, phytest
);
1606 static void tg3_phy_toggle_apd(struct tg3
*tp
, bool enable
)
1610 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
1611 ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
1612 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
) &&
1613 (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)))
1616 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
1617 tg3_phy_fet_toggle_apd(tp
, enable
);
1621 reg
= MII_TG3_MISC_SHDW_WREN
|
1622 MII_TG3_MISC_SHDW_SCR5_SEL
|
1623 MII_TG3_MISC_SHDW_SCR5_LPED
|
1624 MII_TG3_MISC_SHDW_SCR5_DLPTLM
|
1625 MII_TG3_MISC_SHDW_SCR5_SDTL
|
1626 MII_TG3_MISC_SHDW_SCR5_C125OE
;
1627 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
|| !enable
)
1628 reg
|= MII_TG3_MISC_SHDW_SCR5_DLLAPD
;
1630 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1633 reg
= MII_TG3_MISC_SHDW_WREN
|
1634 MII_TG3_MISC_SHDW_APD_SEL
|
1635 MII_TG3_MISC_SHDW_APD_WKTM_84MS
;
1637 reg
|= MII_TG3_MISC_SHDW_APD_ENABLE
;
1639 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1642 static void tg3_phy_toggle_automdix(struct tg3
*tp
, int enable
)
1646 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
1647 (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
1650 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
1653 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &ephy
)) {
1654 u32 reg
= MII_TG3_FET_SHDW_MISCCTRL
;
1656 tg3_writephy(tp
, MII_TG3_FET_TEST
,
1657 ephy
| MII_TG3_FET_SHADOW_EN
);
1658 if (!tg3_readphy(tp
, reg
, &phy
)) {
1660 phy
|= MII_TG3_FET_SHDW_MISCCTRL_MDIX
;
1662 phy
&= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX
;
1663 tg3_writephy(tp
, reg
, phy
);
1665 tg3_writephy(tp
, MII_TG3_FET_TEST
, ephy
);
1668 phy
= MII_TG3_AUXCTL_MISC_RDSEL_MISC
|
1669 MII_TG3_AUXCTL_SHDWSEL_MISC
;
1670 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
) &&
1671 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &phy
)) {
1673 phy
|= MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1675 phy
&= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1676 phy
|= MII_TG3_AUXCTL_MISC_WREN
;
1677 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1682 static void tg3_phy_set_wirespeed(struct tg3
*tp
)
1686 if (tp
->phy_flags
& TG3_PHYFLG_NO_ETH_WIRE_SPEED
)
1689 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x7007) &&
1690 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
))
1691 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
1692 (val
| (1 << 15) | (1 << 4)));
1695 static void tg3_phy_apply_otp(struct tg3
*tp
)
1704 /* Enable SM_DSP clock and tx 6dB coding. */
1705 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1706 MII_TG3_AUXCTL_ACTL_SMDSP_ENA
|
1707 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1708 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1710 phy
= ((otp
& TG3_OTP_AGCTGT_MASK
) >> TG3_OTP_AGCTGT_SHIFT
);
1711 phy
|= MII_TG3_DSP_TAP1_AGCTGT_DFLT
;
1712 tg3_phydsp_write(tp
, MII_TG3_DSP_TAP1
, phy
);
1714 phy
= ((otp
& TG3_OTP_HPFFLTR_MASK
) >> TG3_OTP_HPFFLTR_SHIFT
) |
1715 ((otp
& TG3_OTP_HPFOVER_MASK
) >> TG3_OTP_HPFOVER_SHIFT
);
1716 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH0
, phy
);
1718 phy
= ((otp
& TG3_OTP_LPFDIS_MASK
) >> TG3_OTP_LPFDIS_SHIFT
);
1719 phy
|= MII_TG3_DSP_AADJ1CH3_ADCCKADJ
;
1720 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH3
, phy
);
1722 phy
= ((otp
& TG3_OTP_VDAC_MASK
) >> TG3_OTP_VDAC_SHIFT
);
1723 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP75
, phy
);
1725 phy
= ((otp
& TG3_OTP_10BTAMP_MASK
) >> TG3_OTP_10BTAMP_SHIFT
);
1726 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP96
, phy
);
1728 phy
= ((otp
& TG3_OTP_ROFF_MASK
) >> TG3_OTP_ROFF_SHIFT
) |
1729 ((otp
& TG3_OTP_RCOFF_MASK
) >> TG3_OTP_RCOFF_SHIFT
);
1730 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP97
, phy
);
1732 /* Turn off SM_DSP clock. */
1733 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1734 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1735 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1738 static int tg3_wait_macro_done(struct tg3
*tp
)
1745 if (!tg3_readphy(tp
, MII_TG3_DSP_CONTROL
, &tmp32
)) {
1746 if ((tmp32
& 0x1000) == 0)
1756 static int tg3_phy_write_and_check_testpat(struct tg3
*tp
, int *resetp
)
1758 static const u32 test_pat
[4][6] = {
1759 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1760 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1761 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1762 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1766 for (chan
= 0; chan
< 4; chan
++) {
1769 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1770 (chan
* 0x2000) | 0x0200);
1771 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0002);
1773 for (i
= 0; i
< 6; i
++)
1774 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
,
1777 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0202);
1778 if (tg3_wait_macro_done(tp
)) {
1783 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1784 (chan
* 0x2000) | 0x0200);
1785 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0082);
1786 if (tg3_wait_macro_done(tp
)) {
1791 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0802);
1792 if (tg3_wait_macro_done(tp
)) {
1797 for (i
= 0; i
< 6; i
+= 2) {
1800 if (tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &low
) ||
1801 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &high
) ||
1802 tg3_wait_macro_done(tp
)) {
1808 if (low
!= test_pat
[chan
][i
] ||
1809 high
!= test_pat
[chan
][i
+1]) {
1810 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000b);
1811 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4001);
1812 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4005);
1822 static int tg3_phy_reset_chanpat(struct tg3
*tp
)
1826 for (chan
= 0; chan
< 4; chan
++) {
1829 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1830 (chan
* 0x2000) | 0x0200);
1831 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0002);
1832 for (i
= 0; i
< 6; i
++)
1833 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x000);
1834 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0202);
1835 if (tg3_wait_macro_done(tp
))
1842 static int tg3_phy_reset_5703_4_5(struct tg3
*tp
)
1844 u32 reg32
, phy9_orig
;
1845 int retries
, do_phy_reset
, err
;
1851 err
= tg3_bmcr_reset(tp
);
1857 /* Disable transmitter and interrupt. */
1858 if (tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
))
1862 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1864 /* Set full-duplex, 1000 mbps. */
1865 tg3_writephy(tp
, MII_BMCR
,
1866 BMCR_FULLDPLX
| TG3_BMCR_SPEED1000
);
1868 /* Set to master mode. */
1869 if (tg3_readphy(tp
, MII_TG3_CTRL
, &phy9_orig
))
1872 tg3_writephy(tp
, MII_TG3_CTRL
,
1873 (MII_TG3_CTRL_AS_MASTER
|
1874 MII_TG3_CTRL_ENABLE_AS_MASTER
));
1876 /* Enable SM_DSP_CLOCK and 6dB. */
1877 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1879 /* Block the PHY control access. */
1880 tg3_phydsp_write(tp
, 0x8005, 0x0800);
1882 err
= tg3_phy_write_and_check_testpat(tp
, &do_phy_reset
);
1885 } while (--retries
);
1887 err
= tg3_phy_reset_chanpat(tp
);
1891 tg3_phydsp_write(tp
, 0x8005, 0x0000);
1893 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8200);
1894 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0000);
1896 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1897 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
1898 /* Set Extended packet length bit for jumbo frames */
1899 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4400);
1901 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1904 tg3_writephy(tp
, MII_TG3_CTRL
, phy9_orig
);
1906 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
)) {
1908 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1915 /* This will reset the tigon3 PHY if there is no valid
1916 * link unless the FORCE argument is non-zero.
1918 static int tg3_phy_reset(struct tg3
*tp
)
1924 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
1927 val
= tr32(GRC_MISC_CFG
);
1928 tw32_f(GRC_MISC_CFG
, val
& ~GRC_MISC_CFG_EPHY_IDDQ
);
1931 err
= tg3_readphy(tp
, MII_BMSR
, &phy_status
);
1932 err
|= tg3_readphy(tp
, MII_BMSR
, &phy_status
);
1936 if (netif_running(tp
->dev
) && netif_carrier_ok(tp
->dev
)) {
1937 netif_carrier_off(tp
->dev
);
1938 tg3_link_report(tp
);
1941 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1942 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
1943 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
1944 err
= tg3_phy_reset_5703_4_5(tp
);
1951 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
1952 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
1953 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
1954 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
)
1956 cpmuctrl
& ~CPMU_CTRL_GPHY_10MB_RXONLY
);
1959 err
= tg3_bmcr_reset(tp
);
1963 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
) {
1966 phy
= MII_TG3_DSP_EXP8_AEDW
| MII_TG3_DSP_EXP8_REJ2MHz
;
1967 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP8
, phy
);
1969 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
1972 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
1973 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
1976 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
1977 if ((val
& CPMU_LSPD_1000MB_MACCLK_MASK
) ==
1978 CPMU_LSPD_1000MB_MACCLK_12_5
) {
1979 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
1981 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
1985 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
1986 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
) &&
1987 (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
))
1990 tg3_phy_apply_otp(tp
);
1992 if (tp
->phy_flags
& TG3_PHYFLG_ENABLE_APD
)
1993 tg3_phy_toggle_apd(tp
, true);
1995 tg3_phy_toggle_apd(tp
, false);
1998 if (tp
->phy_flags
& TG3_PHYFLG_ADC_BUG
) {
1999 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
2000 tg3_phydsp_write(tp
, 0x201f, 0x2aaa);
2001 tg3_phydsp_write(tp
, 0x000a, 0x0323);
2002 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
2004 if (tp
->phy_flags
& TG3_PHYFLG_5704_A0_BUG
) {
2005 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8d68);
2006 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8d68);
2008 if (tp
->phy_flags
& TG3_PHYFLG_BER_BUG
) {
2009 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
2010 tg3_phydsp_write(tp
, 0x000a, 0x310b);
2011 tg3_phydsp_write(tp
, 0x201f, 0x9506);
2012 tg3_phydsp_write(tp
, 0x401f, 0x14e2);
2013 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
2014 } else if (tp
->phy_flags
& TG3_PHYFLG_JITTER_BUG
) {
2015 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
2016 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
2017 if (tp
->phy_flags
& TG3_PHYFLG_ADJUST_TRIM
) {
2018 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x110b);
2019 tg3_writephy(tp
, MII_TG3_TEST1
,
2020 MII_TG3_TEST1_TRIM_EN
| 0x4);
2022 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x010b);
2023 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
2025 /* Set Extended packet length bit (bit 14) on all chips that */
2026 /* support jumbo frames */
2027 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
2028 /* Cannot do read-modify-write on 5401 */
2029 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
2030 } else if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
2033 /* Set bit 14 with read-modify-write to preserve other bits */
2034 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0007) &&
2035 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &phy_reg
))
2036 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy_reg
| 0x4000);
2039 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2040 * jumbo frames transmission.
2042 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
2045 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, &phy_reg
))
2046 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
2047 phy_reg
| MII_TG3_EXT_CTRL_FIFO_ELASTIC
);
2050 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2051 /* adjust output voltage */
2052 tg3_writephy(tp
, MII_TG3_FET_PTEST
, 0x12);
2055 tg3_phy_toggle_automdix(tp
, 1);
2056 tg3_phy_set_wirespeed(tp
);
2060 static void tg3_frob_aux_power(struct tg3
*tp
)
2062 struct tg3
*tp_peer
= tp
;
2064 /* The GPIOs do something completely different on 57765. */
2065 if ((tp
->tg3_flags2
& TG3_FLG2_IS_NIC
) == 0 ||
2066 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
2067 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
2070 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2071 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
||
2072 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
) {
2073 struct net_device
*dev_peer
;
2075 dev_peer
= pci_get_drvdata(tp
->pdev_peer
);
2076 /* remove_one() may have been run on the peer. */
2080 tp_peer
= netdev_priv(dev_peer
);
2083 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0 ||
2084 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0 ||
2085 (tp_peer
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0 ||
2086 (tp_peer
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0) {
2087 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2088 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2089 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2090 (GRC_LCLCTRL_GPIO_OE0
|
2091 GRC_LCLCTRL_GPIO_OE1
|
2092 GRC_LCLCTRL_GPIO_OE2
|
2093 GRC_LCLCTRL_GPIO_OUTPUT0
|
2094 GRC_LCLCTRL_GPIO_OUTPUT1
),
2096 } else if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
2097 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
2098 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2099 u32 grc_local_ctrl
= GRC_LCLCTRL_GPIO_OE0
|
2100 GRC_LCLCTRL_GPIO_OE1
|
2101 GRC_LCLCTRL_GPIO_OE2
|
2102 GRC_LCLCTRL_GPIO_OUTPUT0
|
2103 GRC_LCLCTRL_GPIO_OUTPUT1
|
2105 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2107 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT2
;
2108 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2110 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT0
;
2111 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2114 u32 grc_local_ctrl
= 0;
2116 if (tp_peer
!= tp
&&
2117 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
2120 /* Workaround to prevent overdrawing Amps. */
2121 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
2123 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
2124 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2125 grc_local_ctrl
, 100);
2128 /* On 5753 and variants, GPIO2 cannot be used. */
2129 no_gpio2
= tp
->nic_sram_data_cfg
&
2130 NIC_SRAM_DATA_CFG_NO_GPIO2
;
2132 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
2133 GRC_LCLCTRL_GPIO_OE1
|
2134 GRC_LCLCTRL_GPIO_OE2
|
2135 GRC_LCLCTRL_GPIO_OUTPUT1
|
2136 GRC_LCLCTRL_GPIO_OUTPUT2
;
2138 grc_local_ctrl
&= ~(GRC_LCLCTRL_GPIO_OE2
|
2139 GRC_LCLCTRL_GPIO_OUTPUT2
);
2141 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2142 grc_local_ctrl
, 100);
2144 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT0
;
2146 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2147 grc_local_ctrl
, 100);
2150 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT2
;
2151 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2152 grc_local_ctrl
, 100);
2156 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
2157 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
2158 if (tp_peer
!= tp
&&
2159 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
2162 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2163 (GRC_LCLCTRL_GPIO_OE1
|
2164 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2166 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2167 GRC_LCLCTRL_GPIO_OE1
, 100);
2169 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2170 (GRC_LCLCTRL_GPIO_OE1
|
2171 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2176 static int tg3_5700_link_polarity(struct tg3
*tp
, u32 speed
)
2178 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_2
)
2180 else if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5411
) {
2181 if (speed
!= SPEED_10
)
2183 } else if (speed
== SPEED_10
)
2189 static int tg3_setup_phy(struct tg3
*, int);
2191 #define RESET_KIND_SHUTDOWN 0
2192 #define RESET_KIND_INIT 1
2193 #define RESET_KIND_SUSPEND 2
2195 static void tg3_write_sig_post_reset(struct tg3
*, int);
2196 static int tg3_halt_cpu(struct tg3
*, u32
);
2198 static void tg3_power_down_phy(struct tg3
*tp
, bool do_low_power
)
2202 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
2203 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2204 u32 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
2205 u32 serdes_cfg
= tr32(MAC_SERDES_CFG
);
2208 SG_DIG_USING_HW_AUTONEG
| SG_DIG_SOFT_RESET
;
2209 tw32(SG_DIG_CTRL
, sg_dig_ctrl
);
2210 tw32(MAC_SERDES_CFG
, serdes_cfg
| (1 << 15));
2215 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2217 val
= tr32(GRC_MISC_CFG
);
2218 tw32_f(GRC_MISC_CFG
, val
| GRC_MISC_CFG_EPHY_IDDQ
);
2221 } else if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
2223 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &phytest
)) {
2226 tg3_writephy(tp
, MII_ADVERTISE
, 0);
2227 tg3_writephy(tp
, MII_BMCR
,
2228 BMCR_ANENABLE
| BMCR_ANRESTART
);
2230 tg3_writephy(tp
, MII_TG3_FET_TEST
,
2231 phytest
| MII_TG3_FET_SHADOW_EN
);
2232 if (!tg3_readphy(tp
, MII_TG3_FET_SHDW_AUXMODE4
, &phy
)) {
2233 phy
|= MII_TG3_FET_SHDW_AUXMODE4_SBPD
;
2235 MII_TG3_FET_SHDW_AUXMODE4
,
2238 tg3_writephy(tp
, MII_TG3_FET_TEST
, phytest
);
2241 } else if (do_low_power
) {
2242 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
2243 MII_TG3_EXT_CTRL_FORCE_LED_OFF
);
2245 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
2246 MII_TG3_AUXCTL_SHDWSEL_PWRCTL
|
2247 MII_TG3_AUXCTL_PCTL_100TX_LPWR
|
2248 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE
|
2249 MII_TG3_AUXCTL_PCTL_VREG_11V
);
2252 /* The PHY should not be powered down on some chips because
2255 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2256 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2257 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
&&
2258 (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)))
2261 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
2262 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
2263 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
2264 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
2265 val
|= CPMU_LSPD_1000MB_MACCLK_12_5
;
2266 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
2269 tg3_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
2272 /* tp->lock is held. */
2273 static int tg3_nvram_lock(struct tg3
*tp
)
2275 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
2278 if (tp
->nvram_lock_cnt
== 0) {
2279 tw32(NVRAM_SWARB
, SWARB_REQ_SET1
);
2280 for (i
= 0; i
< 8000; i
++) {
2281 if (tr32(NVRAM_SWARB
) & SWARB_GNT1
)
2286 tw32(NVRAM_SWARB
, SWARB_REQ_CLR1
);
2290 tp
->nvram_lock_cnt
++;
2295 /* tp->lock is held. */
2296 static void tg3_nvram_unlock(struct tg3
*tp
)
2298 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
2299 if (tp
->nvram_lock_cnt
> 0)
2300 tp
->nvram_lock_cnt
--;
2301 if (tp
->nvram_lock_cnt
== 0)
2302 tw32_f(NVRAM_SWARB
, SWARB_REQ_CLR1
);
2306 /* tp->lock is held. */
2307 static void tg3_enable_nvram_access(struct tg3
*tp
)
2309 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2310 !(tp
->tg3_flags3
& TG3_FLG3_PROTECTED_NVRAM
)) {
2311 u32 nvaccess
= tr32(NVRAM_ACCESS
);
2313 tw32(NVRAM_ACCESS
, nvaccess
| ACCESS_ENABLE
);
2317 /* tp->lock is held. */
2318 static void tg3_disable_nvram_access(struct tg3
*tp
)
2320 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2321 !(tp
->tg3_flags3
& TG3_FLG3_PROTECTED_NVRAM
)) {
2322 u32 nvaccess
= tr32(NVRAM_ACCESS
);
2324 tw32(NVRAM_ACCESS
, nvaccess
& ~ACCESS_ENABLE
);
2328 static int tg3_nvram_read_using_eeprom(struct tg3
*tp
,
2329 u32 offset
, u32
*val
)
2334 if (offset
> EEPROM_ADDR_ADDR_MASK
|| (offset
% 4) != 0)
2337 tmp
= tr32(GRC_EEPROM_ADDR
) & ~(EEPROM_ADDR_ADDR_MASK
|
2338 EEPROM_ADDR_DEVID_MASK
|
2340 tw32(GRC_EEPROM_ADDR
,
2342 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
2343 ((offset
<< EEPROM_ADDR_ADDR_SHIFT
) &
2344 EEPROM_ADDR_ADDR_MASK
) |
2345 EEPROM_ADDR_READ
| EEPROM_ADDR_START
);
2347 for (i
= 0; i
< 1000; i
++) {
2348 tmp
= tr32(GRC_EEPROM_ADDR
);
2350 if (tmp
& EEPROM_ADDR_COMPLETE
)
2354 if (!(tmp
& EEPROM_ADDR_COMPLETE
))
2357 tmp
= tr32(GRC_EEPROM_DATA
);
2360 * The data will always be opposite the native endian
2361 * format. Perform a blind byteswap to compensate.
2368 #define NVRAM_CMD_TIMEOUT 10000
2370 static int tg3_nvram_exec_cmd(struct tg3
*tp
, u32 nvram_cmd
)
2374 tw32(NVRAM_CMD
, nvram_cmd
);
2375 for (i
= 0; i
< NVRAM_CMD_TIMEOUT
; i
++) {
2377 if (tr32(NVRAM_CMD
) & NVRAM_CMD_DONE
) {
2383 if (i
== NVRAM_CMD_TIMEOUT
)
2389 static u32
tg3_nvram_phys_addr(struct tg3
*tp
, u32 addr
)
2391 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
2392 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
2393 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
2394 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
2395 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
2397 addr
= ((addr
/ tp
->nvram_pagesize
) <<
2398 ATMEL_AT45DB0X1B_PAGE_POS
) +
2399 (addr
% tp
->nvram_pagesize
);
2404 static u32
tg3_nvram_logical_addr(struct tg3
*tp
, u32 addr
)
2406 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
2407 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
2408 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
2409 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
2410 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
2412 addr
= ((addr
>> ATMEL_AT45DB0X1B_PAGE_POS
) *
2413 tp
->nvram_pagesize
) +
2414 (addr
& ((1 << ATMEL_AT45DB0X1B_PAGE_POS
) - 1));
2419 /* NOTE: Data read in from NVRAM is byteswapped according to
2420 * the byteswapping settings for all other register accesses.
2421 * tg3 devices are BE devices, so on a BE machine, the data
2422 * returned will be exactly as it is seen in NVRAM. On a LE
2423 * machine, the 32-bit value will be byteswapped.
2425 static int tg3_nvram_read(struct tg3
*tp
, u32 offset
, u32
*val
)
2429 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
))
2430 return tg3_nvram_read_using_eeprom(tp
, offset
, val
);
2432 offset
= tg3_nvram_phys_addr(tp
, offset
);
2434 if (offset
> NVRAM_ADDR_MSK
)
2437 ret
= tg3_nvram_lock(tp
);
2441 tg3_enable_nvram_access(tp
);
2443 tw32(NVRAM_ADDR
, offset
);
2444 ret
= tg3_nvram_exec_cmd(tp
, NVRAM_CMD_RD
| NVRAM_CMD_GO
|
2445 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_DONE
);
2448 *val
= tr32(NVRAM_RDDATA
);
2450 tg3_disable_nvram_access(tp
);
2452 tg3_nvram_unlock(tp
);
2457 /* Ensures NVRAM data is in bytestream format. */
2458 static int tg3_nvram_read_be32(struct tg3
*tp
, u32 offset
, __be32
*val
)
2461 int res
= tg3_nvram_read(tp
, offset
, &v
);
2463 *val
= cpu_to_be32(v
);
2467 /* tp->lock is held. */
2468 static void __tg3_set_mac_addr(struct tg3
*tp
, int skip_mac_1
)
2470 u32 addr_high
, addr_low
;
2473 addr_high
= ((tp
->dev
->dev_addr
[0] << 8) |
2474 tp
->dev
->dev_addr
[1]);
2475 addr_low
= ((tp
->dev
->dev_addr
[2] << 24) |
2476 (tp
->dev
->dev_addr
[3] << 16) |
2477 (tp
->dev
->dev_addr
[4] << 8) |
2478 (tp
->dev
->dev_addr
[5] << 0));
2479 for (i
= 0; i
< 4; i
++) {
2480 if (i
== 1 && skip_mac_1
)
2482 tw32(MAC_ADDR_0_HIGH
+ (i
* 8), addr_high
);
2483 tw32(MAC_ADDR_0_LOW
+ (i
* 8), addr_low
);
2486 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
2487 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2488 for (i
= 0; i
< 12; i
++) {
2489 tw32(MAC_EXTADDR_0_HIGH
+ (i
* 8), addr_high
);
2490 tw32(MAC_EXTADDR_0_LOW
+ (i
* 8), addr_low
);
2494 addr_high
= (tp
->dev
->dev_addr
[0] +
2495 tp
->dev
->dev_addr
[1] +
2496 tp
->dev
->dev_addr
[2] +
2497 tp
->dev
->dev_addr
[3] +
2498 tp
->dev
->dev_addr
[4] +
2499 tp
->dev
->dev_addr
[5]) &
2500 TX_BACKOFF_SEED_MASK
;
2501 tw32(MAC_TX_BACKOFF_SEED
, addr_high
);
2504 static int tg3_set_power_state(struct tg3
*tp
, pci_power_t state
)
2507 bool device_should_wake
, do_low_power
;
2509 /* Make sure register accesses (indirect or otherwise)
2510 * will function correctly.
2512 pci_write_config_dword(tp
->pdev
,
2513 TG3PCI_MISC_HOST_CTRL
,
2514 tp
->misc_host_ctrl
);
2518 pci_enable_wake(tp
->pdev
, state
, false);
2519 pci_set_power_state(tp
->pdev
, PCI_D0
);
2521 /* Switch out of Vaux if it is a NIC */
2522 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
2523 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
, 100);
2533 netdev_err(tp
->dev
, "Invalid power state (D%d) requested\n",
2538 /* Restore the CLKREQ setting. */
2539 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
2542 pci_read_config_word(tp
->pdev
,
2543 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2545 lnkctl
|= PCI_EXP_LNKCTL_CLKREQ_EN
;
2546 pci_write_config_word(tp
->pdev
,
2547 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2551 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
2552 tw32(TG3PCI_MISC_HOST_CTRL
,
2553 misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
);
2555 device_should_wake
= pci_pme_capable(tp
->pdev
, state
) &&
2556 device_may_wakeup(&tp
->pdev
->dev
) &&
2557 (tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
2559 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
2560 do_low_power
= false;
2561 if ((tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) &&
2562 !(tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)) {
2563 struct phy_device
*phydev
;
2564 u32 phyid
, advertising
;
2566 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
2568 tp
->phy_flags
|= TG3_PHYFLG_IS_LOW_POWER
;
2570 tp
->link_config
.orig_speed
= phydev
->speed
;
2571 tp
->link_config
.orig_duplex
= phydev
->duplex
;
2572 tp
->link_config
.orig_autoneg
= phydev
->autoneg
;
2573 tp
->link_config
.orig_advertising
= phydev
->advertising
;
2575 advertising
= ADVERTISED_TP
|
2577 ADVERTISED_Autoneg
|
2578 ADVERTISED_10baseT_Half
;
2580 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2581 device_should_wake
) {
2582 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2584 ADVERTISED_100baseT_Half
|
2585 ADVERTISED_100baseT_Full
|
2586 ADVERTISED_10baseT_Full
;
2588 advertising
|= ADVERTISED_10baseT_Full
;
2591 phydev
->advertising
= advertising
;
2593 phy_start_aneg(phydev
);
2595 phyid
= phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
;
2596 if (phyid
!= PHY_ID_BCMAC131
) {
2597 phyid
&= PHY_BCM_OUI_MASK
;
2598 if (phyid
== PHY_BCM_OUI_1
||
2599 phyid
== PHY_BCM_OUI_2
||
2600 phyid
== PHY_BCM_OUI_3
)
2601 do_low_power
= true;
2605 do_low_power
= true;
2607 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)) {
2608 tp
->phy_flags
|= TG3_PHYFLG_IS_LOW_POWER
;
2609 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
2610 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
2611 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
2614 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)) {
2615 tp
->link_config
.speed
= SPEED_10
;
2616 tp
->link_config
.duplex
= DUPLEX_HALF
;
2617 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
2618 tg3_setup_phy(tp
, 0);
2622 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2625 val
= tr32(GRC_VCPU_EXT_CTRL
);
2626 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_DISABLE_WOL
);
2627 } else if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2631 for (i
= 0; i
< 200; i
++) {
2632 tg3_read_mem(tp
, NIC_SRAM_FW_ASF_STATUS_MBOX
, &val
);
2633 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
2638 if (tp
->tg3_flags
& TG3_FLAG_WOL_CAP
)
2639 tg3_write_mem(tp
, NIC_SRAM_WOL_MBOX
, WOL_SIGNATURE
|
2640 WOL_DRV_STATE_SHUTDOWN
|
2644 if (device_should_wake
) {
2647 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)) {
2649 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x5a);
2653 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)
2654 mac_mode
= MAC_MODE_PORT_MODE_GMII
;
2656 mac_mode
= MAC_MODE_PORT_MODE_MII
;
2658 mac_mode
|= tp
->mac_mode
& MAC_MODE_LINK_POLARITY
;
2659 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
2661 u32 speed
= (tp
->tg3_flags
&
2662 TG3_FLAG_WOL_SPEED_100MB
) ?
2663 SPEED_100
: SPEED_10
;
2664 if (tg3_5700_link_polarity(tp
, speed
))
2665 mac_mode
|= MAC_MODE_LINK_POLARITY
;
2667 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
2670 mac_mode
= MAC_MODE_PORT_MODE_TBI
;
2673 if (!(tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
2674 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
2676 mac_mode
|= MAC_MODE_MAGIC_PKT_ENABLE
;
2677 if (((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
2678 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) &&
2679 ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2680 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)))
2681 mac_mode
|= MAC_MODE_KEEP_FRAME_IN_WOL
;
2683 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
2684 mac_mode
|= tp
->mac_mode
&
2685 (MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
);
2686 if (mac_mode
& MAC_MODE_APE_TX_EN
)
2687 mac_mode
|= MAC_MODE_TDE_ENABLE
;
2690 tw32_f(MAC_MODE
, mac_mode
);
2693 tw32_f(MAC_RX_MODE
, RX_MODE_ENABLE
);
2697 if (!(tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
) &&
2698 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2699 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
2702 base_val
= tp
->pci_clock_ctrl
;
2703 base_val
|= (CLOCK_CTRL_RXCLK_DISABLE
|
2704 CLOCK_CTRL_TXCLK_DISABLE
);
2706 tw32_wait_f(TG3PCI_CLOCK_CTRL
, base_val
| CLOCK_CTRL_ALTCLK
|
2707 CLOCK_CTRL_PWRDOWN_PLL133
, 40);
2708 } else if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
2709 (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
2710 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)) {
2712 } else if (!((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2713 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))) {
2714 u32 newbits1
, newbits2
;
2716 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2717 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2718 newbits1
= (CLOCK_CTRL_RXCLK_DISABLE
|
2719 CLOCK_CTRL_TXCLK_DISABLE
|
2721 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2722 } else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
2723 newbits1
= CLOCK_CTRL_625_CORE
;
2724 newbits2
= newbits1
| CLOCK_CTRL_ALTCLK
;
2726 newbits1
= CLOCK_CTRL_ALTCLK
;
2727 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2730 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits1
,
2733 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits2
,
2736 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
2739 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2740 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2741 newbits3
= (CLOCK_CTRL_RXCLK_DISABLE
|
2742 CLOCK_CTRL_TXCLK_DISABLE
|
2743 CLOCK_CTRL_44MHZ_CORE
);
2745 newbits3
= CLOCK_CTRL_44MHZ_CORE
;
2748 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
2749 tp
->pci_clock_ctrl
| newbits3
, 40);
2753 if (!(device_should_wake
) &&
2754 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
2755 tg3_power_down_phy(tp
, do_low_power
);
2757 tg3_frob_aux_power(tp
);
2759 /* Workaround for unstable PLL clock */
2760 if ((GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
) ||
2761 (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
)) {
2762 u32 val
= tr32(0x7d00);
2764 val
&= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2766 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2769 err
= tg3_nvram_lock(tp
);
2770 tg3_halt_cpu(tp
, RX_CPU_BASE
);
2772 tg3_nvram_unlock(tp
);
2776 tg3_write_sig_post_reset(tp
, RESET_KIND_SHUTDOWN
);
2778 if (device_should_wake
)
2779 pci_enable_wake(tp
->pdev
, state
, true);
2781 /* Finally, set the new power state. */
2782 pci_set_power_state(tp
->pdev
, state
);
2787 static void tg3_aux_stat_to_speed_duplex(struct tg3
*tp
, u32 val
, u16
*speed
, u8
*duplex
)
2789 switch (val
& MII_TG3_AUX_STAT_SPDMASK
) {
2790 case MII_TG3_AUX_STAT_10HALF
:
2792 *duplex
= DUPLEX_HALF
;
2795 case MII_TG3_AUX_STAT_10FULL
:
2797 *duplex
= DUPLEX_FULL
;
2800 case MII_TG3_AUX_STAT_100HALF
:
2802 *duplex
= DUPLEX_HALF
;
2805 case MII_TG3_AUX_STAT_100FULL
:
2807 *duplex
= DUPLEX_FULL
;
2810 case MII_TG3_AUX_STAT_1000HALF
:
2811 *speed
= SPEED_1000
;
2812 *duplex
= DUPLEX_HALF
;
2815 case MII_TG3_AUX_STAT_1000FULL
:
2816 *speed
= SPEED_1000
;
2817 *duplex
= DUPLEX_FULL
;
2821 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
2822 *speed
= (val
& MII_TG3_AUX_STAT_100
) ? SPEED_100
:
2824 *duplex
= (val
& MII_TG3_AUX_STAT_FULL
) ? DUPLEX_FULL
:
2828 *speed
= SPEED_INVALID
;
2829 *duplex
= DUPLEX_INVALID
;
2834 static void tg3_phy_copper_begin(struct tg3
*tp
)
2839 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
) {
2840 /* Entering low power mode. Disable gigabit and
2841 * 100baseT advertisements.
2843 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2845 new_adv
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
2846 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
2847 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2848 new_adv
|= (ADVERTISE_100HALF
| ADVERTISE_100FULL
);
2850 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2851 } else if (tp
->link_config
.speed
== SPEED_INVALID
) {
2852 if (tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)
2853 tp
->link_config
.advertising
&=
2854 ~(ADVERTISED_1000baseT_Half
|
2855 ADVERTISED_1000baseT_Full
);
2857 new_adv
= ADVERTISE_CSMA
;
2858 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Half
)
2859 new_adv
|= ADVERTISE_10HALF
;
2860 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Full
)
2861 new_adv
|= ADVERTISE_10FULL
;
2862 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Half
)
2863 new_adv
|= ADVERTISE_100HALF
;
2864 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Full
)
2865 new_adv
|= ADVERTISE_100FULL
;
2867 new_adv
|= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2869 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2871 if (tp
->link_config
.advertising
&
2872 (ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
)) {
2874 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
2875 new_adv
|= MII_TG3_CTRL_ADV_1000_HALF
;
2876 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
2877 new_adv
|= MII_TG3_CTRL_ADV_1000_FULL
;
2878 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
) &&
2879 (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2880 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
))
2881 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2882 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2883 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2885 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2888 new_adv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2889 new_adv
|= ADVERTISE_CSMA
;
2891 /* Asking for a specific link mode. */
2892 if (tp
->link_config
.speed
== SPEED_1000
) {
2893 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2895 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2896 new_adv
= MII_TG3_CTRL_ADV_1000_FULL
;
2898 new_adv
= MII_TG3_CTRL_ADV_1000_HALF
;
2899 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2900 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
2901 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2902 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2904 if (tp
->link_config
.speed
== SPEED_100
) {
2905 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2906 new_adv
|= ADVERTISE_100FULL
;
2908 new_adv
|= ADVERTISE_100HALF
;
2910 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2911 new_adv
|= ADVERTISE_10FULL
;
2913 new_adv
|= ADVERTISE_10HALF
;
2915 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2920 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2923 if (tp
->link_config
.autoneg
== AUTONEG_DISABLE
&&
2924 tp
->link_config
.speed
!= SPEED_INVALID
) {
2925 u32 bmcr
, orig_bmcr
;
2927 tp
->link_config
.active_speed
= tp
->link_config
.speed
;
2928 tp
->link_config
.active_duplex
= tp
->link_config
.duplex
;
2931 switch (tp
->link_config
.speed
) {
2937 bmcr
|= BMCR_SPEED100
;
2941 bmcr
|= TG3_BMCR_SPEED1000
;
2945 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2946 bmcr
|= BMCR_FULLDPLX
;
2948 if (!tg3_readphy(tp
, MII_BMCR
, &orig_bmcr
) &&
2949 (bmcr
!= orig_bmcr
)) {
2950 tg3_writephy(tp
, MII_BMCR
, BMCR_LOOPBACK
);
2951 for (i
= 0; i
< 1500; i
++) {
2955 if (tg3_readphy(tp
, MII_BMSR
, &tmp
) ||
2956 tg3_readphy(tp
, MII_BMSR
, &tmp
))
2958 if (!(tmp
& BMSR_LSTATUS
)) {
2963 tg3_writephy(tp
, MII_BMCR
, bmcr
);
2967 tg3_writephy(tp
, MII_BMCR
,
2968 BMCR_ANENABLE
| BMCR_ANRESTART
);
2972 static int tg3_init_5401phy_dsp(struct tg3
*tp
)
2976 /* Turn off tap power management. */
2977 /* Set Extended packet length bit */
2978 err
= tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
2980 err
|= tg3_phydsp_write(tp
, 0x0012, 0x1804);
2981 err
|= tg3_phydsp_write(tp
, 0x0013, 0x1204);
2982 err
|= tg3_phydsp_write(tp
, 0x8006, 0x0132);
2983 err
|= tg3_phydsp_write(tp
, 0x8006, 0x0232);
2984 err
|= tg3_phydsp_write(tp
, 0x201f, 0x0a20);
2991 static int tg3_copper_is_advertising_all(struct tg3
*tp
, u32 mask
)
2993 u32 adv_reg
, all_mask
= 0;
2995 if (mask
& ADVERTISED_10baseT_Half
)
2996 all_mask
|= ADVERTISE_10HALF
;
2997 if (mask
& ADVERTISED_10baseT_Full
)
2998 all_mask
|= ADVERTISE_10FULL
;
2999 if (mask
& ADVERTISED_100baseT_Half
)
3000 all_mask
|= ADVERTISE_100HALF
;
3001 if (mask
& ADVERTISED_100baseT_Full
)
3002 all_mask
|= ADVERTISE_100FULL
;
3004 if (tg3_readphy(tp
, MII_ADVERTISE
, &adv_reg
))
3007 if ((adv_reg
& all_mask
) != all_mask
)
3009 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
3013 if (mask
& ADVERTISED_1000baseT_Half
)
3014 all_mask
|= ADVERTISE_1000HALF
;
3015 if (mask
& ADVERTISED_1000baseT_Full
)
3016 all_mask
|= ADVERTISE_1000FULL
;
3018 if (tg3_readphy(tp
, MII_TG3_CTRL
, &tg3_ctrl
))
3021 if ((tg3_ctrl
& all_mask
) != all_mask
)
3027 static int tg3_adv_1000T_flowctrl_ok(struct tg3
*tp
, u32
*lcladv
, u32
*rmtadv
)
3031 if (tg3_readphy(tp
, MII_ADVERTISE
, lcladv
))
3034 curadv
= *lcladv
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
3035 reqadv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
3037 if (tp
->link_config
.active_duplex
== DUPLEX_FULL
) {
3038 if (curadv
!= reqadv
)
3041 if (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)
3042 tg3_readphy(tp
, MII_LPA
, rmtadv
);
3044 /* Reprogram the advertisement register, even if it
3045 * does not affect the current link. If the link
3046 * gets renegotiated in the future, we can save an
3047 * additional renegotiation cycle by advertising
3048 * it correctly in the first place.
3050 if (curadv
!= reqadv
) {
3051 *lcladv
&= ~(ADVERTISE_PAUSE_CAP
|
3052 ADVERTISE_PAUSE_ASYM
);
3053 tg3_writephy(tp
, MII_ADVERTISE
, *lcladv
| reqadv
);
3060 static int tg3_setup_copper_phy(struct tg3
*tp
, int force_reset
)
3062 int current_link_up
;
3064 u32 lcl_adv
, rmt_adv
;
3072 (MAC_STATUS_SYNC_CHANGED
|
3073 MAC_STATUS_CFG_CHANGED
|
3074 MAC_STATUS_MI_COMPLETION
|
3075 MAC_STATUS_LNKSTATE_CHANGED
));
3078 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
3080 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
3084 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x02);
3086 /* Some third-party PHYs need to be reset on link going
3089 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
3090 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
3091 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
3092 netif_carrier_ok(tp
->dev
)) {
3093 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3094 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3095 !(bmsr
& BMSR_LSTATUS
))
3101 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
3102 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3103 if (tg3_readphy(tp
, MII_BMSR
, &bmsr
) ||
3104 !(tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
))
3107 if (!(bmsr
& BMSR_LSTATUS
)) {
3108 err
= tg3_init_5401phy_dsp(tp
);
3112 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3113 for (i
= 0; i
< 1000; i
++) {
3115 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3116 (bmsr
& BMSR_LSTATUS
)) {
3122 if ((tp
->phy_id
& TG3_PHY_ID_REV_MASK
) ==
3123 TG3_PHY_REV_BCM5401_B0
&&
3124 !(bmsr
& BMSR_LSTATUS
) &&
3125 tp
->link_config
.active_speed
== SPEED_1000
) {
3126 err
= tg3_phy_reset(tp
);
3128 err
= tg3_init_5401phy_dsp(tp
);
3133 } else if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
3134 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
) {
3135 /* 5701 {A0,B0} CRC bug workaround */
3136 tg3_writephy(tp
, 0x15, 0x0a75);
3137 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8c68);
3138 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8d68);
3139 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8c68);
3142 /* Clear pending interrupts... */
3143 tg3_readphy(tp
, MII_TG3_ISTAT
, &dummy
);
3144 tg3_readphy(tp
, MII_TG3_ISTAT
, &dummy
);
3146 if (tp
->phy_flags
& TG3_PHYFLG_USE_MI_INTERRUPT
)
3147 tg3_writephy(tp
, MII_TG3_IMASK
, ~MII_TG3_INT_LINKCHG
);
3148 else if (!(tp
->phy_flags
& TG3_PHYFLG_IS_FET
))
3149 tg3_writephy(tp
, MII_TG3_IMASK
, ~0);
3151 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
3152 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
3153 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_1
)
3154 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
3155 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
3157 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, 0);
3160 current_link_up
= 0;
3161 current_speed
= SPEED_INVALID
;
3162 current_duplex
= DUPLEX_INVALID
;
3164 if (tp
->phy_flags
& TG3_PHYFLG_CAPACITIVE_COUPLING
) {
3167 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4007);
3168 tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
);
3169 if (!(val
& (1 << 10))) {
3171 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, val
);
3177 for (i
= 0; i
< 100; i
++) {
3178 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3179 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3180 (bmsr
& BMSR_LSTATUS
))
3185 if (bmsr
& BMSR_LSTATUS
) {
3188 tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
);
3189 for (i
= 0; i
< 2000; i
++) {
3191 if (!tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
) &&
3196 tg3_aux_stat_to_speed_duplex(tp
, aux_stat
,
3201 for (i
= 0; i
< 200; i
++) {
3202 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
3203 if (tg3_readphy(tp
, MII_BMCR
, &bmcr
))
3205 if (bmcr
&& bmcr
!= 0x7fff)
3213 tp
->link_config
.active_speed
= current_speed
;
3214 tp
->link_config
.active_duplex
= current_duplex
;
3216 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3217 if ((bmcr
& BMCR_ANENABLE
) &&
3218 tg3_copper_is_advertising_all(tp
,
3219 tp
->link_config
.advertising
)) {
3220 if (tg3_adv_1000T_flowctrl_ok(tp
, &lcl_adv
,
3222 current_link_up
= 1;
3225 if (!(bmcr
& BMCR_ANENABLE
) &&
3226 tp
->link_config
.speed
== current_speed
&&
3227 tp
->link_config
.duplex
== current_duplex
&&
3228 tp
->link_config
.flowctrl
==
3229 tp
->link_config
.active_flowctrl
) {
3230 current_link_up
= 1;
3234 if (current_link_up
== 1 &&
3235 tp
->link_config
.active_duplex
== DUPLEX_FULL
)
3236 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
3240 if (current_link_up
== 0 || (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)) {
3243 tg3_phy_copper_begin(tp
);
3245 tg3_readphy(tp
, MII_BMSR
, &tmp
);
3246 if (!tg3_readphy(tp
, MII_BMSR
, &tmp
) &&
3247 (tmp
& BMSR_LSTATUS
))
3248 current_link_up
= 1;
3251 tp
->mac_mode
&= ~MAC_MODE_PORT_MODE_MASK
;
3252 if (current_link_up
== 1) {
3253 if (tp
->link_config
.active_speed
== SPEED_100
||
3254 tp
->link_config
.active_speed
== SPEED_10
)
3255 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
3257 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3258 } else if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
)
3259 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
3261 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3263 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
3264 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
3265 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
3267 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
3268 if (current_link_up
== 1 &&
3269 tg3_5700_link_polarity(tp
, tp
->link_config
.active_speed
))
3270 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
3272 tp
->mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
3275 /* ??? Without this setting Netgear GA302T PHY does not
3276 * ??? send/receive packets...
3278 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5411
&&
3279 tp
->pci_chip_rev_id
== CHIPREV_ID_5700_ALTIMA
) {
3280 tp
->mi_mode
|= MAC_MI_MODE_AUTO_POLL
;
3281 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
3285 tw32_f(MAC_MODE
, tp
->mac_mode
);
3288 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
3289 /* Polled via timer. */
3290 tw32_f(MAC_EVENT
, 0);
3292 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3296 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
&&
3297 current_link_up
== 1 &&
3298 tp
->link_config
.active_speed
== SPEED_1000
&&
3299 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) ||
3300 (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
))) {
3303 (MAC_STATUS_SYNC_CHANGED
|
3304 MAC_STATUS_CFG_CHANGED
));
3307 NIC_SRAM_FIRMWARE_MBOX
,
3308 NIC_SRAM_FIRMWARE_MBOX_MAGIC2
);
3311 /* Prevent send BD corruption. */
3312 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
3313 u16 oldlnkctl
, newlnkctl
;
3315 pci_read_config_word(tp
->pdev
,
3316 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
3318 if (tp
->link_config
.active_speed
== SPEED_100
||
3319 tp
->link_config
.active_speed
== SPEED_10
)
3320 newlnkctl
= oldlnkctl
& ~PCI_EXP_LNKCTL_CLKREQ_EN
;
3322 newlnkctl
= oldlnkctl
| PCI_EXP_LNKCTL_CLKREQ_EN
;
3323 if (newlnkctl
!= oldlnkctl
)
3324 pci_write_config_word(tp
->pdev
,
3325 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
3329 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
3330 if (current_link_up
)
3331 netif_carrier_on(tp
->dev
);
3333 netif_carrier_off(tp
->dev
);
3334 tg3_link_report(tp
);
3340 struct tg3_fiber_aneginfo
{
3342 #define ANEG_STATE_UNKNOWN 0
3343 #define ANEG_STATE_AN_ENABLE 1
3344 #define ANEG_STATE_RESTART_INIT 2
3345 #define ANEG_STATE_RESTART 3
3346 #define ANEG_STATE_DISABLE_LINK_OK 4
3347 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3348 #define ANEG_STATE_ABILITY_DETECT 6
3349 #define ANEG_STATE_ACK_DETECT_INIT 7
3350 #define ANEG_STATE_ACK_DETECT 8
3351 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3352 #define ANEG_STATE_COMPLETE_ACK 10
3353 #define ANEG_STATE_IDLE_DETECT_INIT 11
3354 #define ANEG_STATE_IDLE_DETECT 12
3355 #define ANEG_STATE_LINK_OK 13
3356 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3357 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3360 #define MR_AN_ENABLE 0x00000001
3361 #define MR_RESTART_AN 0x00000002
3362 #define MR_AN_COMPLETE 0x00000004
3363 #define MR_PAGE_RX 0x00000008
3364 #define MR_NP_LOADED 0x00000010
3365 #define MR_TOGGLE_TX 0x00000020
3366 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3367 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3368 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3369 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3370 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3371 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3372 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3373 #define MR_TOGGLE_RX 0x00002000
3374 #define MR_NP_RX 0x00004000
3376 #define MR_LINK_OK 0x80000000
3378 unsigned long link_time
, cur_time
;
3380 u32 ability_match_cfg
;
3381 int ability_match_count
;
3383 char ability_match
, idle_match
, ack_match
;
3385 u32 txconfig
, rxconfig
;
3386 #define ANEG_CFG_NP 0x00000080
3387 #define ANEG_CFG_ACK 0x00000040
3388 #define ANEG_CFG_RF2 0x00000020
3389 #define ANEG_CFG_RF1 0x00000010
3390 #define ANEG_CFG_PS2 0x00000001
3391 #define ANEG_CFG_PS1 0x00008000
3392 #define ANEG_CFG_HD 0x00004000
3393 #define ANEG_CFG_FD 0x00002000
3394 #define ANEG_CFG_INVAL 0x00001f06
3399 #define ANEG_TIMER_ENAB 2
3400 #define ANEG_FAILED -1
3402 #define ANEG_STATE_SETTLE_TIME 10000
3404 static int tg3_fiber_aneg_smachine(struct tg3
*tp
,
3405 struct tg3_fiber_aneginfo
*ap
)
3408 unsigned long delta
;
3412 if (ap
->state
== ANEG_STATE_UNKNOWN
) {
3416 ap
->ability_match_cfg
= 0;
3417 ap
->ability_match_count
= 0;
3418 ap
->ability_match
= 0;
3424 if (tr32(MAC_STATUS
) & MAC_STATUS_RCVD_CFG
) {
3425 rx_cfg_reg
= tr32(MAC_RX_AUTO_NEG
);
3427 if (rx_cfg_reg
!= ap
->ability_match_cfg
) {
3428 ap
->ability_match_cfg
= rx_cfg_reg
;
3429 ap
->ability_match
= 0;
3430 ap
->ability_match_count
= 0;
3432 if (++ap
->ability_match_count
> 1) {
3433 ap
->ability_match
= 1;
3434 ap
->ability_match_cfg
= rx_cfg_reg
;
3437 if (rx_cfg_reg
& ANEG_CFG_ACK
)
3445 ap
->ability_match_cfg
= 0;
3446 ap
->ability_match_count
= 0;
3447 ap
->ability_match
= 0;
3453 ap
->rxconfig
= rx_cfg_reg
;
3456 switch (ap
->state
) {
3457 case ANEG_STATE_UNKNOWN
:
3458 if (ap
->flags
& (MR_AN_ENABLE
| MR_RESTART_AN
))
3459 ap
->state
= ANEG_STATE_AN_ENABLE
;
3462 case ANEG_STATE_AN_ENABLE
:
3463 ap
->flags
&= ~(MR_AN_COMPLETE
| MR_PAGE_RX
);
3464 if (ap
->flags
& MR_AN_ENABLE
) {
3467 ap
->ability_match_cfg
= 0;
3468 ap
->ability_match_count
= 0;
3469 ap
->ability_match
= 0;
3473 ap
->state
= ANEG_STATE_RESTART_INIT
;
3475 ap
->state
= ANEG_STATE_DISABLE_LINK_OK
;
3479 case ANEG_STATE_RESTART_INIT
:
3480 ap
->link_time
= ap
->cur_time
;
3481 ap
->flags
&= ~(MR_NP_LOADED
);
3483 tw32(MAC_TX_AUTO_NEG
, 0);
3484 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3485 tw32_f(MAC_MODE
, tp
->mac_mode
);
3488 ret
= ANEG_TIMER_ENAB
;
3489 ap
->state
= ANEG_STATE_RESTART
;
3492 case ANEG_STATE_RESTART
:
3493 delta
= ap
->cur_time
- ap
->link_time
;
3494 if (delta
> ANEG_STATE_SETTLE_TIME
)
3495 ap
->state
= ANEG_STATE_ABILITY_DETECT_INIT
;
3497 ret
= ANEG_TIMER_ENAB
;
3500 case ANEG_STATE_DISABLE_LINK_OK
:
3504 case ANEG_STATE_ABILITY_DETECT_INIT
:
3505 ap
->flags
&= ~(MR_TOGGLE_TX
);
3506 ap
->txconfig
= ANEG_CFG_FD
;
3507 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3508 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3509 ap
->txconfig
|= ANEG_CFG_PS1
;
3510 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3511 ap
->txconfig
|= ANEG_CFG_PS2
;
3512 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3513 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3514 tw32_f(MAC_MODE
, tp
->mac_mode
);
3517 ap
->state
= ANEG_STATE_ABILITY_DETECT
;
3520 case ANEG_STATE_ABILITY_DETECT
:
3521 if (ap
->ability_match
!= 0 && ap
->rxconfig
!= 0)
3522 ap
->state
= ANEG_STATE_ACK_DETECT_INIT
;
3525 case ANEG_STATE_ACK_DETECT_INIT
:
3526 ap
->txconfig
|= ANEG_CFG_ACK
;
3527 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3528 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3529 tw32_f(MAC_MODE
, tp
->mac_mode
);
3532 ap
->state
= ANEG_STATE_ACK_DETECT
;
3535 case ANEG_STATE_ACK_DETECT
:
3536 if (ap
->ack_match
!= 0) {
3537 if ((ap
->rxconfig
& ~ANEG_CFG_ACK
) ==
3538 (ap
->ability_match_cfg
& ~ANEG_CFG_ACK
)) {
3539 ap
->state
= ANEG_STATE_COMPLETE_ACK_INIT
;
3541 ap
->state
= ANEG_STATE_AN_ENABLE
;
3543 } else if (ap
->ability_match
!= 0 &&
3544 ap
->rxconfig
== 0) {
3545 ap
->state
= ANEG_STATE_AN_ENABLE
;
3549 case ANEG_STATE_COMPLETE_ACK_INIT
:
3550 if (ap
->rxconfig
& ANEG_CFG_INVAL
) {
3554 ap
->flags
&= ~(MR_LP_ADV_FULL_DUPLEX
|
3555 MR_LP_ADV_HALF_DUPLEX
|
3556 MR_LP_ADV_SYM_PAUSE
|
3557 MR_LP_ADV_ASYM_PAUSE
|
3558 MR_LP_ADV_REMOTE_FAULT1
|
3559 MR_LP_ADV_REMOTE_FAULT2
|
3560 MR_LP_ADV_NEXT_PAGE
|
3563 if (ap
->rxconfig
& ANEG_CFG_FD
)
3564 ap
->flags
|= MR_LP_ADV_FULL_DUPLEX
;
3565 if (ap
->rxconfig
& ANEG_CFG_HD
)
3566 ap
->flags
|= MR_LP_ADV_HALF_DUPLEX
;
3567 if (ap
->rxconfig
& ANEG_CFG_PS1
)
3568 ap
->flags
|= MR_LP_ADV_SYM_PAUSE
;
3569 if (ap
->rxconfig
& ANEG_CFG_PS2
)
3570 ap
->flags
|= MR_LP_ADV_ASYM_PAUSE
;
3571 if (ap
->rxconfig
& ANEG_CFG_RF1
)
3572 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT1
;
3573 if (ap
->rxconfig
& ANEG_CFG_RF2
)
3574 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT2
;
3575 if (ap
->rxconfig
& ANEG_CFG_NP
)
3576 ap
->flags
|= MR_LP_ADV_NEXT_PAGE
;
3578 ap
->link_time
= ap
->cur_time
;
3580 ap
->flags
^= (MR_TOGGLE_TX
);
3581 if (ap
->rxconfig
& 0x0008)
3582 ap
->flags
|= MR_TOGGLE_RX
;
3583 if (ap
->rxconfig
& ANEG_CFG_NP
)
3584 ap
->flags
|= MR_NP_RX
;
3585 ap
->flags
|= MR_PAGE_RX
;
3587 ap
->state
= ANEG_STATE_COMPLETE_ACK
;
3588 ret
= ANEG_TIMER_ENAB
;
3591 case ANEG_STATE_COMPLETE_ACK
:
3592 if (ap
->ability_match
!= 0 &&
3593 ap
->rxconfig
== 0) {
3594 ap
->state
= ANEG_STATE_AN_ENABLE
;
3597 delta
= ap
->cur_time
- ap
->link_time
;
3598 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3599 if (!(ap
->flags
& (MR_LP_ADV_NEXT_PAGE
))) {
3600 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3602 if ((ap
->txconfig
& ANEG_CFG_NP
) == 0 &&
3603 !(ap
->flags
& MR_NP_RX
)) {
3604 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3612 case ANEG_STATE_IDLE_DETECT_INIT
:
3613 ap
->link_time
= ap
->cur_time
;
3614 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3615 tw32_f(MAC_MODE
, tp
->mac_mode
);
3618 ap
->state
= ANEG_STATE_IDLE_DETECT
;
3619 ret
= ANEG_TIMER_ENAB
;
3622 case ANEG_STATE_IDLE_DETECT
:
3623 if (ap
->ability_match
!= 0 &&
3624 ap
->rxconfig
== 0) {
3625 ap
->state
= ANEG_STATE_AN_ENABLE
;
3628 delta
= ap
->cur_time
- ap
->link_time
;
3629 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3630 /* XXX another gem from the Broadcom driver :( */
3631 ap
->state
= ANEG_STATE_LINK_OK
;
3635 case ANEG_STATE_LINK_OK
:
3636 ap
->flags
|= (MR_AN_COMPLETE
| MR_LINK_OK
);
3640 case ANEG_STATE_NEXT_PAGE_WAIT_INIT
:
3641 /* ??? unimplemented */
3644 case ANEG_STATE_NEXT_PAGE_WAIT
:
3645 /* ??? unimplemented */
3656 static int fiber_autoneg(struct tg3
*tp
, u32
*txflags
, u32
*rxflags
)
3659 struct tg3_fiber_aneginfo aninfo
;
3660 int status
= ANEG_FAILED
;
3664 tw32_f(MAC_TX_AUTO_NEG
, 0);
3666 tmp
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
3667 tw32_f(MAC_MODE
, tmp
| MAC_MODE_PORT_MODE_GMII
);
3670 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
);
3673 memset(&aninfo
, 0, sizeof(aninfo
));
3674 aninfo
.flags
|= MR_AN_ENABLE
;
3675 aninfo
.state
= ANEG_STATE_UNKNOWN
;
3676 aninfo
.cur_time
= 0;
3678 while (++tick
< 195000) {
3679 status
= tg3_fiber_aneg_smachine(tp
, &aninfo
);
3680 if (status
== ANEG_DONE
|| status
== ANEG_FAILED
)
3686 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3687 tw32_f(MAC_MODE
, tp
->mac_mode
);
3690 *txflags
= aninfo
.txconfig
;
3691 *rxflags
= aninfo
.flags
;
3693 if (status
== ANEG_DONE
&&
3694 (aninfo
.flags
& (MR_AN_COMPLETE
| MR_LINK_OK
|
3695 MR_LP_ADV_FULL_DUPLEX
)))
3701 static void tg3_init_bcm8002(struct tg3
*tp
)
3703 u32 mac_status
= tr32(MAC_STATUS
);
3706 /* Reset when initting first time or we have a link. */
3707 if ((tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) &&
3708 !(mac_status
& MAC_STATUS_PCS_SYNCED
))
3711 /* Set PLL lock range. */
3712 tg3_writephy(tp
, 0x16, 0x8007);
3715 tg3_writephy(tp
, MII_BMCR
, BMCR_RESET
);
3717 /* Wait for reset to complete. */
3718 /* XXX schedule_timeout() ... */
3719 for (i
= 0; i
< 500; i
++)
3722 /* Config mode; select PMA/Ch 1 regs. */
3723 tg3_writephy(tp
, 0x10, 0x8411);
3725 /* Enable auto-lock and comdet, select txclk for tx. */
3726 tg3_writephy(tp
, 0x11, 0x0a10);
3728 tg3_writephy(tp
, 0x18, 0x00a0);
3729 tg3_writephy(tp
, 0x16, 0x41ff);
3731 /* Assert and deassert POR. */
3732 tg3_writephy(tp
, 0x13, 0x0400);
3734 tg3_writephy(tp
, 0x13, 0x0000);
3736 tg3_writephy(tp
, 0x11, 0x0a50);
3738 tg3_writephy(tp
, 0x11, 0x0a10);
3740 /* Wait for signal to stabilize */
3741 /* XXX schedule_timeout() ... */
3742 for (i
= 0; i
< 15000; i
++)
3745 /* Deselect the channel register so we can read the PHYID
3748 tg3_writephy(tp
, 0x10, 0x8011);
3751 static int tg3_setup_fiber_hw_autoneg(struct tg3
*tp
, u32 mac_status
)
3754 u32 sg_dig_ctrl
, sg_dig_status
;
3755 u32 serdes_cfg
, expected_sg_dig_ctrl
;
3756 int workaround
, port_a
;
3757 int current_link_up
;
3760 expected_sg_dig_ctrl
= 0;
3763 current_link_up
= 0;
3765 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A0
&&
3766 tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A1
) {
3768 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
3771 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3772 /* preserve bits 20-23 for voltage regulator */
3773 serdes_cfg
= tr32(MAC_SERDES_CFG
) & 0x00f06fff;
3776 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
3778 if (tp
->link_config
.autoneg
!= AUTONEG_ENABLE
) {
3779 if (sg_dig_ctrl
& SG_DIG_USING_HW_AUTONEG
) {
3781 u32 val
= serdes_cfg
;
3787 tw32_f(MAC_SERDES_CFG
, val
);
3790 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3792 if (mac_status
& MAC_STATUS_PCS_SYNCED
) {
3793 tg3_setup_flow_control(tp
, 0, 0);
3794 current_link_up
= 1;
3799 /* Want auto-negotiation. */
3800 expected_sg_dig_ctrl
= SG_DIG_USING_HW_AUTONEG
| SG_DIG_COMMON_SETUP
;
3802 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3803 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3804 expected_sg_dig_ctrl
|= SG_DIG_PAUSE_CAP
;
3805 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3806 expected_sg_dig_ctrl
|= SG_DIG_ASYM_PAUSE
;
3808 if (sg_dig_ctrl
!= expected_sg_dig_ctrl
) {
3809 if ((tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
) &&
3810 tp
->serdes_counter
&&
3811 ((mac_status
& (MAC_STATUS_PCS_SYNCED
|
3812 MAC_STATUS_RCVD_CFG
)) ==
3813 MAC_STATUS_PCS_SYNCED
)) {
3814 tp
->serdes_counter
--;
3815 current_link_up
= 1;
3820 tw32_f(MAC_SERDES_CFG
, serdes_cfg
| 0xc011000);
3821 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
| SG_DIG_SOFT_RESET
);
3823 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
);
3825 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3826 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
3827 } else if (mac_status
& (MAC_STATUS_PCS_SYNCED
|
3828 MAC_STATUS_SIGNAL_DET
)) {
3829 sg_dig_status
= tr32(SG_DIG_STATUS
);
3830 mac_status
= tr32(MAC_STATUS
);
3832 if ((sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
) &&
3833 (mac_status
& MAC_STATUS_PCS_SYNCED
)) {
3834 u32 local_adv
= 0, remote_adv
= 0;
3836 if (sg_dig_ctrl
& SG_DIG_PAUSE_CAP
)
3837 local_adv
|= ADVERTISE_1000XPAUSE
;
3838 if (sg_dig_ctrl
& SG_DIG_ASYM_PAUSE
)
3839 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
3841 if (sg_dig_status
& SG_DIG_PARTNER_PAUSE_CAPABLE
)
3842 remote_adv
|= LPA_1000XPAUSE
;
3843 if (sg_dig_status
& SG_DIG_PARTNER_ASYM_PAUSE
)
3844 remote_adv
|= LPA_1000XPAUSE_ASYM
;
3846 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3847 current_link_up
= 1;
3848 tp
->serdes_counter
= 0;
3849 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
3850 } else if (!(sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
)) {
3851 if (tp
->serdes_counter
)
3852 tp
->serdes_counter
--;
3855 u32 val
= serdes_cfg
;
3862 tw32_f(MAC_SERDES_CFG
, val
);
3865 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3868 /* Link parallel detection - link is up */
3869 /* only if we have PCS_SYNC and not */
3870 /* receiving config code words */
3871 mac_status
= tr32(MAC_STATUS
);
3872 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) &&
3873 !(mac_status
& MAC_STATUS_RCVD_CFG
)) {
3874 tg3_setup_flow_control(tp
, 0, 0);
3875 current_link_up
= 1;
3877 TG3_PHYFLG_PARALLEL_DETECT
;
3878 tp
->serdes_counter
=
3879 SERDES_PARALLEL_DET_TIMEOUT
;
3881 goto restart_autoneg
;
3885 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3886 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
3890 return current_link_up
;
3893 static int tg3_setup_fiber_by_hand(struct tg3
*tp
, u32 mac_status
)
3895 int current_link_up
= 0;
3897 if (!(mac_status
& MAC_STATUS_PCS_SYNCED
))
3900 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3901 u32 txflags
, rxflags
;
3904 if (fiber_autoneg(tp
, &txflags
, &rxflags
)) {
3905 u32 local_adv
= 0, remote_adv
= 0;
3907 if (txflags
& ANEG_CFG_PS1
)
3908 local_adv
|= ADVERTISE_1000XPAUSE
;
3909 if (txflags
& ANEG_CFG_PS2
)
3910 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
3912 if (rxflags
& MR_LP_ADV_SYM_PAUSE
)
3913 remote_adv
|= LPA_1000XPAUSE
;
3914 if (rxflags
& MR_LP_ADV_ASYM_PAUSE
)
3915 remote_adv
|= LPA_1000XPAUSE_ASYM
;
3917 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3919 current_link_up
= 1;
3921 for (i
= 0; i
< 30; i
++) {
3924 (MAC_STATUS_SYNC_CHANGED
|
3925 MAC_STATUS_CFG_CHANGED
));
3927 if ((tr32(MAC_STATUS
) &
3928 (MAC_STATUS_SYNC_CHANGED
|
3929 MAC_STATUS_CFG_CHANGED
)) == 0)
3933 mac_status
= tr32(MAC_STATUS
);
3934 if (current_link_up
== 0 &&
3935 (mac_status
& MAC_STATUS_PCS_SYNCED
) &&
3936 !(mac_status
& MAC_STATUS_RCVD_CFG
))
3937 current_link_up
= 1;
3939 tg3_setup_flow_control(tp
, 0, 0);
3941 /* Forcing 1000FD link up. */
3942 current_link_up
= 1;
3944 tw32_f(MAC_MODE
, (tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
));
3947 tw32_f(MAC_MODE
, tp
->mac_mode
);
3952 return current_link_up
;
3955 static int tg3_setup_fiber_phy(struct tg3
*tp
, int force_reset
)
3958 u16 orig_active_speed
;
3959 u8 orig_active_duplex
;
3961 int current_link_up
;
3964 orig_pause_cfg
= tp
->link_config
.active_flowctrl
;
3965 orig_active_speed
= tp
->link_config
.active_speed
;
3966 orig_active_duplex
= tp
->link_config
.active_duplex
;
3968 if (!(tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
) &&
3969 netif_carrier_ok(tp
->dev
) &&
3970 (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)) {
3971 mac_status
= tr32(MAC_STATUS
);
3972 mac_status
&= (MAC_STATUS_PCS_SYNCED
|
3973 MAC_STATUS_SIGNAL_DET
|
3974 MAC_STATUS_CFG_CHANGED
|
3975 MAC_STATUS_RCVD_CFG
);
3976 if (mac_status
== (MAC_STATUS_PCS_SYNCED
|
3977 MAC_STATUS_SIGNAL_DET
)) {
3978 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
3979 MAC_STATUS_CFG_CHANGED
));
3984 tw32_f(MAC_TX_AUTO_NEG
, 0);
3986 tp
->mac_mode
&= ~(MAC_MODE_PORT_MODE_MASK
| MAC_MODE_HALF_DUPLEX
);
3987 tp
->mac_mode
|= MAC_MODE_PORT_MODE_TBI
;
3988 tw32_f(MAC_MODE
, tp
->mac_mode
);
3991 if (tp
->phy_id
== TG3_PHY_ID_BCM8002
)
3992 tg3_init_bcm8002(tp
);
3994 /* Enable link change event even when serdes polling. */
3995 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3998 current_link_up
= 0;
3999 mac_status
= tr32(MAC_STATUS
);
4001 if (tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
)
4002 current_link_up
= tg3_setup_fiber_hw_autoneg(tp
, mac_status
);
4004 current_link_up
= tg3_setup_fiber_by_hand(tp
, mac_status
);
4006 tp
->napi
[0].hw_status
->status
=
4007 (SD_STATUS_UPDATED
|
4008 (tp
->napi
[0].hw_status
->status
& ~SD_STATUS_LINK_CHG
));
4010 for (i
= 0; i
< 100; i
++) {
4011 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
4012 MAC_STATUS_CFG_CHANGED
));
4014 if ((tr32(MAC_STATUS
) & (MAC_STATUS_SYNC_CHANGED
|
4015 MAC_STATUS_CFG_CHANGED
|
4016 MAC_STATUS_LNKSTATE_CHANGED
)) == 0)
4020 mac_status
= tr32(MAC_STATUS
);
4021 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) == 0) {
4022 current_link_up
= 0;
4023 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
&&
4024 tp
->serdes_counter
== 0) {
4025 tw32_f(MAC_MODE
, (tp
->mac_mode
|
4026 MAC_MODE_SEND_CONFIGS
));
4028 tw32_f(MAC_MODE
, tp
->mac_mode
);
4032 if (current_link_up
== 1) {
4033 tp
->link_config
.active_speed
= SPEED_1000
;
4034 tp
->link_config
.active_duplex
= DUPLEX_FULL
;
4035 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
4036 LED_CTRL_LNKLED_OVERRIDE
|
4037 LED_CTRL_1000MBPS_ON
));
4039 tp
->link_config
.active_speed
= SPEED_INVALID
;
4040 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
4041 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
4042 LED_CTRL_LNKLED_OVERRIDE
|
4043 LED_CTRL_TRAFFIC_OVERRIDE
));
4046 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
4047 if (current_link_up
)
4048 netif_carrier_on(tp
->dev
);
4050 netif_carrier_off(tp
->dev
);
4051 tg3_link_report(tp
);
4053 u32 now_pause_cfg
= tp
->link_config
.active_flowctrl
;
4054 if (orig_pause_cfg
!= now_pause_cfg
||
4055 orig_active_speed
!= tp
->link_config
.active_speed
||
4056 orig_active_duplex
!= tp
->link_config
.active_duplex
)
4057 tg3_link_report(tp
);
4063 static int tg3_setup_fiber_mii_phy(struct tg3
*tp
, int force_reset
)
4065 int current_link_up
, err
= 0;
4069 u32 local_adv
, remote_adv
;
4071 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
4072 tw32_f(MAC_MODE
, tp
->mac_mode
);
4078 (MAC_STATUS_SYNC_CHANGED
|
4079 MAC_STATUS_CFG_CHANGED
|
4080 MAC_STATUS_MI_COMPLETION
|
4081 MAC_STATUS_LNKSTATE_CHANGED
));
4087 current_link_up
= 0;
4088 current_speed
= SPEED_INVALID
;
4089 current_duplex
= DUPLEX_INVALID
;
4091 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4092 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4093 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
4094 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
4095 bmsr
|= BMSR_LSTATUS
;
4097 bmsr
&= ~BMSR_LSTATUS
;
4100 err
|= tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4102 if ((tp
->link_config
.autoneg
== AUTONEG_ENABLE
) && !force_reset
&&
4103 (tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
)) {
4104 /* do nothing, just check for link up at the end */
4105 } else if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
4108 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
4109 new_adv
= adv
& ~(ADVERTISE_1000XFULL
| ADVERTISE_1000XHALF
|
4110 ADVERTISE_1000XPAUSE
|
4111 ADVERTISE_1000XPSE_ASYM
|
4114 new_adv
|= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
4116 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
4117 new_adv
|= ADVERTISE_1000XHALF
;
4118 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
4119 new_adv
|= ADVERTISE_1000XFULL
;
4121 if ((new_adv
!= adv
) || !(bmcr
& BMCR_ANENABLE
)) {
4122 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
4123 bmcr
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
4124 tg3_writephy(tp
, MII_BMCR
, bmcr
);
4126 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4127 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5714S
;
4128 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
4135 bmcr
&= ~BMCR_SPEED1000
;
4136 new_bmcr
= bmcr
& ~(BMCR_ANENABLE
| BMCR_FULLDPLX
);
4138 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
4139 new_bmcr
|= BMCR_FULLDPLX
;
4141 if (new_bmcr
!= bmcr
) {
4142 /* BMCR_SPEED1000 is a reserved bit that needs
4143 * to be set on write.
4145 new_bmcr
|= BMCR_SPEED1000
;
4147 /* Force a linkdown */
4148 if (netif_carrier_ok(tp
->dev
)) {
4151 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
4152 adv
&= ~(ADVERTISE_1000XFULL
|
4153 ADVERTISE_1000XHALF
|
4155 tg3_writephy(tp
, MII_ADVERTISE
, adv
);
4156 tg3_writephy(tp
, MII_BMCR
, bmcr
|
4160 netif_carrier_off(tp
->dev
);
4162 tg3_writephy(tp
, MII_BMCR
, new_bmcr
);
4164 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4165 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4166 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
4168 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
4169 bmsr
|= BMSR_LSTATUS
;
4171 bmsr
&= ~BMSR_LSTATUS
;
4173 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
4177 if (bmsr
& BMSR_LSTATUS
) {
4178 current_speed
= SPEED_1000
;
4179 current_link_up
= 1;
4180 if (bmcr
& BMCR_FULLDPLX
)
4181 current_duplex
= DUPLEX_FULL
;
4183 current_duplex
= DUPLEX_HALF
;
4188 if (bmcr
& BMCR_ANENABLE
) {
4191 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &local_adv
);
4192 err
|= tg3_readphy(tp
, MII_LPA
, &remote_adv
);
4193 common
= local_adv
& remote_adv
;
4194 if (common
& (ADVERTISE_1000XHALF
|
4195 ADVERTISE_1000XFULL
)) {
4196 if (common
& ADVERTISE_1000XFULL
)
4197 current_duplex
= DUPLEX_FULL
;
4199 current_duplex
= DUPLEX_HALF
;
4200 } else if (!(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
4201 /* Link is up via parallel detect */
4203 current_link_up
= 0;
4208 if (current_link_up
== 1 && current_duplex
== DUPLEX_FULL
)
4209 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
4211 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
4212 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4213 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
4215 tw32_f(MAC_MODE
, tp
->mac_mode
);
4218 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4220 tp
->link_config
.active_speed
= current_speed
;
4221 tp
->link_config
.active_duplex
= current_duplex
;
4223 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
4224 if (current_link_up
)
4225 netif_carrier_on(tp
->dev
);
4227 netif_carrier_off(tp
->dev
);
4228 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
4230 tg3_link_report(tp
);
4235 static void tg3_serdes_parallel_detect(struct tg3
*tp
)
4237 if (tp
->serdes_counter
) {
4238 /* Give autoneg time to complete. */
4239 tp
->serdes_counter
--;
4243 if (!netif_carrier_ok(tp
->dev
) &&
4244 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
)) {
4247 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4248 if (bmcr
& BMCR_ANENABLE
) {
4251 /* Select shadow register 0x1f */
4252 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x7c00);
4253 tg3_readphy(tp
, MII_TG3_MISC_SHDW
, &phy1
);
4255 /* Select expansion interrupt status register */
4256 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
4257 MII_TG3_DSP_EXP1_INT_STAT
);
4258 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &phy2
);
4259 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &phy2
);
4261 if ((phy1
& 0x10) && !(phy2
& 0x20)) {
4262 /* We have signal detect and not receiving
4263 * config code words, link is up by parallel
4267 bmcr
&= ~BMCR_ANENABLE
;
4268 bmcr
|= BMCR_SPEED1000
| BMCR_FULLDPLX
;
4269 tg3_writephy(tp
, MII_BMCR
, bmcr
);
4270 tp
->phy_flags
|= TG3_PHYFLG_PARALLEL_DETECT
;
4273 } else if (netif_carrier_ok(tp
->dev
) &&
4274 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) &&
4275 (tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
)) {
4278 /* Select expansion interrupt status register */
4279 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
4280 MII_TG3_DSP_EXP1_INT_STAT
);
4281 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &phy2
);
4285 /* Config code words received, turn on autoneg. */
4286 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4287 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANENABLE
);
4289 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
4295 static int tg3_setup_phy(struct tg3
*tp
, int force_reset
)
4299 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
4300 err
= tg3_setup_fiber_phy(tp
, force_reset
);
4301 else if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)
4302 err
= tg3_setup_fiber_mii_phy(tp
, force_reset
);
4304 err
= tg3_setup_copper_phy(tp
, force_reset
);
4306 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
4309 val
= tr32(TG3_CPMU_CLCK_STAT
) & CPMU_CLCK_STAT_MAC_CLCK_MASK
;
4310 if (val
== CPMU_CLCK_STAT_MAC_CLCK_62_5
)
4312 else if (val
== CPMU_CLCK_STAT_MAC_CLCK_6_25
)
4317 val
= tr32(GRC_MISC_CFG
) & ~GRC_MISC_CFG_PRESCALAR_MASK
;
4318 val
|= (scale
<< GRC_MISC_CFG_PRESCALAR_SHIFT
);
4319 tw32(GRC_MISC_CFG
, val
);
4322 if (tp
->link_config
.active_speed
== SPEED_1000
&&
4323 tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4324 tw32(MAC_TX_LENGTHS
,
4325 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
4326 (6 << TX_LENGTHS_IPG_SHIFT
) |
4327 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
4329 tw32(MAC_TX_LENGTHS
,
4330 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
4331 (6 << TX_LENGTHS_IPG_SHIFT
) |
4332 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
4334 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
4335 if (netif_carrier_ok(tp
->dev
)) {
4336 tw32(HOSTCC_STAT_COAL_TICKS
,
4337 tp
->coal
.stats_block_coalesce_usecs
);
4339 tw32(HOSTCC_STAT_COAL_TICKS
, 0);
4343 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
) {
4344 u32 val
= tr32(PCIE_PWR_MGMT_THRESH
);
4345 if (!netif_carrier_ok(tp
->dev
))
4346 val
= (val
& ~PCIE_PWR_MGMT_L1_THRESH_MSK
) |
4349 val
|= PCIE_PWR_MGMT_L1_THRESH_MSK
;
4350 tw32(PCIE_PWR_MGMT_THRESH
, val
);
4356 /* This is called whenever we suspect that the system chipset is re-
4357 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4358 * is bogus tx completions. We try to recover by setting the
4359 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4362 static void tg3_tx_recover(struct tg3
*tp
)
4364 BUG_ON((tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) ||
4365 tp
->write32_tx_mbox
== tg3_write_indirect_mbox
);
4367 netdev_warn(tp
->dev
,
4368 "The system may be re-ordering memory-mapped I/O "
4369 "cycles to the network device, attempting to recover. "
4370 "Please report the problem to the driver maintainer "
4371 "and include system chipset information.\n");
4373 spin_lock(&tp
->lock
);
4374 tp
->tg3_flags
|= TG3_FLAG_TX_RECOVERY_PENDING
;
4375 spin_unlock(&tp
->lock
);
4378 static inline u32
tg3_tx_avail(struct tg3_napi
*tnapi
)
4380 /* Tell compiler to fetch tx indices from memory. */
4382 return tnapi
->tx_pending
-
4383 ((tnapi
->tx_prod
- tnapi
->tx_cons
) & (TG3_TX_RING_SIZE
- 1));
4386 /* Tigon3 never reports partial packet sends. So we do not
4387 * need special logic to handle SKBs that have not had all
4388 * of their frags sent yet, like SunGEM does.
4390 static void tg3_tx(struct tg3_napi
*tnapi
)
4392 struct tg3
*tp
= tnapi
->tp
;
4393 u32 hw_idx
= tnapi
->hw_status
->idx
[0].tx_consumer
;
4394 u32 sw_idx
= tnapi
->tx_cons
;
4395 struct netdev_queue
*txq
;
4396 int index
= tnapi
- tp
->napi
;
4398 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
4401 txq
= netdev_get_tx_queue(tp
->dev
, index
);
4403 while (sw_idx
!= hw_idx
) {
4404 struct ring_info
*ri
= &tnapi
->tx_buffers
[sw_idx
];
4405 struct sk_buff
*skb
= ri
->skb
;
4408 if (unlikely(skb
== NULL
)) {
4413 pci_unmap_single(tp
->pdev
,
4414 dma_unmap_addr(ri
, mapping
),
4420 sw_idx
= NEXT_TX(sw_idx
);
4422 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
4423 ri
= &tnapi
->tx_buffers
[sw_idx
];
4424 if (unlikely(ri
->skb
!= NULL
|| sw_idx
== hw_idx
))
4427 pci_unmap_page(tp
->pdev
,
4428 dma_unmap_addr(ri
, mapping
),
4429 skb_shinfo(skb
)->frags
[i
].size
,
4431 sw_idx
= NEXT_TX(sw_idx
);
4436 if (unlikely(tx_bug
)) {
4442 tnapi
->tx_cons
= sw_idx
;
4444 /* Need to make the tx_cons update visible to tg3_start_xmit()
4445 * before checking for netif_queue_stopped(). Without the
4446 * memory barrier, there is a small possibility that tg3_start_xmit()
4447 * will miss it and cause the queue to be stopped forever.
4451 if (unlikely(netif_tx_queue_stopped(txq
) &&
4452 (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
)))) {
4453 __netif_tx_lock(txq
, smp_processor_id());
4454 if (netif_tx_queue_stopped(txq
) &&
4455 (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
)))
4456 netif_tx_wake_queue(txq
);
4457 __netif_tx_unlock(txq
);
4461 static void tg3_rx_skb_free(struct tg3
*tp
, struct ring_info
*ri
, u32 map_sz
)
4466 pci_unmap_single(tp
->pdev
, dma_unmap_addr(ri
, mapping
),
4467 map_sz
, PCI_DMA_FROMDEVICE
);
4468 dev_kfree_skb_any(ri
->skb
);
4472 /* Returns size of skb allocated or < 0 on error.
4474 * We only need to fill in the address because the other members
4475 * of the RX descriptor are invariant, see tg3_init_rings.
4477 * Note the purposeful assymetry of cpu vs. chip accesses. For
4478 * posting buffers we only dirty the first cache line of the RX
4479 * descriptor (containing the address). Whereas for the RX status
4480 * buffers the cpu only reads the last cacheline of the RX descriptor
4481 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4483 static int tg3_alloc_rx_skb(struct tg3
*tp
, struct tg3_rx_prodring_set
*tpr
,
4484 u32 opaque_key
, u32 dest_idx_unmasked
)
4486 struct tg3_rx_buffer_desc
*desc
;
4487 struct ring_info
*map
, *src_map
;
4488 struct sk_buff
*skb
;
4490 int skb_size
, dest_idx
;
4493 switch (opaque_key
) {
4494 case RXD_OPAQUE_RING_STD
:
4495 dest_idx
= dest_idx_unmasked
% TG3_RX_RING_SIZE
;
4496 desc
= &tpr
->rx_std
[dest_idx
];
4497 map
= &tpr
->rx_std_buffers
[dest_idx
];
4498 skb_size
= tp
->rx_pkt_map_sz
;
4501 case RXD_OPAQUE_RING_JUMBO
:
4502 dest_idx
= dest_idx_unmasked
% TG3_RX_JUMBO_RING_SIZE
;
4503 desc
= &tpr
->rx_jmb
[dest_idx
].std
;
4504 map
= &tpr
->rx_jmb_buffers
[dest_idx
];
4505 skb_size
= TG3_RX_JMB_MAP_SZ
;
4512 /* Do not overwrite any of the map or rp information
4513 * until we are sure we can commit to a new buffer.
4515 * Callers depend upon this behavior and assume that
4516 * we leave everything unchanged if we fail.
4518 skb
= netdev_alloc_skb(tp
->dev
, skb_size
+ tp
->rx_offset
);
4522 skb_reserve(skb
, tp
->rx_offset
);
4524 mapping
= pci_map_single(tp
->pdev
, skb
->data
, skb_size
,
4525 PCI_DMA_FROMDEVICE
);
4526 if (pci_dma_mapping_error(tp
->pdev
, mapping
)) {
4532 dma_unmap_addr_set(map
, mapping
, mapping
);
4534 desc
->addr_hi
= ((u64
)mapping
>> 32);
4535 desc
->addr_lo
= ((u64
)mapping
& 0xffffffff);
4540 /* We only need to move over in the address because the other
4541 * members of the RX descriptor are invariant. See notes above
4542 * tg3_alloc_rx_skb for full details.
4544 static void tg3_recycle_rx(struct tg3_napi
*tnapi
,
4545 struct tg3_rx_prodring_set
*dpr
,
4546 u32 opaque_key
, int src_idx
,
4547 u32 dest_idx_unmasked
)
4549 struct tg3
*tp
= tnapi
->tp
;
4550 struct tg3_rx_buffer_desc
*src_desc
, *dest_desc
;
4551 struct ring_info
*src_map
, *dest_map
;
4552 struct tg3_rx_prodring_set
*spr
= &tp
->prodring
[0];
4555 switch (opaque_key
) {
4556 case RXD_OPAQUE_RING_STD
:
4557 dest_idx
= dest_idx_unmasked
% TG3_RX_RING_SIZE
;
4558 dest_desc
= &dpr
->rx_std
[dest_idx
];
4559 dest_map
= &dpr
->rx_std_buffers
[dest_idx
];
4560 src_desc
= &spr
->rx_std
[src_idx
];
4561 src_map
= &spr
->rx_std_buffers
[src_idx
];
4564 case RXD_OPAQUE_RING_JUMBO
:
4565 dest_idx
= dest_idx_unmasked
% TG3_RX_JUMBO_RING_SIZE
;
4566 dest_desc
= &dpr
->rx_jmb
[dest_idx
].std
;
4567 dest_map
= &dpr
->rx_jmb_buffers
[dest_idx
];
4568 src_desc
= &spr
->rx_jmb
[src_idx
].std
;
4569 src_map
= &spr
->rx_jmb_buffers
[src_idx
];
4576 dest_map
->skb
= src_map
->skb
;
4577 dma_unmap_addr_set(dest_map
, mapping
,
4578 dma_unmap_addr(src_map
, mapping
));
4579 dest_desc
->addr_hi
= src_desc
->addr_hi
;
4580 dest_desc
->addr_lo
= src_desc
->addr_lo
;
4582 /* Ensure that the update to the skb happens after the physical
4583 * addresses have been transferred to the new BD location.
4587 src_map
->skb
= NULL
;
4590 /* The RX ring scheme is composed of multiple rings which post fresh
4591 * buffers to the chip, and one special ring the chip uses to report
4592 * status back to the host.
4594 * The special ring reports the status of received packets to the
4595 * host. The chip does not write into the original descriptor the
4596 * RX buffer was obtained from. The chip simply takes the original
4597 * descriptor as provided by the host, updates the status and length
4598 * field, then writes this into the next status ring entry.
4600 * Each ring the host uses to post buffers to the chip is described
4601 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4602 * it is first placed into the on-chip ram. When the packet's length
4603 * is known, it walks down the TG3_BDINFO entries to select the ring.
4604 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4605 * which is within the range of the new packet's length is chosen.
4607 * The "separate ring for rx status" scheme may sound queer, but it makes
4608 * sense from a cache coherency perspective. If only the host writes
4609 * to the buffer post rings, and only the chip writes to the rx status
4610 * rings, then cache lines never move beyond shared-modified state.
4611 * If both the host and chip were to write into the same ring, cache line
4612 * eviction could occur since both entities want it in an exclusive state.
4614 static int tg3_rx(struct tg3_napi
*tnapi
, int budget
)
4616 struct tg3
*tp
= tnapi
->tp
;
4617 u32 work_mask
, rx_std_posted
= 0;
4618 u32 std_prod_idx
, jmb_prod_idx
;
4619 u32 sw_idx
= tnapi
->rx_rcb_ptr
;
4622 struct tg3_rx_prodring_set
*tpr
= tnapi
->prodring
;
4624 hw_idx
= *(tnapi
->rx_rcb_prod_idx
);
4626 * We need to order the read of hw_idx and the read of
4627 * the opaque cookie.
4632 std_prod_idx
= tpr
->rx_std_prod_idx
;
4633 jmb_prod_idx
= tpr
->rx_jmb_prod_idx
;
4634 while (sw_idx
!= hw_idx
&& budget
> 0) {
4635 struct ring_info
*ri
;
4636 struct tg3_rx_buffer_desc
*desc
= &tnapi
->rx_rcb
[sw_idx
];
4638 struct sk_buff
*skb
;
4639 dma_addr_t dma_addr
;
4640 u32 opaque_key
, desc_idx
, *post_ptr
;
4641 bool hw_vlan __maybe_unused
= false;
4642 u16 vtag __maybe_unused
= 0;
4644 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
4645 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
4646 if (opaque_key
== RXD_OPAQUE_RING_STD
) {
4647 ri
= &tp
->prodring
[0].rx_std_buffers
[desc_idx
];
4648 dma_addr
= dma_unmap_addr(ri
, mapping
);
4650 post_ptr
= &std_prod_idx
;
4652 } else if (opaque_key
== RXD_OPAQUE_RING_JUMBO
) {
4653 ri
= &tp
->prodring
[0].rx_jmb_buffers
[desc_idx
];
4654 dma_addr
= dma_unmap_addr(ri
, mapping
);
4656 post_ptr
= &jmb_prod_idx
;
4658 goto next_pkt_nopost
;
4660 work_mask
|= opaque_key
;
4662 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
4663 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
)) {
4665 tg3_recycle_rx(tnapi
, tpr
, opaque_key
,
4666 desc_idx
, *post_ptr
);
4668 /* Other statistics kept track of by card. */
4669 tp
->net_stats
.rx_dropped
++;
4673 len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) -
4676 if (len
> TG3_RX_COPY_THRESH(tp
)) {
4679 skb_size
= tg3_alloc_rx_skb(tp
, tpr
, opaque_key
,
4684 pci_unmap_single(tp
->pdev
, dma_addr
, skb_size
,
4685 PCI_DMA_FROMDEVICE
);
4687 /* Ensure that the update to the skb happens
4688 * after the usage of the old DMA mapping.
4696 struct sk_buff
*copy_skb
;
4698 tg3_recycle_rx(tnapi
, tpr
, opaque_key
,
4699 desc_idx
, *post_ptr
);
4701 copy_skb
= netdev_alloc_skb(tp
->dev
, len
+ VLAN_HLEN
+
4703 if (copy_skb
== NULL
)
4704 goto drop_it_no_recycle
;
4706 skb_reserve(copy_skb
, TG3_RAW_IP_ALIGN
+ VLAN_HLEN
);
4707 skb_put(copy_skb
, len
);
4708 pci_dma_sync_single_for_cpu(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4709 skb_copy_from_linear_data(skb
, copy_skb
->data
, len
);
4710 pci_dma_sync_single_for_device(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4712 /* We'll reuse the original ring buffer. */
4716 if ((tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) &&
4717 (desc
->type_flags
& RXD_FLAG_TCPUDP_CSUM
) &&
4718 (((desc
->ip_tcp_csum
& RXD_TCPCSUM_MASK
)
4719 >> RXD_TCPCSUM_SHIFT
) == 0xffff))
4720 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4722 skb
->ip_summed
= CHECKSUM_NONE
;
4724 skb
->protocol
= eth_type_trans(skb
, tp
->dev
);
4726 if (len
> (tp
->dev
->mtu
+ ETH_HLEN
) &&
4727 skb
->protocol
!= htons(ETH_P_8021Q
)) {
4732 if (desc
->type_flags
& RXD_FLAG_VLAN
&&
4733 !(tp
->rx_mode
& RX_MODE_KEEP_VLAN_TAG
)) {
4734 vtag
= desc
->err_vlan
& RXD_VLAN_MASK
;
4735 #if TG3_VLAN_TAG_USED
4741 struct vlan_ethhdr
*ve
= (struct vlan_ethhdr
*)
4742 __skb_push(skb
, VLAN_HLEN
);
4744 memmove(ve
, skb
->data
+ VLAN_HLEN
,
4746 ve
->h_vlan_proto
= htons(ETH_P_8021Q
);
4747 ve
->h_vlan_TCI
= htons(vtag
);
4751 #if TG3_VLAN_TAG_USED
4753 vlan_gro_receive(&tnapi
->napi
, tp
->vlgrp
, vtag
, skb
);
4756 napi_gro_receive(&tnapi
->napi
, skb
);
4764 if (unlikely(rx_std_posted
>= tp
->rx_std_max_post
)) {
4765 tpr
->rx_std_prod_idx
= std_prod_idx
% TG3_RX_RING_SIZE
;
4766 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
4767 tpr
->rx_std_prod_idx
);
4768 work_mask
&= ~RXD_OPAQUE_RING_STD
;
4773 sw_idx
&= (TG3_RX_RCB_RING_SIZE(tp
) - 1);
4775 /* Refresh hw_idx to see if there is new work */
4776 if (sw_idx
== hw_idx
) {
4777 hw_idx
= *(tnapi
->rx_rcb_prod_idx
);
4782 /* ACK the status ring. */
4783 tnapi
->rx_rcb_ptr
= sw_idx
;
4784 tw32_rx_mbox(tnapi
->consmbox
, sw_idx
);
4786 /* Refill RX ring(s). */
4787 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)) {
4788 if (work_mask
& RXD_OPAQUE_RING_STD
) {
4789 tpr
->rx_std_prod_idx
= std_prod_idx
% TG3_RX_RING_SIZE
;
4790 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
4791 tpr
->rx_std_prod_idx
);
4793 if (work_mask
& RXD_OPAQUE_RING_JUMBO
) {
4794 tpr
->rx_jmb_prod_idx
= jmb_prod_idx
%
4795 TG3_RX_JUMBO_RING_SIZE
;
4796 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
,
4797 tpr
->rx_jmb_prod_idx
);
4800 } else if (work_mask
) {
4801 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4802 * updated before the producer indices can be updated.
4806 tpr
->rx_std_prod_idx
= std_prod_idx
% TG3_RX_RING_SIZE
;
4807 tpr
->rx_jmb_prod_idx
= jmb_prod_idx
% TG3_RX_JUMBO_RING_SIZE
;
4809 if (tnapi
!= &tp
->napi
[1])
4810 napi_schedule(&tp
->napi
[1].napi
);
4816 static void tg3_poll_link(struct tg3
*tp
)
4818 /* handle link change and other phy events */
4819 if (!(tp
->tg3_flags
&
4820 (TG3_FLAG_USE_LINKCHG_REG
|
4821 TG3_FLAG_POLL_SERDES
))) {
4822 struct tg3_hw_status
*sblk
= tp
->napi
[0].hw_status
;
4824 if (sblk
->status
& SD_STATUS_LINK_CHG
) {
4825 sblk
->status
= SD_STATUS_UPDATED
|
4826 (sblk
->status
& ~SD_STATUS_LINK_CHG
);
4827 spin_lock(&tp
->lock
);
4828 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
4830 (MAC_STATUS_SYNC_CHANGED
|
4831 MAC_STATUS_CFG_CHANGED
|
4832 MAC_STATUS_MI_COMPLETION
|
4833 MAC_STATUS_LNKSTATE_CHANGED
));
4836 tg3_setup_phy(tp
, 0);
4837 spin_unlock(&tp
->lock
);
4842 static int tg3_rx_prodring_xfer(struct tg3
*tp
,
4843 struct tg3_rx_prodring_set
*dpr
,
4844 struct tg3_rx_prodring_set
*spr
)
4846 u32 si
, di
, cpycnt
, src_prod_idx
;
4850 src_prod_idx
= spr
->rx_std_prod_idx
;
4852 /* Make sure updates to the rx_std_buffers[] entries and the
4853 * standard producer index are seen in the correct order.
4857 if (spr
->rx_std_cons_idx
== src_prod_idx
)
4860 if (spr
->rx_std_cons_idx
< src_prod_idx
)
4861 cpycnt
= src_prod_idx
- spr
->rx_std_cons_idx
;
4863 cpycnt
= TG3_RX_RING_SIZE
- spr
->rx_std_cons_idx
;
4865 cpycnt
= min(cpycnt
, TG3_RX_RING_SIZE
- dpr
->rx_std_prod_idx
);
4867 si
= spr
->rx_std_cons_idx
;
4868 di
= dpr
->rx_std_prod_idx
;
4870 for (i
= di
; i
< di
+ cpycnt
; i
++) {
4871 if (dpr
->rx_std_buffers
[i
].skb
) {
4881 /* Ensure that updates to the rx_std_buffers ring and the
4882 * shadowed hardware producer ring from tg3_recycle_skb() are
4883 * ordered correctly WRT the skb check above.
4887 memcpy(&dpr
->rx_std_buffers
[di
],
4888 &spr
->rx_std_buffers
[si
],
4889 cpycnt
* sizeof(struct ring_info
));
4891 for (i
= 0; i
< cpycnt
; i
++, di
++, si
++) {
4892 struct tg3_rx_buffer_desc
*sbd
, *dbd
;
4893 sbd
= &spr
->rx_std
[si
];
4894 dbd
= &dpr
->rx_std
[di
];
4895 dbd
->addr_hi
= sbd
->addr_hi
;
4896 dbd
->addr_lo
= sbd
->addr_lo
;
4899 spr
->rx_std_cons_idx
= (spr
->rx_std_cons_idx
+ cpycnt
) %
4901 dpr
->rx_std_prod_idx
= (dpr
->rx_std_prod_idx
+ cpycnt
) %
4906 src_prod_idx
= spr
->rx_jmb_prod_idx
;
4908 /* Make sure updates to the rx_jmb_buffers[] entries and
4909 * the jumbo producer index are seen in the correct order.
4913 if (spr
->rx_jmb_cons_idx
== src_prod_idx
)
4916 if (spr
->rx_jmb_cons_idx
< src_prod_idx
)
4917 cpycnt
= src_prod_idx
- spr
->rx_jmb_cons_idx
;
4919 cpycnt
= TG3_RX_JUMBO_RING_SIZE
- spr
->rx_jmb_cons_idx
;
4921 cpycnt
= min(cpycnt
,
4922 TG3_RX_JUMBO_RING_SIZE
- dpr
->rx_jmb_prod_idx
);
4924 si
= spr
->rx_jmb_cons_idx
;
4925 di
= dpr
->rx_jmb_prod_idx
;
4927 for (i
= di
; i
< di
+ cpycnt
; i
++) {
4928 if (dpr
->rx_jmb_buffers
[i
].skb
) {
4938 /* Ensure that updates to the rx_jmb_buffers ring and the
4939 * shadowed hardware producer ring from tg3_recycle_skb() are
4940 * ordered correctly WRT the skb check above.
4944 memcpy(&dpr
->rx_jmb_buffers
[di
],
4945 &spr
->rx_jmb_buffers
[si
],
4946 cpycnt
* sizeof(struct ring_info
));
4948 for (i
= 0; i
< cpycnt
; i
++, di
++, si
++) {
4949 struct tg3_rx_buffer_desc
*sbd
, *dbd
;
4950 sbd
= &spr
->rx_jmb
[si
].std
;
4951 dbd
= &dpr
->rx_jmb
[di
].std
;
4952 dbd
->addr_hi
= sbd
->addr_hi
;
4953 dbd
->addr_lo
= sbd
->addr_lo
;
4956 spr
->rx_jmb_cons_idx
= (spr
->rx_jmb_cons_idx
+ cpycnt
) %
4957 TG3_RX_JUMBO_RING_SIZE
;
4958 dpr
->rx_jmb_prod_idx
= (dpr
->rx_jmb_prod_idx
+ cpycnt
) %
4959 TG3_RX_JUMBO_RING_SIZE
;
4965 static int tg3_poll_work(struct tg3_napi
*tnapi
, int work_done
, int budget
)
4967 struct tg3
*tp
= tnapi
->tp
;
4969 /* run TX completion thread */
4970 if (tnapi
->hw_status
->idx
[0].tx_consumer
!= tnapi
->tx_cons
) {
4972 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
4976 /* run RX thread, within the bounds set by NAPI.
4977 * All RX "locking" is done by ensuring outside
4978 * code synchronizes with tg3->napi.poll()
4980 if (*(tnapi
->rx_rcb_prod_idx
) != tnapi
->rx_rcb_ptr
)
4981 work_done
+= tg3_rx(tnapi
, budget
- work_done
);
4983 if ((tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
) && tnapi
== &tp
->napi
[1]) {
4984 struct tg3_rx_prodring_set
*dpr
= &tp
->prodring
[0];
4986 u32 std_prod_idx
= dpr
->rx_std_prod_idx
;
4987 u32 jmb_prod_idx
= dpr
->rx_jmb_prod_idx
;
4989 for (i
= 1; i
< tp
->irq_cnt
; i
++)
4990 err
|= tg3_rx_prodring_xfer(tp
, dpr
,
4991 tp
->napi
[i
].prodring
);
4995 if (std_prod_idx
!= dpr
->rx_std_prod_idx
)
4996 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
4997 dpr
->rx_std_prod_idx
);
4999 if (jmb_prod_idx
!= dpr
->rx_jmb_prod_idx
)
5000 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
,
5001 dpr
->rx_jmb_prod_idx
);
5006 tw32_f(HOSTCC_MODE
, tp
->coal_now
);
5012 static int tg3_poll_msix(struct napi_struct
*napi
, int budget
)
5014 struct tg3_napi
*tnapi
= container_of(napi
, struct tg3_napi
, napi
);
5015 struct tg3
*tp
= tnapi
->tp
;
5017 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5020 work_done
= tg3_poll_work(tnapi
, work_done
, budget
);
5022 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
5025 if (unlikely(work_done
>= budget
))
5028 /* tp->last_tag is used in tg3_int_reenable() below
5029 * to tell the hw how much work has been processed,
5030 * so we must read it before checking for more work.
5032 tnapi
->last_tag
= sblk
->status_tag
;
5033 tnapi
->last_irq_tag
= tnapi
->last_tag
;
5036 /* check for RX/TX work to do */
5037 if (likely(sblk
->idx
[0].tx_consumer
== tnapi
->tx_cons
&&
5038 *(tnapi
->rx_rcb_prod_idx
) == tnapi
->rx_rcb_ptr
)) {
5039 napi_complete(napi
);
5040 /* Reenable interrupts. */
5041 tw32_mailbox(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
5050 /* work_done is guaranteed to be less than budget. */
5051 napi_complete(napi
);
5052 schedule_work(&tp
->reset_task
);
5056 static int tg3_poll(struct napi_struct
*napi
, int budget
)
5058 struct tg3_napi
*tnapi
= container_of(napi
, struct tg3_napi
, napi
);
5059 struct tg3
*tp
= tnapi
->tp
;
5061 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5066 work_done
= tg3_poll_work(tnapi
, work_done
, budget
);
5068 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
5071 if (unlikely(work_done
>= budget
))
5074 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
5075 /* tp->last_tag is used in tg3_int_reenable() below
5076 * to tell the hw how much work has been processed,
5077 * so we must read it before checking for more work.
5079 tnapi
->last_tag
= sblk
->status_tag
;
5080 tnapi
->last_irq_tag
= tnapi
->last_tag
;
5083 sblk
->status
&= ~SD_STATUS_UPDATED
;
5085 if (likely(!tg3_has_work(tnapi
))) {
5086 napi_complete(napi
);
5087 tg3_int_reenable(tnapi
);
5095 /* work_done is guaranteed to be less than budget. */
5096 napi_complete(napi
);
5097 schedule_work(&tp
->reset_task
);
5101 static void tg3_irq_quiesce(struct tg3
*tp
)
5105 BUG_ON(tp
->irq_sync
);
5110 for (i
= 0; i
< tp
->irq_cnt
; i
++)
5111 synchronize_irq(tp
->napi
[i
].irq_vec
);
5114 static inline int tg3_irq_sync(struct tg3
*tp
)
5116 return tp
->irq_sync
;
5119 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5120 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5121 * with as well. Most of the time, this is not necessary except when
5122 * shutting down the device.
5124 static inline void tg3_full_lock(struct tg3
*tp
, int irq_sync
)
5126 spin_lock_bh(&tp
->lock
);
5128 tg3_irq_quiesce(tp
);
5131 static inline void tg3_full_unlock(struct tg3
*tp
)
5133 spin_unlock_bh(&tp
->lock
);
5136 /* One-shot MSI handler - Chip automatically disables interrupt
5137 * after sending MSI so driver doesn't have to do it.
5139 static irqreturn_t
tg3_msi_1shot(int irq
, void *dev_id
)
5141 struct tg3_napi
*tnapi
= dev_id
;
5142 struct tg3
*tp
= tnapi
->tp
;
5144 prefetch(tnapi
->hw_status
);
5146 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5148 if (likely(!tg3_irq_sync(tp
)))
5149 napi_schedule(&tnapi
->napi
);
5154 /* MSI ISR - No need to check for interrupt sharing and no need to
5155 * flush status block and interrupt mailbox. PCI ordering rules
5156 * guarantee that MSI will arrive after the status block.
5158 static irqreturn_t
tg3_msi(int irq
, void *dev_id
)
5160 struct tg3_napi
*tnapi
= dev_id
;
5161 struct tg3
*tp
= tnapi
->tp
;
5163 prefetch(tnapi
->hw_status
);
5165 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5167 * Writing any value to intr-mbox-0 clears PCI INTA# and
5168 * chip-internal interrupt pending events.
5169 * Writing non-zero to intr-mbox-0 additional tells the
5170 * NIC to stop sending us irqs, engaging "in-intr-handler"
5173 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
5174 if (likely(!tg3_irq_sync(tp
)))
5175 napi_schedule(&tnapi
->napi
);
5177 return IRQ_RETVAL(1);
5180 static irqreturn_t
tg3_interrupt(int irq
, void *dev_id
)
5182 struct tg3_napi
*tnapi
= dev_id
;
5183 struct tg3
*tp
= tnapi
->tp
;
5184 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5185 unsigned int handled
= 1;
5187 /* In INTx mode, it is possible for the interrupt to arrive at
5188 * the CPU before the status block posted prior to the interrupt.
5189 * Reading the PCI State register will confirm whether the
5190 * interrupt is ours and will flush the status block.
5192 if (unlikely(!(sblk
->status
& SD_STATUS_UPDATED
))) {
5193 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
5194 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
5201 * Writing any value to intr-mbox-0 clears PCI INTA# and
5202 * chip-internal interrupt pending events.
5203 * Writing non-zero to intr-mbox-0 additional tells the
5204 * NIC to stop sending us irqs, engaging "in-intr-handler"
5207 * Flush the mailbox to de-assert the IRQ immediately to prevent
5208 * spurious interrupts. The flush impacts performance but
5209 * excessive spurious interrupts can be worse in some cases.
5211 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
5212 if (tg3_irq_sync(tp
))
5214 sblk
->status
&= ~SD_STATUS_UPDATED
;
5215 if (likely(tg3_has_work(tnapi
))) {
5216 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5217 napi_schedule(&tnapi
->napi
);
5219 /* No work, shared interrupt perhaps? re-enable
5220 * interrupts, and flush that PCI write
5222 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
5226 return IRQ_RETVAL(handled
);
5229 static irqreturn_t
tg3_interrupt_tagged(int irq
, void *dev_id
)
5231 struct tg3_napi
*tnapi
= dev_id
;
5232 struct tg3
*tp
= tnapi
->tp
;
5233 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5234 unsigned int handled
= 1;
5236 /* In INTx mode, it is possible for the interrupt to arrive at
5237 * the CPU before the status block posted prior to the interrupt.
5238 * Reading the PCI State register will confirm whether the
5239 * interrupt is ours and will flush the status block.
5241 if (unlikely(sblk
->status_tag
== tnapi
->last_irq_tag
)) {
5242 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
5243 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
5250 * writing any value to intr-mbox-0 clears PCI INTA# and
5251 * chip-internal interrupt pending events.
5252 * writing non-zero to intr-mbox-0 additional tells the
5253 * NIC to stop sending us irqs, engaging "in-intr-handler"
5256 * Flush the mailbox to de-assert the IRQ immediately to prevent
5257 * spurious interrupts. The flush impacts performance but
5258 * excessive spurious interrupts can be worse in some cases.
5260 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
5263 * In a shared interrupt configuration, sometimes other devices'
5264 * interrupts will scream. We record the current status tag here
5265 * so that the above check can report that the screaming interrupts
5266 * are unhandled. Eventually they will be silenced.
5268 tnapi
->last_irq_tag
= sblk
->status_tag
;
5270 if (tg3_irq_sync(tp
))
5273 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5275 napi_schedule(&tnapi
->napi
);
5278 return IRQ_RETVAL(handled
);
5281 /* ISR for interrupt test */
5282 static irqreturn_t
tg3_test_isr(int irq
, void *dev_id
)
5284 struct tg3_napi
*tnapi
= dev_id
;
5285 struct tg3
*tp
= tnapi
->tp
;
5286 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5288 if ((sblk
->status
& SD_STATUS_UPDATED
) ||
5289 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
5290 tg3_disable_ints(tp
);
5291 return IRQ_RETVAL(1);
5293 return IRQ_RETVAL(0);
5296 static int tg3_init_hw(struct tg3
*, int);
5297 static int tg3_halt(struct tg3
*, int, int);
5299 /* Restart hardware after configuration changes, self-test, etc.
5300 * Invoked with tp->lock held.
5302 static int tg3_restart_hw(struct tg3
*tp
, int reset_phy
)
5303 __releases(tp
->lock
)
5304 __acquires(tp
->lock
)
5308 err
= tg3_init_hw(tp
, reset_phy
);
5311 "Failed to re-initialize device, aborting\n");
5312 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
5313 tg3_full_unlock(tp
);
5314 del_timer_sync(&tp
->timer
);
5316 tg3_napi_enable(tp
);
5318 tg3_full_lock(tp
, 0);
5323 #ifdef CONFIG_NET_POLL_CONTROLLER
5324 static void tg3_poll_controller(struct net_device
*dev
)
5327 struct tg3
*tp
= netdev_priv(dev
);
5329 for (i
= 0; i
< tp
->irq_cnt
; i
++)
5330 tg3_interrupt(tp
->napi
[i
].irq_vec
, &tp
->napi
[i
]);
5334 static void tg3_reset_task(struct work_struct
*work
)
5336 struct tg3
*tp
= container_of(work
, struct tg3
, reset_task
);
5338 unsigned int restart_timer
;
5340 tg3_full_lock(tp
, 0);
5342 if (!netif_running(tp
->dev
)) {
5343 tg3_full_unlock(tp
);
5347 tg3_full_unlock(tp
);
5353 tg3_full_lock(tp
, 1);
5355 restart_timer
= tp
->tg3_flags2
& TG3_FLG2_RESTART_TIMER
;
5356 tp
->tg3_flags2
&= ~TG3_FLG2_RESTART_TIMER
;
5358 if (tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
) {
5359 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
5360 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
5361 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
5362 tp
->tg3_flags
&= ~TG3_FLAG_TX_RECOVERY_PENDING
;
5365 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 0);
5366 err
= tg3_init_hw(tp
, 1);
5370 tg3_netif_start(tp
);
5373 mod_timer(&tp
->timer
, jiffies
+ 1);
5376 tg3_full_unlock(tp
);
5382 static void tg3_dump_short_state(struct tg3
*tp
)
5384 netdev_err(tp
->dev
, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5385 tr32(MAC_TX_STATUS
), tr32(MAC_RX_STATUS
));
5386 netdev_err(tp
->dev
, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5387 tr32(RDMAC_STATUS
), tr32(WDMAC_STATUS
));
5390 static void tg3_tx_timeout(struct net_device
*dev
)
5392 struct tg3
*tp
= netdev_priv(dev
);
5394 if (netif_msg_tx_err(tp
)) {
5395 netdev_err(dev
, "transmit timed out, resetting\n");
5396 tg3_dump_short_state(tp
);
5399 schedule_work(&tp
->reset_task
);
5402 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5403 static inline int tg3_4g_overflow_test(dma_addr_t mapping
, int len
)
5405 u32 base
= (u32
) mapping
& 0xffffffff;
5407 return ((base
> 0xffffdcc0) &&
5408 (base
+ len
+ 8 < base
));
5411 /* Test for DMA addresses > 40-bit */
5412 static inline int tg3_40bit_overflow_test(struct tg3
*tp
, dma_addr_t mapping
,
5415 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5416 if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
)
5417 return (((u64
) mapping
+ len
) > DMA_BIT_MASK(40));
5424 static void tg3_set_txd(struct tg3_napi
*, int, dma_addr_t
, int, u32
, u32
);
5426 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5427 static int tigon3_dma_hwbug_workaround(struct tg3_napi
*tnapi
,
5428 struct sk_buff
*skb
, u32 last_plus_one
,
5429 u32
*start
, u32 base_flags
, u32 mss
)
5431 struct tg3
*tp
= tnapi
->tp
;
5432 struct sk_buff
*new_skb
;
5433 dma_addr_t new_addr
= 0;
5437 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
5438 new_skb
= skb_copy(skb
, GFP_ATOMIC
);
5440 int more_headroom
= 4 - ((unsigned long)skb
->data
& 3);
5442 new_skb
= skb_copy_expand(skb
,
5443 skb_headroom(skb
) + more_headroom
,
5444 skb_tailroom(skb
), GFP_ATOMIC
);
5450 /* New SKB is guaranteed to be linear. */
5452 new_addr
= pci_map_single(tp
->pdev
, new_skb
->data
, new_skb
->len
,
5454 /* Make sure the mapping succeeded */
5455 if (pci_dma_mapping_error(tp
->pdev
, new_addr
)) {
5457 dev_kfree_skb(new_skb
);
5460 /* Make sure new skb does not cross any 4G boundaries.
5461 * Drop the packet if it does.
5463 } else if ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
5464 tg3_4g_overflow_test(new_addr
, new_skb
->len
)) {
5465 pci_unmap_single(tp
->pdev
, new_addr
, new_skb
->len
,
5468 dev_kfree_skb(new_skb
);
5471 tg3_set_txd(tnapi
, entry
, new_addr
, new_skb
->len
,
5472 base_flags
, 1 | (mss
<< 1));
5473 *start
= NEXT_TX(entry
);
5477 /* Now clean up the sw ring entries. */
5479 while (entry
!= last_plus_one
) {
5483 len
= skb_headlen(skb
);
5485 len
= skb_shinfo(skb
)->frags
[i
-1].size
;
5487 pci_unmap_single(tp
->pdev
,
5488 dma_unmap_addr(&tnapi
->tx_buffers
[entry
],
5490 len
, PCI_DMA_TODEVICE
);
5492 tnapi
->tx_buffers
[entry
].skb
= new_skb
;
5493 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
,
5496 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5498 entry
= NEXT_TX(entry
);
5507 static void tg3_set_txd(struct tg3_napi
*tnapi
, int entry
,
5508 dma_addr_t mapping
, int len
, u32 flags
,
5511 struct tg3_tx_buffer_desc
*txd
= &tnapi
->tx_ring
[entry
];
5512 int is_end
= (mss_and_is_end
& 0x1);
5513 u32 mss
= (mss_and_is_end
>> 1);
5517 flags
|= TXD_FLAG_END
;
5518 if (flags
& TXD_FLAG_VLAN
) {
5519 vlan_tag
= flags
>> 16;
5522 vlan_tag
|= (mss
<< TXD_MSS_SHIFT
);
5524 txd
->addr_hi
= ((u64
) mapping
>> 32);
5525 txd
->addr_lo
= ((u64
) mapping
& 0xffffffff);
5526 txd
->len_flags
= (len
<< TXD_LEN_SHIFT
) | flags
;
5527 txd
->vlan_tag
= vlan_tag
<< TXD_VLAN_TAG_SHIFT
;
5530 /* hard_start_xmit for devices that don't have any bugs and
5531 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5533 static netdev_tx_t
tg3_start_xmit(struct sk_buff
*skb
,
5534 struct net_device
*dev
)
5536 struct tg3
*tp
= netdev_priv(dev
);
5537 u32 len
, entry
, base_flags
, mss
;
5539 struct tg3_napi
*tnapi
;
5540 struct netdev_queue
*txq
;
5541 unsigned int i
, last
;
5543 txq
= netdev_get_tx_queue(dev
, skb_get_queue_mapping(skb
));
5544 tnapi
= &tp
->napi
[skb_get_queue_mapping(skb
)];
5545 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
5548 /* We are running in BH disabled context with netif_tx_lock
5549 * and TX reclaim runs via tp->napi.poll inside of a software
5550 * interrupt. Furthermore, IRQ processing runs lockless so we have
5551 * no IRQ context deadlocks to worry about either. Rejoice!
5553 if (unlikely(tg3_tx_avail(tnapi
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
5554 if (!netif_tx_queue_stopped(txq
)) {
5555 netif_tx_stop_queue(txq
);
5557 /* This is a hard error, log it. */
5559 "BUG! Tx Ring full when queue awake!\n");
5561 return NETDEV_TX_BUSY
;
5564 entry
= tnapi
->tx_prod
;
5566 mss
= skb_shinfo(skb
)->gso_size
;
5568 int tcp_opt_len
, ip_tcp_len
;
5571 if (skb_header_cloned(skb
) &&
5572 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
5577 if (skb_shinfo(skb
)->gso_type
& SKB_GSO_TCPV6
)
5578 hdrlen
= skb_headlen(skb
) - ETH_HLEN
;
5580 struct iphdr
*iph
= ip_hdr(skb
);
5582 tcp_opt_len
= tcp_optlen(skb
);
5583 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
5586 iph
->tot_len
= htons(mss
+ ip_tcp_len
+ tcp_opt_len
);
5587 hdrlen
= ip_tcp_len
+ tcp_opt_len
;
5590 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) {
5591 mss
|= (hdrlen
& 0xc) << 12;
5593 base_flags
|= 0x00000010;
5594 base_flags
|= (hdrlen
& 0x3e0) << 5;
5598 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
5599 TXD_FLAG_CPU_POST_DMA
);
5601 tcp_hdr(skb
)->check
= 0;
5603 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5604 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
5607 #if TG3_VLAN_TAG_USED
5608 if (tp
->vlgrp
!= NULL
&& vlan_tx_tag_present(skb
))
5609 base_flags
|= (TXD_FLAG_VLAN
|
5610 (vlan_tx_tag_get(skb
) << 16));
5613 len
= skb_headlen(skb
);
5615 /* Queue skb data, a.k.a. the main skb fragment. */
5616 mapping
= pci_map_single(tp
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
5617 if (pci_dma_mapping_error(tp
->pdev
, mapping
)) {
5622 tnapi
->tx_buffers
[entry
].skb
= skb
;
5623 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
, mapping
);
5625 if ((tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
) &&
5626 !mss
&& skb
->len
> ETH_DATA_LEN
)
5627 base_flags
|= TXD_FLAG_JMB_PKT
;
5629 tg3_set_txd(tnapi
, entry
, mapping
, len
, base_flags
,
5630 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
5632 entry
= NEXT_TX(entry
);
5634 /* Now loop through additional data fragments, and queue them. */
5635 if (skb_shinfo(skb
)->nr_frags
> 0) {
5636 last
= skb_shinfo(skb
)->nr_frags
- 1;
5637 for (i
= 0; i
<= last
; i
++) {
5638 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5641 mapping
= pci_map_page(tp
->pdev
,
5644 len
, PCI_DMA_TODEVICE
);
5645 if (pci_dma_mapping_error(tp
->pdev
, mapping
))
5648 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5649 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
,
5652 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5653 base_flags
, (i
== last
) | (mss
<< 1));
5655 entry
= NEXT_TX(entry
);
5659 /* Packets are ready, update Tx producer idx local and on card. */
5660 tw32_tx_mbox(tnapi
->prodmbox
, entry
);
5662 tnapi
->tx_prod
= entry
;
5663 if (unlikely(tg3_tx_avail(tnapi
) <= (MAX_SKB_FRAGS
+ 1))) {
5664 netif_tx_stop_queue(txq
);
5666 /* netif_tx_stop_queue() must be done before checking
5667 * checking tx index in tg3_tx_avail() below, because in
5668 * tg3_tx(), we update tx index before checking for
5669 * netif_tx_queue_stopped().
5672 if (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
))
5673 netif_tx_wake_queue(txq
);
5679 return NETDEV_TX_OK
;
5683 entry
= tnapi
->tx_prod
;
5684 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5685 pci_unmap_single(tp
->pdev
,
5686 dma_unmap_addr(&tnapi
->tx_buffers
[entry
], mapping
),
5689 for (i
= 0; i
<= last
; i
++) {
5690 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5691 entry
= NEXT_TX(entry
);
5693 pci_unmap_page(tp
->pdev
,
5694 dma_unmap_addr(&tnapi
->tx_buffers
[entry
],
5696 frag
->size
, PCI_DMA_TODEVICE
);
5700 return NETDEV_TX_OK
;
5703 static netdev_tx_t
tg3_start_xmit_dma_bug(struct sk_buff
*,
5704 struct net_device
*);
5706 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5707 * TSO header is greater than 80 bytes.
5709 static int tg3_tso_bug(struct tg3
*tp
, struct sk_buff
*skb
)
5711 struct sk_buff
*segs
, *nskb
;
5712 u32 frag_cnt_est
= skb_shinfo(skb
)->gso_segs
* 3;
5714 /* Estimate the number of fragments in the worst case */
5715 if (unlikely(tg3_tx_avail(&tp
->napi
[0]) <= frag_cnt_est
)) {
5716 netif_stop_queue(tp
->dev
);
5718 /* netif_tx_stop_queue() must be done before checking
5719 * checking tx index in tg3_tx_avail() below, because in
5720 * tg3_tx(), we update tx index before checking for
5721 * netif_tx_queue_stopped().
5724 if (tg3_tx_avail(&tp
->napi
[0]) <= frag_cnt_est
)
5725 return NETDEV_TX_BUSY
;
5727 netif_wake_queue(tp
->dev
);
5730 segs
= skb_gso_segment(skb
, tp
->dev
->features
& ~NETIF_F_TSO
);
5732 goto tg3_tso_bug_end
;
5738 tg3_start_xmit_dma_bug(nskb
, tp
->dev
);
5744 return NETDEV_TX_OK
;
5747 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5748 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5750 static netdev_tx_t
tg3_start_xmit_dma_bug(struct sk_buff
*skb
,
5751 struct net_device
*dev
)
5753 struct tg3
*tp
= netdev_priv(dev
);
5754 u32 len
, entry
, base_flags
, mss
;
5755 int would_hit_hwbug
;
5757 struct tg3_napi
*tnapi
;
5758 struct netdev_queue
*txq
;
5759 unsigned int i
, last
;
5761 txq
= netdev_get_tx_queue(dev
, skb_get_queue_mapping(skb
));
5762 tnapi
= &tp
->napi
[skb_get_queue_mapping(skb
)];
5763 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
5766 /* We are running in BH disabled context with netif_tx_lock
5767 * and TX reclaim runs via tp->napi.poll inside of a software
5768 * interrupt. Furthermore, IRQ processing runs lockless so we have
5769 * no IRQ context deadlocks to worry about either. Rejoice!
5771 if (unlikely(tg3_tx_avail(tnapi
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
5772 if (!netif_tx_queue_stopped(txq
)) {
5773 netif_tx_stop_queue(txq
);
5775 /* This is a hard error, log it. */
5777 "BUG! Tx Ring full when queue awake!\n");
5779 return NETDEV_TX_BUSY
;
5782 entry
= tnapi
->tx_prod
;
5784 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5785 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
5787 mss
= skb_shinfo(skb
)->gso_size
;
5790 u32 tcp_opt_len
, hdr_len
;
5792 if (skb_header_cloned(skb
) &&
5793 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
5799 tcp_opt_len
= tcp_optlen(skb
);
5801 if (skb_shinfo(skb
)->gso_type
& SKB_GSO_TCPV6
) {
5802 hdr_len
= skb_headlen(skb
) - ETH_HLEN
;
5806 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
5807 hdr_len
= ip_tcp_len
+ tcp_opt_len
;
5810 iph
->tot_len
= htons(mss
+ hdr_len
);
5813 if (unlikely((ETH_HLEN
+ hdr_len
) > 80) &&
5814 (tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
))
5815 return tg3_tso_bug(tp
, skb
);
5817 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
5818 TXD_FLAG_CPU_POST_DMA
);
5820 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
5821 tcp_hdr(skb
)->check
= 0;
5822 base_flags
&= ~TXD_FLAG_TCPUDP_CSUM
;
5824 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
5829 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) {
5830 mss
|= (hdr_len
& 0xc) << 12;
5832 base_flags
|= 0x00000010;
5833 base_flags
|= (hdr_len
& 0x3e0) << 5;
5834 } else if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
)
5835 mss
|= hdr_len
<< 9;
5836 else if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_1
) ||
5837 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
5838 if (tcp_opt_len
|| iph
->ihl
> 5) {
5841 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
5842 mss
|= (tsflags
<< 11);
5845 if (tcp_opt_len
|| iph
->ihl
> 5) {
5848 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
5849 base_flags
|= tsflags
<< 12;
5853 #if TG3_VLAN_TAG_USED
5854 if (tp
->vlgrp
!= NULL
&& vlan_tx_tag_present(skb
))
5855 base_flags
|= (TXD_FLAG_VLAN
|
5856 (vlan_tx_tag_get(skb
) << 16));
5859 if ((tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
) &&
5860 !mss
&& skb
->len
> ETH_DATA_LEN
)
5861 base_flags
|= TXD_FLAG_JMB_PKT
;
5863 len
= skb_headlen(skb
);
5865 mapping
= pci_map_single(tp
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
5866 if (pci_dma_mapping_error(tp
->pdev
, mapping
)) {
5871 tnapi
->tx_buffers
[entry
].skb
= skb
;
5872 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
, mapping
);
5874 would_hit_hwbug
= 0;
5876 if ((tp
->tg3_flags3
& TG3_FLG3_SHORT_DMA_BUG
) && len
<= 8)
5877 would_hit_hwbug
= 1;
5879 if ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
5880 tg3_4g_overflow_test(mapping
, len
))
5881 would_hit_hwbug
= 1;
5883 if ((tp
->tg3_flags3
& TG3_FLG3_40BIT_DMA_LIMIT_BUG
) &&
5884 tg3_40bit_overflow_test(tp
, mapping
, len
))
5885 would_hit_hwbug
= 1;
5887 if (tp
->tg3_flags3
& TG3_FLG3_5701_DMA_BUG
)
5888 would_hit_hwbug
= 1;
5890 tg3_set_txd(tnapi
, entry
, mapping
, len
, base_flags
,
5891 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
5893 entry
= NEXT_TX(entry
);
5895 /* Now loop through additional data fragments, and queue them. */
5896 if (skb_shinfo(skb
)->nr_frags
> 0) {
5897 last
= skb_shinfo(skb
)->nr_frags
- 1;
5898 for (i
= 0; i
<= last
; i
++) {
5899 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5902 mapping
= pci_map_page(tp
->pdev
,
5905 len
, PCI_DMA_TODEVICE
);
5907 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5908 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
,
5910 if (pci_dma_mapping_error(tp
->pdev
, mapping
))
5913 if ((tp
->tg3_flags3
& TG3_FLG3_SHORT_DMA_BUG
) &&
5915 would_hit_hwbug
= 1;
5917 if ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
5918 tg3_4g_overflow_test(mapping
, len
))
5919 would_hit_hwbug
= 1;
5921 if ((tp
->tg3_flags3
& TG3_FLG3_40BIT_DMA_LIMIT_BUG
) &&
5922 tg3_40bit_overflow_test(tp
, mapping
, len
))
5923 would_hit_hwbug
= 1;
5925 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
5926 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5927 base_flags
, (i
== last
)|(mss
<< 1));
5929 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5930 base_flags
, (i
== last
));
5932 entry
= NEXT_TX(entry
);
5936 if (would_hit_hwbug
) {
5937 u32 last_plus_one
= entry
;
5940 start
= entry
- 1 - skb_shinfo(skb
)->nr_frags
;
5941 start
&= (TG3_TX_RING_SIZE
- 1);
5943 /* If the workaround fails due to memory/mapping
5944 * failure, silently drop this packet.
5946 if (tigon3_dma_hwbug_workaround(tnapi
, skb
, last_plus_one
,
5947 &start
, base_flags
, mss
))
5953 /* Packets are ready, update Tx producer idx local and on card. */
5954 tw32_tx_mbox(tnapi
->prodmbox
, entry
);
5956 tnapi
->tx_prod
= entry
;
5957 if (unlikely(tg3_tx_avail(tnapi
) <= (MAX_SKB_FRAGS
+ 1))) {
5958 netif_tx_stop_queue(txq
);
5960 /* netif_tx_stop_queue() must be done before checking
5961 * checking tx index in tg3_tx_avail() below, because in
5962 * tg3_tx(), we update tx index before checking for
5963 * netif_tx_queue_stopped().
5966 if (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
))
5967 netif_tx_wake_queue(txq
);
5973 return NETDEV_TX_OK
;
5977 entry
= tnapi
->tx_prod
;
5978 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5979 pci_unmap_single(tp
->pdev
,
5980 dma_unmap_addr(&tnapi
->tx_buffers
[entry
], mapping
),
5983 for (i
= 0; i
<= last
; i
++) {
5984 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5985 entry
= NEXT_TX(entry
);
5987 pci_unmap_page(tp
->pdev
,
5988 dma_unmap_addr(&tnapi
->tx_buffers
[entry
],
5990 frag
->size
, PCI_DMA_TODEVICE
);
5994 return NETDEV_TX_OK
;
5997 static inline void tg3_set_mtu(struct net_device
*dev
, struct tg3
*tp
,
6002 if (new_mtu
> ETH_DATA_LEN
) {
6003 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
6004 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
6005 ethtool_op_set_tso(dev
, 0);
6007 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
6010 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
6011 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
6012 tp
->tg3_flags
&= ~TG3_FLAG_JUMBO_RING_ENABLE
;
6016 static int tg3_change_mtu(struct net_device
*dev
, int new_mtu
)
6018 struct tg3
*tp
= netdev_priv(dev
);
6021 if (new_mtu
< TG3_MIN_MTU
|| new_mtu
> TG3_MAX_MTU(tp
))
6024 if (!netif_running(dev
)) {
6025 /* We'll just catch it later when the
6028 tg3_set_mtu(dev
, tp
, new_mtu
);
6036 tg3_full_lock(tp
, 1);
6038 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
6040 tg3_set_mtu(dev
, tp
, new_mtu
);
6042 err
= tg3_restart_hw(tp
, 0);
6045 tg3_netif_start(tp
);
6047 tg3_full_unlock(tp
);
6055 static void tg3_rx_prodring_free(struct tg3
*tp
,
6056 struct tg3_rx_prodring_set
*tpr
)
6060 if (tpr
!= &tp
->prodring
[0]) {
6061 for (i
= tpr
->rx_std_cons_idx
; i
!= tpr
->rx_std_prod_idx
;
6062 i
= (i
+ 1) % TG3_RX_RING_SIZE
)
6063 tg3_rx_skb_free(tp
, &tpr
->rx_std_buffers
[i
],
6066 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
6067 for (i
= tpr
->rx_jmb_cons_idx
;
6068 i
!= tpr
->rx_jmb_prod_idx
;
6069 i
= (i
+ 1) % TG3_RX_JUMBO_RING_SIZE
) {
6070 tg3_rx_skb_free(tp
, &tpr
->rx_jmb_buffers
[i
],
6078 for (i
= 0; i
< TG3_RX_RING_SIZE
; i
++)
6079 tg3_rx_skb_free(tp
, &tpr
->rx_std_buffers
[i
],
6082 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
6083 for (i
= 0; i
< TG3_RX_JUMBO_RING_SIZE
; i
++)
6084 tg3_rx_skb_free(tp
, &tpr
->rx_jmb_buffers
[i
],
6089 /* Initialize rx rings for packet processing.
6091 * The chip has been shut down and the driver detached from
6092 * the networking, so no interrupts or new tx packets will
6093 * end up in the driver. tp->{tx,}lock are held and thus
6096 static int tg3_rx_prodring_alloc(struct tg3
*tp
,
6097 struct tg3_rx_prodring_set
*tpr
)
6099 u32 i
, rx_pkt_dma_sz
;
6101 tpr
->rx_std_cons_idx
= 0;
6102 tpr
->rx_std_prod_idx
= 0;
6103 tpr
->rx_jmb_cons_idx
= 0;
6104 tpr
->rx_jmb_prod_idx
= 0;
6106 if (tpr
!= &tp
->prodring
[0]) {
6107 memset(&tpr
->rx_std_buffers
[0], 0, TG3_RX_STD_BUFF_RING_SIZE
);
6108 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
)
6109 memset(&tpr
->rx_jmb_buffers
[0], 0,
6110 TG3_RX_JMB_BUFF_RING_SIZE
);
6114 /* Zero out all descriptors. */
6115 memset(tpr
->rx_std
, 0, TG3_RX_RING_BYTES
);
6117 rx_pkt_dma_sz
= TG3_RX_STD_DMA_SZ
;
6118 if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) &&
6119 tp
->dev
->mtu
> ETH_DATA_LEN
)
6120 rx_pkt_dma_sz
= TG3_RX_JMB_DMA_SZ
;
6121 tp
->rx_pkt_map_sz
= TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz
);
6123 /* Initialize invariants of the rings, we only set this
6124 * stuff once. This works because the card does not
6125 * write into the rx buffer posting rings.
6127 for (i
= 0; i
< TG3_RX_RING_SIZE
; i
++) {
6128 struct tg3_rx_buffer_desc
*rxd
;
6130 rxd
= &tpr
->rx_std
[i
];
6131 rxd
->idx_len
= rx_pkt_dma_sz
<< RXD_LEN_SHIFT
;
6132 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
);
6133 rxd
->opaque
= (RXD_OPAQUE_RING_STD
|
6134 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
6137 /* Now allocate fresh SKBs for each rx ring. */
6138 for (i
= 0; i
< tp
->rx_pending
; i
++) {
6139 if (tg3_alloc_rx_skb(tp
, tpr
, RXD_OPAQUE_RING_STD
, i
) < 0) {
6140 netdev_warn(tp
->dev
,
6141 "Using a smaller RX standard ring. Only "
6142 "%d out of %d buffers were allocated "
6143 "successfully\n", i
, tp
->rx_pending
);
6151 if (!(tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
))
6154 memset(tpr
->rx_jmb
, 0, TG3_RX_JUMBO_RING_BYTES
);
6156 if (!(tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
))
6159 for (i
= 0; i
< TG3_RX_JUMBO_RING_SIZE
; i
++) {
6160 struct tg3_rx_buffer_desc
*rxd
;
6162 rxd
= &tpr
->rx_jmb
[i
].std
;
6163 rxd
->idx_len
= TG3_RX_JMB_DMA_SZ
<< RXD_LEN_SHIFT
;
6164 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
) |
6166 rxd
->opaque
= (RXD_OPAQUE_RING_JUMBO
|
6167 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
6170 for (i
= 0; i
< tp
->rx_jumbo_pending
; i
++) {
6171 if (tg3_alloc_rx_skb(tp
, tpr
, RXD_OPAQUE_RING_JUMBO
, i
) < 0) {
6172 netdev_warn(tp
->dev
,
6173 "Using a smaller RX jumbo ring. Only %d "
6174 "out of %d buffers were allocated "
6175 "successfully\n", i
, tp
->rx_jumbo_pending
);
6178 tp
->rx_jumbo_pending
= i
;
6187 tg3_rx_prodring_free(tp
, tpr
);
6191 static void tg3_rx_prodring_fini(struct tg3
*tp
,
6192 struct tg3_rx_prodring_set
*tpr
)
6194 kfree(tpr
->rx_std_buffers
);
6195 tpr
->rx_std_buffers
= NULL
;
6196 kfree(tpr
->rx_jmb_buffers
);
6197 tpr
->rx_jmb_buffers
= NULL
;
6199 pci_free_consistent(tp
->pdev
, TG3_RX_RING_BYTES
,
6200 tpr
->rx_std
, tpr
->rx_std_mapping
);
6204 pci_free_consistent(tp
->pdev
, TG3_RX_JUMBO_RING_BYTES
,
6205 tpr
->rx_jmb
, tpr
->rx_jmb_mapping
);
6210 static int tg3_rx_prodring_init(struct tg3
*tp
,
6211 struct tg3_rx_prodring_set
*tpr
)
6213 tpr
->rx_std_buffers
= kzalloc(TG3_RX_STD_BUFF_RING_SIZE
, GFP_KERNEL
);
6214 if (!tpr
->rx_std_buffers
)
6217 tpr
->rx_std
= pci_alloc_consistent(tp
->pdev
, TG3_RX_RING_BYTES
,
6218 &tpr
->rx_std_mapping
);
6222 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
6223 tpr
->rx_jmb_buffers
= kzalloc(TG3_RX_JMB_BUFF_RING_SIZE
,
6225 if (!tpr
->rx_jmb_buffers
)
6228 tpr
->rx_jmb
= pci_alloc_consistent(tp
->pdev
,
6229 TG3_RX_JUMBO_RING_BYTES
,
6230 &tpr
->rx_jmb_mapping
);
6238 tg3_rx_prodring_fini(tp
, tpr
);
6242 /* Free up pending packets in all rx/tx rings.
6244 * The chip has been shut down and the driver detached from
6245 * the networking, so no interrupts or new tx packets will
6246 * end up in the driver. tp->{tx,}lock is not held and we are not
6247 * in an interrupt context and thus may sleep.
6249 static void tg3_free_rings(struct tg3
*tp
)
6253 for (j
= 0; j
< tp
->irq_cnt
; j
++) {
6254 struct tg3_napi
*tnapi
= &tp
->napi
[j
];
6256 tg3_rx_prodring_free(tp
, &tp
->prodring
[j
]);
6258 if (!tnapi
->tx_buffers
)
6261 for (i
= 0; i
< TG3_TX_RING_SIZE
; ) {
6262 struct ring_info
*txp
;
6263 struct sk_buff
*skb
;
6266 txp
= &tnapi
->tx_buffers
[i
];
6274 pci_unmap_single(tp
->pdev
,
6275 dma_unmap_addr(txp
, mapping
),
6282 for (k
= 0; k
< skb_shinfo(skb
)->nr_frags
; k
++) {
6283 txp
= &tnapi
->tx_buffers
[i
& (TG3_TX_RING_SIZE
- 1)];
6284 pci_unmap_page(tp
->pdev
,
6285 dma_unmap_addr(txp
, mapping
),
6286 skb_shinfo(skb
)->frags
[k
].size
,
6291 dev_kfree_skb_any(skb
);
6296 /* Initialize tx/rx rings for packet processing.
6298 * The chip has been shut down and the driver detached from
6299 * the networking, so no interrupts or new tx packets will
6300 * end up in the driver. tp->{tx,}lock are held and thus
6303 static int tg3_init_rings(struct tg3
*tp
)
6307 /* Free up all the SKBs. */
6310 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6311 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6313 tnapi
->last_tag
= 0;
6314 tnapi
->last_irq_tag
= 0;
6315 tnapi
->hw_status
->status
= 0;
6316 tnapi
->hw_status
->status_tag
= 0;
6317 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6322 memset(tnapi
->tx_ring
, 0, TG3_TX_RING_BYTES
);
6324 tnapi
->rx_rcb_ptr
= 0;
6326 memset(tnapi
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
6328 if (tg3_rx_prodring_alloc(tp
, &tp
->prodring
[i
])) {
6338 * Must not be invoked with interrupt sources disabled and
6339 * the hardware shutdown down.
6341 static void tg3_free_consistent(struct tg3
*tp
)
6345 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6346 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6348 if (tnapi
->tx_ring
) {
6349 pci_free_consistent(tp
->pdev
, TG3_TX_RING_BYTES
,
6350 tnapi
->tx_ring
, tnapi
->tx_desc_mapping
);
6351 tnapi
->tx_ring
= NULL
;
6354 kfree(tnapi
->tx_buffers
);
6355 tnapi
->tx_buffers
= NULL
;
6357 if (tnapi
->rx_rcb
) {
6358 pci_free_consistent(tp
->pdev
, TG3_RX_RCB_RING_BYTES(tp
),
6360 tnapi
->rx_rcb_mapping
);
6361 tnapi
->rx_rcb
= NULL
;
6364 if (tnapi
->hw_status
) {
6365 pci_free_consistent(tp
->pdev
, TG3_HW_STATUS_SIZE
,
6367 tnapi
->status_mapping
);
6368 tnapi
->hw_status
= NULL
;
6373 pci_free_consistent(tp
->pdev
, sizeof(struct tg3_hw_stats
),
6374 tp
->hw_stats
, tp
->stats_mapping
);
6375 tp
->hw_stats
= NULL
;
6378 for (i
= 0; i
< tp
->irq_cnt
; i
++)
6379 tg3_rx_prodring_fini(tp
, &tp
->prodring
[i
]);
6383 * Must not be invoked with interrupt sources disabled and
6384 * the hardware shutdown down. Can sleep.
6386 static int tg3_alloc_consistent(struct tg3
*tp
)
6390 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6391 if (tg3_rx_prodring_init(tp
, &tp
->prodring
[i
]))
6395 tp
->hw_stats
= pci_alloc_consistent(tp
->pdev
,
6396 sizeof(struct tg3_hw_stats
),
6397 &tp
->stats_mapping
);
6401 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
6403 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6404 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6405 struct tg3_hw_status
*sblk
;
6407 tnapi
->hw_status
= pci_alloc_consistent(tp
->pdev
,
6409 &tnapi
->status_mapping
);
6410 if (!tnapi
->hw_status
)
6413 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6414 sblk
= tnapi
->hw_status
;
6416 /* If multivector TSS is enabled, vector 0 does not handle
6417 * tx interrupts. Don't allocate any resources for it.
6419 if ((!i
&& !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)) ||
6420 (i
&& (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
))) {
6421 tnapi
->tx_buffers
= kzalloc(sizeof(struct ring_info
) *
6424 if (!tnapi
->tx_buffers
)
6427 tnapi
->tx_ring
= pci_alloc_consistent(tp
->pdev
,
6429 &tnapi
->tx_desc_mapping
);
6430 if (!tnapi
->tx_ring
)
6435 * When RSS is enabled, the status block format changes
6436 * slightly. The "rx_jumbo_consumer", "reserved",
6437 * and "rx_mini_consumer" members get mapped to the
6438 * other three rx return ring producer indexes.
6442 tnapi
->rx_rcb_prod_idx
= &sblk
->idx
[0].rx_producer
;
6445 tnapi
->rx_rcb_prod_idx
= &sblk
->rx_jumbo_consumer
;
6448 tnapi
->rx_rcb_prod_idx
= &sblk
->reserved
;
6451 tnapi
->rx_rcb_prod_idx
= &sblk
->rx_mini_consumer
;
6455 tnapi
->prodring
= &tp
->prodring
[i
];
6458 * If multivector RSS is enabled, vector 0 does not handle
6459 * rx or tx interrupts. Don't allocate any resources for it.
6461 if (!i
&& (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
))
6464 tnapi
->rx_rcb
= pci_alloc_consistent(tp
->pdev
,
6465 TG3_RX_RCB_RING_BYTES(tp
),
6466 &tnapi
->rx_rcb_mapping
);
6470 memset(tnapi
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
6476 tg3_free_consistent(tp
);
6480 #define MAX_WAIT_CNT 1000
6482 /* To stop a block, clear the enable bit and poll till it
6483 * clears. tp->lock is held.
6485 static int tg3_stop_block(struct tg3
*tp
, unsigned long ofs
, u32 enable_bit
, int silent
)
6490 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
6497 /* We can't enable/disable these bits of the
6498 * 5705/5750, just say success.
6511 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
6514 if ((val
& enable_bit
) == 0)
6518 if (i
== MAX_WAIT_CNT
&& !silent
) {
6519 dev_err(&tp
->pdev
->dev
,
6520 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6528 /* tp->lock is held. */
6529 static int tg3_abort_hw(struct tg3
*tp
, int silent
)
6533 tg3_disable_ints(tp
);
6535 tp
->rx_mode
&= ~RX_MODE_ENABLE
;
6536 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
6539 err
= tg3_stop_block(tp
, RCVBDI_MODE
, RCVBDI_MODE_ENABLE
, silent
);
6540 err
|= tg3_stop_block(tp
, RCVLPC_MODE
, RCVLPC_MODE_ENABLE
, silent
);
6541 err
|= tg3_stop_block(tp
, RCVLSC_MODE
, RCVLSC_MODE_ENABLE
, silent
);
6542 err
|= tg3_stop_block(tp
, RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
, silent
);
6543 err
|= tg3_stop_block(tp
, RCVDCC_MODE
, RCVDCC_MODE_ENABLE
, silent
);
6544 err
|= tg3_stop_block(tp
, RCVCC_MODE
, RCVCC_MODE_ENABLE
, silent
);
6546 err
|= tg3_stop_block(tp
, SNDBDS_MODE
, SNDBDS_MODE_ENABLE
, silent
);
6547 err
|= tg3_stop_block(tp
, SNDBDI_MODE
, SNDBDI_MODE_ENABLE
, silent
);
6548 err
|= tg3_stop_block(tp
, SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
, silent
);
6549 err
|= tg3_stop_block(tp
, RDMAC_MODE
, RDMAC_MODE_ENABLE
, silent
);
6550 err
|= tg3_stop_block(tp
, SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
, silent
);
6551 err
|= tg3_stop_block(tp
, DMAC_MODE
, DMAC_MODE_ENABLE
, silent
);
6552 err
|= tg3_stop_block(tp
, SNDBDC_MODE
, SNDBDC_MODE_ENABLE
, silent
);
6554 tp
->mac_mode
&= ~MAC_MODE_TDE_ENABLE
;
6555 tw32_f(MAC_MODE
, tp
->mac_mode
);
6558 tp
->tx_mode
&= ~TX_MODE_ENABLE
;
6559 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
6561 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
6563 if (!(tr32(MAC_TX_MODE
) & TX_MODE_ENABLE
))
6566 if (i
>= MAX_WAIT_CNT
) {
6567 dev_err(&tp
->pdev
->dev
,
6568 "%s timed out, TX_MODE_ENABLE will not clear "
6569 "MAC_TX_MODE=%08x\n", __func__
, tr32(MAC_TX_MODE
));
6573 err
|= tg3_stop_block(tp
, HOSTCC_MODE
, HOSTCC_MODE_ENABLE
, silent
);
6574 err
|= tg3_stop_block(tp
, WDMAC_MODE
, WDMAC_MODE_ENABLE
, silent
);
6575 err
|= tg3_stop_block(tp
, MBFREE_MODE
, MBFREE_MODE_ENABLE
, silent
);
6577 tw32(FTQ_RESET
, 0xffffffff);
6578 tw32(FTQ_RESET
, 0x00000000);
6580 err
|= tg3_stop_block(tp
, BUFMGR_MODE
, BUFMGR_MODE_ENABLE
, silent
);
6581 err
|= tg3_stop_block(tp
, MEMARB_MODE
, MEMARB_MODE_ENABLE
, silent
);
6583 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6584 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6585 if (tnapi
->hw_status
)
6586 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6589 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
6594 static void tg3_ape_send_event(struct tg3
*tp
, u32 event
)
6599 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
6600 if (apedata
!= APE_SEG_SIG_MAGIC
)
6603 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
6604 if (!(apedata
& APE_FW_STATUS_READY
))
6607 /* Wait for up to 1 millisecond for APE to service previous event. */
6608 for (i
= 0; i
< 10; i
++) {
6609 if (tg3_ape_lock(tp
, TG3_APE_LOCK_MEM
))
6612 apedata
= tg3_ape_read32(tp
, TG3_APE_EVENT_STATUS
);
6614 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6615 tg3_ape_write32(tp
, TG3_APE_EVENT_STATUS
,
6616 event
| APE_EVENT_STATUS_EVENT_PENDING
);
6618 tg3_ape_unlock(tp
, TG3_APE_LOCK_MEM
);
6620 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6626 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6627 tg3_ape_write32(tp
, TG3_APE_EVENT
, APE_EVENT_1
);
6630 static void tg3_ape_driver_state_change(struct tg3
*tp
, int kind
)
6635 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
6639 case RESET_KIND_INIT
:
6640 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
,
6641 APE_HOST_SEG_SIG_MAGIC
);
6642 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_LEN
,
6643 APE_HOST_SEG_LEN_MAGIC
);
6644 apedata
= tg3_ape_read32(tp
, TG3_APE_HOST_INIT_COUNT
);
6645 tg3_ape_write32(tp
, TG3_APE_HOST_INIT_COUNT
, ++apedata
);
6646 tg3_ape_write32(tp
, TG3_APE_HOST_DRIVER_ID
,
6647 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM
, TG3_MIN_NUM
));
6648 tg3_ape_write32(tp
, TG3_APE_HOST_BEHAVIOR
,
6649 APE_HOST_BEHAV_NO_PHYLOCK
);
6651 event
= APE_EVENT_STATUS_STATE_START
;
6653 case RESET_KIND_SHUTDOWN
:
6654 /* With the interface we are currently using,
6655 * APE does not track driver state. Wiping
6656 * out the HOST SEGMENT SIGNATURE forces
6657 * the APE to assume OS absent status.
6659 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
, 0x0);
6661 event
= APE_EVENT_STATUS_STATE_UNLOAD
;
6663 case RESET_KIND_SUSPEND
:
6664 event
= APE_EVENT_STATUS_STATE_SUSPEND
;
6670 event
|= APE_EVENT_STATUS_DRIVER_EVNT
| APE_EVENT_STATUS_STATE_CHNGE
;
6672 tg3_ape_send_event(tp
, event
);
6675 /* tp->lock is held. */
6676 static void tg3_write_sig_pre_reset(struct tg3
*tp
, int kind
)
6678 tg3_write_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
,
6679 NIC_SRAM_FIRMWARE_MBOX_MAGIC1
);
6681 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
6683 case RESET_KIND_INIT
:
6684 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6688 case RESET_KIND_SHUTDOWN
:
6689 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6693 case RESET_KIND_SUSPEND
:
6694 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6703 if (kind
== RESET_KIND_INIT
||
6704 kind
== RESET_KIND_SUSPEND
)
6705 tg3_ape_driver_state_change(tp
, kind
);
6708 /* tp->lock is held. */
6709 static void tg3_write_sig_post_reset(struct tg3
*tp
, int kind
)
6711 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
6713 case RESET_KIND_INIT
:
6714 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6715 DRV_STATE_START_DONE
);
6718 case RESET_KIND_SHUTDOWN
:
6719 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6720 DRV_STATE_UNLOAD_DONE
);
6728 if (kind
== RESET_KIND_SHUTDOWN
)
6729 tg3_ape_driver_state_change(tp
, kind
);
6732 /* tp->lock is held. */
6733 static void tg3_write_sig_legacy(struct tg3
*tp
, int kind
)
6735 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
6737 case RESET_KIND_INIT
:
6738 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6742 case RESET_KIND_SHUTDOWN
:
6743 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6747 case RESET_KIND_SUSPEND
:
6748 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6758 static int tg3_poll_fw(struct tg3
*tp
)
6763 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6764 /* Wait up to 20ms for init done. */
6765 for (i
= 0; i
< 200; i
++) {
6766 if (tr32(VCPU_STATUS
) & VCPU_STATUS_INIT_DONE
)
6773 /* Wait for firmware initialization to complete. */
6774 for (i
= 0; i
< 100000; i
++) {
6775 tg3_read_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
, &val
);
6776 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
6781 /* Chip might not be fitted with firmware. Some Sun onboard
6782 * parts are configured like that. So don't signal the timeout
6783 * of the above loop as an error, but do report the lack of
6784 * running firmware once.
6787 !(tp
->tg3_flags2
& TG3_FLG2_NO_FWARE_REPORTED
)) {
6788 tp
->tg3_flags2
|= TG3_FLG2_NO_FWARE_REPORTED
;
6790 netdev_info(tp
->dev
, "No firmware running\n");
6793 if (tp
->pci_chip_rev_id
== CHIPREV_ID_57765_A0
) {
6794 /* The 57765 A0 needs a little more
6795 * time to do some important work.
6803 /* Save PCI command register before chip reset */
6804 static void tg3_save_pci_state(struct tg3
*tp
)
6806 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &tp
->pci_cmd
);
6809 /* Restore PCI state after chip reset */
6810 static void tg3_restore_pci_state(struct tg3
*tp
)
6814 /* Re-enable indirect register accesses. */
6815 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
6816 tp
->misc_host_ctrl
);
6818 /* Set MAX PCI retry to zero. */
6819 val
= (PCISTATE_ROM_ENABLE
| PCISTATE_ROM_RETRY_ENABLE
);
6820 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
6821 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
))
6822 val
|= PCISTATE_RETRY_SAME_DMA
;
6823 /* Allow reads and writes to the APE register and memory space. */
6824 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
6825 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
6826 PCISTATE_ALLOW_APE_SHMEM_WR
|
6827 PCISTATE_ALLOW_APE_PSPACE_WR
;
6828 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, val
);
6830 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, tp
->pci_cmd
);
6832 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
) {
6833 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
6834 pcie_set_readrq(tp
->pdev
, 4096);
6836 pci_write_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
6837 tp
->pci_cacheline_sz
);
6838 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
6843 /* Make sure PCI-X relaxed ordering bit is clear. */
6844 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
6847 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
6849 pcix_cmd
&= ~PCI_X_CMD_ERO
;
6850 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
6854 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
6856 /* Chip reset on 5780 will reset MSI enable bit,
6857 * so need to restore it.
6859 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
6862 pci_read_config_word(tp
->pdev
,
6863 tp
->msi_cap
+ PCI_MSI_FLAGS
,
6865 pci_write_config_word(tp
->pdev
,
6866 tp
->msi_cap
+ PCI_MSI_FLAGS
,
6867 ctrl
| PCI_MSI_FLAGS_ENABLE
);
6868 val
= tr32(MSGINT_MODE
);
6869 tw32(MSGINT_MODE
, val
| MSGINT_MODE_ENABLE
);
6874 static void tg3_stop_fw(struct tg3
*);
6876 /* tp->lock is held. */
6877 static int tg3_chip_reset(struct tg3
*tp
)
6880 void (*write_op
)(struct tg3
*, u32
, u32
);
6885 tg3_ape_lock(tp
, TG3_APE_LOCK_GRC
);
6887 /* No matching tg3_nvram_unlock() after this because
6888 * chip reset below will undo the nvram lock.
6890 tp
->nvram_lock_cnt
= 0;
6892 /* GRC_MISC_CFG core clock reset will clear the memory
6893 * enable bit in PCI register 4 and the MSI enable bit
6894 * on some chips, so we save relevant registers here.
6896 tg3_save_pci_state(tp
);
6898 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
6899 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
))
6900 tw32(GRC_FASTBOOT_PC
, 0);
6903 * We must avoid the readl() that normally takes place.
6904 * It locks machines, causes machine checks, and other
6905 * fun things. So, temporarily disable the 5701
6906 * hardware workaround, while we do the reset.
6908 write_op
= tp
->write32
;
6909 if (write_op
== tg3_write_flush_reg32
)
6910 tp
->write32
= tg3_write32
;
6912 /* Prevent the irq handler from reading or writing PCI registers
6913 * during chip reset when the memory enable bit in the PCI command
6914 * register may be cleared. The chip does not generate interrupt
6915 * at this time, but the irq handler may still be called due to irq
6916 * sharing or irqpoll.
6918 tp
->tg3_flags
|= TG3_FLAG_CHIP_RESETTING
;
6919 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6920 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6921 if (tnapi
->hw_status
) {
6922 tnapi
->hw_status
->status
= 0;
6923 tnapi
->hw_status
->status_tag
= 0;
6925 tnapi
->last_tag
= 0;
6926 tnapi
->last_irq_tag
= 0;
6930 for (i
= 0; i
< tp
->irq_cnt
; i
++)
6931 synchronize_irq(tp
->napi
[i
].irq_vec
);
6933 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
6934 val
= tr32(TG3_PCIE_LNKCTL
) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
6935 tw32(TG3_PCIE_LNKCTL
, val
| TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
);
6939 val
= GRC_MISC_CFG_CORECLK_RESET
;
6941 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
6942 /* Force PCIe 1.0a mode */
6943 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
6944 !(tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) &&
6945 tr32(TG3_PCIE_PHY_TSTCTL
) ==
6946 (TG3_PCIE_PHY_TSTCTL_PCIE10
| TG3_PCIE_PHY_TSTCTL_PSCRAM
))
6947 tw32(TG3_PCIE_PHY_TSTCTL
, TG3_PCIE_PHY_TSTCTL_PSCRAM
);
6949 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
) {
6950 tw32(GRC_MISC_CFG
, (1 << 29));
6955 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6956 tw32(VCPU_STATUS
, tr32(VCPU_STATUS
) | VCPU_STATUS_DRV_RESET
);
6957 tw32(GRC_VCPU_EXT_CTRL
,
6958 tr32(GRC_VCPU_EXT_CTRL
) & ~GRC_VCPU_EXT_CTRL_HALT_CPU
);
6961 /* Manage gphy power for all CPMU absent PCIe devices. */
6962 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
6963 !(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
))
6964 val
|= GRC_MISC_CFG_KEEP_GPHY_POWER
;
6966 tw32(GRC_MISC_CFG
, val
);
6968 /* restore 5701 hardware bug workaround write method */
6969 tp
->write32
= write_op
;
6971 /* Unfortunately, we have to delay before the PCI read back.
6972 * Some 575X chips even will not respond to a PCI cfg access
6973 * when the reset command is given to the chip.
6975 * How do these hardware designers expect things to work
6976 * properly if the PCI write is posted for a long period
6977 * of time? It is always necessary to have some method by
6978 * which a register read back can occur to push the write
6979 * out which does the reset.
6981 * For most tg3 variants the trick below was working.
6986 /* Flush PCI posted writes. The normal MMIO registers
6987 * are inaccessible at this time so this is the only
6988 * way to make this reliably (actually, this is no longer
6989 * the case, see above). I tried to use indirect
6990 * register read/write but this upset some 5701 variants.
6992 pci_read_config_dword(tp
->pdev
, PCI_COMMAND
, &val
);
6996 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) && tp
->pcie_cap
) {
6999 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
) {
7003 /* Wait for link training to complete. */
7004 for (i
= 0; i
< 5000; i
++)
7007 pci_read_config_dword(tp
->pdev
, 0xc4, &cfg_val
);
7008 pci_write_config_dword(tp
->pdev
, 0xc4,
7009 cfg_val
| (1 << 15));
7012 /* Clear the "no snoop" and "relaxed ordering" bits. */
7013 pci_read_config_word(tp
->pdev
,
7014 tp
->pcie_cap
+ PCI_EXP_DEVCTL
,
7016 val16
&= ~(PCI_EXP_DEVCTL_RELAX_EN
|
7017 PCI_EXP_DEVCTL_NOSNOOP_EN
);
7019 * Older PCIe devices only support the 128 byte
7020 * MPS setting. Enforce the restriction.
7022 if (!(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
))
7023 val16
&= ~PCI_EXP_DEVCTL_PAYLOAD
;
7024 pci_write_config_word(tp
->pdev
,
7025 tp
->pcie_cap
+ PCI_EXP_DEVCTL
,
7028 pcie_set_readrq(tp
->pdev
, 4096);
7030 /* Clear error status */
7031 pci_write_config_word(tp
->pdev
,
7032 tp
->pcie_cap
+ PCI_EXP_DEVSTA
,
7033 PCI_EXP_DEVSTA_CED
|
7034 PCI_EXP_DEVSTA_NFED
|
7035 PCI_EXP_DEVSTA_FED
|
7036 PCI_EXP_DEVSTA_URD
);
7039 tg3_restore_pci_state(tp
);
7041 tp
->tg3_flags
&= ~TG3_FLAG_CHIP_RESETTING
;
7044 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
7045 val
= tr32(MEMARB_MODE
);
7046 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
7048 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A3
) {
7050 tw32(0x5000, 0x400);
7053 tw32(GRC_MODE
, tp
->grc_mode
);
7055 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
) {
7058 tw32(0xc4, val
| (1 << 15));
7061 if ((tp
->nic_sram_data_cfg
& NIC_SRAM_DATA_CFG_MINI_PCI
) != 0 &&
7062 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
7063 tp
->pci_clock_ctrl
|= CLOCK_CTRL_CLKRUN_OENABLE
;
7064 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
)
7065 tp
->pci_clock_ctrl
|= CLOCK_CTRL_FORCE_CLKRUN
;
7066 tw32(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
7069 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
7070 tp
->mac_mode
= MAC_MODE_PORT_MODE_TBI
;
7071 tw32_f(MAC_MODE
, tp
->mac_mode
);
7072 } else if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) {
7073 tp
->mac_mode
= MAC_MODE_PORT_MODE_GMII
;
7074 tw32_f(MAC_MODE
, tp
->mac_mode
);
7075 } else if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
7076 tp
->mac_mode
&= (MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
);
7077 if (tp
->mac_mode
& MAC_MODE_APE_TX_EN
)
7078 tp
->mac_mode
|= MAC_MODE_TDE_ENABLE
;
7079 tw32_f(MAC_MODE
, tp
->mac_mode
);
7081 tw32_f(MAC_MODE
, 0);
7084 tg3_ape_unlock(tp
, TG3_APE_LOCK_GRC
);
7086 err
= tg3_poll_fw(tp
);
7092 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
7093 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
&&
7094 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
7095 !(tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)) {
7098 tw32(0x7c00, val
| (1 << 25));
7101 /* Reprobe ASF enable state. */
7102 tp
->tg3_flags
&= ~TG3_FLAG_ENABLE_ASF
;
7103 tp
->tg3_flags2
&= ~TG3_FLG2_ASF_NEW_HANDSHAKE
;
7104 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
7105 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
7108 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
7109 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
7110 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
7111 tp
->last_event_jiffies
= jiffies
;
7112 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
7113 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
7120 /* tp->lock is held. */
7121 static void tg3_stop_fw(struct tg3
*tp
)
7123 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
7124 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
7125 /* Wait for RX cpu to ACK the previous event. */
7126 tg3_wait_for_event_ack(tp
);
7128 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_PAUSE_FW
);
7130 tg3_generate_fw_event(tp
);
7132 /* Wait for RX cpu to ACK this event. */
7133 tg3_wait_for_event_ack(tp
);
7137 /* tp->lock is held. */
7138 static int tg3_halt(struct tg3
*tp
, int kind
, int silent
)
7144 tg3_write_sig_pre_reset(tp
, kind
);
7146 tg3_abort_hw(tp
, silent
);
7147 err
= tg3_chip_reset(tp
);
7149 __tg3_set_mac_addr(tp
, 0);
7151 tg3_write_sig_legacy(tp
, kind
);
7152 tg3_write_sig_post_reset(tp
, kind
);
7160 #define RX_CPU_SCRATCH_BASE 0x30000
7161 #define RX_CPU_SCRATCH_SIZE 0x04000
7162 #define TX_CPU_SCRATCH_BASE 0x34000
7163 #define TX_CPU_SCRATCH_SIZE 0x04000
7165 /* tp->lock is held. */
7166 static int tg3_halt_cpu(struct tg3
*tp
, u32 offset
)
7170 BUG_ON(offset
== TX_CPU_BASE
&&
7171 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
));
7173 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
7174 u32 val
= tr32(GRC_VCPU_EXT_CTRL
);
7176 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_HALT_CPU
);
7179 if (offset
== RX_CPU_BASE
) {
7180 for (i
= 0; i
< 10000; i
++) {
7181 tw32(offset
+ CPU_STATE
, 0xffffffff);
7182 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
7183 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
7187 tw32(offset
+ CPU_STATE
, 0xffffffff);
7188 tw32_f(offset
+ CPU_MODE
, CPU_MODE_HALT
);
7191 for (i
= 0; i
< 10000; i
++) {
7192 tw32(offset
+ CPU_STATE
, 0xffffffff);
7193 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
7194 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
7200 netdev_err(tp
->dev
, "%s timed out, %s CPU\n",
7201 __func__
, offset
== RX_CPU_BASE
? "RX" : "TX");
7205 /* Clear firmware's nvram arbitration. */
7206 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
7207 tw32(NVRAM_SWARB
, SWARB_REQ_CLR0
);
7212 unsigned int fw_base
;
7213 unsigned int fw_len
;
7214 const __be32
*fw_data
;
7217 /* tp->lock is held. */
7218 static int tg3_load_firmware_cpu(struct tg3
*tp
, u32 cpu_base
, u32 cpu_scratch_base
,
7219 int cpu_scratch_size
, struct fw_info
*info
)
7221 int err
, lock_err
, i
;
7222 void (*write_op
)(struct tg3
*, u32
, u32
);
7224 if (cpu_base
== TX_CPU_BASE
&&
7225 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7227 "%s: Trying to load TX cpu firmware which is 5705\n",
7232 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
7233 write_op
= tg3_write_mem
;
7235 write_op
= tg3_write_indirect_reg32
;
7237 /* It is possible that bootcode is still loading at this point.
7238 * Get the nvram lock first before halting the cpu.
7240 lock_err
= tg3_nvram_lock(tp
);
7241 err
= tg3_halt_cpu(tp
, cpu_base
);
7243 tg3_nvram_unlock(tp
);
7247 for (i
= 0; i
< cpu_scratch_size
; i
+= sizeof(u32
))
7248 write_op(tp
, cpu_scratch_base
+ i
, 0);
7249 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7250 tw32(cpu_base
+ CPU_MODE
, tr32(cpu_base
+CPU_MODE
)|CPU_MODE_HALT
);
7251 for (i
= 0; i
< (info
->fw_len
/ sizeof(u32
)); i
++)
7252 write_op(tp
, (cpu_scratch_base
+
7253 (info
->fw_base
& 0xffff) +
7255 be32_to_cpu(info
->fw_data
[i
]));
7263 /* tp->lock is held. */
7264 static int tg3_load_5701_a0_firmware_fix(struct tg3
*tp
)
7266 struct fw_info info
;
7267 const __be32
*fw_data
;
7270 fw_data
= (void *)tp
->fw
->data
;
7272 /* Firmware blob starts with version numbers, followed by
7273 start address and length. We are setting complete length.
7274 length = end_address_of_bss - start_address_of_text.
7275 Remainder is the blob to be loaded contiguously
7276 from start address. */
7278 info
.fw_base
= be32_to_cpu(fw_data
[1]);
7279 info
.fw_len
= tp
->fw
->size
- 12;
7280 info
.fw_data
= &fw_data
[3];
7282 err
= tg3_load_firmware_cpu(tp
, RX_CPU_BASE
,
7283 RX_CPU_SCRATCH_BASE
, RX_CPU_SCRATCH_SIZE
,
7288 err
= tg3_load_firmware_cpu(tp
, TX_CPU_BASE
,
7289 TX_CPU_SCRATCH_BASE
, TX_CPU_SCRATCH_SIZE
,
7294 /* Now startup only the RX cpu. */
7295 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
7296 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
7298 for (i
= 0; i
< 5; i
++) {
7299 if (tr32(RX_CPU_BASE
+ CPU_PC
) == info
.fw_base
)
7301 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
7302 tw32(RX_CPU_BASE
+ CPU_MODE
, CPU_MODE_HALT
);
7303 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
7307 netdev_err(tp
->dev
, "%s fails to set RX CPU PC, is %08x "
7308 "should be %08x\n", __func__
,
7309 tr32(RX_CPU_BASE
+ CPU_PC
), info
.fw_base
);
7312 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
7313 tw32_f(RX_CPU_BASE
+ CPU_MODE
, 0x00000000);
7318 /* 5705 needs a special version of the TSO firmware. */
7320 /* tp->lock is held. */
7321 static int tg3_load_tso_firmware(struct tg3
*tp
)
7323 struct fw_info info
;
7324 const __be32
*fw_data
;
7325 unsigned long cpu_base
, cpu_scratch_base
, cpu_scratch_size
;
7328 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
7331 fw_data
= (void *)tp
->fw
->data
;
7333 /* Firmware blob starts with version numbers, followed by
7334 start address and length. We are setting complete length.
7335 length = end_address_of_bss - start_address_of_text.
7336 Remainder is the blob to be loaded contiguously
7337 from start address. */
7339 info
.fw_base
= be32_to_cpu(fw_data
[1]);
7340 cpu_scratch_size
= tp
->fw_len
;
7341 info
.fw_len
= tp
->fw
->size
- 12;
7342 info
.fw_data
= &fw_data
[3];
7344 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
7345 cpu_base
= RX_CPU_BASE
;
7346 cpu_scratch_base
= NIC_SRAM_MBUF_POOL_BASE5705
;
7348 cpu_base
= TX_CPU_BASE
;
7349 cpu_scratch_base
= TX_CPU_SCRATCH_BASE
;
7350 cpu_scratch_size
= TX_CPU_SCRATCH_SIZE
;
7353 err
= tg3_load_firmware_cpu(tp
, cpu_base
,
7354 cpu_scratch_base
, cpu_scratch_size
,
7359 /* Now startup the cpu. */
7360 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7361 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
7363 for (i
= 0; i
< 5; i
++) {
7364 if (tr32(cpu_base
+ CPU_PC
) == info
.fw_base
)
7366 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7367 tw32(cpu_base
+ CPU_MODE
, CPU_MODE_HALT
);
7368 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
7373 "%s fails to set CPU PC, is %08x should be %08x\n",
7374 __func__
, tr32(cpu_base
+ CPU_PC
), info
.fw_base
);
7377 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7378 tw32_f(cpu_base
+ CPU_MODE
, 0x00000000);
7383 static int tg3_set_mac_addr(struct net_device
*dev
, void *p
)
7385 struct tg3
*tp
= netdev_priv(dev
);
7386 struct sockaddr
*addr
= p
;
7387 int err
= 0, skip_mac_1
= 0;
7389 if (!is_valid_ether_addr(addr
->sa_data
))
7392 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
7394 if (!netif_running(dev
))
7397 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
7398 u32 addr0_high
, addr0_low
, addr1_high
, addr1_low
;
7400 addr0_high
= tr32(MAC_ADDR_0_HIGH
);
7401 addr0_low
= tr32(MAC_ADDR_0_LOW
);
7402 addr1_high
= tr32(MAC_ADDR_1_HIGH
);
7403 addr1_low
= tr32(MAC_ADDR_1_LOW
);
7405 /* Skip MAC addr 1 if ASF is using it. */
7406 if ((addr0_high
!= addr1_high
|| addr0_low
!= addr1_low
) &&
7407 !(addr1_high
== 0 && addr1_low
== 0))
7410 spin_lock_bh(&tp
->lock
);
7411 __tg3_set_mac_addr(tp
, skip_mac_1
);
7412 spin_unlock_bh(&tp
->lock
);
7417 /* tp->lock is held. */
7418 static void tg3_set_bdinfo(struct tg3
*tp
, u32 bdinfo_addr
,
7419 dma_addr_t mapping
, u32 maxlen_flags
,
7423 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
7424 ((u64
) mapping
>> 32));
7426 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
),
7427 ((u64
) mapping
& 0xffffffff));
7429 (bdinfo_addr
+ TG3_BDINFO_MAXLEN_FLAGS
),
7432 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7434 (bdinfo_addr
+ TG3_BDINFO_NIC_ADDR
),
7438 static void __tg3_set_rx_mode(struct net_device
*);
7439 static void __tg3_set_coalesce(struct tg3
*tp
, struct ethtool_coalesce
*ec
)
7443 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)) {
7444 tw32(HOSTCC_TXCOL_TICKS
, ec
->tx_coalesce_usecs
);
7445 tw32(HOSTCC_TXMAX_FRAMES
, ec
->tx_max_coalesced_frames
);
7446 tw32(HOSTCC_TXCOAL_MAXF_INT
, ec
->tx_max_coalesced_frames_irq
);
7448 tw32(HOSTCC_TXCOL_TICKS
, 0);
7449 tw32(HOSTCC_TXMAX_FRAMES
, 0);
7450 tw32(HOSTCC_TXCOAL_MAXF_INT
, 0);
7453 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)) {
7454 tw32(HOSTCC_RXCOL_TICKS
, ec
->rx_coalesce_usecs
);
7455 tw32(HOSTCC_RXMAX_FRAMES
, ec
->rx_max_coalesced_frames
);
7456 tw32(HOSTCC_RXCOAL_MAXF_INT
, ec
->rx_max_coalesced_frames_irq
);
7458 tw32(HOSTCC_RXCOL_TICKS
, 0);
7459 tw32(HOSTCC_RXMAX_FRAMES
, 0);
7460 tw32(HOSTCC_RXCOAL_MAXF_INT
, 0);
7463 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7464 u32 val
= ec
->stats_block_coalesce_usecs
;
7466 tw32(HOSTCC_RXCOAL_TICK_INT
, ec
->rx_coalesce_usecs_irq
);
7467 tw32(HOSTCC_TXCOAL_TICK_INT
, ec
->tx_coalesce_usecs_irq
);
7469 if (!netif_carrier_ok(tp
->dev
))
7472 tw32(HOSTCC_STAT_COAL_TICKS
, val
);
7475 for (i
= 0; i
< tp
->irq_cnt
- 1; i
++) {
7478 reg
= HOSTCC_RXCOL_TICKS_VEC1
+ i
* 0x18;
7479 tw32(reg
, ec
->rx_coalesce_usecs
);
7480 reg
= HOSTCC_RXMAX_FRAMES_VEC1
+ i
* 0x18;
7481 tw32(reg
, ec
->rx_max_coalesced_frames
);
7482 reg
= HOSTCC_RXCOAL_MAXF_INT_VEC1
+ i
* 0x18;
7483 tw32(reg
, ec
->rx_max_coalesced_frames_irq
);
7485 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
) {
7486 reg
= HOSTCC_TXCOL_TICKS_VEC1
+ i
* 0x18;
7487 tw32(reg
, ec
->tx_coalesce_usecs
);
7488 reg
= HOSTCC_TXMAX_FRAMES_VEC1
+ i
* 0x18;
7489 tw32(reg
, ec
->tx_max_coalesced_frames
);
7490 reg
= HOSTCC_TXCOAL_MAXF_INT_VEC1
+ i
* 0x18;
7491 tw32(reg
, ec
->tx_max_coalesced_frames_irq
);
7495 for (; i
< tp
->irq_max
- 1; i
++) {
7496 tw32(HOSTCC_RXCOL_TICKS_VEC1
+ i
* 0x18, 0);
7497 tw32(HOSTCC_RXMAX_FRAMES_VEC1
+ i
* 0x18, 0);
7498 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1
+ i
* 0x18, 0);
7500 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
) {
7501 tw32(HOSTCC_TXCOL_TICKS_VEC1
+ i
* 0x18, 0);
7502 tw32(HOSTCC_TXMAX_FRAMES_VEC1
+ i
* 0x18, 0);
7503 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1
+ i
* 0x18, 0);
7508 /* tp->lock is held. */
7509 static void tg3_rings_reset(struct tg3
*tp
)
7512 u32 stblk
, txrcb
, rxrcb
, limit
;
7513 struct tg3_napi
*tnapi
= &tp
->napi
[0];
7515 /* Disable all transmit rings but the first. */
7516 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7517 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 16;
7518 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
7519 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 2;
7521 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
;
7523 for (txrcb
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
;
7524 txrcb
< limit
; txrcb
+= TG3_BDINFO_SIZE
)
7525 tg3_write_mem(tp
, txrcb
+ TG3_BDINFO_MAXLEN_FLAGS
,
7526 BDINFO_FLAGS_DISABLED
);
7529 /* Disable all receive return rings but the first. */
7530 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
7531 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
)
7532 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 17;
7533 else if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7534 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 16;
7535 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
7536 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
7537 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 4;
7539 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
;
7541 for (rxrcb
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
;
7542 rxrcb
< limit
; rxrcb
+= TG3_BDINFO_SIZE
)
7543 tg3_write_mem(tp
, rxrcb
+ TG3_BDINFO_MAXLEN_FLAGS
,
7544 BDINFO_FLAGS_DISABLED
);
7546 /* Disable interrupts */
7547 tw32_mailbox_f(tp
->napi
[0].int_mbox
, 1);
7549 /* Zero mailbox registers. */
7550 if (tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
) {
7551 for (i
= 1; i
< TG3_IRQ_MAX_VECS
; i
++) {
7552 tp
->napi
[i
].tx_prod
= 0;
7553 tp
->napi
[i
].tx_cons
= 0;
7554 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
7555 tw32_mailbox(tp
->napi
[i
].prodmbox
, 0);
7556 tw32_rx_mbox(tp
->napi
[i
].consmbox
, 0);
7557 tw32_mailbox_f(tp
->napi
[i
].int_mbox
, 1);
7559 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
))
7560 tw32_mailbox(tp
->napi
[0].prodmbox
, 0);
7562 tp
->napi
[0].tx_prod
= 0;
7563 tp
->napi
[0].tx_cons
= 0;
7564 tw32_mailbox(tp
->napi
[0].prodmbox
, 0);
7565 tw32_rx_mbox(tp
->napi
[0].consmbox
, 0);
7568 /* Make sure the NIC-based send BD rings are disabled. */
7569 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7570 u32 mbox
= MAILBOX_SNDNIC_PROD_IDX_0
+ TG3_64BIT_REG_LOW
;
7571 for (i
= 0; i
< 16; i
++)
7572 tw32_tx_mbox(mbox
+ i
* 8, 0);
7575 txrcb
= NIC_SRAM_SEND_RCB
;
7576 rxrcb
= NIC_SRAM_RCV_RET_RCB
;
7578 /* Clear status block in ram. */
7579 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
7581 /* Set status block DMA address */
7582 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7583 ((u64
) tnapi
->status_mapping
>> 32));
7584 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7585 ((u64
) tnapi
->status_mapping
& 0xffffffff));
7587 if (tnapi
->tx_ring
) {
7588 tg3_set_bdinfo(tp
, txrcb
, tnapi
->tx_desc_mapping
,
7589 (TG3_TX_RING_SIZE
<<
7590 BDINFO_FLAGS_MAXLEN_SHIFT
),
7591 NIC_SRAM_TX_BUFFER_DESC
);
7592 txrcb
+= TG3_BDINFO_SIZE
;
7595 if (tnapi
->rx_rcb
) {
7596 tg3_set_bdinfo(tp
, rxrcb
, tnapi
->rx_rcb_mapping
,
7597 (TG3_RX_RCB_RING_SIZE(tp
) <<
7598 BDINFO_FLAGS_MAXLEN_SHIFT
), 0);
7599 rxrcb
+= TG3_BDINFO_SIZE
;
7602 stblk
= HOSTCC_STATBLCK_RING1
;
7604 for (i
= 1, tnapi
++; i
< tp
->irq_cnt
; i
++, tnapi
++) {
7605 u64 mapping
= (u64
)tnapi
->status_mapping
;
7606 tw32(stblk
+ TG3_64BIT_REG_HIGH
, mapping
>> 32);
7607 tw32(stblk
+ TG3_64BIT_REG_LOW
, mapping
& 0xffffffff);
7609 /* Clear status block in ram. */
7610 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
7612 if (tnapi
->tx_ring
) {
7613 tg3_set_bdinfo(tp
, txrcb
, tnapi
->tx_desc_mapping
,
7614 (TG3_TX_RING_SIZE
<<
7615 BDINFO_FLAGS_MAXLEN_SHIFT
),
7616 NIC_SRAM_TX_BUFFER_DESC
);
7617 txrcb
+= TG3_BDINFO_SIZE
;
7620 tg3_set_bdinfo(tp
, rxrcb
, tnapi
->rx_rcb_mapping
,
7621 (TG3_RX_RCB_RING_SIZE(tp
) <<
7622 BDINFO_FLAGS_MAXLEN_SHIFT
), 0);
7625 rxrcb
+= TG3_BDINFO_SIZE
;
7629 /* tp->lock is held. */
7630 static int tg3_reset_hw(struct tg3
*tp
, int reset_phy
)
7632 u32 val
, rdmac_mode
;
7634 struct tg3_rx_prodring_set
*tpr
= &tp
->prodring
[0];
7636 tg3_disable_ints(tp
);
7640 tg3_write_sig_pre_reset(tp
, RESET_KIND_INIT
);
7642 if (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)
7643 tg3_abort_hw(tp
, 1);
7648 err
= tg3_chip_reset(tp
);
7652 tg3_write_sig_legacy(tp
, RESET_KIND_INIT
);
7654 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
7655 val
= tr32(TG3_CPMU_CTRL
);
7656 val
&= ~(CPMU_CTRL_LINK_AWARE_MODE
| CPMU_CTRL_LINK_IDLE_MODE
);
7657 tw32(TG3_CPMU_CTRL
, val
);
7659 val
= tr32(TG3_CPMU_LSPD_10MB_CLK
);
7660 val
&= ~CPMU_LSPD_10MB_MACCLK_MASK
;
7661 val
|= CPMU_LSPD_10MB_MACCLK_6_25
;
7662 tw32(TG3_CPMU_LSPD_10MB_CLK
, val
);
7664 val
= tr32(TG3_CPMU_LNK_AWARE_PWRMD
);
7665 val
&= ~CPMU_LNK_AWARE_MACCLK_MASK
;
7666 val
|= CPMU_LNK_AWARE_MACCLK_6_25
;
7667 tw32(TG3_CPMU_LNK_AWARE_PWRMD
, val
);
7669 val
= tr32(TG3_CPMU_HST_ACC
);
7670 val
&= ~CPMU_HST_ACC_MACCLK_MASK
;
7671 val
|= CPMU_HST_ACC_MACCLK_6_25
;
7672 tw32(TG3_CPMU_HST_ACC
, val
);
7675 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
7676 val
= tr32(PCIE_PWR_MGMT_THRESH
) & ~PCIE_PWR_MGMT_L1_THRESH_MSK
;
7677 val
|= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN
|
7678 PCIE_PWR_MGMT_L1_THRESH_4MS
;
7679 tw32(PCIE_PWR_MGMT_THRESH
, val
);
7681 val
= tr32(TG3_PCIE_EIDLE_DELAY
) & ~TG3_PCIE_EIDLE_DELAY_MASK
;
7682 tw32(TG3_PCIE_EIDLE_DELAY
, val
| TG3_PCIE_EIDLE_DELAY_13_CLKS
);
7684 tw32(TG3_CORR_ERR_STAT
, TG3_CORR_ERR_STAT_CLEAR
);
7686 val
= tr32(TG3_PCIE_LNKCTL
) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
7687 tw32(TG3_PCIE_LNKCTL
, val
| TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
);
7690 if (tp
->tg3_flags3
& TG3_FLG3_L1PLLPD_EN
) {
7691 u32 grc_mode
= tr32(GRC_MODE
);
7693 /* Access the lower 1K of PL PCIE block registers. */
7694 val
= grc_mode
& ~GRC_MODE_PCIE_PORT_MASK
;
7695 tw32(GRC_MODE
, val
| GRC_MODE_PCIE_PL_SEL
);
7697 val
= tr32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL1
);
7698 tw32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL1
,
7699 val
| TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN
);
7701 tw32(GRC_MODE
, grc_mode
);
7704 if (tp
->pci_chip_rev_id
== CHIPREV_ID_57765_A0
) {
7705 u32 grc_mode
= tr32(GRC_MODE
);
7707 /* Access the lower 1K of PL PCIE block registers. */
7708 val
= grc_mode
& ~GRC_MODE_PCIE_PORT_MASK
;
7709 tw32(GRC_MODE
, val
| GRC_MODE_PCIE_PL_SEL
);
7711 val
= tr32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL5
);
7712 tw32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL5
,
7713 val
| TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ
);
7715 tw32(GRC_MODE
, grc_mode
);
7717 val
= tr32(TG3_CPMU_LSPD_10MB_CLK
);
7718 val
&= ~CPMU_LSPD_10MB_MACCLK_MASK
;
7719 val
|= CPMU_LSPD_10MB_MACCLK_6_25
;
7720 tw32(TG3_CPMU_LSPD_10MB_CLK
, val
);
7723 /* This works around an issue with Athlon chipsets on
7724 * B3 tigon3 silicon. This bit has no effect on any
7725 * other revision. But do not set this on PCI Express
7726 * chips and don't even touch the clocks if the CPMU is present.
7728 if (!(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)) {
7729 if (!(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
7730 tp
->pci_clock_ctrl
|= CLOCK_CTRL_DELAY_PCI_GRANT
;
7731 tw32_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
7734 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
7735 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
7736 val
= tr32(TG3PCI_PCISTATE
);
7737 val
|= PCISTATE_RETRY_SAME_DMA
;
7738 tw32(TG3PCI_PCISTATE
, val
);
7741 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
7742 /* Allow reads and writes to the
7743 * APE register and memory space.
7745 val
= tr32(TG3PCI_PCISTATE
);
7746 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
7747 PCISTATE_ALLOW_APE_SHMEM_WR
|
7748 PCISTATE_ALLOW_APE_PSPACE_WR
;
7749 tw32(TG3PCI_PCISTATE
, val
);
7752 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_BX
) {
7753 /* Enable some hw fixes. */
7754 val
= tr32(TG3PCI_MSI_DATA
);
7755 val
|= (1 << 26) | (1 << 28) | (1 << 29);
7756 tw32(TG3PCI_MSI_DATA
, val
);
7759 /* Descriptor ring init may make accesses to the
7760 * NIC SRAM area to setup the TX descriptors, so we
7761 * can only do this after the hardware has been
7762 * successfully reset.
7764 err
= tg3_init_rings(tp
);
7768 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) {
7769 val
= tr32(TG3PCI_DMA_RW_CTRL
) &
7770 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT
;
7771 if (tp
->pci_chip_rev_id
== CHIPREV_ID_57765_A0
)
7772 val
&= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK
;
7773 tw32(TG3PCI_DMA_RW_CTRL
, val
| tp
->dma_rwctrl
);
7774 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
&&
7775 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5761
) {
7776 /* This value is determined during the probe time DMA
7777 * engine test, tg3_test_dma.
7779 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
7782 tp
->grc_mode
&= ~(GRC_MODE_HOST_SENDBDS
|
7783 GRC_MODE_4X_NIC_SEND_RINGS
|
7784 GRC_MODE_NO_TX_PHDR_CSUM
|
7785 GRC_MODE_NO_RX_PHDR_CSUM
);
7786 tp
->grc_mode
|= GRC_MODE_HOST_SENDBDS
;
7788 /* Pseudo-header checksum is done by hardware logic and not
7789 * the offload processers, so make the chip do the pseudo-
7790 * header checksums on receive. For transmit it is more
7791 * convenient to do the pseudo-header checksum in software
7792 * as Linux does that on transmit for us in all cases.
7794 tp
->grc_mode
|= GRC_MODE_NO_TX_PHDR_CSUM
;
7798 (GRC_MODE_IRQ_ON_MAC_ATTN
| GRC_MODE_HOST_STACKUP
));
7800 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7801 val
= tr32(GRC_MISC_CFG
);
7803 val
|= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT
);
7804 tw32(GRC_MISC_CFG
, val
);
7806 /* Initialize MBUF/DESC pool. */
7807 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
7809 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5705
) {
7810 tw32(BUFMGR_MB_POOL_ADDR
, NIC_SRAM_MBUF_POOL_BASE
);
7811 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
7812 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE64
);
7814 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE96
);
7815 tw32(BUFMGR_DMA_DESC_POOL_ADDR
, NIC_SRAM_DMA_DESC_POOL_BASE
);
7816 tw32(BUFMGR_DMA_DESC_POOL_SIZE
, NIC_SRAM_DMA_DESC_POOL_SIZE
);
7817 } else if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
7820 fw_len
= tp
->fw_len
;
7821 fw_len
= (fw_len
+ (0x80 - 1)) & ~(0x80 - 1);
7822 tw32(BUFMGR_MB_POOL_ADDR
,
7823 NIC_SRAM_MBUF_POOL_BASE5705
+ fw_len
);
7824 tw32(BUFMGR_MB_POOL_SIZE
,
7825 NIC_SRAM_MBUF_POOL_SIZE5705
- fw_len
- 0xa00);
7828 if (tp
->dev
->mtu
<= ETH_DATA_LEN
) {
7829 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
7830 tp
->bufmgr_config
.mbuf_read_dma_low_water
);
7831 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
7832 tp
->bufmgr_config
.mbuf_mac_rx_low_water
);
7833 tw32(BUFMGR_MB_HIGH_WATER
,
7834 tp
->bufmgr_config
.mbuf_high_water
);
7836 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
7837 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
);
7838 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
7839 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
);
7840 tw32(BUFMGR_MB_HIGH_WATER
,
7841 tp
->bufmgr_config
.mbuf_high_water_jumbo
);
7843 tw32(BUFMGR_DMA_LOW_WATER
,
7844 tp
->bufmgr_config
.dma_low_water
);
7845 tw32(BUFMGR_DMA_HIGH_WATER
,
7846 tp
->bufmgr_config
.dma_high_water
);
7848 tw32(BUFMGR_MODE
, BUFMGR_MODE_ENABLE
| BUFMGR_MODE_ATTN_ENABLE
);
7849 for (i
= 0; i
< 2000; i
++) {
7850 if (tr32(BUFMGR_MODE
) & BUFMGR_MODE_ENABLE
)
7855 netdev_err(tp
->dev
, "%s cannot enable BUFMGR\n", __func__
);
7859 /* Setup replenish threshold. */
7860 val
= tp
->rx_pending
/ 8;
7863 else if (val
> tp
->rx_std_max_post
)
7864 val
= tp
->rx_std_max_post
;
7865 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
7866 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5906_A1
)
7867 tw32(ISO_PKT_TX
, (tr32(ISO_PKT_TX
) & ~0x3) | 0x2);
7869 if (val
> (TG3_RX_INTERNAL_RING_SZ_5906
/ 2))
7870 val
= TG3_RX_INTERNAL_RING_SZ_5906
/ 2;
7873 tw32(RCVBDI_STD_THRESH
, val
);
7875 /* Initialize TG3_BDINFO's at:
7876 * RCVDBDI_STD_BD: standard eth size rx ring
7877 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7878 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7881 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7882 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7883 * ring attribute flags
7884 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7886 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7887 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7889 * The size of each ring is fixed in the firmware, but the location is
7892 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7893 ((u64
) tpr
->rx_std_mapping
>> 32));
7894 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7895 ((u64
) tpr
->rx_std_mapping
& 0xffffffff));
7896 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
&&
7897 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5719
)
7898 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_NIC_ADDR
,
7899 NIC_SRAM_RX_BUFFER_DESC
);
7901 /* Disable the mini ring */
7902 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7903 tw32(RCVDBDI_MINI_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7904 BDINFO_FLAGS_DISABLED
);
7906 /* Program the jumbo buffer descriptor ring control
7907 * blocks on those devices that have them.
7909 if ((tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) &&
7910 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
7911 /* Setup replenish threshold. */
7912 tw32(RCVBDI_JUMBO_THRESH
, tp
->rx_jumbo_pending
/ 8);
7914 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) {
7915 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7916 ((u64
) tpr
->rx_jmb_mapping
>> 32));
7917 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7918 ((u64
) tpr
->rx_jmb_mapping
& 0xffffffff));
7919 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7920 (RX_JUMBO_MAX_SIZE
<< BDINFO_FLAGS_MAXLEN_SHIFT
) |
7921 BDINFO_FLAGS_USE_EXT_RECV
);
7922 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
) ||
7923 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
7924 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_NIC_ADDR
,
7925 NIC_SRAM_RX_JUMBO_BUFFER_DESC
);
7927 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7928 BDINFO_FLAGS_DISABLED
);
7931 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)
7932 val
= (RX_STD_MAX_SIZE_5705
<< BDINFO_FLAGS_MAXLEN_SHIFT
) |
7933 (TG3_RX_STD_DMA_SZ
<< 2);
7935 val
= TG3_RX_STD_DMA_SZ
<< BDINFO_FLAGS_MAXLEN_SHIFT
;
7937 val
= RX_STD_MAX_SIZE_5705
<< BDINFO_FLAGS_MAXLEN_SHIFT
;
7939 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_MAXLEN_FLAGS
, val
);
7941 tpr
->rx_std_prod_idx
= tp
->rx_pending
;
7942 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
, tpr
->rx_std_prod_idx
);
7944 tpr
->rx_jmb_prod_idx
= (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) ?
7945 tp
->rx_jumbo_pending
: 0;
7946 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
, tpr
->rx_jmb_prod_idx
);
7948 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) {
7949 tw32(STD_REPLENISH_LWM
, 32);
7950 tw32(JMB_REPLENISH_LWM
, 16);
7953 tg3_rings_reset(tp
);
7955 /* Initialize MAC address and backoff seed. */
7956 __tg3_set_mac_addr(tp
, 0);
7958 /* MTU + ethernet header + FCS + optional VLAN tag */
7959 tw32(MAC_RX_MTU_SIZE
,
7960 tp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
);
7962 /* The slot time is changed by tg3_setup_phy if we
7963 * run at gigabit with half duplex.
7965 tw32(MAC_TX_LENGTHS
,
7966 (2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
7967 (6 << TX_LENGTHS_IPG_SHIFT
) |
7968 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
));
7970 /* Receive rules. */
7971 tw32(MAC_RCV_RULE_CFG
, RCV_RULE_CFG_DEFAULT_CLASS
);
7972 tw32(RCVLPC_CONFIG
, 0x0181);
7974 /* Calculate RDMAC_MODE setting early, we need it to determine
7975 * the RCVLPC_STATE_ENABLE mask.
7977 rdmac_mode
= (RDMAC_MODE_ENABLE
| RDMAC_MODE_TGTABORT_ENAB
|
7978 RDMAC_MODE_MSTABORT_ENAB
| RDMAC_MODE_PARITYERR_ENAB
|
7979 RDMAC_MODE_ADDROFLOW_ENAB
| RDMAC_MODE_FIFOOFLOW_ENAB
|
7980 RDMAC_MODE_FIFOURUN_ENAB
| RDMAC_MODE_FIFOOREAD_ENAB
|
7981 RDMAC_MODE_LNGREAD_ENAB
);
7983 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
7984 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
)
7985 rdmac_mode
|= RDMAC_MODE_MULT_DMA_RD_DIS
;
7987 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
7988 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
7989 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
7990 rdmac_mode
|= RDMAC_MODE_BD_SBD_CRPT_ENAB
|
7991 RDMAC_MODE_MBUF_RBD_CRPT_ENAB
|
7992 RDMAC_MODE_MBUF_SBD_CRPT_ENAB
;
7994 /* If statement applies to 5705 and 5750 PCI devices only */
7995 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
7996 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
7997 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)) {
7998 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
&&
7999 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
8000 rdmac_mode
|= RDMAC_MODE_FIFO_SIZE_128
;
8001 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
8002 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
)) {
8003 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
8007 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
8008 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
8010 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
8011 rdmac_mode
|= RDMAC_MODE_IPV4_LSO_EN
;
8013 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) ||
8014 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
8015 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
8016 rdmac_mode
|= RDMAC_MODE_IPV6_LSO_EN
;
8018 /* Receive/send statistics. */
8019 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
8020 val
= tr32(RCVLPC_STATS_ENABLE
);
8021 val
&= ~RCVLPC_STATSENAB_DACK_FIX
;
8022 tw32(RCVLPC_STATS_ENABLE
, val
);
8023 } else if ((rdmac_mode
& RDMAC_MODE_FIFO_SIZE_128
) &&
8024 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
8025 val
= tr32(RCVLPC_STATS_ENABLE
);
8026 val
&= ~RCVLPC_STATSENAB_LNGBRST_RFIX
;
8027 tw32(RCVLPC_STATS_ENABLE
, val
);
8029 tw32(RCVLPC_STATS_ENABLE
, 0xffffff);
8031 tw32(RCVLPC_STATSCTRL
, RCVLPC_STATSCTRL_ENABLE
);
8032 tw32(SNDDATAI_STATSENAB
, 0xffffff);
8033 tw32(SNDDATAI_STATSCTRL
,
8034 (SNDDATAI_SCTRL_ENABLE
|
8035 SNDDATAI_SCTRL_FASTUPD
));
8037 /* Setup host coalescing engine. */
8038 tw32(HOSTCC_MODE
, 0);
8039 for (i
= 0; i
< 2000; i
++) {
8040 if (!(tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
))
8045 __tg3_set_coalesce(tp
, &tp
->coal
);
8047 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
8048 /* Status/statistics block address. See tg3_timer,
8049 * the tg3_periodic_fetch_stats call there, and
8050 * tg3_get_stats to see how this works for 5705/5750 chips.
8052 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
8053 ((u64
) tp
->stats_mapping
>> 32));
8054 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
8055 ((u64
) tp
->stats_mapping
& 0xffffffff));
8056 tw32(HOSTCC_STATS_BLK_NIC_ADDR
, NIC_SRAM_STATS_BLK
);
8058 tw32(HOSTCC_STATUS_BLK_NIC_ADDR
, NIC_SRAM_STATUS_BLK
);
8060 /* Clear statistics and status block memory areas */
8061 for (i
= NIC_SRAM_STATS_BLK
;
8062 i
< NIC_SRAM_STATUS_BLK
+ TG3_HW_STATUS_SIZE
;
8064 tg3_write_mem(tp
, i
, 0);
8069 tw32(HOSTCC_MODE
, HOSTCC_MODE_ENABLE
| tp
->coalesce_mode
);
8071 tw32(RCVCC_MODE
, RCVCC_MODE_ENABLE
| RCVCC_MODE_ATTN_ENABLE
);
8072 tw32(RCVLPC_MODE
, RCVLPC_MODE_ENABLE
);
8073 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
8074 tw32(RCVLSC_MODE
, RCVLSC_MODE_ENABLE
| RCVLSC_MODE_ATTN_ENABLE
);
8076 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) {
8077 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
8078 /* reset to prevent losing 1st rx packet intermittently */
8079 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
8083 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
8084 tp
->mac_mode
&= MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
8087 tp
->mac_mode
|= MAC_MODE_TXSTAT_ENABLE
| MAC_MODE_RXSTAT_ENABLE
|
8088 MAC_MODE_TDE_ENABLE
| MAC_MODE_RDE_ENABLE
| MAC_MODE_FHDE_ENABLE
;
8089 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
8090 !(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
8091 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
)
8092 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
8093 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_RXSTAT_CLEAR
| MAC_MODE_TXSTAT_CLEAR
);
8096 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8097 * If TG3_FLG2_IS_NIC is zero, we should read the
8098 * register to preserve the GPIO settings for LOMs. The GPIOs,
8099 * whether used as inputs or outputs, are set by boot code after
8102 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)) {
8105 gpio_mask
= GRC_LCLCTRL_GPIO_OE0
| GRC_LCLCTRL_GPIO_OE1
|
8106 GRC_LCLCTRL_GPIO_OE2
| GRC_LCLCTRL_GPIO_OUTPUT0
|
8107 GRC_LCLCTRL_GPIO_OUTPUT1
| GRC_LCLCTRL_GPIO_OUTPUT2
;
8109 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
8110 gpio_mask
|= GRC_LCLCTRL_GPIO_OE3
|
8111 GRC_LCLCTRL_GPIO_OUTPUT3
;
8113 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
8114 gpio_mask
|= GRC_LCLCTRL_GPIO_UART_SEL
;
8116 tp
->grc_local_ctrl
&= ~gpio_mask
;
8117 tp
->grc_local_ctrl
|= tr32(GRC_LOCAL_CTRL
) & gpio_mask
;
8119 /* GPIO1 must be driven high for eeprom write protect */
8120 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
)
8121 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
8122 GRC_LCLCTRL_GPIO_OUTPUT1
);
8124 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
8127 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
) {
8128 val
= tr32(MSGINT_MODE
);
8129 val
|= MSGINT_MODE_MULTIVEC_EN
| MSGINT_MODE_ENABLE
;
8130 tw32(MSGINT_MODE
, val
);
8133 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
8134 tw32_f(DMAC_MODE
, DMAC_MODE_ENABLE
);
8138 val
= (WDMAC_MODE_ENABLE
| WDMAC_MODE_TGTABORT_ENAB
|
8139 WDMAC_MODE_MSTABORT_ENAB
| WDMAC_MODE_PARITYERR_ENAB
|
8140 WDMAC_MODE_ADDROFLOW_ENAB
| WDMAC_MODE_FIFOOFLOW_ENAB
|
8141 WDMAC_MODE_FIFOURUN_ENAB
| WDMAC_MODE_FIFOOREAD_ENAB
|
8142 WDMAC_MODE_LNGREAD_ENAB
);
8144 /* If statement applies to 5705 and 5750 PCI devices only */
8145 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
8146 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
8147 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) {
8148 if ((tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
8149 (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
||
8150 tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A2
)) {
8152 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
8153 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
8154 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
8155 val
|= WDMAC_MODE_RX_ACCEL
;
8159 /* Enable host coalescing bug fix */
8160 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
8161 val
|= WDMAC_MODE_STATUS_TAG_FIX
;
8163 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
8164 val
|= WDMAC_MODE_BURST_ALL_DATA
;
8166 tw32_f(WDMAC_MODE
, val
);
8169 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
8172 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
8174 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
) {
8175 pcix_cmd
&= ~PCI_X_CMD_MAX_READ
;
8176 pcix_cmd
|= PCI_X_CMD_READ_2K
;
8177 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
8178 pcix_cmd
&= ~(PCI_X_CMD_MAX_SPLIT
| PCI_X_CMD_MAX_READ
);
8179 pcix_cmd
|= PCI_X_CMD_READ_2K
;
8181 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
8185 tw32_f(RDMAC_MODE
, rdmac_mode
);
8188 tw32(RCVDCC_MODE
, RCVDCC_MODE_ENABLE
| RCVDCC_MODE_ATTN_ENABLE
);
8189 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
8190 tw32(MBFREE_MODE
, MBFREE_MODE_ENABLE
);
8192 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
8194 SNDDATAC_MODE_ENABLE
| SNDDATAC_MODE_CDELAY
);
8196 tw32(SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
);
8198 tw32(SNDBDC_MODE
, SNDBDC_MODE_ENABLE
| SNDBDC_MODE_ATTN_ENABLE
);
8199 tw32(RCVBDI_MODE
, RCVBDI_MODE_ENABLE
| RCVBDI_MODE_RCB_ATTN_ENAB
);
8200 tw32(RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
| RCVDBDI_MODE_INV_RING_SZ
);
8201 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
);
8202 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
8203 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
| 0x8);
8204 val
= SNDBDI_MODE_ENABLE
| SNDBDI_MODE_ATTN_ENABLE
;
8205 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
8206 val
|= SNDBDI_MODE_MULTI_TXQ_EN
;
8207 tw32(SNDBDI_MODE
, val
);
8208 tw32(SNDBDS_MODE
, SNDBDS_MODE_ENABLE
| SNDBDS_MODE_ATTN_ENABLE
);
8210 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
8211 err
= tg3_load_5701_a0_firmware_fix(tp
);
8216 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
8217 err
= tg3_load_tso_firmware(tp
);
8222 tp
->tx_mode
= TX_MODE_ENABLE
;
8223 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
8224 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
8225 tp
->tx_mode
|= TX_MODE_MBUF_LOCKUP_FIX
;
8226 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
8229 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
) {
8230 u32 reg
= MAC_RSS_INDIR_TBL_0
;
8231 u8
*ent
= (u8
*)&val
;
8233 /* Setup the indirection table */
8234 for (i
= 0; i
< TG3_RSS_INDIR_TBL_SIZE
; i
++) {
8235 int idx
= i
% sizeof(val
);
8237 ent
[idx
] = i
% (tp
->irq_cnt
- 1);
8238 if (idx
== sizeof(val
) - 1) {
8244 /* Setup the "secret" hash key. */
8245 tw32(MAC_RSS_HASH_KEY_0
, 0x5f865437);
8246 tw32(MAC_RSS_HASH_KEY_1
, 0xe4ac62cc);
8247 tw32(MAC_RSS_HASH_KEY_2
, 0x50103a45);
8248 tw32(MAC_RSS_HASH_KEY_3
, 0x36621985);
8249 tw32(MAC_RSS_HASH_KEY_4
, 0xbf14c0e8);
8250 tw32(MAC_RSS_HASH_KEY_5
, 0x1bc27a1e);
8251 tw32(MAC_RSS_HASH_KEY_6
, 0x84f4b556);
8252 tw32(MAC_RSS_HASH_KEY_7
, 0x094ea6fe);
8253 tw32(MAC_RSS_HASH_KEY_8
, 0x7dda01e7);
8254 tw32(MAC_RSS_HASH_KEY_9
, 0xc04d7481);
8257 tp
->rx_mode
= RX_MODE_ENABLE
;
8258 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
8259 tp
->rx_mode
|= RX_MODE_IPV6_CSUM_ENABLE
;
8261 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)
8262 tp
->rx_mode
|= RX_MODE_RSS_ENABLE
|
8263 RX_MODE_RSS_ITBL_HASH_BITS_7
|
8264 RX_MODE_RSS_IPV6_HASH_EN
|
8265 RX_MODE_RSS_TCP_IPV6_HASH_EN
|
8266 RX_MODE_RSS_IPV4_HASH_EN
|
8267 RX_MODE_RSS_TCP_IPV4_HASH_EN
;
8269 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
8272 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
8274 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
8275 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
8276 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
8279 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
8282 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
8283 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) &&
8284 !(tp
->phy_flags
& TG3_PHYFLG_SERDES_PREEMPHASIS
)) {
8285 /* Set drive transmission level to 1.2V */
8286 /* only if the signal pre-emphasis bit is not set */
8287 val
= tr32(MAC_SERDES_CFG
);
8290 tw32(MAC_SERDES_CFG
, val
);
8292 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
)
8293 tw32(MAC_SERDES_CFG
, 0x616000);
8296 /* Prevent chip from dropping frames when flow control
8299 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
8303 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME
, val
);
8305 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
&&
8306 (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)) {
8307 /* Use hardware link auto-negotiation */
8308 tp
->tg3_flags2
|= TG3_FLG2_HW_AUTONEG
;
8311 if ((tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) &&
8312 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
)) {
8315 tmp
= tr32(SERDES_RX_CTRL
);
8316 tw32(SERDES_RX_CTRL
, tmp
| SERDES_RX_SIG_DETECT
);
8317 tp
->grc_local_ctrl
&= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT
;
8318 tp
->grc_local_ctrl
|= GRC_LCLCTRL_USE_SIG_DETECT
;
8319 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
8322 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
8323 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
) {
8324 tp
->phy_flags
&= ~TG3_PHYFLG_IS_LOW_POWER
;
8325 tp
->link_config
.speed
= tp
->link_config
.orig_speed
;
8326 tp
->link_config
.duplex
= tp
->link_config
.orig_duplex
;
8327 tp
->link_config
.autoneg
= tp
->link_config
.orig_autoneg
;
8330 err
= tg3_setup_phy(tp
, 0);
8334 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
8335 !(tp
->phy_flags
& TG3_PHYFLG_IS_FET
)) {
8338 /* Clear CRC stats. */
8339 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &tmp
)) {
8340 tg3_writephy(tp
, MII_TG3_TEST1
,
8341 tmp
| MII_TG3_TEST1_CRC_EN
);
8342 tg3_readphy(tp
, MII_TG3_RXR_COUNTERS
, &tmp
);
8347 __tg3_set_rx_mode(tp
->dev
);
8349 /* Initialize receive rules. */
8350 tw32(MAC_RCV_RULE_0
, 0xc2000000 & RCV_RULE_DISABLE_MASK
);
8351 tw32(MAC_RCV_VALUE_0
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
8352 tw32(MAC_RCV_RULE_1
, 0x86000004 & RCV_RULE_DISABLE_MASK
);
8353 tw32(MAC_RCV_VALUE_1
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
8355 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
8356 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
8360 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
8364 tw32(MAC_RCV_RULE_15
, 0); tw32(MAC_RCV_VALUE_15
, 0);
8366 tw32(MAC_RCV_RULE_14
, 0); tw32(MAC_RCV_VALUE_14
, 0);
8368 tw32(MAC_RCV_RULE_13
, 0); tw32(MAC_RCV_VALUE_13
, 0);
8370 tw32(MAC_RCV_RULE_12
, 0); tw32(MAC_RCV_VALUE_12
, 0);
8372 tw32(MAC_RCV_RULE_11
, 0); tw32(MAC_RCV_VALUE_11
, 0);
8374 tw32(MAC_RCV_RULE_10
, 0); tw32(MAC_RCV_VALUE_10
, 0);
8376 tw32(MAC_RCV_RULE_9
, 0); tw32(MAC_RCV_VALUE_9
, 0);
8378 tw32(MAC_RCV_RULE_8
, 0); tw32(MAC_RCV_VALUE_8
, 0);
8380 tw32(MAC_RCV_RULE_7
, 0); tw32(MAC_RCV_VALUE_7
, 0);
8382 tw32(MAC_RCV_RULE_6
, 0); tw32(MAC_RCV_VALUE_6
, 0);
8384 tw32(MAC_RCV_RULE_5
, 0); tw32(MAC_RCV_VALUE_5
, 0);
8386 tw32(MAC_RCV_RULE_4
, 0); tw32(MAC_RCV_VALUE_4
, 0);
8388 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8390 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8398 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
8399 /* Write our heartbeat update interval to APE. */
8400 tg3_ape_write32(tp
, TG3_APE_HOST_HEARTBEAT_INT_MS
,
8401 APE_HOST_HEARTBEAT_INT_DISABLE
);
8403 tg3_write_sig_post_reset(tp
, RESET_KIND_INIT
);
8408 /* Called at device open time to get the chip ready for
8409 * packet processing. Invoked with tp->lock held.
8411 static int tg3_init_hw(struct tg3
*tp
, int reset_phy
)
8413 tg3_switch_clocks(tp
);
8415 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
8417 return tg3_reset_hw(tp
, reset_phy
);
8420 #define TG3_STAT_ADD32(PSTAT, REG) \
8421 do { u32 __val = tr32(REG); \
8422 (PSTAT)->low += __val; \
8423 if ((PSTAT)->low < __val) \
8424 (PSTAT)->high += 1; \
8427 static void tg3_periodic_fetch_stats(struct tg3
*tp
)
8429 struct tg3_hw_stats
*sp
= tp
->hw_stats
;
8431 if (!netif_carrier_ok(tp
->dev
))
8434 TG3_STAT_ADD32(&sp
->tx_octets
, MAC_TX_STATS_OCTETS
);
8435 TG3_STAT_ADD32(&sp
->tx_collisions
, MAC_TX_STATS_COLLISIONS
);
8436 TG3_STAT_ADD32(&sp
->tx_xon_sent
, MAC_TX_STATS_XON_SENT
);
8437 TG3_STAT_ADD32(&sp
->tx_xoff_sent
, MAC_TX_STATS_XOFF_SENT
);
8438 TG3_STAT_ADD32(&sp
->tx_mac_errors
, MAC_TX_STATS_MAC_ERRORS
);
8439 TG3_STAT_ADD32(&sp
->tx_single_collisions
, MAC_TX_STATS_SINGLE_COLLISIONS
);
8440 TG3_STAT_ADD32(&sp
->tx_mult_collisions
, MAC_TX_STATS_MULT_COLLISIONS
);
8441 TG3_STAT_ADD32(&sp
->tx_deferred
, MAC_TX_STATS_DEFERRED
);
8442 TG3_STAT_ADD32(&sp
->tx_excessive_collisions
, MAC_TX_STATS_EXCESSIVE_COL
);
8443 TG3_STAT_ADD32(&sp
->tx_late_collisions
, MAC_TX_STATS_LATE_COL
);
8444 TG3_STAT_ADD32(&sp
->tx_ucast_packets
, MAC_TX_STATS_UCAST
);
8445 TG3_STAT_ADD32(&sp
->tx_mcast_packets
, MAC_TX_STATS_MCAST
);
8446 TG3_STAT_ADD32(&sp
->tx_bcast_packets
, MAC_TX_STATS_BCAST
);
8448 TG3_STAT_ADD32(&sp
->rx_octets
, MAC_RX_STATS_OCTETS
);
8449 TG3_STAT_ADD32(&sp
->rx_fragments
, MAC_RX_STATS_FRAGMENTS
);
8450 TG3_STAT_ADD32(&sp
->rx_ucast_packets
, MAC_RX_STATS_UCAST
);
8451 TG3_STAT_ADD32(&sp
->rx_mcast_packets
, MAC_RX_STATS_MCAST
);
8452 TG3_STAT_ADD32(&sp
->rx_bcast_packets
, MAC_RX_STATS_BCAST
);
8453 TG3_STAT_ADD32(&sp
->rx_fcs_errors
, MAC_RX_STATS_FCS_ERRORS
);
8454 TG3_STAT_ADD32(&sp
->rx_align_errors
, MAC_RX_STATS_ALIGN_ERRORS
);
8455 TG3_STAT_ADD32(&sp
->rx_xon_pause_rcvd
, MAC_RX_STATS_XON_PAUSE_RECVD
);
8456 TG3_STAT_ADD32(&sp
->rx_xoff_pause_rcvd
, MAC_RX_STATS_XOFF_PAUSE_RECVD
);
8457 TG3_STAT_ADD32(&sp
->rx_mac_ctrl_rcvd
, MAC_RX_STATS_MAC_CTRL_RECVD
);
8458 TG3_STAT_ADD32(&sp
->rx_xoff_entered
, MAC_RX_STATS_XOFF_ENTERED
);
8459 TG3_STAT_ADD32(&sp
->rx_frame_too_long_errors
, MAC_RX_STATS_FRAME_TOO_LONG
);
8460 TG3_STAT_ADD32(&sp
->rx_jabbers
, MAC_RX_STATS_JABBERS
);
8461 TG3_STAT_ADD32(&sp
->rx_undersize_packets
, MAC_RX_STATS_UNDERSIZE
);
8463 TG3_STAT_ADD32(&sp
->rxbds_empty
, RCVLPC_NO_RCV_BD_CNT
);
8464 TG3_STAT_ADD32(&sp
->rx_discards
, RCVLPC_IN_DISCARDS_CNT
);
8465 TG3_STAT_ADD32(&sp
->rx_errors
, RCVLPC_IN_ERRORS_CNT
);
8468 static void tg3_timer(unsigned long __opaque
)
8470 struct tg3
*tp
= (struct tg3
*) __opaque
;
8475 spin_lock(&tp
->lock
);
8477 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
8478 /* All of this garbage is because when using non-tagged
8479 * IRQ status the mailbox/status_block protocol the chip
8480 * uses with the cpu is race prone.
8482 if (tp
->napi
[0].hw_status
->status
& SD_STATUS_UPDATED
) {
8483 tw32(GRC_LOCAL_CTRL
,
8484 tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
8486 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
8487 HOSTCC_MODE_ENABLE
| HOSTCC_MODE_NOW
);
8490 if (!(tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
8491 tp
->tg3_flags2
|= TG3_FLG2_RESTART_TIMER
;
8492 spin_unlock(&tp
->lock
);
8493 schedule_work(&tp
->reset_task
);
8498 /* This part only runs once per second. */
8499 if (!--tp
->timer_counter
) {
8500 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
8501 tg3_periodic_fetch_stats(tp
);
8503 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
8507 mac_stat
= tr32(MAC_STATUS
);
8510 if (tp
->phy_flags
& TG3_PHYFLG_USE_MI_INTERRUPT
) {
8511 if (mac_stat
& MAC_STATUS_MI_INTERRUPT
)
8513 } else if (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)
8517 tg3_setup_phy(tp
, 0);
8518 } else if (tp
->tg3_flags
& TG3_FLAG_POLL_SERDES
) {
8519 u32 mac_stat
= tr32(MAC_STATUS
);
8522 if (netif_carrier_ok(tp
->dev
) &&
8523 (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)) {
8526 if (!netif_carrier_ok(tp
->dev
) &&
8527 (mac_stat
& (MAC_STATUS_PCS_SYNCED
|
8528 MAC_STATUS_SIGNAL_DET
))) {
8532 if (!tp
->serdes_counter
) {
8535 ~MAC_MODE_PORT_MODE_MASK
));
8537 tw32_f(MAC_MODE
, tp
->mac_mode
);
8540 tg3_setup_phy(tp
, 0);
8542 } else if ((tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) &&
8543 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
8544 tg3_serdes_parallel_detect(tp
);
8547 tp
->timer_counter
= tp
->timer_multiplier
;
8550 /* Heartbeat is only sent once every 2 seconds.
8552 * The heartbeat is to tell the ASF firmware that the host
8553 * driver is still alive. In the event that the OS crashes,
8554 * ASF needs to reset the hardware to free up the FIFO space
8555 * that may be filled with rx packets destined for the host.
8556 * If the FIFO is full, ASF will no longer function properly.
8558 * Unintended resets have been reported on real time kernels
8559 * where the timer doesn't run on time. Netpoll will also have
8562 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8563 * to check the ring condition when the heartbeat is expiring
8564 * before doing the reset. This will prevent most unintended
8567 if (!--tp
->asf_counter
) {
8568 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
8569 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
8570 tg3_wait_for_event_ack(tp
);
8572 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
,
8573 FWCMD_NICDRV_ALIVE3
);
8574 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 4);
8575 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
,
8576 TG3_FW_UPDATE_TIMEOUT_SEC
);
8578 tg3_generate_fw_event(tp
);
8580 tp
->asf_counter
= tp
->asf_multiplier
;
8583 spin_unlock(&tp
->lock
);
8586 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
8587 add_timer(&tp
->timer
);
8590 static int tg3_request_irq(struct tg3
*tp
, int irq_num
)
8593 unsigned long flags
;
8595 struct tg3_napi
*tnapi
= &tp
->napi
[irq_num
];
8597 if (tp
->irq_cnt
== 1)
8598 name
= tp
->dev
->name
;
8600 name
= &tnapi
->irq_lbl
[0];
8601 snprintf(name
, IFNAMSIZ
, "%s-%d", tp
->dev
->name
, irq_num
);
8602 name
[IFNAMSIZ
-1] = 0;
8605 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI_OR_MSIX
) {
8607 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
8609 flags
= IRQF_SAMPLE_RANDOM
;
8612 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
8613 fn
= tg3_interrupt_tagged
;
8614 flags
= IRQF_SHARED
| IRQF_SAMPLE_RANDOM
;
8617 return request_irq(tnapi
->irq_vec
, fn
, flags
, name
, tnapi
);
8620 static int tg3_test_interrupt(struct tg3
*tp
)
8622 struct tg3_napi
*tnapi
= &tp
->napi
[0];
8623 struct net_device
*dev
= tp
->dev
;
8624 int err
, i
, intr_ok
= 0;
8627 if (!netif_running(dev
))
8630 tg3_disable_ints(tp
);
8632 free_irq(tnapi
->irq_vec
, tnapi
);
8635 * Turn off MSI one shot mode. Otherwise this test has no
8636 * observable way to know whether the interrupt was delivered.
8638 if ((tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) &&
8639 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)) {
8640 val
= tr32(MSGINT_MODE
) | MSGINT_MODE_ONE_SHOT_DISABLE
;
8641 tw32(MSGINT_MODE
, val
);
8644 err
= request_irq(tnapi
->irq_vec
, tg3_test_isr
,
8645 IRQF_SHARED
| IRQF_SAMPLE_RANDOM
, dev
->name
, tnapi
);
8649 tnapi
->hw_status
->status
&= ~SD_STATUS_UPDATED
;
8650 tg3_enable_ints(tp
);
8652 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
8655 for (i
= 0; i
< 5; i
++) {
8656 u32 int_mbox
, misc_host_ctrl
;
8658 int_mbox
= tr32_mailbox(tnapi
->int_mbox
);
8659 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
8661 if ((int_mbox
!= 0) ||
8662 (misc_host_ctrl
& MISC_HOST_CTRL_MASK_PCI_INT
)) {
8670 tg3_disable_ints(tp
);
8672 free_irq(tnapi
->irq_vec
, tnapi
);
8674 err
= tg3_request_irq(tp
, 0);
8680 /* Reenable MSI one shot mode. */
8681 if ((tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) &&
8682 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)) {
8683 val
= tr32(MSGINT_MODE
) & ~MSGINT_MODE_ONE_SHOT_DISABLE
;
8684 tw32(MSGINT_MODE
, val
);
8692 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8693 * successfully restored
8695 static int tg3_test_msi(struct tg3
*tp
)
8700 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSI
))
8703 /* Turn off SERR reporting in case MSI terminates with Master
8706 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
8707 pci_write_config_word(tp
->pdev
, PCI_COMMAND
,
8708 pci_cmd
& ~PCI_COMMAND_SERR
);
8710 err
= tg3_test_interrupt(tp
);
8712 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
8717 /* other failures */
8721 /* MSI test failed, go back to INTx mode */
8722 netdev_warn(tp
->dev
, "No interrupt was generated using MSI. Switching "
8723 "to INTx mode. Please report this failure to the PCI "
8724 "maintainer and include system chipset information\n");
8726 free_irq(tp
->napi
[0].irq_vec
, &tp
->napi
[0]);
8728 pci_disable_msi(tp
->pdev
);
8730 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
8731 tp
->napi
[0].irq_vec
= tp
->pdev
->irq
;
8733 err
= tg3_request_irq(tp
, 0);
8737 /* Need to reset the chip because the MSI cycle may have terminated
8738 * with Master Abort.
8740 tg3_full_lock(tp
, 1);
8742 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8743 err
= tg3_init_hw(tp
, 1);
8745 tg3_full_unlock(tp
);
8748 free_irq(tp
->napi
[0].irq_vec
, &tp
->napi
[0]);
8753 static int tg3_request_firmware(struct tg3
*tp
)
8755 const __be32
*fw_data
;
8757 if (request_firmware(&tp
->fw
, tp
->fw_needed
, &tp
->pdev
->dev
)) {
8758 netdev_err(tp
->dev
, "Failed to load firmware \"%s\"\n",
8763 fw_data
= (void *)tp
->fw
->data
;
8765 /* Firmware blob starts with version numbers, followed by
8766 * start address and _full_ length including BSS sections
8767 * (which must be longer than the actual data, of course
8770 tp
->fw_len
= be32_to_cpu(fw_data
[2]); /* includes bss */
8771 if (tp
->fw_len
< (tp
->fw
->size
- 12)) {
8772 netdev_err(tp
->dev
, "bogus length %d in \"%s\"\n",
8773 tp
->fw_len
, tp
->fw_needed
);
8774 release_firmware(tp
->fw
);
8779 /* We no longer need firmware; we have it. */
8780 tp
->fw_needed
= NULL
;
8784 static bool tg3_enable_msix(struct tg3
*tp
)
8786 int i
, rc
, cpus
= num_online_cpus();
8787 struct msix_entry msix_ent
[tp
->irq_max
];
8790 /* Just fallback to the simpler MSI mode. */
8794 * We want as many rx rings enabled as there are cpus.
8795 * The first MSIX vector only deals with link interrupts, etc,
8796 * so we add one to the number of vectors we are requesting.
8798 tp
->irq_cnt
= min_t(unsigned, cpus
+ 1, tp
->irq_max
);
8800 for (i
= 0; i
< tp
->irq_max
; i
++) {
8801 msix_ent
[i
].entry
= i
;
8802 msix_ent
[i
].vector
= 0;
8805 rc
= pci_enable_msix(tp
->pdev
, msix_ent
, tp
->irq_cnt
);
8808 } else if (rc
!= 0) {
8809 if (pci_enable_msix(tp
->pdev
, msix_ent
, rc
))
8811 netdev_notice(tp
->dev
, "Requested %d MSI-X vectors, received %d\n",
8816 for (i
= 0; i
< tp
->irq_max
; i
++)
8817 tp
->napi
[i
].irq_vec
= msix_ent
[i
].vector
;
8819 tp
->dev
->real_num_tx_queues
= 1;
8820 if (tp
->irq_cnt
> 1) {
8821 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_RSS
;
8823 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
8824 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
) {
8825 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_TSS
;
8826 tp
->dev
->real_num_tx_queues
= tp
->irq_cnt
- 1;
8833 static void tg3_ints_init(struct tg3
*tp
)
8835 if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSI_OR_MSIX
) &&
8836 !(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
8837 /* All MSI supporting chips should support tagged
8838 * status. Assert that this is the case.
8840 netdev_warn(tp
->dev
,
8841 "MSI without TAGGED_STATUS? Not using MSI\n");
8845 if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
) && tg3_enable_msix(tp
))
8846 tp
->tg3_flags2
|= TG3_FLG2_USING_MSIX
;
8847 else if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSI
) &&
8848 pci_enable_msi(tp
->pdev
) == 0)
8849 tp
->tg3_flags2
|= TG3_FLG2_USING_MSI
;
8851 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI_OR_MSIX
) {
8852 u32 msi_mode
= tr32(MSGINT_MODE
);
8853 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)
8854 msi_mode
|= MSGINT_MODE_MULTIVEC_EN
;
8855 tw32(MSGINT_MODE
, msi_mode
| MSGINT_MODE_ENABLE
);
8858 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)) {
8860 tp
->napi
[0].irq_vec
= tp
->pdev
->irq
;
8861 tp
->dev
->real_num_tx_queues
= 1;
8865 static void tg3_ints_fini(struct tg3
*tp
)
8867 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)
8868 pci_disable_msix(tp
->pdev
);
8869 else if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)
8870 pci_disable_msi(tp
->pdev
);
8871 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI_OR_MSIX
;
8872 tp
->tg3_flags3
&= ~(TG3_FLG3_ENABLE_RSS
| TG3_FLG3_ENABLE_TSS
);
8875 static int tg3_open(struct net_device
*dev
)
8877 struct tg3
*tp
= netdev_priv(dev
);
8880 if (tp
->fw_needed
) {
8881 err
= tg3_request_firmware(tp
);
8882 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
8886 netdev_warn(tp
->dev
, "TSO capability disabled\n");
8887 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
8888 } else if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
8889 netdev_notice(tp
->dev
, "TSO capability restored\n");
8890 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
8894 netif_carrier_off(tp
->dev
);
8896 err
= tg3_set_power_state(tp
, PCI_D0
);
8900 tg3_full_lock(tp
, 0);
8902 tg3_disable_ints(tp
);
8903 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
8905 tg3_full_unlock(tp
);
8908 * Setup interrupts first so we know how
8909 * many NAPI resources to allocate
8913 /* The placement of this call is tied
8914 * to the setup and use of Host TX descriptors.
8916 err
= tg3_alloc_consistent(tp
);
8920 tg3_napi_enable(tp
);
8922 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
8923 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8924 err
= tg3_request_irq(tp
, i
);
8926 for (i
--; i
>= 0; i
--)
8927 free_irq(tnapi
->irq_vec
, tnapi
);
8935 tg3_full_lock(tp
, 0);
8937 err
= tg3_init_hw(tp
, 1);
8939 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8942 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
8943 tp
->timer_offset
= HZ
;
8945 tp
->timer_offset
= HZ
/ 10;
8947 BUG_ON(tp
->timer_offset
> HZ
);
8948 tp
->timer_counter
= tp
->timer_multiplier
=
8949 (HZ
/ tp
->timer_offset
);
8950 tp
->asf_counter
= tp
->asf_multiplier
=
8951 ((HZ
/ tp
->timer_offset
) * 2);
8953 init_timer(&tp
->timer
);
8954 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
8955 tp
->timer
.data
= (unsigned long) tp
;
8956 tp
->timer
.function
= tg3_timer
;
8959 tg3_full_unlock(tp
);
8964 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
8965 err
= tg3_test_msi(tp
);
8968 tg3_full_lock(tp
, 0);
8969 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8971 tg3_full_unlock(tp
);
8976 if (!(tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) &&
8977 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)) {
8978 u32 val
= tr32(PCIE_TRANSACTION_CFG
);
8980 tw32(PCIE_TRANSACTION_CFG
,
8981 val
| PCIE_TRANS_CFG_1SHOT_MSI
);
8987 tg3_full_lock(tp
, 0);
8989 add_timer(&tp
->timer
);
8990 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
8991 tg3_enable_ints(tp
);
8993 tg3_full_unlock(tp
);
8995 netif_tx_start_all_queues(dev
);
9000 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--) {
9001 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
9002 free_irq(tnapi
->irq_vec
, tnapi
);
9006 tg3_napi_disable(tp
);
9007 tg3_free_consistent(tp
);
9014 static struct rtnl_link_stats64
*tg3_get_stats64(struct net_device
*,
9015 struct rtnl_link_stats64
*);
9016 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*);
9018 static int tg3_close(struct net_device
*dev
)
9021 struct tg3
*tp
= netdev_priv(dev
);
9023 tg3_napi_disable(tp
);
9024 cancel_work_sync(&tp
->reset_task
);
9026 netif_tx_stop_all_queues(dev
);
9028 del_timer_sync(&tp
->timer
);
9032 tg3_full_lock(tp
, 1);
9034 tg3_disable_ints(tp
);
9036 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9038 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
9040 tg3_full_unlock(tp
);
9042 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--) {
9043 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
9044 free_irq(tnapi
->irq_vec
, tnapi
);
9049 tg3_get_stats64(tp
->dev
, &tp
->net_stats_prev
);
9051 memcpy(&tp
->estats_prev
, tg3_get_estats(tp
),
9052 sizeof(tp
->estats_prev
));
9054 tg3_free_consistent(tp
);
9056 tg3_set_power_state(tp
, PCI_D3hot
);
9058 netif_carrier_off(tp
->dev
);
9063 static inline u64
get_stat64(tg3_stat64_t
*val
)
9065 return ((u64
)val
->high
<< 32) | ((u64
)val
->low
);
9068 static u64
calc_crc_errors(struct tg3
*tp
)
9070 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
9072 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
9073 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
9074 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
9077 spin_lock_bh(&tp
->lock
);
9078 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &val
)) {
9079 tg3_writephy(tp
, MII_TG3_TEST1
,
9080 val
| MII_TG3_TEST1_CRC_EN
);
9081 tg3_readphy(tp
, MII_TG3_RXR_COUNTERS
, &val
);
9084 spin_unlock_bh(&tp
->lock
);
9086 tp
->phy_crc_errors
+= val
;
9088 return tp
->phy_crc_errors
;
9091 return get_stat64(&hw_stats
->rx_fcs_errors
);
9094 #define ESTAT_ADD(member) \
9095 estats->member = old_estats->member + \
9096 get_stat64(&hw_stats->member)
9098 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*tp
)
9100 struct tg3_ethtool_stats
*estats
= &tp
->estats
;
9101 struct tg3_ethtool_stats
*old_estats
= &tp
->estats_prev
;
9102 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
9107 ESTAT_ADD(rx_octets
);
9108 ESTAT_ADD(rx_fragments
);
9109 ESTAT_ADD(rx_ucast_packets
);
9110 ESTAT_ADD(rx_mcast_packets
);
9111 ESTAT_ADD(rx_bcast_packets
);
9112 ESTAT_ADD(rx_fcs_errors
);
9113 ESTAT_ADD(rx_align_errors
);
9114 ESTAT_ADD(rx_xon_pause_rcvd
);
9115 ESTAT_ADD(rx_xoff_pause_rcvd
);
9116 ESTAT_ADD(rx_mac_ctrl_rcvd
);
9117 ESTAT_ADD(rx_xoff_entered
);
9118 ESTAT_ADD(rx_frame_too_long_errors
);
9119 ESTAT_ADD(rx_jabbers
);
9120 ESTAT_ADD(rx_undersize_packets
);
9121 ESTAT_ADD(rx_in_length_errors
);
9122 ESTAT_ADD(rx_out_length_errors
);
9123 ESTAT_ADD(rx_64_or_less_octet_packets
);
9124 ESTAT_ADD(rx_65_to_127_octet_packets
);
9125 ESTAT_ADD(rx_128_to_255_octet_packets
);
9126 ESTAT_ADD(rx_256_to_511_octet_packets
);
9127 ESTAT_ADD(rx_512_to_1023_octet_packets
);
9128 ESTAT_ADD(rx_1024_to_1522_octet_packets
);
9129 ESTAT_ADD(rx_1523_to_2047_octet_packets
);
9130 ESTAT_ADD(rx_2048_to_4095_octet_packets
);
9131 ESTAT_ADD(rx_4096_to_8191_octet_packets
);
9132 ESTAT_ADD(rx_8192_to_9022_octet_packets
);
9134 ESTAT_ADD(tx_octets
);
9135 ESTAT_ADD(tx_collisions
);
9136 ESTAT_ADD(tx_xon_sent
);
9137 ESTAT_ADD(tx_xoff_sent
);
9138 ESTAT_ADD(tx_flow_control
);
9139 ESTAT_ADD(tx_mac_errors
);
9140 ESTAT_ADD(tx_single_collisions
);
9141 ESTAT_ADD(tx_mult_collisions
);
9142 ESTAT_ADD(tx_deferred
);
9143 ESTAT_ADD(tx_excessive_collisions
);
9144 ESTAT_ADD(tx_late_collisions
);
9145 ESTAT_ADD(tx_collide_2times
);
9146 ESTAT_ADD(tx_collide_3times
);
9147 ESTAT_ADD(tx_collide_4times
);
9148 ESTAT_ADD(tx_collide_5times
);
9149 ESTAT_ADD(tx_collide_6times
);
9150 ESTAT_ADD(tx_collide_7times
);
9151 ESTAT_ADD(tx_collide_8times
);
9152 ESTAT_ADD(tx_collide_9times
);
9153 ESTAT_ADD(tx_collide_10times
);
9154 ESTAT_ADD(tx_collide_11times
);
9155 ESTAT_ADD(tx_collide_12times
);
9156 ESTAT_ADD(tx_collide_13times
);
9157 ESTAT_ADD(tx_collide_14times
);
9158 ESTAT_ADD(tx_collide_15times
);
9159 ESTAT_ADD(tx_ucast_packets
);
9160 ESTAT_ADD(tx_mcast_packets
);
9161 ESTAT_ADD(tx_bcast_packets
);
9162 ESTAT_ADD(tx_carrier_sense_errors
);
9163 ESTAT_ADD(tx_discards
);
9164 ESTAT_ADD(tx_errors
);
9166 ESTAT_ADD(dma_writeq_full
);
9167 ESTAT_ADD(dma_write_prioq_full
);
9168 ESTAT_ADD(rxbds_empty
);
9169 ESTAT_ADD(rx_discards
);
9170 ESTAT_ADD(rx_errors
);
9171 ESTAT_ADD(rx_threshold_hit
);
9173 ESTAT_ADD(dma_readq_full
);
9174 ESTAT_ADD(dma_read_prioq_full
);
9175 ESTAT_ADD(tx_comp_queue_full
);
9177 ESTAT_ADD(ring_set_send_prod_index
);
9178 ESTAT_ADD(ring_status_update
);
9179 ESTAT_ADD(nic_irqs
);
9180 ESTAT_ADD(nic_avoided_irqs
);
9181 ESTAT_ADD(nic_tx_threshold_hit
);
9186 static struct rtnl_link_stats64
*tg3_get_stats64(struct net_device
*dev
,
9187 struct rtnl_link_stats64
*stats
)
9189 struct tg3
*tp
= netdev_priv(dev
);
9190 struct rtnl_link_stats64
*old_stats
= &tp
->net_stats_prev
;
9191 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
9196 stats
->rx_packets
= old_stats
->rx_packets
+
9197 get_stat64(&hw_stats
->rx_ucast_packets
) +
9198 get_stat64(&hw_stats
->rx_mcast_packets
) +
9199 get_stat64(&hw_stats
->rx_bcast_packets
);
9201 stats
->tx_packets
= old_stats
->tx_packets
+
9202 get_stat64(&hw_stats
->tx_ucast_packets
) +
9203 get_stat64(&hw_stats
->tx_mcast_packets
) +
9204 get_stat64(&hw_stats
->tx_bcast_packets
);
9206 stats
->rx_bytes
= old_stats
->rx_bytes
+
9207 get_stat64(&hw_stats
->rx_octets
);
9208 stats
->tx_bytes
= old_stats
->tx_bytes
+
9209 get_stat64(&hw_stats
->tx_octets
);
9211 stats
->rx_errors
= old_stats
->rx_errors
+
9212 get_stat64(&hw_stats
->rx_errors
);
9213 stats
->tx_errors
= old_stats
->tx_errors
+
9214 get_stat64(&hw_stats
->tx_errors
) +
9215 get_stat64(&hw_stats
->tx_mac_errors
) +
9216 get_stat64(&hw_stats
->tx_carrier_sense_errors
) +
9217 get_stat64(&hw_stats
->tx_discards
);
9219 stats
->multicast
= old_stats
->multicast
+
9220 get_stat64(&hw_stats
->rx_mcast_packets
);
9221 stats
->collisions
= old_stats
->collisions
+
9222 get_stat64(&hw_stats
->tx_collisions
);
9224 stats
->rx_length_errors
= old_stats
->rx_length_errors
+
9225 get_stat64(&hw_stats
->rx_frame_too_long_errors
) +
9226 get_stat64(&hw_stats
->rx_undersize_packets
);
9228 stats
->rx_over_errors
= old_stats
->rx_over_errors
+
9229 get_stat64(&hw_stats
->rxbds_empty
);
9230 stats
->rx_frame_errors
= old_stats
->rx_frame_errors
+
9231 get_stat64(&hw_stats
->rx_align_errors
);
9232 stats
->tx_aborted_errors
= old_stats
->tx_aborted_errors
+
9233 get_stat64(&hw_stats
->tx_discards
);
9234 stats
->tx_carrier_errors
= old_stats
->tx_carrier_errors
+
9235 get_stat64(&hw_stats
->tx_carrier_sense_errors
);
9237 stats
->rx_crc_errors
= old_stats
->rx_crc_errors
+
9238 calc_crc_errors(tp
);
9240 stats
->rx_missed_errors
= old_stats
->rx_missed_errors
+
9241 get_stat64(&hw_stats
->rx_discards
);
9246 static inline u32
calc_crc(unsigned char *buf
, int len
)
9254 for (j
= 0; j
< len
; j
++) {
9257 for (k
= 0; k
< 8; k
++) {
9270 static void tg3_set_multi(struct tg3
*tp
, unsigned int accept_all
)
9272 /* accept or reject all multicast frames */
9273 tw32(MAC_HASH_REG_0
, accept_all
? 0xffffffff : 0);
9274 tw32(MAC_HASH_REG_1
, accept_all
? 0xffffffff : 0);
9275 tw32(MAC_HASH_REG_2
, accept_all
? 0xffffffff : 0);
9276 tw32(MAC_HASH_REG_3
, accept_all
? 0xffffffff : 0);
9279 static void __tg3_set_rx_mode(struct net_device
*dev
)
9281 struct tg3
*tp
= netdev_priv(dev
);
9284 rx_mode
= tp
->rx_mode
& ~(RX_MODE_PROMISC
|
9285 RX_MODE_KEEP_VLAN_TAG
);
9287 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9290 #if TG3_VLAN_TAG_USED
9292 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
9293 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
9295 /* By definition, VLAN is disabled always in this
9298 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
9299 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
9302 if (dev
->flags
& IFF_PROMISC
) {
9303 /* Promiscuous mode. */
9304 rx_mode
|= RX_MODE_PROMISC
;
9305 } else if (dev
->flags
& IFF_ALLMULTI
) {
9306 /* Accept all multicast. */
9307 tg3_set_multi(tp
, 1);
9308 } else if (netdev_mc_empty(dev
)) {
9309 /* Reject all multicast. */
9310 tg3_set_multi(tp
, 0);
9312 /* Accept one or more multicast(s). */
9313 struct netdev_hw_addr
*ha
;
9314 u32 mc_filter
[4] = { 0, };
9319 netdev_for_each_mc_addr(ha
, dev
) {
9320 crc
= calc_crc(ha
->addr
, ETH_ALEN
);
9322 regidx
= (bit
& 0x60) >> 5;
9324 mc_filter
[regidx
] |= (1 << bit
);
9327 tw32(MAC_HASH_REG_0
, mc_filter
[0]);
9328 tw32(MAC_HASH_REG_1
, mc_filter
[1]);
9329 tw32(MAC_HASH_REG_2
, mc_filter
[2]);
9330 tw32(MAC_HASH_REG_3
, mc_filter
[3]);
9333 if (rx_mode
!= tp
->rx_mode
) {
9334 tp
->rx_mode
= rx_mode
;
9335 tw32_f(MAC_RX_MODE
, rx_mode
);
9340 static void tg3_set_rx_mode(struct net_device
*dev
)
9342 struct tg3
*tp
= netdev_priv(dev
);
9344 if (!netif_running(dev
))
9347 tg3_full_lock(tp
, 0);
9348 __tg3_set_rx_mode(dev
);
9349 tg3_full_unlock(tp
);
9352 #define TG3_REGDUMP_LEN (32 * 1024)
9354 static int tg3_get_regs_len(struct net_device
*dev
)
9356 return TG3_REGDUMP_LEN
;
9359 static void tg3_get_regs(struct net_device
*dev
,
9360 struct ethtool_regs
*regs
, void *_p
)
9363 struct tg3
*tp
= netdev_priv(dev
);
9369 memset(p
, 0, TG3_REGDUMP_LEN
);
9371 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
9374 tg3_full_lock(tp
, 0);
9376 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9377 #define GET_REG32_LOOP(base, len) \
9378 do { p = (u32 *)(orig_p + (base)); \
9379 for (i = 0; i < len; i += 4) \
9380 __GET_REG32((base) + i); \
9382 #define GET_REG32_1(reg) \
9383 do { p = (u32 *)(orig_p + (reg)); \
9384 __GET_REG32((reg)); \
9387 GET_REG32_LOOP(TG3PCI_VENDOR
, 0xb0);
9388 GET_REG32_LOOP(MAILBOX_INTERRUPT_0
, 0x200);
9389 GET_REG32_LOOP(MAC_MODE
, 0x4f0);
9390 GET_REG32_LOOP(SNDDATAI_MODE
, 0xe0);
9391 GET_REG32_1(SNDDATAC_MODE
);
9392 GET_REG32_LOOP(SNDBDS_MODE
, 0x80);
9393 GET_REG32_LOOP(SNDBDI_MODE
, 0x48);
9394 GET_REG32_1(SNDBDC_MODE
);
9395 GET_REG32_LOOP(RCVLPC_MODE
, 0x20);
9396 GET_REG32_LOOP(RCVLPC_SELLST_BASE
, 0x15c);
9397 GET_REG32_LOOP(RCVDBDI_MODE
, 0x0c);
9398 GET_REG32_LOOP(RCVDBDI_JUMBO_BD
, 0x3c);
9399 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0
, 0x44);
9400 GET_REG32_1(RCVDCC_MODE
);
9401 GET_REG32_LOOP(RCVBDI_MODE
, 0x20);
9402 GET_REG32_LOOP(RCVCC_MODE
, 0x14);
9403 GET_REG32_LOOP(RCVLSC_MODE
, 0x08);
9404 GET_REG32_1(MBFREE_MODE
);
9405 GET_REG32_LOOP(HOSTCC_MODE
, 0x100);
9406 GET_REG32_LOOP(MEMARB_MODE
, 0x10);
9407 GET_REG32_LOOP(BUFMGR_MODE
, 0x58);
9408 GET_REG32_LOOP(RDMAC_MODE
, 0x08);
9409 GET_REG32_LOOP(WDMAC_MODE
, 0x08);
9410 GET_REG32_1(RX_CPU_MODE
);
9411 GET_REG32_1(RX_CPU_STATE
);
9412 GET_REG32_1(RX_CPU_PGMCTR
);
9413 GET_REG32_1(RX_CPU_HWBKPT
);
9414 GET_REG32_1(TX_CPU_MODE
);
9415 GET_REG32_1(TX_CPU_STATE
);
9416 GET_REG32_1(TX_CPU_PGMCTR
);
9417 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0
, 0x110);
9418 GET_REG32_LOOP(FTQ_RESET
, 0x120);
9419 GET_REG32_LOOP(MSGINT_MODE
, 0x0c);
9420 GET_REG32_1(DMAC_MODE
);
9421 GET_REG32_LOOP(GRC_MODE
, 0x4c);
9422 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
9423 GET_REG32_LOOP(NVRAM_CMD
, 0x24);
9426 #undef GET_REG32_LOOP
9429 tg3_full_unlock(tp
);
9432 static int tg3_get_eeprom_len(struct net_device
*dev
)
9434 struct tg3
*tp
= netdev_priv(dev
);
9436 return tp
->nvram_size
;
9439 static int tg3_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
9441 struct tg3
*tp
= netdev_priv(dev
);
9444 u32 i
, offset
, len
, b_offset
, b_count
;
9447 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
)
9450 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
9453 offset
= eeprom
->offset
;
9457 eeprom
->magic
= TG3_EEPROM_MAGIC
;
9460 /* adjustments to start on required 4 byte boundary */
9461 b_offset
= offset
& 3;
9462 b_count
= 4 - b_offset
;
9463 if (b_count
> len
) {
9464 /* i.e. offset=1 len=2 */
9467 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &val
);
9470 memcpy(data
, ((char *)&val
) + b_offset
, b_count
);
9473 eeprom
->len
+= b_count
;
9476 /* read bytes upto the last 4 byte boundary */
9477 pd
= &data
[eeprom
->len
];
9478 for (i
= 0; i
< (len
- (len
& 3)); i
+= 4) {
9479 ret
= tg3_nvram_read_be32(tp
, offset
+ i
, &val
);
9484 memcpy(pd
+ i
, &val
, 4);
9489 /* read last bytes not ending on 4 byte boundary */
9490 pd
= &data
[eeprom
->len
];
9492 b_offset
= offset
+ len
- b_count
;
9493 ret
= tg3_nvram_read_be32(tp
, b_offset
, &val
);
9496 memcpy(pd
, &val
, b_count
);
9497 eeprom
->len
+= b_count
;
9502 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
);
9504 static int tg3_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
9506 struct tg3
*tp
= netdev_priv(dev
);
9508 u32 offset
, len
, b_offset
, odd_len
;
9512 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
9515 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
9516 eeprom
->magic
!= TG3_EEPROM_MAGIC
)
9519 offset
= eeprom
->offset
;
9522 if ((b_offset
= (offset
& 3))) {
9523 /* adjustments to start on required 4 byte boundary */
9524 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &start
);
9535 /* adjustments to end on required 4 byte boundary */
9537 len
= (len
+ 3) & ~3;
9538 ret
= tg3_nvram_read_be32(tp
, offset
+len
-4, &end
);
9544 if (b_offset
|| odd_len
) {
9545 buf
= kmalloc(len
, GFP_KERNEL
);
9549 memcpy(buf
, &start
, 4);
9551 memcpy(buf
+len
-4, &end
, 4);
9552 memcpy(buf
+ b_offset
, data
, eeprom
->len
);
9555 ret
= tg3_nvram_write_block(tp
, offset
, len
, buf
);
9563 static int tg3_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
9565 struct tg3
*tp
= netdev_priv(dev
);
9567 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9568 struct phy_device
*phydev
;
9569 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
9571 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
9572 return phy_ethtool_gset(phydev
, cmd
);
9575 cmd
->supported
= (SUPPORTED_Autoneg
);
9577 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
9578 cmd
->supported
|= (SUPPORTED_1000baseT_Half
|
9579 SUPPORTED_1000baseT_Full
);
9581 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)) {
9582 cmd
->supported
|= (SUPPORTED_100baseT_Half
|
9583 SUPPORTED_100baseT_Full
|
9584 SUPPORTED_10baseT_Half
|
9585 SUPPORTED_10baseT_Full
|
9587 cmd
->port
= PORT_TP
;
9589 cmd
->supported
|= SUPPORTED_FIBRE
;
9590 cmd
->port
= PORT_FIBRE
;
9593 cmd
->advertising
= tp
->link_config
.advertising
;
9594 if (netif_running(dev
)) {
9595 cmd
->speed
= tp
->link_config
.active_speed
;
9596 cmd
->duplex
= tp
->link_config
.active_duplex
;
9598 cmd
->phy_address
= tp
->phy_addr
;
9599 cmd
->transceiver
= XCVR_INTERNAL
;
9600 cmd
->autoneg
= tp
->link_config
.autoneg
;
9606 static int tg3_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
9608 struct tg3
*tp
= netdev_priv(dev
);
9610 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9611 struct phy_device
*phydev
;
9612 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
9614 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
9615 return phy_ethtool_sset(phydev
, cmd
);
9618 if (cmd
->autoneg
!= AUTONEG_ENABLE
&&
9619 cmd
->autoneg
!= AUTONEG_DISABLE
)
9622 if (cmd
->autoneg
== AUTONEG_DISABLE
&&
9623 cmd
->duplex
!= DUPLEX_FULL
&&
9624 cmd
->duplex
!= DUPLEX_HALF
)
9627 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
9628 u32 mask
= ADVERTISED_Autoneg
|
9630 ADVERTISED_Asym_Pause
;
9632 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
9633 mask
|= ADVERTISED_1000baseT_Half
|
9634 ADVERTISED_1000baseT_Full
;
9636 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
9637 mask
|= ADVERTISED_100baseT_Half
|
9638 ADVERTISED_100baseT_Full
|
9639 ADVERTISED_10baseT_Half
|
9640 ADVERTISED_10baseT_Full
|
9643 mask
|= ADVERTISED_FIBRE
;
9645 if (cmd
->advertising
& ~mask
)
9648 mask
&= (ADVERTISED_1000baseT_Half
|
9649 ADVERTISED_1000baseT_Full
|
9650 ADVERTISED_100baseT_Half
|
9651 ADVERTISED_100baseT_Full
|
9652 ADVERTISED_10baseT_Half
|
9653 ADVERTISED_10baseT_Full
);
9655 cmd
->advertising
&= mask
;
9657 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
) {
9658 if (cmd
->speed
!= SPEED_1000
)
9661 if (cmd
->duplex
!= DUPLEX_FULL
)
9664 if (cmd
->speed
!= SPEED_100
&&
9665 cmd
->speed
!= SPEED_10
)
9670 tg3_full_lock(tp
, 0);
9672 tp
->link_config
.autoneg
= cmd
->autoneg
;
9673 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
9674 tp
->link_config
.advertising
= (cmd
->advertising
|
9675 ADVERTISED_Autoneg
);
9676 tp
->link_config
.speed
= SPEED_INVALID
;
9677 tp
->link_config
.duplex
= DUPLEX_INVALID
;
9679 tp
->link_config
.advertising
= 0;
9680 tp
->link_config
.speed
= cmd
->speed
;
9681 tp
->link_config
.duplex
= cmd
->duplex
;
9684 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
9685 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
9686 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
9688 if (netif_running(dev
))
9689 tg3_setup_phy(tp
, 1);
9691 tg3_full_unlock(tp
);
9696 static void tg3_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
9698 struct tg3
*tp
= netdev_priv(dev
);
9700 strcpy(info
->driver
, DRV_MODULE_NAME
);
9701 strcpy(info
->version
, DRV_MODULE_VERSION
);
9702 strcpy(info
->fw_version
, tp
->fw_ver
);
9703 strcpy(info
->bus_info
, pci_name(tp
->pdev
));
9706 static void tg3_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
9708 struct tg3
*tp
= netdev_priv(dev
);
9710 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
9711 device_can_wakeup(&tp
->pdev
->dev
))
9712 wol
->supported
= WAKE_MAGIC
;
9716 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) &&
9717 device_can_wakeup(&tp
->pdev
->dev
))
9718 wol
->wolopts
= WAKE_MAGIC
;
9719 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
9722 static int tg3_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
9724 struct tg3
*tp
= netdev_priv(dev
);
9725 struct device
*dp
= &tp
->pdev
->dev
;
9727 if (wol
->wolopts
& ~WAKE_MAGIC
)
9729 if ((wol
->wolopts
& WAKE_MAGIC
) &&
9730 !((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) && device_can_wakeup(dp
)))
9733 spin_lock_bh(&tp
->lock
);
9734 if (wol
->wolopts
& WAKE_MAGIC
) {
9735 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
9736 device_set_wakeup_enable(dp
, true);
9738 tp
->tg3_flags
&= ~TG3_FLAG_WOL_ENABLE
;
9739 device_set_wakeup_enable(dp
, false);
9741 spin_unlock_bh(&tp
->lock
);
9746 static u32
tg3_get_msglevel(struct net_device
*dev
)
9748 struct tg3
*tp
= netdev_priv(dev
);
9749 return tp
->msg_enable
;
9752 static void tg3_set_msglevel(struct net_device
*dev
, u32 value
)
9754 struct tg3
*tp
= netdev_priv(dev
);
9755 tp
->msg_enable
= value
;
9758 static int tg3_set_tso(struct net_device
*dev
, u32 value
)
9760 struct tg3
*tp
= netdev_priv(dev
);
9762 if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
9767 if ((dev
->features
& NETIF_F_IPV6_CSUM
) &&
9768 ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
) ||
9769 (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
))) {
9771 dev
->features
|= NETIF_F_TSO6
;
9772 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) ||
9773 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
9774 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
9775 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) ||
9776 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
9777 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
9778 dev
->features
|= NETIF_F_TSO_ECN
;
9780 dev
->features
&= ~(NETIF_F_TSO6
| NETIF_F_TSO_ECN
);
9782 return ethtool_op_set_tso(dev
, value
);
9785 static int tg3_nway_reset(struct net_device
*dev
)
9787 struct tg3
*tp
= netdev_priv(dev
);
9790 if (!netif_running(dev
))
9793 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
9796 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9797 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
9799 r
= phy_start_aneg(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
9803 spin_lock_bh(&tp
->lock
);
9805 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
9806 if (!tg3_readphy(tp
, MII_BMCR
, &bmcr
) &&
9807 ((bmcr
& BMCR_ANENABLE
) ||
9808 (tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
))) {
9809 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANRESTART
|
9813 spin_unlock_bh(&tp
->lock
);
9819 static void tg3_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
9821 struct tg3
*tp
= netdev_priv(dev
);
9823 ering
->rx_max_pending
= TG3_RX_RING_SIZE
- 1;
9824 ering
->rx_mini_max_pending
= 0;
9825 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
9826 ering
->rx_jumbo_max_pending
= TG3_RX_JUMBO_RING_SIZE
- 1;
9828 ering
->rx_jumbo_max_pending
= 0;
9830 ering
->tx_max_pending
= TG3_TX_RING_SIZE
- 1;
9832 ering
->rx_pending
= tp
->rx_pending
;
9833 ering
->rx_mini_pending
= 0;
9834 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
9835 ering
->rx_jumbo_pending
= tp
->rx_jumbo_pending
;
9837 ering
->rx_jumbo_pending
= 0;
9839 ering
->tx_pending
= tp
->napi
[0].tx_pending
;
9842 static int tg3_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
9844 struct tg3
*tp
= netdev_priv(dev
);
9845 int i
, irq_sync
= 0, err
= 0;
9847 if ((ering
->rx_pending
> TG3_RX_RING_SIZE
- 1) ||
9848 (ering
->rx_jumbo_pending
> TG3_RX_JUMBO_RING_SIZE
- 1) ||
9849 (ering
->tx_pending
> TG3_TX_RING_SIZE
- 1) ||
9850 (ering
->tx_pending
<= MAX_SKB_FRAGS
) ||
9851 ((tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
) &&
9852 (ering
->tx_pending
<= (MAX_SKB_FRAGS
* 3))))
9855 if (netif_running(dev
)) {
9861 tg3_full_lock(tp
, irq_sync
);
9863 tp
->rx_pending
= ering
->rx_pending
;
9865 if ((tp
->tg3_flags2
& TG3_FLG2_MAX_RXPEND_64
) &&
9866 tp
->rx_pending
> 63)
9867 tp
->rx_pending
= 63;
9868 tp
->rx_jumbo_pending
= ering
->rx_jumbo_pending
;
9870 for (i
= 0; i
< TG3_IRQ_MAX_VECS
; i
++)
9871 tp
->napi
[i
].tx_pending
= ering
->tx_pending
;
9873 if (netif_running(dev
)) {
9874 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9875 err
= tg3_restart_hw(tp
, 1);
9877 tg3_netif_start(tp
);
9880 tg3_full_unlock(tp
);
9882 if (irq_sync
&& !err
)
9888 static void tg3_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
9890 struct tg3
*tp
= netdev_priv(dev
);
9892 epause
->autoneg
= (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
) != 0;
9894 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
)
9895 epause
->rx_pause
= 1;
9897 epause
->rx_pause
= 0;
9899 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
)
9900 epause
->tx_pause
= 1;
9902 epause
->tx_pause
= 0;
9905 static int tg3_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
9907 struct tg3
*tp
= netdev_priv(dev
);
9910 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9912 struct phy_device
*phydev
;
9914 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
9916 if (!(phydev
->supported
& SUPPORTED_Pause
) ||
9917 (!(phydev
->supported
& SUPPORTED_Asym_Pause
) &&
9918 ((epause
->rx_pause
&& !epause
->tx_pause
) ||
9919 (!epause
->rx_pause
&& epause
->tx_pause
))))
9922 tp
->link_config
.flowctrl
= 0;
9923 if (epause
->rx_pause
) {
9924 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
9926 if (epause
->tx_pause
) {
9927 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
9928 newadv
= ADVERTISED_Pause
;
9930 newadv
= ADVERTISED_Pause
|
9931 ADVERTISED_Asym_Pause
;
9932 } else if (epause
->tx_pause
) {
9933 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
9934 newadv
= ADVERTISED_Asym_Pause
;
9938 if (epause
->autoneg
)
9939 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
9941 tp
->tg3_flags
&= ~TG3_FLAG_PAUSE_AUTONEG
;
9943 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) {
9944 u32 oldadv
= phydev
->advertising
&
9945 (ADVERTISED_Pause
| ADVERTISED_Asym_Pause
);
9946 if (oldadv
!= newadv
) {
9947 phydev
->advertising
&=
9948 ~(ADVERTISED_Pause
|
9949 ADVERTISED_Asym_Pause
);
9950 phydev
->advertising
|= newadv
;
9951 if (phydev
->autoneg
) {
9953 * Always renegotiate the link to
9954 * inform our link partner of our
9955 * flow control settings, even if the
9956 * flow control is forced. Let
9957 * tg3_adjust_link() do the final
9958 * flow control setup.
9960 return phy_start_aneg(phydev
);
9964 if (!epause
->autoneg
)
9965 tg3_setup_flow_control(tp
, 0, 0);
9967 tp
->link_config
.orig_advertising
&=
9968 ~(ADVERTISED_Pause
|
9969 ADVERTISED_Asym_Pause
);
9970 tp
->link_config
.orig_advertising
|= newadv
;
9975 if (netif_running(dev
)) {
9980 tg3_full_lock(tp
, irq_sync
);
9982 if (epause
->autoneg
)
9983 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
9985 tp
->tg3_flags
&= ~TG3_FLAG_PAUSE_AUTONEG
;
9986 if (epause
->rx_pause
)
9987 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
9989 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_RX
;
9990 if (epause
->tx_pause
)
9991 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
9993 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_TX
;
9995 if (netif_running(dev
)) {
9996 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9997 err
= tg3_restart_hw(tp
, 1);
9999 tg3_netif_start(tp
);
10002 tg3_full_unlock(tp
);
10008 static u32
tg3_get_rx_csum(struct net_device
*dev
)
10010 struct tg3
*tp
= netdev_priv(dev
);
10011 return (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0;
10014 static int tg3_set_rx_csum(struct net_device
*dev
, u32 data
)
10016 struct tg3
*tp
= netdev_priv(dev
);
10018 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
10024 spin_lock_bh(&tp
->lock
);
10026 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
10028 tp
->tg3_flags
&= ~TG3_FLAG_RX_CHECKSUMS
;
10029 spin_unlock_bh(&tp
->lock
);
10034 static int tg3_set_tx_csum(struct net_device
*dev
, u32 data
)
10036 struct tg3
*tp
= netdev_priv(dev
);
10038 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
10044 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
10045 ethtool_op_set_tx_ipv6_csum(dev
, data
);
10047 ethtool_op_set_tx_csum(dev
, data
);
10052 static int tg3_get_sset_count(struct net_device
*dev
, int sset
)
10056 return TG3_NUM_TEST
;
10058 return TG3_NUM_STATS
;
10060 return -EOPNOTSUPP
;
10064 static void tg3_get_strings(struct net_device
*dev
, u32 stringset
, u8
*buf
)
10066 switch (stringset
) {
10068 memcpy(buf
, ðtool_stats_keys
, sizeof(ethtool_stats_keys
));
10071 memcpy(buf
, ðtool_test_keys
, sizeof(ethtool_test_keys
));
10074 WARN_ON(1); /* we need a WARN() */
10079 static int tg3_phys_id(struct net_device
*dev
, u32 data
)
10081 struct tg3
*tp
= netdev_priv(dev
);
10084 if (!netif_running(tp
->dev
))
10088 data
= UINT_MAX
/ 2;
10090 for (i
= 0; i
< (data
* 2); i
++) {
10092 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
10093 LED_CTRL_1000MBPS_ON
|
10094 LED_CTRL_100MBPS_ON
|
10095 LED_CTRL_10MBPS_ON
|
10096 LED_CTRL_TRAFFIC_OVERRIDE
|
10097 LED_CTRL_TRAFFIC_BLINK
|
10098 LED_CTRL_TRAFFIC_LED
);
10101 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
10102 LED_CTRL_TRAFFIC_OVERRIDE
);
10104 if (msleep_interruptible(500))
10107 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
10111 static void tg3_get_ethtool_stats(struct net_device
*dev
,
10112 struct ethtool_stats
*estats
, u64
*tmp_stats
)
10114 struct tg3
*tp
= netdev_priv(dev
);
10115 memcpy(tmp_stats
, tg3_get_estats(tp
), sizeof(tp
->estats
));
10118 #define NVRAM_TEST_SIZE 0x100
10119 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10120 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10121 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10122 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10123 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10125 static int tg3_test_nvram(struct tg3
*tp
)
10129 int i
, j
, k
, err
= 0, size
;
10131 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
)
10134 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
10137 if (magic
== TG3_EEPROM_MAGIC
)
10138 size
= NVRAM_TEST_SIZE
;
10139 else if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
) {
10140 if ((magic
& TG3_EEPROM_SB_FORMAT_MASK
) ==
10141 TG3_EEPROM_SB_FORMAT_1
) {
10142 switch (magic
& TG3_EEPROM_SB_REVISION_MASK
) {
10143 case TG3_EEPROM_SB_REVISION_0
:
10144 size
= NVRAM_SELFBOOT_FORMAT1_0_SIZE
;
10146 case TG3_EEPROM_SB_REVISION_2
:
10147 size
= NVRAM_SELFBOOT_FORMAT1_2_SIZE
;
10149 case TG3_EEPROM_SB_REVISION_3
:
10150 size
= NVRAM_SELFBOOT_FORMAT1_3_SIZE
;
10157 } else if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
10158 size
= NVRAM_SELFBOOT_HW_SIZE
;
10162 buf
= kmalloc(size
, GFP_KERNEL
);
10167 for (i
= 0, j
= 0; i
< size
; i
+= 4, j
++) {
10168 err
= tg3_nvram_read_be32(tp
, i
, &buf
[j
]);
10175 /* Selfboot format */
10176 magic
= be32_to_cpu(buf
[0]);
10177 if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) ==
10178 TG3_EEPROM_MAGIC_FW
) {
10179 u8
*buf8
= (u8
*) buf
, csum8
= 0;
10181 if ((magic
& TG3_EEPROM_SB_REVISION_MASK
) ==
10182 TG3_EEPROM_SB_REVISION_2
) {
10183 /* For rev 2, the csum doesn't include the MBA. */
10184 for (i
= 0; i
< TG3_EEPROM_SB_F1R2_MBA_OFF
; i
++)
10186 for (i
= TG3_EEPROM_SB_F1R2_MBA_OFF
+ 4; i
< size
; i
++)
10189 for (i
= 0; i
< size
; i
++)
10202 if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) ==
10203 TG3_EEPROM_MAGIC_HW
) {
10204 u8 data
[NVRAM_SELFBOOT_DATA_SIZE
];
10205 u8 parity
[NVRAM_SELFBOOT_DATA_SIZE
];
10206 u8
*buf8
= (u8
*) buf
;
10208 /* Separate the parity bits and the data bytes. */
10209 for (i
= 0, j
= 0, k
= 0; i
< NVRAM_SELFBOOT_HW_SIZE
; i
++) {
10210 if ((i
== 0) || (i
== 8)) {
10214 for (l
= 0, msk
= 0x80; l
< 7; l
++, msk
>>= 1)
10215 parity
[k
++] = buf8
[i
] & msk
;
10217 } else if (i
== 16) {
10221 for (l
= 0, msk
= 0x20; l
< 6; l
++, msk
>>= 1)
10222 parity
[k
++] = buf8
[i
] & msk
;
10225 for (l
= 0, msk
= 0x80; l
< 8; l
++, msk
>>= 1)
10226 parity
[k
++] = buf8
[i
] & msk
;
10229 data
[j
++] = buf8
[i
];
10233 for (i
= 0; i
< NVRAM_SELFBOOT_DATA_SIZE
; i
++) {
10234 u8 hw8
= hweight8(data
[i
]);
10236 if ((hw8
& 0x1) && parity
[i
])
10238 else if (!(hw8
& 0x1) && !parity
[i
])
10245 /* Bootstrap checksum at offset 0x10 */
10246 csum
= calc_crc((unsigned char *) buf
, 0x10);
10247 if (csum
!= be32_to_cpu(buf
[0x10/4]))
10250 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10251 csum
= calc_crc((unsigned char *) &buf
[0x74/4], 0x88);
10252 if (csum
!= be32_to_cpu(buf
[0xfc/4]))
10262 #define TG3_SERDES_TIMEOUT_SEC 2
10263 #define TG3_COPPER_TIMEOUT_SEC 6
10265 static int tg3_test_link(struct tg3
*tp
)
10269 if (!netif_running(tp
->dev
))
10272 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
10273 max
= TG3_SERDES_TIMEOUT_SEC
;
10275 max
= TG3_COPPER_TIMEOUT_SEC
;
10277 for (i
= 0; i
< max
; i
++) {
10278 if (netif_carrier_ok(tp
->dev
))
10281 if (msleep_interruptible(1000))
10288 /* Only test the commonly used registers */
10289 static int tg3_test_registers(struct tg3
*tp
)
10291 int i
, is_5705
, is_5750
;
10292 u32 offset
, read_mask
, write_mask
, val
, save_val
, read_val
;
10296 #define TG3_FL_5705 0x1
10297 #define TG3_FL_NOT_5705 0x2
10298 #define TG3_FL_NOT_5788 0x4
10299 #define TG3_FL_NOT_5750 0x8
10303 /* MAC Control Registers */
10304 { MAC_MODE
, TG3_FL_NOT_5705
,
10305 0x00000000, 0x00ef6f8c },
10306 { MAC_MODE
, TG3_FL_5705
,
10307 0x00000000, 0x01ef6b8c },
10308 { MAC_STATUS
, TG3_FL_NOT_5705
,
10309 0x03800107, 0x00000000 },
10310 { MAC_STATUS
, TG3_FL_5705
,
10311 0x03800100, 0x00000000 },
10312 { MAC_ADDR_0_HIGH
, 0x0000,
10313 0x00000000, 0x0000ffff },
10314 { MAC_ADDR_0_LOW
, 0x0000,
10315 0x00000000, 0xffffffff },
10316 { MAC_RX_MTU_SIZE
, 0x0000,
10317 0x00000000, 0x0000ffff },
10318 { MAC_TX_MODE
, 0x0000,
10319 0x00000000, 0x00000070 },
10320 { MAC_TX_LENGTHS
, 0x0000,
10321 0x00000000, 0x00003fff },
10322 { MAC_RX_MODE
, TG3_FL_NOT_5705
,
10323 0x00000000, 0x000007fc },
10324 { MAC_RX_MODE
, TG3_FL_5705
,
10325 0x00000000, 0x000007dc },
10326 { MAC_HASH_REG_0
, 0x0000,
10327 0x00000000, 0xffffffff },
10328 { MAC_HASH_REG_1
, 0x0000,
10329 0x00000000, 0xffffffff },
10330 { MAC_HASH_REG_2
, 0x0000,
10331 0x00000000, 0xffffffff },
10332 { MAC_HASH_REG_3
, 0x0000,
10333 0x00000000, 0xffffffff },
10335 /* Receive Data and Receive BD Initiator Control Registers. */
10336 { RCVDBDI_JUMBO_BD
+0, TG3_FL_NOT_5705
,
10337 0x00000000, 0xffffffff },
10338 { RCVDBDI_JUMBO_BD
+4, TG3_FL_NOT_5705
,
10339 0x00000000, 0xffffffff },
10340 { RCVDBDI_JUMBO_BD
+8, TG3_FL_NOT_5705
,
10341 0x00000000, 0x00000003 },
10342 { RCVDBDI_JUMBO_BD
+0xc, TG3_FL_NOT_5705
,
10343 0x00000000, 0xffffffff },
10344 { RCVDBDI_STD_BD
+0, 0x0000,
10345 0x00000000, 0xffffffff },
10346 { RCVDBDI_STD_BD
+4, 0x0000,
10347 0x00000000, 0xffffffff },
10348 { RCVDBDI_STD_BD
+8, 0x0000,
10349 0x00000000, 0xffff0002 },
10350 { RCVDBDI_STD_BD
+0xc, 0x0000,
10351 0x00000000, 0xffffffff },
10353 /* Receive BD Initiator Control Registers. */
10354 { RCVBDI_STD_THRESH
, TG3_FL_NOT_5705
,
10355 0x00000000, 0xffffffff },
10356 { RCVBDI_STD_THRESH
, TG3_FL_5705
,
10357 0x00000000, 0x000003ff },
10358 { RCVBDI_JUMBO_THRESH
, TG3_FL_NOT_5705
,
10359 0x00000000, 0xffffffff },
10361 /* Host Coalescing Control Registers. */
10362 { HOSTCC_MODE
, TG3_FL_NOT_5705
,
10363 0x00000000, 0x00000004 },
10364 { HOSTCC_MODE
, TG3_FL_5705
,
10365 0x00000000, 0x000000f6 },
10366 { HOSTCC_RXCOL_TICKS
, TG3_FL_NOT_5705
,
10367 0x00000000, 0xffffffff },
10368 { HOSTCC_RXCOL_TICKS
, TG3_FL_5705
,
10369 0x00000000, 0x000003ff },
10370 { HOSTCC_TXCOL_TICKS
, TG3_FL_NOT_5705
,
10371 0x00000000, 0xffffffff },
10372 { HOSTCC_TXCOL_TICKS
, TG3_FL_5705
,
10373 0x00000000, 0x000003ff },
10374 { HOSTCC_RXMAX_FRAMES
, TG3_FL_NOT_5705
,
10375 0x00000000, 0xffffffff },
10376 { HOSTCC_RXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10377 0x00000000, 0x000000ff },
10378 { HOSTCC_TXMAX_FRAMES
, TG3_FL_NOT_5705
,
10379 0x00000000, 0xffffffff },
10380 { HOSTCC_TXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10381 0x00000000, 0x000000ff },
10382 { HOSTCC_RXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
10383 0x00000000, 0xffffffff },
10384 { HOSTCC_TXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
10385 0x00000000, 0xffffffff },
10386 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
10387 0x00000000, 0xffffffff },
10388 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10389 0x00000000, 0x000000ff },
10390 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
10391 0x00000000, 0xffffffff },
10392 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10393 0x00000000, 0x000000ff },
10394 { HOSTCC_STAT_COAL_TICKS
, TG3_FL_NOT_5705
,
10395 0x00000000, 0xffffffff },
10396 { HOSTCC_STATS_BLK_HOST_ADDR
, TG3_FL_NOT_5705
,
10397 0x00000000, 0xffffffff },
10398 { HOSTCC_STATS_BLK_HOST_ADDR
+4, TG3_FL_NOT_5705
,
10399 0x00000000, 0xffffffff },
10400 { HOSTCC_STATUS_BLK_HOST_ADDR
, 0x0000,
10401 0x00000000, 0xffffffff },
10402 { HOSTCC_STATUS_BLK_HOST_ADDR
+4, 0x0000,
10403 0x00000000, 0xffffffff },
10404 { HOSTCC_STATS_BLK_NIC_ADDR
, 0x0000,
10405 0xffffffff, 0x00000000 },
10406 { HOSTCC_STATUS_BLK_NIC_ADDR
, 0x0000,
10407 0xffffffff, 0x00000000 },
10409 /* Buffer Manager Control Registers. */
10410 { BUFMGR_MB_POOL_ADDR
, TG3_FL_NOT_5750
,
10411 0x00000000, 0x007fff80 },
10412 { BUFMGR_MB_POOL_SIZE
, TG3_FL_NOT_5750
,
10413 0x00000000, 0x007fffff },
10414 { BUFMGR_MB_RDMA_LOW_WATER
, 0x0000,
10415 0x00000000, 0x0000003f },
10416 { BUFMGR_MB_MACRX_LOW_WATER
, 0x0000,
10417 0x00000000, 0x000001ff },
10418 { BUFMGR_MB_HIGH_WATER
, 0x0000,
10419 0x00000000, 0x000001ff },
10420 { BUFMGR_DMA_DESC_POOL_ADDR
, TG3_FL_NOT_5705
,
10421 0xffffffff, 0x00000000 },
10422 { BUFMGR_DMA_DESC_POOL_SIZE
, TG3_FL_NOT_5705
,
10423 0xffffffff, 0x00000000 },
10425 /* Mailbox Registers */
10426 { GRCMBOX_RCVSTD_PROD_IDX
+4, 0x0000,
10427 0x00000000, 0x000001ff },
10428 { GRCMBOX_RCVJUMBO_PROD_IDX
+4, TG3_FL_NOT_5705
,
10429 0x00000000, 0x000001ff },
10430 { GRCMBOX_RCVRET_CON_IDX_0
+4, 0x0000,
10431 0x00000000, 0x000007ff },
10432 { GRCMBOX_SNDHOST_PROD_IDX_0
+4, 0x0000,
10433 0x00000000, 0x000001ff },
10435 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10438 is_5705
= is_5750
= 0;
10439 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
10441 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
10445 for (i
= 0; reg_tbl
[i
].offset
!= 0xffff; i
++) {
10446 if (is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5705
))
10449 if (!is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_5705
))
10452 if ((tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
10453 (reg_tbl
[i
].flags
& TG3_FL_NOT_5788
))
10456 if (is_5750
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5750
))
10459 offset
= (u32
) reg_tbl
[i
].offset
;
10460 read_mask
= reg_tbl
[i
].read_mask
;
10461 write_mask
= reg_tbl
[i
].write_mask
;
10463 /* Save the original register content */
10464 save_val
= tr32(offset
);
10466 /* Determine the read-only value. */
10467 read_val
= save_val
& read_mask
;
10469 /* Write zero to the register, then make sure the read-only bits
10470 * are not changed and the read/write bits are all zeros.
10474 val
= tr32(offset
);
10476 /* Test the read-only and read/write bits. */
10477 if (((val
& read_mask
) != read_val
) || (val
& write_mask
))
10480 /* Write ones to all the bits defined by RdMask and WrMask, then
10481 * make sure the read-only bits are not changed and the
10482 * read/write bits are all ones.
10484 tw32(offset
, read_mask
| write_mask
);
10486 val
= tr32(offset
);
10488 /* Test the read-only bits. */
10489 if ((val
& read_mask
) != read_val
)
10492 /* Test the read/write bits. */
10493 if ((val
& write_mask
) != write_mask
)
10496 tw32(offset
, save_val
);
10502 if (netif_msg_hw(tp
))
10503 netdev_err(tp
->dev
,
10504 "Register test failed at offset %x\n", offset
);
10505 tw32(offset
, save_val
);
10509 static int tg3_do_mem_test(struct tg3
*tp
, u32 offset
, u32 len
)
10511 static const u32 test_pattern
[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10515 for (i
= 0; i
< ARRAY_SIZE(test_pattern
); i
++) {
10516 for (j
= 0; j
< len
; j
+= 4) {
10519 tg3_write_mem(tp
, offset
+ j
, test_pattern
[i
]);
10520 tg3_read_mem(tp
, offset
+ j
, &val
);
10521 if (val
!= test_pattern
[i
])
10528 static int tg3_test_memory(struct tg3
*tp
)
10530 static struct mem_entry
{
10533 } mem_tbl_570x
[] = {
10534 { 0x00000000, 0x00b50},
10535 { 0x00002000, 0x1c000},
10536 { 0xffffffff, 0x00000}
10537 }, mem_tbl_5705
[] = {
10538 { 0x00000100, 0x0000c},
10539 { 0x00000200, 0x00008},
10540 { 0x00004000, 0x00800},
10541 { 0x00006000, 0x01000},
10542 { 0x00008000, 0x02000},
10543 { 0x00010000, 0x0e000},
10544 { 0xffffffff, 0x00000}
10545 }, mem_tbl_5755
[] = {
10546 { 0x00000200, 0x00008},
10547 { 0x00004000, 0x00800},
10548 { 0x00006000, 0x00800},
10549 { 0x00008000, 0x02000},
10550 { 0x00010000, 0x0c000},
10551 { 0xffffffff, 0x00000}
10552 }, mem_tbl_5906
[] = {
10553 { 0x00000200, 0x00008},
10554 { 0x00004000, 0x00400},
10555 { 0x00006000, 0x00400},
10556 { 0x00008000, 0x01000},
10557 { 0x00010000, 0x01000},
10558 { 0xffffffff, 0x00000}
10559 }, mem_tbl_5717
[] = {
10560 { 0x00000200, 0x00008},
10561 { 0x00010000, 0x0a000},
10562 { 0x00020000, 0x13c00},
10563 { 0xffffffff, 0x00000}
10564 }, mem_tbl_57765
[] = {
10565 { 0x00000200, 0x00008},
10566 { 0x00004000, 0x00800},
10567 { 0x00006000, 0x09800},
10568 { 0x00010000, 0x0a000},
10569 { 0xffffffff, 0x00000}
10571 struct mem_entry
*mem_tbl
;
10575 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
10576 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
)
10577 mem_tbl
= mem_tbl_5717
;
10578 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
10579 mem_tbl
= mem_tbl_57765
;
10580 else if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
10581 mem_tbl
= mem_tbl_5755
;
10582 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
10583 mem_tbl
= mem_tbl_5906
;
10584 else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
10585 mem_tbl
= mem_tbl_5705
;
10587 mem_tbl
= mem_tbl_570x
;
10589 for (i
= 0; mem_tbl
[i
].offset
!= 0xffffffff; i
++) {
10590 err
= tg3_do_mem_test(tp
, mem_tbl
[i
].offset
, mem_tbl
[i
].len
);
10598 #define TG3_MAC_LOOPBACK 0
10599 #define TG3_PHY_LOOPBACK 1
10601 static int tg3_run_loopback(struct tg3
*tp
, int loopback_mode
)
10603 u32 mac_mode
, rx_start_idx
, rx_idx
, tx_idx
, opaque_key
;
10604 u32 desc_idx
, coal_now
;
10605 struct sk_buff
*skb
, *rx_skb
;
10608 int num_pkts
, tx_len
, rx_len
, i
, err
;
10609 struct tg3_rx_buffer_desc
*desc
;
10610 struct tg3_napi
*tnapi
, *rnapi
;
10611 struct tg3_rx_prodring_set
*tpr
= &tp
->prodring
[0];
10613 tnapi
= &tp
->napi
[0];
10614 rnapi
= &tp
->napi
[0];
10615 if (tp
->irq_cnt
> 1) {
10616 rnapi
= &tp
->napi
[1];
10617 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
10618 tnapi
= &tp
->napi
[1];
10620 coal_now
= tnapi
->coal_now
| rnapi
->coal_now
;
10622 if (loopback_mode
== TG3_MAC_LOOPBACK
) {
10623 /* HW errata - mac loopback fails in some cases on 5780.
10624 * Normal traffic and PHY loopback are not affected by
10627 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
)
10630 mac_mode
= (tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
) |
10631 MAC_MODE_PORT_INT_LPBACK
;
10632 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
10633 mac_mode
|= MAC_MODE_LINK_POLARITY
;
10634 if (tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)
10635 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
10637 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
10638 tw32(MAC_MODE
, mac_mode
);
10639 } else if (loopback_mode
== TG3_PHY_LOOPBACK
) {
10642 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
10643 tg3_phy_fet_toggle_apd(tp
, false);
10644 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED100
;
10646 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED1000
;
10648 tg3_phy_toggle_automdix(tp
, 0);
10650 tg3_writephy(tp
, MII_BMCR
, val
);
10653 mac_mode
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
10654 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
10655 tg3_writephy(tp
, MII_TG3_FET_PTEST
,
10656 MII_TG3_FET_PTEST_FRC_TX_LINK
|
10657 MII_TG3_FET_PTEST_FRC_TX_LOCK
);
10658 /* The write needs to be flushed for the AC131 */
10659 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
10660 tg3_readphy(tp
, MII_TG3_FET_PTEST
, &val
);
10661 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
10663 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
10665 /* reset to prevent losing 1st rx packet intermittently */
10666 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) {
10667 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
10669 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
10671 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
10672 u32 masked_phy_id
= tp
->phy_id
& TG3_PHY_ID_MASK
;
10673 if (masked_phy_id
== TG3_PHY_ID_BCM5401
)
10674 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
10675 else if (masked_phy_id
== TG3_PHY_ID_BCM5411
)
10676 mac_mode
|= MAC_MODE_LINK_POLARITY
;
10677 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
10678 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
10680 tw32(MAC_MODE
, mac_mode
);
10688 skb
= netdev_alloc_skb(tp
->dev
, tx_len
);
10692 tx_data
= skb_put(skb
, tx_len
);
10693 memcpy(tx_data
, tp
->dev
->dev_addr
, 6);
10694 memset(tx_data
+ 6, 0x0, 8);
10696 tw32(MAC_RX_MTU_SIZE
, tx_len
+ 4);
10698 for (i
= 14; i
< tx_len
; i
++)
10699 tx_data
[i
] = (u8
) (i
& 0xff);
10701 map
= pci_map_single(tp
->pdev
, skb
->data
, tx_len
, PCI_DMA_TODEVICE
);
10702 if (pci_dma_mapping_error(tp
->pdev
, map
)) {
10703 dev_kfree_skb(skb
);
10707 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
10712 rx_start_idx
= rnapi
->hw_status
->idx
[0].rx_producer
;
10716 tg3_set_txd(tnapi
, tnapi
->tx_prod
, map
, tx_len
, 0, 1);
10721 tw32_tx_mbox(tnapi
->prodmbox
, tnapi
->tx_prod
);
10722 tr32_mailbox(tnapi
->prodmbox
);
10726 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10727 for (i
= 0; i
< 35; i
++) {
10728 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
10733 tx_idx
= tnapi
->hw_status
->idx
[0].tx_consumer
;
10734 rx_idx
= rnapi
->hw_status
->idx
[0].rx_producer
;
10735 if ((tx_idx
== tnapi
->tx_prod
) &&
10736 (rx_idx
== (rx_start_idx
+ num_pkts
)))
10740 pci_unmap_single(tp
->pdev
, map
, tx_len
, PCI_DMA_TODEVICE
);
10741 dev_kfree_skb(skb
);
10743 if (tx_idx
!= tnapi
->tx_prod
)
10746 if (rx_idx
!= rx_start_idx
+ num_pkts
)
10749 desc
= &rnapi
->rx_rcb
[rx_start_idx
];
10750 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
10751 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
10752 if (opaque_key
!= RXD_OPAQUE_RING_STD
)
10755 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
10756 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
))
10759 rx_len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) - 4;
10760 if (rx_len
!= tx_len
)
10763 rx_skb
= tpr
->rx_std_buffers
[desc_idx
].skb
;
10765 map
= dma_unmap_addr(&tpr
->rx_std_buffers
[desc_idx
], mapping
);
10766 pci_dma_sync_single_for_cpu(tp
->pdev
, map
, rx_len
, PCI_DMA_FROMDEVICE
);
10768 for (i
= 14; i
< tx_len
; i
++) {
10769 if (*(rx_skb
->data
+ i
) != (u8
) (i
& 0xff))
10774 /* tg3_free_rings will unmap and free the rx_skb */
10779 #define TG3_MAC_LOOPBACK_FAILED 1
10780 #define TG3_PHY_LOOPBACK_FAILED 2
10781 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10782 TG3_PHY_LOOPBACK_FAILED)
10784 static int tg3_test_loopback(struct tg3
*tp
)
10789 if (!netif_running(tp
->dev
))
10790 return TG3_LOOPBACK_FAILED
;
10792 err
= tg3_reset_hw(tp
, 1);
10794 return TG3_LOOPBACK_FAILED
;
10796 /* Turn off gphy autopowerdown. */
10797 if (tp
->phy_flags
& TG3_PHYFLG_ENABLE_APD
)
10798 tg3_phy_toggle_apd(tp
, false);
10800 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
10804 tw32(TG3_CPMU_MUTEX_REQ
, CPMU_MUTEX_REQ_DRIVER
);
10806 /* Wait for up to 40 microseconds to acquire lock. */
10807 for (i
= 0; i
< 4; i
++) {
10808 status
= tr32(TG3_CPMU_MUTEX_GNT
);
10809 if (status
== CPMU_MUTEX_GNT_DRIVER
)
10814 if (status
!= CPMU_MUTEX_GNT_DRIVER
)
10815 return TG3_LOOPBACK_FAILED
;
10817 /* Turn off link-based power management. */
10818 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
10819 tw32(TG3_CPMU_CTRL
,
10820 cpmuctrl
& ~(CPMU_CTRL_LINK_SPEED_MODE
|
10821 CPMU_CTRL_LINK_AWARE_MODE
));
10824 if (tg3_run_loopback(tp
, TG3_MAC_LOOPBACK
))
10825 err
|= TG3_MAC_LOOPBACK_FAILED
;
10827 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
10828 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
10830 /* Release the mutex */
10831 tw32(TG3_CPMU_MUTEX_GNT
, CPMU_MUTEX_GNT_DRIVER
);
10834 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
10835 !(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
10836 if (tg3_run_loopback(tp
, TG3_PHY_LOOPBACK
))
10837 err
|= TG3_PHY_LOOPBACK_FAILED
;
10840 /* Re-enable gphy autopowerdown. */
10841 if (tp
->phy_flags
& TG3_PHYFLG_ENABLE_APD
)
10842 tg3_phy_toggle_apd(tp
, true);
10847 static void tg3_self_test(struct net_device
*dev
, struct ethtool_test
*etest
,
10850 struct tg3
*tp
= netdev_priv(dev
);
10852 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
10853 tg3_set_power_state(tp
, PCI_D0
);
10855 memset(data
, 0, sizeof(u64
) * TG3_NUM_TEST
);
10857 if (tg3_test_nvram(tp
) != 0) {
10858 etest
->flags
|= ETH_TEST_FL_FAILED
;
10861 if (tg3_test_link(tp
) != 0) {
10862 etest
->flags
|= ETH_TEST_FL_FAILED
;
10865 if (etest
->flags
& ETH_TEST_FL_OFFLINE
) {
10866 int err
, err2
= 0, irq_sync
= 0;
10868 if (netif_running(dev
)) {
10870 tg3_netif_stop(tp
);
10874 tg3_full_lock(tp
, irq_sync
);
10876 tg3_halt(tp
, RESET_KIND_SUSPEND
, 1);
10877 err
= tg3_nvram_lock(tp
);
10878 tg3_halt_cpu(tp
, RX_CPU_BASE
);
10879 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
10880 tg3_halt_cpu(tp
, TX_CPU_BASE
);
10882 tg3_nvram_unlock(tp
);
10884 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)
10887 if (tg3_test_registers(tp
) != 0) {
10888 etest
->flags
|= ETH_TEST_FL_FAILED
;
10891 if (tg3_test_memory(tp
) != 0) {
10892 etest
->flags
|= ETH_TEST_FL_FAILED
;
10895 if ((data
[4] = tg3_test_loopback(tp
)) != 0)
10896 etest
->flags
|= ETH_TEST_FL_FAILED
;
10898 tg3_full_unlock(tp
);
10900 if (tg3_test_interrupt(tp
) != 0) {
10901 etest
->flags
|= ETH_TEST_FL_FAILED
;
10905 tg3_full_lock(tp
, 0);
10907 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
10908 if (netif_running(dev
)) {
10909 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
10910 err2
= tg3_restart_hw(tp
, 1);
10912 tg3_netif_start(tp
);
10915 tg3_full_unlock(tp
);
10917 if (irq_sync
&& !err2
)
10920 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
10921 tg3_set_power_state(tp
, PCI_D3hot
);
10925 static int tg3_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
10927 struct mii_ioctl_data
*data
= if_mii(ifr
);
10928 struct tg3
*tp
= netdev_priv(dev
);
10931 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
10932 struct phy_device
*phydev
;
10933 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
10935 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
10936 return phy_mii_ioctl(phydev
, ifr
, cmd
);
10941 data
->phy_id
= tp
->phy_addr
;
10944 case SIOCGMIIREG
: {
10947 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
10948 break; /* We have no PHY */
10950 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
10953 spin_lock_bh(&tp
->lock
);
10954 err
= tg3_readphy(tp
, data
->reg_num
& 0x1f, &mii_regval
);
10955 spin_unlock_bh(&tp
->lock
);
10957 data
->val_out
= mii_regval
;
10963 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
10964 break; /* We have no PHY */
10966 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
10969 spin_lock_bh(&tp
->lock
);
10970 err
= tg3_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
10971 spin_unlock_bh(&tp
->lock
);
10979 return -EOPNOTSUPP
;
10982 #if TG3_VLAN_TAG_USED
10983 static void tg3_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
10985 struct tg3
*tp
= netdev_priv(dev
);
10987 if (!netif_running(dev
)) {
10992 tg3_netif_stop(tp
);
10994 tg3_full_lock(tp
, 0);
10998 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10999 __tg3_set_rx_mode(dev
);
11001 tg3_netif_start(tp
);
11003 tg3_full_unlock(tp
);
11007 static int tg3_get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
11009 struct tg3
*tp
= netdev_priv(dev
);
11011 memcpy(ec
, &tp
->coal
, sizeof(*ec
));
11015 static int tg3_set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
11017 struct tg3
*tp
= netdev_priv(dev
);
11018 u32 max_rxcoal_tick_int
= 0, max_txcoal_tick_int
= 0;
11019 u32 max_stat_coal_ticks
= 0, min_stat_coal_ticks
= 0;
11021 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
11022 max_rxcoal_tick_int
= MAX_RXCOAL_TICK_INT
;
11023 max_txcoal_tick_int
= MAX_TXCOAL_TICK_INT
;
11024 max_stat_coal_ticks
= MAX_STAT_COAL_TICKS
;
11025 min_stat_coal_ticks
= MIN_STAT_COAL_TICKS
;
11028 if ((ec
->rx_coalesce_usecs
> MAX_RXCOL_TICKS
) ||
11029 (ec
->tx_coalesce_usecs
> MAX_TXCOL_TICKS
) ||
11030 (ec
->rx_max_coalesced_frames
> MAX_RXMAX_FRAMES
) ||
11031 (ec
->tx_max_coalesced_frames
> MAX_TXMAX_FRAMES
) ||
11032 (ec
->rx_coalesce_usecs_irq
> max_rxcoal_tick_int
) ||
11033 (ec
->tx_coalesce_usecs_irq
> max_txcoal_tick_int
) ||
11034 (ec
->rx_max_coalesced_frames_irq
> MAX_RXCOAL_MAXF_INT
) ||
11035 (ec
->tx_max_coalesced_frames_irq
> MAX_TXCOAL_MAXF_INT
) ||
11036 (ec
->stats_block_coalesce_usecs
> max_stat_coal_ticks
) ||
11037 (ec
->stats_block_coalesce_usecs
< min_stat_coal_ticks
))
11040 /* No rx interrupts will be generated if both are zero */
11041 if ((ec
->rx_coalesce_usecs
== 0) &&
11042 (ec
->rx_max_coalesced_frames
== 0))
11045 /* No tx interrupts will be generated if both are zero */
11046 if ((ec
->tx_coalesce_usecs
== 0) &&
11047 (ec
->tx_max_coalesced_frames
== 0))
11050 /* Only copy relevant parameters, ignore all others. */
11051 tp
->coal
.rx_coalesce_usecs
= ec
->rx_coalesce_usecs
;
11052 tp
->coal
.tx_coalesce_usecs
= ec
->tx_coalesce_usecs
;
11053 tp
->coal
.rx_max_coalesced_frames
= ec
->rx_max_coalesced_frames
;
11054 tp
->coal
.tx_max_coalesced_frames
= ec
->tx_max_coalesced_frames
;
11055 tp
->coal
.rx_coalesce_usecs_irq
= ec
->rx_coalesce_usecs_irq
;
11056 tp
->coal
.tx_coalesce_usecs_irq
= ec
->tx_coalesce_usecs_irq
;
11057 tp
->coal
.rx_max_coalesced_frames_irq
= ec
->rx_max_coalesced_frames_irq
;
11058 tp
->coal
.tx_max_coalesced_frames_irq
= ec
->tx_max_coalesced_frames_irq
;
11059 tp
->coal
.stats_block_coalesce_usecs
= ec
->stats_block_coalesce_usecs
;
11061 if (netif_running(dev
)) {
11062 tg3_full_lock(tp
, 0);
11063 __tg3_set_coalesce(tp
, &tp
->coal
);
11064 tg3_full_unlock(tp
);
11069 static const struct ethtool_ops tg3_ethtool_ops
= {
11070 .get_settings
= tg3_get_settings
,
11071 .set_settings
= tg3_set_settings
,
11072 .get_drvinfo
= tg3_get_drvinfo
,
11073 .get_regs_len
= tg3_get_regs_len
,
11074 .get_regs
= tg3_get_regs
,
11075 .get_wol
= tg3_get_wol
,
11076 .set_wol
= tg3_set_wol
,
11077 .get_msglevel
= tg3_get_msglevel
,
11078 .set_msglevel
= tg3_set_msglevel
,
11079 .nway_reset
= tg3_nway_reset
,
11080 .get_link
= ethtool_op_get_link
,
11081 .get_eeprom_len
= tg3_get_eeprom_len
,
11082 .get_eeprom
= tg3_get_eeprom
,
11083 .set_eeprom
= tg3_set_eeprom
,
11084 .get_ringparam
= tg3_get_ringparam
,
11085 .set_ringparam
= tg3_set_ringparam
,
11086 .get_pauseparam
= tg3_get_pauseparam
,
11087 .set_pauseparam
= tg3_set_pauseparam
,
11088 .get_rx_csum
= tg3_get_rx_csum
,
11089 .set_rx_csum
= tg3_set_rx_csum
,
11090 .set_tx_csum
= tg3_set_tx_csum
,
11091 .set_sg
= ethtool_op_set_sg
,
11092 .set_tso
= tg3_set_tso
,
11093 .self_test
= tg3_self_test
,
11094 .get_strings
= tg3_get_strings
,
11095 .phys_id
= tg3_phys_id
,
11096 .get_ethtool_stats
= tg3_get_ethtool_stats
,
11097 .get_coalesce
= tg3_get_coalesce
,
11098 .set_coalesce
= tg3_set_coalesce
,
11099 .get_sset_count
= tg3_get_sset_count
,
11102 static void __devinit
tg3_get_eeprom_size(struct tg3
*tp
)
11104 u32 cursize
, val
, magic
;
11106 tp
->nvram_size
= EEPROM_CHIP_SIZE
;
11108 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
11111 if ((magic
!= TG3_EEPROM_MAGIC
) &&
11112 ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) != TG3_EEPROM_MAGIC_FW
) &&
11113 ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) != TG3_EEPROM_MAGIC_HW
))
11117 * Size the chip by reading offsets at increasing powers of two.
11118 * When we encounter our validation signature, we know the addressing
11119 * has wrapped around, and thus have our chip size.
11123 while (cursize
< tp
->nvram_size
) {
11124 if (tg3_nvram_read(tp
, cursize
, &val
) != 0)
11133 tp
->nvram_size
= cursize
;
11136 static void __devinit
tg3_get_nvram_size(struct tg3
*tp
)
11140 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
11141 tg3_nvram_read(tp
, 0, &val
) != 0)
11144 /* Selfboot format */
11145 if (val
!= TG3_EEPROM_MAGIC
) {
11146 tg3_get_eeprom_size(tp
);
11150 if (tg3_nvram_read(tp
, 0xf0, &val
) == 0) {
11152 /* This is confusing. We want to operate on the
11153 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11154 * call will read from NVRAM and byteswap the data
11155 * according to the byteswapping settings for all
11156 * other register accesses. This ensures the data we
11157 * want will always reside in the lower 16-bits.
11158 * However, the data in NVRAM is in LE format, which
11159 * means the data from the NVRAM read will always be
11160 * opposite the endianness of the CPU. The 16-bit
11161 * byteswap then brings the data to CPU endianness.
11163 tp
->nvram_size
= swab16((u16
)(val
& 0x0000ffff)) * 1024;
11167 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11170 static void __devinit
tg3_get_nvram_info(struct tg3
*tp
)
11174 nvcfg1
= tr32(NVRAM_CFG1
);
11175 if (nvcfg1
& NVRAM_CFG1_FLASHIF_ENAB
) {
11176 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11178 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11179 tw32(NVRAM_CFG1
, nvcfg1
);
11182 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) ||
11183 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
11184 switch (nvcfg1
& NVRAM_CFG1_VENDOR_MASK
) {
11185 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED
:
11186 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11187 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
11188 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11190 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED
:
11191 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11192 tp
->nvram_pagesize
= ATMEL_AT25F512_PAGE_SIZE
;
11194 case FLASH_VENDOR_ATMEL_EEPROM
:
11195 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11196 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11197 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11199 case FLASH_VENDOR_ST
:
11200 tp
->nvram_jedecnum
= JEDEC_ST
;
11201 tp
->nvram_pagesize
= ST_M45PEX0_PAGE_SIZE
;
11202 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11204 case FLASH_VENDOR_SAIFUN
:
11205 tp
->nvram_jedecnum
= JEDEC_SAIFUN
;
11206 tp
->nvram_pagesize
= SAIFUN_SA25F0XX_PAGE_SIZE
;
11208 case FLASH_VENDOR_SST_SMALL
:
11209 case FLASH_VENDOR_SST_LARGE
:
11210 tp
->nvram_jedecnum
= JEDEC_SST
;
11211 tp
->nvram_pagesize
= SST_25VF0X0_PAGE_SIZE
;
11215 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11216 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
11217 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11221 static void __devinit
tg3_nvram_get_pagesize(struct tg3
*tp
, u32 nvmcfg1
)
11223 switch (nvmcfg1
& NVRAM_CFG1_5752PAGE_SIZE_MASK
) {
11224 case FLASH_5752PAGE_SIZE_256
:
11225 tp
->nvram_pagesize
= 256;
11227 case FLASH_5752PAGE_SIZE_512
:
11228 tp
->nvram_pagesize
= 512;
11230 case FLASH_5752PAGE_SIZE_1K
:
11231 tp
->nvram_pagesize
= 1024;
11233 case FLASH_5752PAGE_SIZE_2K
:
11234 tp
->nvram_pagesize
= 2048;
11236 case FLASH_5752PAGE_SIZE_4K
:
11237 tp
->nvram_pagesize
= 4096;
11239 case FLASH_5752PAGE_SIZE_264
:
11240 tp
->nvram_pagesize
= 264;
11242 case FLASH_5752PAGE_SIZE_528
:
11243 tp
->nvram_pagesize
= 528;
11248 static void __devinit
tg3_get_5752_nvram_info(struct tg3
*tp
)
11252 nvcfg1
= tr32(NVRAM_CFG1
);
11254 /* NVRAM protection for TPM */
11255 if (nvcfg1
& (1 << 27))
11256 tp
->tg3_flags3
|= TG3_FLG3_PROTECTED_NVRAM
;
11258 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11259 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ
:
11260 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ
:
11261 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11262 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11264 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11265 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11266 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11267 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11269 case FLASH_5752VENDOR_ST_M45PE10
:
11270 case FLASH_5752VENDOR_ST_M45PE20
:
11271 case FLASH_5752VENDOR_ST_M45PE40
:
11272 tp
->nvram_jedecnum
= JEDEC_ST
;
11273 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11274 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11278 if (tp
->tg3_flags2
& TG3_FLG2_FLASH
) {
11279 tg3_nvram_get_pagesize(tp
, nvcfg1
);
11281 /* For eeprom, set pagesize to maximum eeprom size */
11282 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11284 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11285 tw32(NVRAM_CFG1
, nvcfg1
);
11289 static void __devinit
tg3_get_5755_nvram_info(struct tg3
*tp
)
11291 u32 nvcfg1
, protect
= 0;
11293 nvcfg1
= tr32(NVRAM_CFG1
);
11295 /* NVRAM protection for TPM */
11296 if (nvcfg1
& (1 << 27)) {
11297 tp
->tg3_flags3
|= TG3_FLG3_PROTECTED_NVRAM
;
11301 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
11303 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
11304 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
11305 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
11306 case FLASH_5755VENDOR_ATMEL_FLASH_5
:
11307 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11308 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11309 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11310 tp
->nvram_pagesize
= 264;
11311 if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_1
||
11312 nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_5
)
11313 tp
->nvram_size
= (protect
? 0x3e200 :
11314 TG3_NVRAM_SIZE_512KB
);
11315 else if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_2
)
11316 tp
->nvram_size
= (protect
? 0x1f200 :
11317 TG3_NVRAM_SIZE_256KB
);
11319 tp
->nvram_size
= (protect
? 0x1f200 :
11320 TG3_NVRAM_SIZE_128KB
);
11322 case FLASH_5752VENDOR_ST_M45PE10
:
11323 case FLASH_5752VENDOR_ST_M45PE20
:
11324 case FLASH_5752VENDOR_ST_M45PE40
:
11325 tp
->nvram_jedecnum
= JEDEC_ST
;
11326 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11327 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11328 tp
->nvram_pagesize
= 256;
11329 if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE10
)
11330 tp
->nvram_size
= (protect
?
11331 TG3_NVRAM_SIZE_64KB
:
11332 TG3_NVRAM_SIZE_128KB
);
11333 else if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE20
)
11334 tp
->nvram_size
= (protect
?
11335 TG3_NVRAM_SIZE_64KB
:
11336 TG3_NVRAM_SIZE_256KB
);
11338 tp
->nvram_size
= (protect
?
11339 TG3_NVRAM_SIZE_128KB
:
11340 TG3_NVRAM_SIZE_512KB
);
11345 static void __devinit
tg3_get_5787_nvram_info(struct tg3
*tp
)
11349 nvcfg1
= tr32(NVRAM_CFG1
);
11351 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11352 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ
:
11353 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
11354 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ
:
11355 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
11356 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11357 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11358 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11360 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11361 tw32(NVRAM_CFG1
, nvcfg1
);
11363 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11364 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
11365 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
11366 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
11367 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11368 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11369 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11370 tp
->nvram_pagesize
= 264;
11372 case FLASH_5752VENDOR_ST_M45PE10
:
11373 case FLASH_5752VENDOR_ST_M45PE20
:
11374 case FLASH_5752VENDOR_ST_M45PE40
:
11375 tp
->nvram_jedecnum
= JEDEC_ST
;
11376 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11377 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11378 tp
->nvram_pagesize
= 256;
11383 static void __devinit
tg3_get_5761_nvram_info(struct tg3
*tp
)
11385 u32 nvcfg1
, protect
= 0;
11387 nvcfg1
= tr32(NVRAM_CFG1
);
11389 /* NVRAM protection for TPM */
11390 if (nvcfg1
& (1 << 27)) {
11391 tp
->tg3_flags3
|= TG3_FLG3_PROTECTED_NVRAM
;
11395 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
11397 case FLASH_5761VENDOR_ATMEL_ADB021D
:
11398 case FLASH_5761VENDOR_ATMEL_ADB041D
:
11399 case FLASH_5761VENDOR_ATMEL_ADB081D
:
11400 case FLASH_5761VENDOR_ATMEL_ADB161D
:
11401 case FLASH_5761VENDOR_ATMEL_MDB021D
:
11402 case FLASH_5761VENDOR_ATMEL_MDB041D
:
11403 case FLASH_5761VENDOR_ATMEL_MDB081D
:
11404 case FLASH_5761VENDOR_ATMEL_MDB161D
:
11405 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11406 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11407 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11408 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
11409 tp
->nvram_pagesize
= 256;
11411 case FLASH_5761VENDOR_ST_A_M45PE20
:
11412 case FLASH_5761VENDOR_ST_A_M45PE40
:
11413 case FLASH_5761VENDOR_ST_A_M45PE80
:
11414 case FLASH_5761VENDOR_ST_A_M45PE16
:
11415 case FLASH_5761VENDOR_ST_M_M45PE20
:
11416 case FLASH_5761VENDOR_ST_M_M45PE40
:
11417 case FLASH_5761VENDOR_ST_M_M45PE80
:
11418 case FLASH_5761VENDOR_ST_M_M45PE16
:
11419 tp
->nvram_jedecnum
= JEDEC_ST
;
11420 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11421 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11422 tp
->nvram_pagesize
= 256;
11427 tp
->nvram_size
= tr32(NVRAM_ADDR_LOCKOUT
);
11430 case FLASH_5761VENDOR_ATMEL_ADB161D
:
11431 case FLASH_5761VENDOR_ATMEL_MDB161D
:
11432 case FLASH_5761VENDOR_ST_A_M45PE16
:
11433 case FLASH_5761VENDOR_ST_M_M45PE16
:
11434 tp
->nvram_size
= TG3_NVRAM_SIZE_2MB
;
11436 case FLASH_5761VENDOR_ATMEL_ADB081D
:
11437 case FLASH_5761VENDOR_ATMEL_MDB081D
:
11438 case FLASH_5761VENDOR_ST_A_M45PE80
:
11439 case FLASH_5761VENDOR_ST_M_M45PE80
:
11440 tp
->nvram_size
= TG3_NVRAM_SIZE_1MB
;
11442 case FLASH_5761VENDOR_ATMEL_ADB041D
:
11443 case FLASH_5761VENDOR_ATMEL_MDB041D
:
11444 case FLASH_5761VENDOR_ST_A_M45PE40
:
11445 case FLASH_5761VENDOR_ST_M_M45PE40
:
11446 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11448 case FLASH_5761VENDOR_ATMEL_ADB021D
:
11449 case FLASH_5761VENDOR_ATMEL_MDB021D
:
11450 case FLASH_5761VENDOR_ST_A_M45PE20
:
11451 case FLASH_5761VENDOR_ST_M_M45PE20
:
11452 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11458 static void __devinit
tg3_get_5906_nvram_info(struct tg3
*tp
)
11460 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11461 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11462 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11465 static void __devinit
tg3_get_57780_nvram_info(struct tg3
*tp
)
11469 nvcfg1
= tr32(NVRAM_CFG1
);
11471 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11472 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
11473 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
11474 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11475 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11476 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11478 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11479 tw32(NVRAM_CFG1
, nvcfg1
);
11481 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11482 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
11483 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
11484 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
11485 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
11486 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
11487 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
11488 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11489 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11490 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11492 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11493 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11494 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
11495 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
11496 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11498 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
11499 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
11500 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11502 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
11503 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
11504 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11508 case FLASH_5752VENDOR_ST_M45PE10
:
11509 case FLASH_5752VENDOR_ST_M45PE20
:
11510 case FLASH_5752VENDOR_ST_M45PE40
:
11511 tp
->nvram_jedecnum
= JEDEC_ST
;
11512 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11513 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11515 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11516 case FLASH_5752VENDOR_ST_M45PE10
:
11517 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11519 case FLASH_5752VENDOR_ST_M45PE20
:
11520 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11522 case FLASH_5752VENDOR_ST_M45PE40
:
11523 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11528 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM
;
11532 tg3_nvram_get_pagesize(tp
, nvcfg1
);
11533 if (tp
->nvram_pagesize
!= 264 && tp
->nvram_pagesize
!= 528)
11534 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
11538 static void __devinit
tg3_get_5717_nvram_info(struct tg3
*tp
)
11542 nvcfg1
= tr32(NVRAM_CFG1
);
11544 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11545 case FLASH_5717VENDOR_ATMEL_EEPROM
:
11546 case FLASH_5717VENDOR_MICRO_EEPROM
:
11547 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11548 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11549 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11551 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11552 tw32(NVRAM_CFG1
, nvcfg1
);
11554 case FLASH_5717VENDOR_ATMEL_MDB011D
:
11555 case FLASH_5717VENDOR_ATMEL_ADB011B
:
11556 case FLASH_5717VENDOR_ATMEL_ADB011D
:
11557 case FLASH_5717VENDOR_ATMEL_MDB021D
:
11558 case FLASH_5717VENDOR_ATMEL_ADB021B
:
11559 case FLASH_5717VENDOR_ATMEL_ADB021D
:
11560 case FLASH_5717VENDOR_ATMEL_45USPT
:
11561 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11562 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11563 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11565 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11566 case FLASH_5717VENDOR_ATMEL_MDB021D
:
11567 case FLASH_5717VENDOR_ATMEL_ADB021B
:
11568 case FLASH_5717VENDOR_ATMEL_ADB021D
:
11569 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11572 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11576 case FLASH_5717VENDOR_ST_M_M25PE10
:
11577 case FLASH_5717VENDOR_ST_A_M25PE10
:
11578 case FLASH_5717VENDOR_ST_M_M45PE10
:
11579 case FLASH_5717VENDOR_ST_A_M45PE10
:
11580 case FLASH_5717VENDOR_ST_M_M25PE20
:
11581 case FLASH_5717VENDOR_ST_A_M25PE20
:
11582 case FLASH_5717VENDOR_ST_M_M45PE20
:
11583 case FLASH_5717VENDOR_ST_A_M45PE20
:
11584 case FLASH_5717VENDOR_ST_25USPT
:
11585 case FLASH_5717VENDOR_ST_45USPT
:
11586 tp
->nvram_jedecnum
= JEDEC_ST
;
11587 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11588 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11590 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11591 case FLASH_5717VENDOR_ST_M_M25PE20
:
11592 case FLASH_5717VENDOR_ST_A_M25PE20
:
11593 case FLASH_5717VENDOR_ST_M_M45PE20
:
11594 case FLASH_5717VENDOR_ST_A_M45PE20
:
11595 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11598 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11603 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM
;
11607 tg3_nvram_get_pagesize(tp
, nvcfg1
);
11608 if (tp
->nvram_pagesize
!= 264 && tp
->nvram_pagesize
!= 528)
11609 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
11612 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11613 static void __devinit
tg3_nvram_init(struct tg3
*tp
)
11615 tw32_f(GRC_EEPROM_ADDR
,
11616 (EEPROM_ADDR_FSM_RESET
|
11617 (EEPROM_DEFAULT_CLOCK_PERIOD
<<
11618 EEPROM_ADDR_CLKPERD_SHIFT
)));
11622 /* Enable seeprom accesses. */
11623 tw32_f(GRC_LOCAL_CTRL
,
11624 tr32(GRC_LOCAL_CTRL
) | GRC_LCLCTRL_AUTO_SEEPROM
);
11627 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
11628 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
11629 tp
->tg3_flags
|= TG3_FLAG_NVRAM
;
11631 if (tg3_nvram_lock(tp
)) {
11632 netdev_warn(tp
->dev
,
11633 "Cannot get nvram lock, %s failed\n",
11637 tg3_enable_nvram_access(tp
);
11639 tp
->nvram_size
= 0;
11641 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
11642 tg3_get_5752_nvram_info(tp
);
11643 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
11644 tg3_get_5755_nvram_info(tp
);
11645 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
11646 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
11647 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
11648 tg3_get_5787_nvram_info(tp
);
11649 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
11650 tg3_get_5761_nvram_info(tp
);
11651 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
11652 tg3_get_5906_nvram_info(tp
);
11653 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
11654 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
11655 tg3_get_57780_nvram_info(tp
);
11656 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
11657 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
)
11658 tg3_get_5717_nvram_info(tp
);
11660 tg3_get_nvram_info(tp
);
11662 if (tp
->nvram_size
== 0)
11663 tg3_get_nvram_size(tp
);
11665 tg3_disable_nvram_access(tp
);
11666 tg3_nvram_unlock(tp
);
11669 tp
->tg3_flags
&= ~(TG3_FLAG_NVRAM
| TG3_FLAG_NVRAM_BUFFERED
);
11671 tg3_get_eeprom_size(tp
);
11675 static int tg3_nvram_write_block_using_eeprom(struct tg3
*tp
,
11676 u32 offset
, u32 len
, u8
*buf
)
11681 for (i
= 0; i
< len
; i
+= 4) {
11687 memcpy(&data
, buf
+ i
, 4);
11690 * The SEEPROM interface expects the data to always be opposite
11691 * the native endian format. We accomplish this by reversing
11692 * all the operations that would have been performed on the
11693 * data from a call to tg3_nvram_read_be32().
11695 tw32(GRC_EEPROM_DATA
, swab32(be32_to_cpu(data
)));
11697 val
= tr32(GRC_EEPROM_ADDR
);
11698 tw32(GRC_EEPROM_ADDR
, val
| EEPROM_ADDR_COMPLETE
);
11700 val
&= ~(EEPROM_ADDR_ADDR_MASK
| EEPROM_ADDR_DEVID_MASK
|
11702 tw32(GRC_EEPROM_ADDR
, val
|
11703 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
11704 (addr
& EEPROM_ADDR_ADDR_MASK
) |
11705 EEPROM_ADDR_START
|
11706 EEPROM_ADDR_WRITE
);
11708 for (j
= 0; j
< 1000; j
++) {
11709 val
= tr32(GRC_EEPROM_ADDR
);
11711 if (val
& EEPROM_ADDR_COMPLETE
)
11715 if (!(val
& EEPROM_ADDR_COMPLETE
)) {
11724 /* offset and length are dword aligned */
11725 static int tg3_nvram_write_block_unbuffered(struct tg3
*tp
, u32 offset
, u32 len
,
11729 u32 pagesize
= tp
->nvram_pagesize
;
11730 u32 pagemask
= pagesize
- 1;
11734 tmp
= kmalloc(pagesize
, GFP_KERNEL
);
11740 u32 phy_addr
, page_off
, size
;
11742 phy_addr
= offset
& ~pagemask
;
11744 for (j
= 0; j
< pagesize
; j
+= 4) {
11745 ret
= tg3_nvram_read_be32(tp
, phy_addr
+ j
,
11746 (__be32
*) (tmp
+ j
));
11753 page_off
= offset
& pagemask
;
11760 memcpy(tmp
+ page_off
, buf
, size
);
11762 offset
= offset
+ (pagesize
- page_off
);
11764 tg3_enable_nvram_access(tp
);
11767 * Before we can erase the flash page, we need
11768 * to issue a special "write enable" command.
11770 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
11772 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
11775 /* Erase the target page */
11776 tw32(NVRAM_ADDR
, phy_addr
);
11778 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
|
11779 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_ERASE
;
11781 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
11784 /* Issue another write enable to start the write. */
11785 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
11787 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
11790 for (j
= 0; j
< pagesize
; j
+= 4) {
11793 data
= *((__be32
*) (tmp
+ j
));
11795 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
11797 tw32(NVRAM_ADDR
, phy_addr
+ j
);
11799 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
|
11803 nvram_cmd
|= NVRAM_CMD_FIRST
;
11804 else if (j
== (pagesize
- 4))
11805 nvram_cmd
|= NVRAM_CMD_LAST
;
11807 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
11814 nvram_cmd
= NVRAM_CMD_WRDI
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
11815 tg3_nvram_exec_cmd(tp
, nvram_cmd
);
11822 /* offset and length are dword aligned */
11823 static int tg3_nvram_write_block_buffered(struct tg3
*tp
, u32 offset
, u32 len
,
11828 for (i
= 0; i
< len
; i
+= 4, offset
+= 4) {
11829 u32 page_off
, phy_addr
, nvram_cmd
;
11832 memcpy(&data
, buf
+ i
, 4);
11833 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
11835 page_off
= offset
% tp
->nvram_pagesize
;
11837 phy_addr
= tg3_nvram_phys_addr(tp
, offset
);
11839 tw32(NVRAM_ADDR
, phy_addr
);
11841 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
;
11843 if (page_off
== 0 || i
== 0)
11844 nvram_cmd
|= NVRAM_CMD_FIRST
;
11845 if (page_off
== (tp
->nvram_pagesize
- 4))
11846 nvram_cmd
|= NVRAM_CMD_LAST
;
11848 if (i
== (len
- 4))
11849 nvram_cmd
|= NVRAM_CMD_LAST
;
11851 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5752
&&
11852 !(tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) &&
11853 (tp
->nvram_jedecnum
== JEDEC_ST
) &&
11854 (nvram_cmd
& NVRAM_CMD_FIRST
)) {
11856 if ((ret
= tg3_nvram_exec_cmd(tp
,
11857 NVRAM_CMD_WREN
| NVRAM_CMD_GO
|
11862 if (!(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
11863 /* We always do complete word writes to eeprom. */
11864 nvram_cmd
|= (NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
);
11867 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
11873 /* offset and length are dword aligned */
11874 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
)
11878 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
11879 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
&
11880 ~GRC_LCLCTRL_GPIO_OUTPUT1
);
11884 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
)) {
11885 ret
= tg3_nvram_write_block_using_eeprom(tp
, offset
, len
, buf
);
11889 ret
= tg3_nvram_lock(tp
);
11893 tg3_enable_nvram_access(tp
);
11894 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
11895 !(tp
->tg3_flags3
& TG3_FLG3_PROTECTED_NVRAM
))
11896 tw32(NVRAM_WRITE1
, 0x406);
11898 grc_mode
= tr32(GRC_MODE
);
11899 tw32(GRC_MODE
, grc_mode
| GRC_MODE_NVRAM_WR_ENABLE
);
11901 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) ||
11902 !(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
11904 ret
= tg3_nvram_write_block_buffered(tp
, offset
, len
,
11907 ret
= tg3_nvram_write_block_unbuffered(tp
, offset
, len
,
11911 grc_mode
= tr32(GRC_MODE
);
11912 tw32(GRC_MODE
, grc_mode
& ~GRC_MODE_NVRAM_WR_ENABLE
);
11914 tg3_disable_nvram_access(tp
);
11915 tg3_nvram_unlock(tp
);
11918 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
11919 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
11926 struct subsys_tbl_ent
{
11927 u16 subsys_vendor
, subsys_devid
;
11931 static struct subsys_tbl_ent subsys_id_to_phy_id
[] __devinitdata
= {
11932 /* Broadcom boards. */
11933 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11934 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6
, TG3_PHY_ID_BCM5401
},
11935 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11936 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5
, TG3_PHY_ID_BCM5701
},
11937 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11938 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6
, TG3_PHY_ID_BCM8002
},
11939 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11940 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9
, 0 },
11941 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11942 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1
, TG3_PHY_ID_BCM5701
},
11943 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11944 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8
, TG3_PHY_ID_BCM5701
},
11945 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11946 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7
, 0 },
11947 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11948 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10
, TG3_PHY_ID_BCM5701
},
11949 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11950 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12
, TG3_PHY_ID_BCM5701
},
11951 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11952 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1
, TG3_PHY_ID_BCM5703
},
11953 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11954 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2
, TG3_PHY_ID_BCM5703
},
11957 { TG3PCI_SUBVENDOR_ID_3COM
,
11958 TG3PCI_SUBDEVICE_ID_3COM_3C996T
, TG3_PHY_ID_BCM5401
},
11959 { TG3PCI_SUBVENDOR_ID_3COM
,
11960 TG3PCI_SUBDEVICE_ID_3COM_3C996BT
, TG3_PHY_ID_BCM5701
},
11961 { TG3PCI_SUBVENDOR_ID_3COM
,
11962 TG3PCI_SUBDEVICE_ID_3COM_3C996SX
, 0 },
11963 { TG3PCI_SUBVENDOR_ID_3COM
,
11964 TG3PCI_SUBDEVICE_ID_3COM_3C1000T
, TG3_PHY_ID_BCM5701
},
11965 { TG3PCI_SUBVENDOR_ID_3COM
,
11966 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01
, TG3_PHY_ID_BCM5701
},
11969 { TG3PCI_SUBVENDOR_ID_DELL
,
11970 TG3PCI_SUBDEVICE_ID_DELL_VIPER
, TG3_PHY_ID_BCM5401
},
11971 { TG3PCI_SUBVENDOR_ID_DELL
,
11972 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR
, TG3_PHY_ID_BCM5401
},
11973 { TG3PCI_SUBVENDOR_ID_DELL
,
11974 TG3PCI_SUBDEVICE_ID_DELL_MERLOT
, TG3_PHY_ID_BCM5411
},
11975 { TG3PCI_SUBVENDOR_ID_DELL
,
11976 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT
, TG3_PHY_ID_BCM5411
},
11978 /* Compaq boards. */
11979 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
11980 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE
, TG3_PHY_ID_BCM5701
},
11981 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
11982 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2
, TG3_PHY_ID_BCM5701
},
11983 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
11984 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING
, 0 },
11985 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
11986 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780
, TG3_PHY_ID_BCM5701
},
11987 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
11988 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2
, TG3_PHY_ID_BCM5701
},
11991 { TG3PCI_SUBVENDOR_ID_IBM
,
11992 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2
, 0 }
11995 static struct subsys_tbl_ent
* __devinit
tg3_lookup_by_subsys(struct tg3
*tp
)
11999 for (i
= 0; i
< ARRAY_SIZE(subsys_id_to_phy_id
); i
++) {
12000 if ((subsys_id_to_phy_id
[i
].subsys_vendor
==
12001 tp
->pdev
->subsystem_vendor
) &&
12002 (subsys_id_to_phy_id
[i
].subsys_devid
==
12003 tp
->pdev
->subsystem_device
))
12004 return &subsys_id_to_phy_id
[i
];
12009 static void __devinit
tg3_get_eeprom_hw_cfg(struct tg3
*tp
)
12014 /* On some early chips the SRAM cannot be accessed in D3hot state,
12015 * so need make sure we're in D0.
12017 pci_read_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
12018 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
12019 pci_write_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
12022 /* Make sure register accesses (indirect or otherwise)
12023 * will function correctly.
12025 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12026 tp
->misc_host_ctrl
);
12028 /* The memory arbiter has to be enabled in order for SRAM accesses
12029 * to succeed. Normally on powerup the tg3 chip firmware will make
12030 * sure it is enabled, but other entities such as system netboot
12031 * code might disable it.
12033 val
= tr32(MEMARB_MODE
);
12034 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
12036 tp
->phy_id
= TG3_PHY_ID_INVALID
;
12037 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12039 /* Assume an onboard device and WOL capable by default. */
12040 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
| TG3_FLAG_WOL_CAP
;
12042 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
12043 if (!(tr32(PCIE_TRANSACTION_CFG
) & PCIE_TRANS_CFG_LOM
)) {
12044 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
12045 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
12047 val
= tr32(VCPU_CFGSHDW
);
12048 if (val
& VCPU_CFGSHDW_ASPM_DBNC
)
12049 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
12050 if ((val
& VCPU_CFGSHDW_WOL_ENABLE
) &&
12051 (val
& VCPU_CFGSHDW_WOL_MAGPKT
))
12052 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
12056 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
12057 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
12058 u32 nic_cfg
, led_cfg
;
12059 u32 nic_phy_id
, ver
, cfg2
= 0, cfg4
= 0, eeprom_phy_id
;
12060 int eeprom_phy_serdes
= 0;
12062 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
12063 tp
->nic_sram_data_cfg
= nic_cfg
;
12065 tg3_read_mem(tp
, NIC_SRAM_DATA_VER
, &ver
);
12066 ver
>>= NIC_SRAM_DATA_VER_SHIFT
;
12067 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
) &&
12068 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) &&
12069 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5703
) &&
12070 (ver
> 0) && (ver
< 0x100))
12071 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_2
, &cfg2
);
12073 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
12074 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_4
, &cfg4
);
12076 if ((nic_cfg
& NIC_SRAM_DATA_CFG_PHY_TYPE_MASK
) ==
12077 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER
)
12078 eeprom_phy_serdes
= 1;
12080 tg3_read_mem(tp
, NIC_SRAM_DATA_PHY_ID
, &nic_phy_id
);
12081 if (nic_phy_id
!= 0) {
12082 u32 id1
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID1_MASK
;
12083 u32 id2
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID2_MASK
;
12085 eeprom_phy_id
= (id1
>> 16) << 10;
12086 eeprom_phy_id
|= (id2
& 0xfc00) << 16;
12087 eeprom_phy_id
|= (id2
& 0x03ff) << 0;
12091 tp
->phy_id
= eeprom_phy_id
;
12092 if (eeprom_phy_serdes
) {
12093 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
12094 tp
->phy_flags
|= TG3_PHYFLG_PHY_SERDES
;
12096 tp
->phy_flags
|= TG3_PHYFLG_MII_SERDES
;
12099 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
12100 led_cfg
= cfg2
& (NIC_SRAM_DATA_CFG_LED_MODE_MASK
|
12101 SHASTA_EXT_LED_MODE_MASK
);
12103 led_cfg
= nic_cfg
& NIC_SRAM_DATA_CFG_LED_MODE_MASK
;
12107 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1
:
12108 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12111 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2
:
12112 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
12115 case NIC_SRAM_DATA_CFG_LED_MODE_MAC
:
12116 tp
->led_ctrl
= LED_CTRL_MODE_MAC
;
12118 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12119 * read on some older 5700/5701 bootcode.
12121 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
12123 GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
12125 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12129 case SHASTA_EXT_LED_SHARED
:
12130 tp
->led_ctrl
= LED_CTRL_MODE_SHARED
;
12131 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
&&
12132 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A1
)
12133 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
12134 LED_CTRL_MODE_PHY_2
);
12137 case SHASTA_EXT_LED_MAC
:
12138 tp
->led_ctrl
= LED_CTRL_MODE_SHASTA_MAC
;
12141 case SHASTA_EXT_LED_COMBO
:
12142 tp
->led_ctrl
= LED_CTRL_MODE_COMBO
;
12143 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
)
12144 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
12145 LED_CTRL_MODE_PHY_2
);
12150 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
12151 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) &&
12152 tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
)
12153 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
12155 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
)
12156 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12158 if (nic_cfg
& NIC_SRAM_DATA_CFG_EEPROM_WP
) {
12159 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
;
12160 if ((tp
->pdev
->subsystem_vendor
==
12161 PCI_VENDOR_ID_ARIMA
) &&
12162 (tp
->pdev
->subsystem_device
== 0x205a ||
12163 tp
->pdev
->subsystem_device
== 0x2063))
12164 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
12166 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
12167 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
12170 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
12171 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
12172 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
12173 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
12176 if ((nic_cfg
& NIC_SRAM_DATA_CFG_APE_ENABLE
) &&
12177 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
12178 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_APE
;
12180 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
&&
12181 !(nic_cfg
& NIC_SRAM_DATA_CFG_FIBER_WOL
))
12182 tp
->tg3_flags
&= ~TG3_FLAG_WOL_CAP
;
12184 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
12185 (nic_cfg
& NIC_SRAM_DATA_CFG_WOL_ENABLE
))
12186 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
12188 if (cfg2
& (1 << 17))
12189 tp
->phy_flags
|= TG3_PHYFLG_CAPACITIVE_COUPLING
;
12191 /* serdes signal pre-emphasis in register 0x590 set by */
12192 /* bootcode if bit 18 is set */
12193 if (cfg2
& (1 << 18))
12194 tp
->phy_flags
|= TG3_PHYFLG_SERDES_PREEMPHASIS
;
12196 if (((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
12197 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
)) &&
12198 (cfg2
& NIC_SRAM_DATA_CFG_2_APD_EN
))
12199 tp
->phy_flags
|= TG3_PHYFLG_ENABLE_APD
;
12201 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
12202 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
12203 !(tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)) {
12206 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_3
, &cfg3
);
12207 if (cfg3
& NIC_SRAM_ASPM_DEBOUNCE
)
12208 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
12211 if (cfg4
& NIC_SRAM_RGMII_INBAND_DISABLE
)
12212 tp
->tg3_flags3
|= TG3_FLG3_RGMII_INBAND_DISABLE
;
12213 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_RX_EN
)
12214 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_RX_EN
;
12215 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_TX_EN
)
12216 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_TX_EN
;
12219 device_init_wakeup(&tp
->pdev
->dev
, tp
->tg3_flags
& TG3_FLAG_WOL_CAP
);
12220 device_set_wakeup_enable(&tp
->pdev
->dev
,
12221 tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
12224 static int __devinit
tg3_issue_otp_command(struct tg3
*tp
, u32 cmd
)
12229 tw32(OTP_CTRL
, cmd
| OTP_CTRL_OTP_CMD_START
);
12230 tw32(OTP_CTRL
, cmd
);
12232 /* Wait for up to 1 ms for command to execute. */
12233 for (i
= 0; i
< 100; i
++) {
12234 val
= tr32(OTP_STATUS
);
12235 if (val
& OTP_STATUS_CMD_DONE
)
12240 return (val
& OTP_STATUS_CMD_DONE
) ? 0 : -EBUSY
;
12243 /* Read the gphy configuration from the OTP region of the chip. The gphy
12244 * configuration is a 32-bit value that straddles the alignment boundary.
12245 * We do two 32-bit reads and then shift and merge the results.
12247 static u32 __devinit
tg3_read_otp_phycfg(struct tg3
*tp
)
12249 u32 bhalf_otp
, thalf_otp
;
12251 tw32(OTP_MODE
, OTP_MODE_OTP_THRU_GRC
);
12253 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_INIT
))
12256 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC1
);
12258 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
12261 thalf_otp
= tr32(OTP_READ_DATA
);
12263 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC2
);
12265 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
12268 bhalf_otp
= tr32(OTP_READ_DATA
);
12270 return ((thalf_otp
& 0x0000ffff) << 16) | (bhalf_otp
>> 16);
12273 static int __devinit
tg3_phy_probe(struct tg3
*tp
)
12275 u32 hw_phy_id_1
, hw_phy_id_2
;
12276 u32 hw_phy_id
, hw_phy_id_masked
;
12279 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
12280 return tg3_phy_init(tp
);
12282 /* Reading the PHY ID register can conflict with ASF
12283 * firmware access to the PHY hardware.
12286 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
12287 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
12288 hw_phy_id
= hw_phy_id_masked
= TG3_PHY_ID_INVALID
;
12290 /* Now read the physical PHY_ID from the chip and verify
12291 * that it is sane. If it doesn't look good, we fall back
12292 * to either the hard-coded table based PHY_ID and failing
12293 * that the value found in the eeprom area.
12295 err
|= tg3_readphy(tp
, MII_PHYSID1
, &hw_phy_id_1
);
12296 err
|= tg3_readphy(tp
, MII_PHYSID2
, &hw_phy_id_2
);
12298 hw_phy_id
= (hw_phy_id_1
& 0xffff) << 10;
12299 hw_phy_id
|= (hw_phy_id_2
& 0xfc00) << 16;
12300 hw_phy_id
|= (hw_phy_id_2
& 0x03ff) << 0;
12302 hw_phy_id_masked
= hw_phy_id
& TG3_PHY_ID_MASK
;
12305 if (!err
&& TG3_KNOWN_PHY_ID(hw_phy_id_masked
)) {
12306 tp
->phy_id
= hw_phy_id
;
12307 if (hw_phy_id_masked
== TG3_PHY_ID_BCM8002
)
12308 tp
->phy_flags
|= TG3_PHYFLG_PHY_SERDES
;
12310 tp
->phy_flags
&= ~TG3_PHYFLG_PHY_SERDES
;
12312 if (tp
->phy_id
!= TG3_PHY_ID_INVALID
) {
12313 /* Do nothing, phy ID already set up in
12314 * tg3_get_eeprom_hw_cfg().
12317 struct subsys_tbl_ent
*p
;
12319 /* No eeprom signature? Try the hardcoded
12320 * subsys device table.
12322 p
= tg3_lookup_by_subsys(tp
);
12326 tp
->phy_id
= p
->phy_id
;
12328 tp
->phy_id
== TG3_PHY_ID_BCM8002
)
12329 tp
->phy_flags
|= TG3_PHYFLG_PHY_SERDES
;
12333 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
) &&
12334 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) &&
12335 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
12336 u32 bmsr
, adv_reg
, tg3_ctrl
, mask
;
12338 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
12339 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
12340 (bmsr
& BMSR_LSTATUS
))
12341 goto skip_phy_reset
;
12343 err
= tg3_phy_reset(tp
);
12347 adv_reg
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
12348 ADVERTISE_100HALF
| ADVERTISE_100FULL
|
12349 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
12351 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
12352 tg3_ctrl
= (MII_TG3_CTRL_ADV_1000_HALF
|
12353 MII_TG3_CTRL_ADV_1000_FULL
);
12354 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
12355 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
12356 tg3_ctrl
|= (MII_TG3_CTRL_AS_MASTER
|
12357 MII_TG3_CTRL_ENABLE_AS_MASTER
);
12360 mask
= (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
12361 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
12362 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
);
12363 if (!tg3_copper_is_advertising_all(tp
, mask
)) {
12364 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
12366 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
12367 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
12369 tg3_writephy(tp
, MII_BMCR
,
12370 BMCR_ANENABLE
| BMCR_ANRESTART
);
12372 tg3_phy_set_wirespeed(tp
);
12374 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
12375 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
12376 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
12380 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
12381 err
= tg3_init_5401phy_dsp(tp
);
12385 err
= tg3_init_5401phy_dsp(tp
);
12388 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
12389 tp
->link_config
.advertising
=
12390 (ADVERTISED_1000baseT_Half
|
12391 ADVERTISED_1000baseT_Full
|
12392 ADVERTISED_Autoneg
|
12394 if (tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)
12395 tp
->link_config
.advertising
&=
12396 ~(ADVERTISED_1000baseT_Half
|
12397 ADVERTISED_1000baseT_Full
);
12402 static void __devinit
tg3_read_vpd(struct tg3
*tp
)
12404 u8 vpd_data
[TG3_NVM_VPD_LEN
];
12405 unsigned int block_end
, rosize
, len
;
12409 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
12410 tg3_nvram_read(tp
, 0x0, &magic
))
12411 goto out_not_found
;
12413 if (magic
== TG3_EEPROM_MAGIC
) {
12414 for (i
= 0; i
< TG3_NVM_VPD_LEN
; i
+= 4) {
12417 /* The data is in little-endian format in NVRAM.
12418 * Use the big-endian read routines to preserve
12419 * the byte order as it exists in NVRAM.
12421 if (tg3_nvram_read_be32(tp
, TG3_NVM_VPD_OFF
+ i
, &tmp
))
12422 goto out_not_found
;
12424 memcpy(&vpd_data
[i
], &tmp
, sizeof(tmp
));
12428 unsigned int pos
= 0;
12430 for (; pos
< TG3_NVM_VPD_LEN
&& i
< 3; i
++, pos
+= cnt
) {
12431 cnt
= pci_read_vpd(tp
->pdev
, pos
,
12432 TG3_NVM_VPD_LEN
- pos
,
12434 if (cnt
== -ETIMEDOUT
|| -EINTR
)
12437 goto out_not_found
;
12439 if (pos
!= TG3_NVM_VPD_LEN
)
12440 goto out_not_found
;
12443 i
= pci_vpd_find_tag(vpd_data
, 0, TG3_NVM_VPD_LEN
,
12444 PCI_VPD_LRDT_RO_DATA
);
12446 goto out_not_found
;
12448 rosize
= pci_vpd_lrdt_size(&vpd_data
[i
]);
12449 block_end
= i
+ PCI_VPD_LRDT_TAG_SIZE
+ rosize
;
12450 i
+= PCI_VPD_LRDT_TAG_SIZE
;
12452 if (block_end
> TG3_NVM_VPD_LEN
)
12453 goto out_not_found
;
12455 j
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
12456 PCI_VPD_RO_KEYWORD_MFR_ID
);
12458 len
= pci_vpd_info_field_size(&vpd_data
[j
]);
12460 j
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12461 if (j
+ len
> block_end
|| len
!= 4 ||
12462 memcmp(&vpd_data
[j
], "1028", 4))
12465 j
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
12466 PCI_VPD_RO_KEYWORD_VENDOR0
);
12470 len
= pci_vpd_info_field_size(&vpd_data
[j
]);
12472 j
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12473 if (j
+ len
> block_end
)
12476 memcpy(tp
->fw_ver
, &vpd_data
[j
], len
);
12477 strncat(tp
->fw_ver
, " bc ", TG3_NVM_VPD_LEN
- len
- 1);
12481 i
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
12482 PCI_VPD_RO_KEYWORD_PARTNO
);
12484 goto out_not_found
;
12486 len
= pci_vpd_info_field_size(&vpd_data
[i
]);
12488 i
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12489 if (len
> TG3_BPN_SIZE
||
12490 (len
+ i
) > TG3_NVM_VPD_LEN
)
12491 goto out_not_found
;
12493 memcpy(tp
->board_part_number
, &vpd_data
[i
], len
);
12498 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
12499 strcpy(tp
->board_part_number
, "BCM95906");
12500 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
12501 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57780
)
12502 strcpy(tp
->board_part_number
, "BCM57780");
12503 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
12504 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57760
)
12505 strcpy(tp
->board_part_number
, "BCM57760");
12506 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
12507 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
)
12508 strcpy(tp
->board_part_number
, "BCM57790");
12509 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
12510 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57788
)
12511 strcpy(tp
->board_part_number
, "BCM57788");
12512 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
&&
12513 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57761
)
12514 strcpy(tp
->board_part_number
, "BCM57761");
12515 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
&&
12516 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57765
)
12517 strcpy(tp
->board_part_number
, "BCM57765");
12518 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
&&
12519 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57781
)
12520 strcpy(tp
->board_part_number
, "BCM57781");
12521 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
&&
12522 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57785
)
12523 strcpy(tp
->board_part_number
, "BCM57785");
12524 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
&&
12525 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
)
12526 strcpy(tp
->board_part_number
, "BCM57791");
12527 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
&&
12528 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
)
12529 strcpy(tp
->board_part_number
, "BCM57795");
12531 strcpy(tp
->board_part_number
, "none");
12534 static int __devinit
tg3_fw_img_is_valid(struct tg3
*tp
, u32 offset
)
12538 if (tg3_nvram_read(tp
, offset
, &val
) ||
12539 (val
& 0xfc000000) != 0x0c000000 ||
12540 tg3_nvram_read(tp
, offset
+ 4, &val
) ||
12547 static void __devinit
tg3_read_bc_ver(struct tg3
*tp
)
12549 u32 val
, offset
, start
, ver_offset
;
12551 bool newver
= false;
12553 if (tg3_nvram_read(tp
, 0xc, &offset
) ||
12554 tg3_nvram_read(tp
, 0x4, &start
))
12557 offset
= tg3_nvram_logical_addr(tp
, offset
);
12559 if (tg3_nvram_read(tp
, offset
, &val
))
12562 if ((val
& 0xfc000000) == 0x0c000000) {
12563 if (tg3_nvram_read(tp
, offset
+ 4, &val
))
12570 dst_off
= strlen(tp
->fw_ver
);
12573 if (TG3_VER_SIZE
- dst_off
< 16 ||
12574 tg3_nvram_read(tp
, offset
+ 8, &ver_offset
))
12577 offset
= offset
+ ver_offset
- start
;
12578 for (i
= 0; i
< 16; i
+= 4) {
12580 if (tg3_nvram_read_be32(tp
, offset
+ i
, &v
))
12583 memcpy(tp
->fw_ver
+ dst_off
+ i
, &v
, sizeof(v
));
12588 if (tg3_nvram_read(tp
, TG3_NVM_PTREV_BCVER
, &ver_offset
))
12591 major
= (ver_offset
& TG3_NVM_BCVER_MAJMSK
) >>
12592 TG3_NVM_BCVER_MAJSFT
;
12593 minor
= ver_offset
& TG3_NVM_BCVER_MINMSK
;
12594 snprintf(&tp
->fw_ver
[dst_off
], TG3_VER_SIZE
- dst_off
,
12595 "v%d.%02d", major
, minor
);
12599 static void __devinit
tg3_read_hwsb_ver(struct tg3
*tp
)
12601 u32 val
, major
, minor
;
12603 /* Use native endian representation */
12604 if (tg3_nvram_read(tp
, TG3_NVM_HWSB_CFG1
, &val
))
12607 major
= (val
& TG3_NVM_HWSB_CFG1_MAJMSK
) >>
12608 TG3_NVM_HWSB_CFG1_MAJSFT
;
12609 minor
= (val
& TG3_NVM_HWSB_CFG1_MINMSK
) >>
12610 TG3_NVM_HWSB_CFG1_MINSFT
;
12612 snprintf(&tp
->fw_ver
[0], 32, "sb v%d.%02d", major
, minor
);
12615 static void __devinit
tg3_read_sb_ver(struct tg3
*tp
, u32 val
)
12617 u32 offset
, major
, minor
, build
;
12619 strncat(tp
->fw_ver
, "sb", TG3_VER_SIZE
- strlen(tp
->fw_ver
) - 1);
12621 if ((val
& TG3_EEPROM_SB_FORMAT_MASK
) != TG3_EEPROM_SB_FORMAT_1
)
12624 switch (val
& TG3_EEPROM_SB_REVISION_MASK
) {
12625 case TG3_EEPROM_SB_REVISION_0
:
12626 offset
= TG3_EEPROM_SB_F1R0_EDH_OFF
;
12628 case TG3_EEPROM_SB_REVISION_2
:
12629 offset
= TG3_EEPROM_SB_F1R2_EDH_OFF
;
12631 case TG3_EEPROM_SB_REVISION_3
:
12632 offset
= TG3_EEPROM_SB_F1R3_EDH_OFF
;
12634 case TG3_EEPROM_SB_REVISION_4
:
12635 offset
= TG3_EEPROM_SB_F1R4_EDH_OFF
;
12637 case TG3_EEPROM_SB_REVISION_5
:
12638 offset
= TG3_EEPROM_SB_F1R5_EDH_OFF
;
12644 if (tg3_nvram_read(tp
, offset
, &val
))
12647 build
= (val
& TG3_EEPROM_SB_EDH_BLD_MASK
) >>
12648 TG3_EEPROM_SB_EDH_BLD_SHFT
;
12649 major
= (val
& TG3_EEPROM_SB_EDH_MAJ_MASK
) >>
12650 TG3_EEPROM_SB_EDH_MAJ_SHFT
;
12651 minor
= val
& TG3_EEPROM_SB_EDH_MIN_MASK
;
12653 if (minor
> 99 || build
> 26)
12656 offset
= strlen(tp
->fw_ver
);
12657 snprintf(&tp
->fw_ver
[offset
], TG3_VER_SIZE
- offset
,
12658 " v%d.%02d", major
, minor
);
12661 offset
= strlen(tp
->fw_ver
);
12662 if (offset
< TG3_VER_SIZE
- 1)
12663 tp
->fw_ver
[offset
] = 'a' + build
- 1;
12667 static void __devinit
tg3_read_mgmtfw_ver(struct tg3
*tp
)
12669 u32 val
, offset
, start
;
12672 for (offset
= TG3_NVM_DIR_START
;
12673 offset
< TG3_NVM_DIR_END
;
12674 offset
+= TG3_NVM_DIRENT_SIZE
) {
12675 if (tg3_nvram_read(tp
, offset
, &val
))
12678 if ((val
>> TG3_NVM_DIRTYPE_SHIFT
) == TG3_NVM_DIRTYPE_ASFINI
)
12682 if (offset
== TG3_NVM_DIR_END
)
12685 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
12686 start
= 0x08000000;
12687 else if (tg3_nvram_read(tp
, offset
- 4, &start
))
12690 if (tg3_nvram_read(tp
, offset
+ 4, &offset
) ||
12691 !tg3_fw_img_is_valid(tp
, offset
) ||
12692 tg3_nvram_read(tp
, offset
+ 8, &val
))
12695 offset
+= val
- start
;
12697 vlen
= strlen(tp
->fw_ver
);
12699 tp
->fw_ver
[vlen
++] = ',';
12700 tp
->fw_ver
[vlen
++] = ' ';
12702 for (i
= 0; i
< 4; i
++) {
12704 if (tg3_nvram_read_be32(tp
, offset
, &v
))
12707 offset
+= sizeof(v
);
12709 if (vlen
> TG3_VER_SIZE
- sizeof(v
)) {
12710 memcpy(&tp
->fw_ver
[vlen
], &v
, TG3_VER_SIZE
- vlen
);
12714 memcpy(&tp
->fw_ver
[vlen
], &v
, sizeof(v
));
12719 static void __devinit
tg3_read_dash_ver(struct tg3
*tp
)
12725 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) ||
12726 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
12729 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
12730 if (apedata
!= APE_SEG_SIG_MAGIC
)
12733 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
12734 if (!(apedata
& APE_FW_STATUS_READY
))
12737 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_VERSION
);
12739 if (tg3_ape_read32(tp
, TG3_APE_FW_FEATURES
) & TG3_APE_FW_FEATURE_NCSI
)
12744 vlen
= strlen(tp
->fw_ver
);
12746 snprintf(&tp
->fw_ver
[vlen
], TG3_VER_SIZE
- vlen
, " %s v%d.%d.%d.%d",
12748 (apedata
& APE_FW_VERSION_MAJMSK
) >> APE_FW_VERSION_MAJSFT
,
12749 (apedata
& APE_FW_VERSION_MINMSK
) >> APE_FW_VERSION_MINSFT
,
12750 (apedata
& APE_FW_VERSION_REVMSK
) >> APE_FW_VERSION_REVSFT
,
12751 (apedata
& APE_FW_VERSION_BLDMSK
));
12754 static void __devinit
tg3_read_fw_ver(struct tg3
*tp
)
12757 bool vpd_vers
= false;
12759 if (tp
->fw_ver
[0] != 0)
12762 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) {
12763 strcat(tp
->fw_ver
, "sb");
12767 if (tg3_nvram_read(tp
, 0, &val
))
12770 if (val
== TG3_EEPROM_MAGIC
)
12771 tg3_read_bc_ver(tp
);
12772 else if ((val
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
)
12773 tg3_read_sb_ver(tp
, val
);
12774 else if ((val
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
12775 tg3_read_hwsb_ver(tp
);
12779 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
12780 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) || vpd_vers
)
12783 tg3_read_mgmtfw_ver(tp
);
12786 tp
->fw_ver
[TG3_VER_SIZE
- 1] = 0;
12789 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*);
12791 static void inline vlan_features_add(struct net_device
*dev
, unsigned long flags
)
12793 #if TG3_VLAN_TAG_USED
12794 dev
->vlan_features
|= flags
;
12798 static int __devinit
tg3_get_invariants(struct tg3
*tp
)
12800 static struct pci_device_id write_reorder_chipsets
[] = {
12801 { PCI_DEVICE(PCI_VENDOR_ID_AMD
,
12802 PCI_DEVICE_ID_AMD_FE_GATE_700C
) },
12803 { PCI_DEVICE(PCI_VENDOR_ID_AMD
,
12804 PCI_DEVICE_ID_AMD_8131_BRIDGE
) },
12805 { PCI_DEVICE(PCI_VENDOR_ID_VIA
,
12806 PCI_DEVICE_ID_VIA_8385_0
) },
12810 u32 pci_state_reg
, grc_misc_cfg
;
12815 /* Force memory write invalidate off. If we leave it on,
12816 * then on 5700_BX chips we have to enable a workaround.
12817 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12818 * to match the cacheline size. The Broadcom driver have this
12819 * workaround but turns MWI off all the times so never uses
12820 * it. This seems to suggest that the workaround is insufficient.
12822 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
12823 pci_cmd
&= ~PCI_COMMAND_INVALIDATE
;
12824 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
12826 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12827 * has the register indirect write enable bit set before
12828 * we try to access any of the MMIO registers. It is also
12829 * critical that the PCI-X hw workaround situation is decided
12830 * before that as well.
12832 pci_read_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12835 tp
->pci_chip_rev_id
= (misc_ctrl_reg
>>
12836 MISC_HOST_CTRL_CHIPREV_SHIFT
);
12837 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_USE_PROD_ID_REG
) {
12838 u32 prod_id_asic_rev
;
12840 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5717
||
12841 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5718
||
12842 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5724
||
12843 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5719
)
12844 pci_read_config_dword(tp
->pdev
,
12845 TG3PCI_GEN2_PRODID_ASICREV
,
12846 &prod_id_asic_rev
);
12847 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57781
||
12848 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57785
||
12849 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57761
||
12850 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57765
||
12851 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
||
12852 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
)
12853 pci_read_config_dword(tp
->pdev
,
12854 TG3PCI_GEN15_PRODID_ASICREV
,
12855 &prod_id_asic_rev
);
12857 pci_read_config_dword(tp
->pdev
, TG3PCI_PRODID_ASICREV
,
12858 &prod_id_asic_rev
);
12860 tp
->pci_chip_rev_id
= prod_id_asic_rev
;
12863 /* Wrong chip ID in 5752 A0. This code can be removed later
12864 * as A0 is not in production.
12866 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5752_A0_HW
)
12867 tp
->pci_chip_rev_id
= CHIPREV_ID_5752_A0
;
12869 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12870 * we need to disable memory and use config. cycles
12871 * only to access all registers. The 5702/03 chips
12872 * can mistakenly decode the special cycles from the
12873 * ICH chipsets as memory write cycles, causing corruption
12874 * of register and memory space. Only certain ICH bridges
12875 * will drive special cycles with non-zero data during the
12876 * address phase which can fall within the 5703's address
12877 * range. This is not an ICH bug as the PCI spec allows
12878 * non-zero address during special cycles. However, only
12879 * these ICH bridges are known to drive non-zero addresses
12880 * during special cycles.
12882 * Since special cycles do not cross PCI bridges, we only
12883 * enable this workaround if the 5703 is on the secondary
12884 * bus of these ICH bridges.
12886 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
) ||
12887 (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A2
)) {
12888 static struct tg3_dev_id
{
12892 } ich_chipsets
[] = {
12893 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_8
,
12895 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_8
,
12897 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_11
,
12899 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_6
,
12903 struct tg3_dev_id
*pci_id
= &ich_chipsets
[0];
12904 struct pci_dev
*bridge
= NULL
;
12906 while (pci_id
->vendor
!= 0) {
12907 bridge
= pci_get_device(pci_id
->vendor
, pci_id
->device
,
12913 if (pci_id
->rev
!= PCI_ANY_ID
) {
12914 if (bridge
->revision
> pci_id
->rev
)
12917 if (bridge
->subordinate
&&
12918 (bridge
->subordinate
->number
==
12919 tp
->pdev
->bus
->number
)) {
12921 tp
->tg3_flags2
|= TG3_FLG2_ICH_WORKAROUND
;
12922 pci_dev_put(bridge
);
12928 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
12929 static struct tg3_dev_id
{
12932 } bridge_chipsets
[] = {
12933 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
},
12934 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
},
12937 struct tg3_dev_id
*pci_id
= &bridge_chipsets
[0];
12938 struct pci_dev
*bridge
= NULL
;
12940 while (pci_id
->vendor
!= 0) {
12941 bridge
= pci_get_device(pci_id
->vendor
,
12948 if (bridge
->subordinate
&&
12949 (bridge
->subordinate
->number
<=
12950 tp
->pdev
->bus
->number
) &&
12951 (bridge
->subordinate
->subordinate
>=
12952 tp
->pdev
->bus
->number
)) {
12953 tp
->tg3_flags3
|= TG3_FLG3_5701_DMA_BUG
;
12954 pci_dev_put(bridge
);
12960 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12961 * DMA addresses > 40-bit. This bridge may have other additional
12962 * 57xx devices behind it in some 4-port NIC designs for example.
12963 * Any tg3 device found behind the bridge will also need the 40-bit
12966 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
||
12967 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
12968 tp
->tg3_flags2
|= TG3_FLG2_5780_CLASS
;
12969 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
12970 tp
->msi_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_MSI
);
12972 struct pci_dev
*bridge
= NULL
;
12975 bridge
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
12976 PCI_DEVICE_ID_SERVERWORKS_EPB
,
12978 if (bridge
&& bridge
->subordinate
&&
12979 (bridge
->subordinate
->number
<=
12980 tp
->pdev
->bus
->number
) &&
12981 (bridge
->subordinate
->subordinate
>=
12982 tp
->pdev
->bus
->number
)) {
12983 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
12984 pci_dev_put(bridge
);
12990 /* Initialize misc host control in PCI block. */
12991 tp
->misc_host_ctrl
|= (misc_ctrl_reg
&
12992 MISC_HOST_CTRL_CHIPREV
);
12993 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12994 tp
->misc_host_ctrl
);
12996 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
12997 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
||
12998 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
12999 tp
->pdev_peer
= tg3_find_peer(tp
);
13001 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13002 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
13003 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
13004 tp
->tg3_flags3
|= TG3_FLG3_5717_PLUS
;
13006 /* Intentionally exclude ASIC_REV_5906 */
13007 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
13008 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
13009 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13010 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
13011 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
13012 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
13013 (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
))
13014 tp
->tg3_flags3
|= TG3_FLG3_5755_PLUS
;
13016 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
13017 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
13018 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
||
13019 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13020 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
13021 tp
->tg3_flags2
|= TG3_FLG2_5750_PLUS
;
13023 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) ||
13024 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
13025 tp
->tg3_flags2
|= TG3_FLG2_5705_PLUS
;
13027 /* 5700 B0 chips do not support checksumming correctly due
13028 * to hardware bugs.
13030 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5700_B0
)
13031 tp
->tg3_flags
|= TG3_FLAG_BROKEN_CHECKSUMS
;
13033 unsigned long features
= NETIF_F_IP_CSUM
| NETIF_F_SG
| NETIF_F_GRO
;
13035 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
13036 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
13037 features
|= NETIF_F_IPV6_CSUM
;
13038 tp
->dev
->features
|= features
;
13039 vlan_features_add(tp
->dev
, features
);
13042 /* Determine TSO capabilities */
13043 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)
13044 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_3
;
13045 else if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13046 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13047 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_2
;
13048 else if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
13049 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_1
| TG3_FLG2_TSO_BUG
;
13050 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
&&
13051 tp
->pci_chip_rev_id
>= CHIPREV_ID_5750_C2
)
13052 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_BUG
;
13053 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
13054 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
&&
13055 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) {
13056 tp
->tg3_flags2
|= TG3_FLG2_TSO_BUG
;
13057 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
)
13058 tp
->fw_needed
= FIRMWARE_TG3TSO5
;
13060 tp
->fw_needed
= FIRMWARE_TG3TSO
;
13065 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
13066 tp
->tg3_flags
|= TG3_FLAG_SUPPORT_MSI
;
13067 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
||
13068 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
||
13069 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
&&
13070 tp
->pci_chip_rev_id
<= CHIPREV_ID_5714_A2
&&
13071 tp
->pdev_peer
== tp
->pdev
))
13072 tp
->tg3_flags
&= ~TG3_FLAG_SUPPORT_MSI
;
13074 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13075 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
13076 tp
->tg3_flags2
|= TG3_FLG2_1SHOT_MSI
;
13079 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) {
13080 tp
->tg3_flags
|= TG3_FLAG_SUPPORT_MSIX
;
13081 tp
->irq_max
= TG3_IRQ_MAX_VECS
;
13085 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13086 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
13087 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13088 tp
->tg3_flags3
|= TG3_FLG3_SHORT_DMA_BUG
;
13089 else if (!(tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)) {
13090 tp
->tg3_flags3
|= TG3_FLG3_4G_DMA_BNDRY_BUG
;
13091 tp
->tg3_flags3
|= TG3_FLG3_40BIT_DMA_LIMIT_BUG
;
13094 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)
13095 tp
->tg3_flags3
|= TG3_FLG3_USE_JUMBO_BDFLAG
;
13097 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
13098 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
13099 (tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
))
13100 tp
->tg3_flags
|= TG3_FLAG_JUMBO_CAPABLE
;
13102 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
13105 tp
->pcie_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_EXP
);
13106 if (tp
->pcie_cap
!= 0) {
13109 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
13111 pcie_set_readrq(tp
->pdev
, 4096);
13113 pci_read_config_word(tp
->pdev
,
13114 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
13116 if (lnkctl
& PCI_EXP_LNKCTL_CLKREQ_EN
) {
13117 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13118 tp
->tg3_flags2
&= ~TG3_FLG2_HW_TSO_2
;
13119 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13120 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
13121 tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A0
||
13122 tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A1
)
13123 tp
->tg3_flags3
|= TG3_FLG3_CLKREQ_BUG
;
13124 } else if (tp
->pci_chip_rev_id
== CHIPREV_ID_5717_A0
) {
13125 tp
->tg3_flags3
|= TG3_FLG3_L1PLLPD_EN
;
13127 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
13128 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
13129 } else if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
13130 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
13131 tp
->pcix_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_PCIX
);
13132 if (!tp
->pcix_cap
) {
13133 dev_err(&tp
->pdev
->dev
,
13134 "Cannot find PCI-X capability, aborting\n");
13138 if (!(pci_state_reg
& PCISTATE_CONV_PCI_MODE
))
13139 tp
->tg3_flags
|= TG3_FLAG_PCIX_MODE
;
13142 /* If we have an AMD 762 or VIA K8T800 chipset, write
13143 * reordering to the mailbox registers done by the host
13144 * controller can cause major troubles. We read back from
13145 * every mailbox register write to force the writes to be
13146 * posted to the chip in order.
13148 if (pci_dev_present(write_reorder_chipsets
) &&
13149 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
13150 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
13152 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
13153 &tp
->pci_cacheline_sz
);
13154 pci_read_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
13155 &tp
->pci_lat_timer
);
13156 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
13157 tp
->pci_lat_timer
< 64) {
13158 tp
->pci_lat_timer
= 64;
13159 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
13160 tp
->pci_lat_timer
);
13163 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5700_BX
) {
13164 /* 5700 BX chips need to have their TX producer index
13165 * mailboxes written twice to workaround a bug.
13167 tp
->tg3_flags
|= TG3_FLAG_TXD_MBOX_HWBUG
;
13169 /* If we are in PCI-X mode, enable register write workaround.
13171 * The workaround is to use indirect register accesses
13172 * for all chip writes not to mailbox registers.
13174 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
13177 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
13179 /* The chip can have it's power management PCI config
13180 * space registers clobbered due to this bug.
13181 * So explicitly force the chip into D0 here.
13183 pci_read_config_dword(tp
->pdev
,
13184 tp
->pm_cap
+ PCI_PM_CTRL
,
13186 pm_reg
&= ~PCI_PM_CTRL_STATE_MASK
;
13187 pm_reg
|= PCI_PM_CTRL_PME_ENABLE
| 0 /* D0 */;
13188 pci_write_config_dword(tp
->pdev
,
13189 tp
->pm_cap
+ PCI_PM_CTRL
,
13192 /* Also, force SERR#/PERR# in PCI command. */
13193 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
13194 pci_cmd
|= PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
;
13195 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
13199 if ((pci_state_reg
& PCISTATE_BUS_SPEED_HIGH
) != 0)
13200 tp
->tg3_flags
|= TG3_FLAG_PCI_HIGH_SPEED
;
13201 if ((pci_state_reg
& PCISTATE_BUS_32BIT
) != 0)
13202 tp
->tg3_flags
|= TG3_FLAG_PCI_32BIT
;
13204 /* Chip-specific fixup from Broadcom driver */
13205 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
) &&
13206 (!(pci_state_reg
& PCISTATE_RETRY_SAME_DMA
))) {
13207 pci_state_reg
|= PCISTATE_RETRY_SAME_DMA
;
13208 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, pci_state_reg
);
13211 /* Default fast path register access methods */
13212 tp
->read32
= tg3_read32
;
13213 tp
->write32
= tg3_write32
;
13214 tp
->read32_mbox
= tg3_read32
;
13215 tp
->write32_mbox
= tg3_write32
;
13216 tp
->write32_tx_mbox
= tg3_write32
;
13217 tp
->write32_rx_mbox
= tg3_write32
;
13219 /* Various workaround register access methods */
13220 if (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
)
13221 tp
->write32
= tg3_write_indirect_reg32
;
13222 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
||
13223 ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
13224 tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
)) {
13226 * Back to back register writes can cause problems on these
13227 * chips, the workaround is to read back all reg writes
13228 * except those to mailbox regs.
13230 * See tg3_write_indirect_reg32().
13232 tp
->write32
= tg3_write_flush_reg32
;
13235 if ((tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
) ||
13236 (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)) {
13237 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
13238 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
13239 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
13242 if (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
) {
13243 tp
->read32
= tg3_read_indirect_reg32
;
13244 tp
->write32
= tg3_write_indirect_reg32
;
13245 tp
->read32_mbox
= tg3_read_indirect_mbox
;
13246 tp
->write32_mbox
= tg3_write_indirect_mbox
;
13247 tp
->write32_tx_mbox
= tg3_write_indirect_mbox
;
13248 tp
->write32_rx_mbox
= tg3_write_indirect_mbox
;
13253 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
13254 pci_cmd
&= ~PCI_COMMAND_MEMORY
;
13255 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
13257 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
13258 tp
->read32_mbox
= tg3_read32_mbox_5906
;
13259 tp
->write32_mbox
= tg3_write32_mbox_5906
;
13260 tp
->write32_tx_mbox
= tg3_write32_mbox_5906
;
13261 tp
->write32_rx_mbox
= tg3_write32_mbox_5906
;
13264 if (tp
->write32
== tg3_write_indirect_reg32
||
13265 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
13266 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13267 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)))
13268 tp
->tg3_flags
|= TG3_FLAG_SRAM_USE_CONFIG
;
13270 /* Get eeprom hw config before calling tg3_set_power_state().
13271 * In particular, the TG3_FLG2_IS_NIC flag must be
13272 * determined before calling tg3_set_power_state() so that
13273 * we know whether or not to switch out of Vaux power.
13274 * When the flag is set, it means that GPIO1 is used for eeprom
13275 * write protect and also implies that it is a LOM where GPIOs
13276 * are not used to switch power.
13278 tg3_get_eeprom_hw_cfg(tp
);
13280 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
13281 /* Allow reads and writes to the
13282 * APE register and memory space.
13284 pci_state_reg
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
13285 PCISTATE_ALLOW_APE_SHMEM_WR
|
13286 PCISTATE_ALLOW_APE_PSPACE_WR
;
13287 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
13291 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13292 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
13293 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
13294 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
13295 (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
))
13296 tp
->tg3_flags
|= TG3_FLAG_CPMU_PRESENT
;
13298 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13299 * GPIO1 driven high will bring 5700's external PHY out of reset.
13300 * It is also used as eeprom write protect on LOMs.
13302 tp
->grc_local_ctrl
= GRC_LCLCTRL_INT_ON_ATTN
| GRC_LCLCTRL_AUTO_SEEPROM
;
13303 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
13304 (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
))
13305 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
13306 GRC_LCLCTRL_GPIO_OUTPUT1
);
13307 /* Unused GPIO3 must be driven as output on 5752 because there
13308 * are no pull-up resistors on unused GPIO pins.
13310 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
13311 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
13313 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
13314 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
13315 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
13316 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
13318 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
13319 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
13320 /* Turn off the debug UART. */
13321 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
13322 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
13323 /* Keep VMain power. */
13324 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
13325 GRC_LCLCTRL_GPIO_OUTPUT0
;
13328 /* Force the chip into D0. */
13329 err
= tg3_set_power_state(tp
, PCI_D0
);
13331 dev_err(&tp
->pdev
->dev
, "Transition to D0 failed\n");
13335 /* Derive initial jumbo mode from MTU assigned in
13336 * ether_setup() via the alloc_etherdev() call
13338 if (tp
->dev
->mtu
> ETH_DATA_LEN
&&
13339 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
13340 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
13342 /* Determine WakeOnLan speed to use. */
13343 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13344 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
13345 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
||
13346 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B2
) {
13347 tp
->tg3_flags
&= ~(TG3_FLAG_WOL_SPEED_100MB
);
13349 tp
->tg3_flags
|= TG3_FLAG_WOL_SPEED_100MB
;
13352 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13353 tp
->phy_flags
|= TG3_PHYFLG_IS_FET
;
13355 /* A few boards don't want Ethernet@WireSpeed phy feature */
13356 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
13357 ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
13358 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) &&
13359 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A1
)) ||
13360 (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) ||
13361 (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
13362 tp
->phy_flags
|= TG3_PHYFLG_NO_ETH_WIRE_SPEED
;
13364 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5703_AX
||
13365 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_AX
)
13366 tp
->phy_flags
|= TG3_PHYFLG_ADC_BUG
;
13367 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
)
13368 tp
->phy_flags
|= TG3_PHYFLG_5704_A0_BUG
;
13370 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
13371 !(tp
->phy_flags
& TG3_PHYFLG_IS_FET
) &&
13372 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
13373 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_57780
&&
13374 !(tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)) {
13375 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
13376 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
13377 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13378 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
) {
13379 if (tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5756
&&
13380 tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5722
)
13381 tp
->phy_flags
|= TG3_PHYFLG_JITTER_BUG
;
13382 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5755M
)
13383 tp
->phy_flags
|= TG3_PHYFLG_ADJUST_TRIM
;
13385 tp
->phy_flags
|= TG3_PHYFLG_BER_BUG
;
13388 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
13389 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
13390 tp
->phy_otp
= tg3_read_otp_phycfg(tp
);
13391 if (tp
->phy_otp
== 0)
13392 tp
->phy_otp
= TG3_OTP_DEFAULT
;
13395 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)
13396 tp
->mi_mode
= MAC_MI_MODE_500KHZ_CONST
;
13398 tp
->mi_mode
= MAC_MI_MODE_BASE
;
13400 tp
->coalesce_mode
= 0;
13401 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_AX
&&
13402 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_BX
)
13403 tp
->coalesce_mode
|= HOSTCC_MODE_32BYTE
;
13405 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
13406 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
13407 tp
->tg3_flags3
|= TG3_FLG3_USE_PHYLIB
;
13409 err
= tg3_mdio_init(tp
);
13413 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
&&
13414 tp
->pci_chip_rev_id
!= CHIPREV_ID_5717_A0
)
13417 /* Initialize data/descriptor byte/word swapping. */
13418 val
= tr32(GRC_MODE
);
13419 val
&= GRC_MODE_HOST_STACKUP
;
13420 tw32(GRC_MODE
, val
| tp
->grc_mode
);
13422 tg3_switch_clocks(tp
);
13424 /* Clear this out for sanity. */
13425 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
13427 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
13429 if ((pci_state_reg
& PCISTATE_CONV_PCI_MODE
) == 0 &&
13430 (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) == 0) {
13431 u32 chiprevid
= GET_CHIP_REV_ID(tp
->misc_host_ctrl
);
13433 if (chiprevid
== CHIPREV_ID_5701_A0
||
13434 chiprevid
== CHIPREV_ID_5701_B0
||
13435 chiprevid
== CHIPREV_ID_5701_B2
||
13436 chiprevid
== CHIPREV_ID_5701_B5
) {
13437 void __iomem
*sram_base
;
13439 /* Write some dummy words into the SRAM status block
13440 * area, see if it reads back correctly. If the return
13441 * value is bad, force enable the PCIX workaround.
13443 sram_base
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_STATS_BLK
;
13445 writel(0x00000000, sram_base
);
13446 writel(0x00000000, sram_base
+ 4);
13447 writel(0xffffffff, sram_base
+ 4);
13448 if (readl(sram_base
) != 0x00000000)
13449 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
13454 tg3_nvram_init(tp
);
13456 grc_misc_cfg
= tr32(GRC_MISC_CFG
);
13457 grc_misc_cfg
&= GRC_MISC_CFG_BOARD_ID_MASK
;
13459 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
13460 (grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788
||
13461 grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788M
))
13462 tp
->tg3_flags2
|= TG3_FLG2_IS_5788
;
13464 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
13465 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
))
13466 tp
->tg3_flags
|= TG3_FLAG_TAGGED_STATUS
;
13467 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
13468 tp
->coalesce_mode
|= (HOSTCC_MODE_CLRTICK_RXBD
|
13469 HOSTCC_MODE_CLRTICK_TXBD
);
13471 tp
->misc_host_ctrl
|= MISC_HOST_CTRL_TAGGED_STATUS
;
13472 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
13473 tp
->misc_host_ctrl
);
13476 /* Preserve the APE MAC_MODE bits */
13477 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
13478 tp
->mac_mode
= tr32(MAC_MODE
) |
13479 MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
13481 tp
->mac_mode
= TG3_DEF_MAC_MODE
;
13483 /* these are limited to 10/100 only */
13484 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
13485 (grc_misc_cfg
== 0x8000 || grc_misc_cfg
== 0x4000)) ||
13486 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
13487 tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
13488 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901
||
13489 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901_2
||
13490 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5705F
)) ||
13491 (tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
13492 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5751F
||
13493 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5753F
||
13494 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5787F
)) ||
13495 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
||
13496 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
||
13497 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
||
13498 (tp
->phy_flags
& TG3_PHYFLG_IS_FET
))
13499 tp
->phy_flags
|= TG3_PHYFLG_10_100_ONLY
;
13501 err
= tg3_phy_probe(tp
);
13503 dev_err(&tp
->pdev
->dev
, "phy probe failed, err %d\n", err
);
13504 /* ... but do not return immediately ... */
13509 tg3_read_fw_ver(tp
);
13511 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
13512 tp
->phy_flags
&= ~TG3_PHYFLG_USE_MI_INTERRUPT
;
13514 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
13515 tp
->phy_flags
|= TG3_PHYFLG_USE_MI_INTERRUPT
;
13517 tp
->phy_flags
&= ~TG3_PHYFLG_USE_MI_INTERRUPT
;
13520 /* 5700 {AX,BX} chips have a broken status block link
13521 * change bit implementation, so we must use the
13522 * status register in those cases.
13524 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
13525 tp
->tg3_flags
|= TG3_FLAG_USE_LINKCHG_REG
;
13527 tp
->tg3_flags
&= ~TG3_FLAG_USE_LINKCHG_REG
;
13529 /* The led_ctrl is set during tg3_phy_probe, here we might
13530 * have to force the link status polling mechanism based
13531 * upon subsystem IDs.
13533 if (tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
&&
13534 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
13535 !(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)) {
13536 tp
->phy_flags
|= TG3_PHYFLG_USE_MI_INTERRUPT
;
13537 tp
->tg3_flags
|= TG3_FLAG_USE_LINKCHG_REG
;
13540 /* For all SERDES we poll the MAC status register. */
13541 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
13542 tp
->tg3_flags
|= TG3_FLAG_POLL_SERDES
;
13544 tp
->tg3_flags
&= ~TG3_FLAG_POLL_SERDES
;
13546 tp
->rx_offset
= NET_IP_ALIGN
+ TG3_RX_HEADROOM
;
13547 tp
->rx_copy_thresh
= TG3_RX_COPY_THRESHOLD
;
13548 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
13549 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) != 0) {
13550 tp
->rx_offset
-= NET_IP_ALIGN
;
13551 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13552 tp
->rx_copy_thresh
= ~(u16
)0;
13556 tp
->rx_std_max_post
= TG3_RX_RING_SIZE
;
13558 /* Increment the rx prod index on the rx std ring by at most
13559 * 8 for these chips to workaround hw errata.
13561 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
13562 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
13563 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
13564 tp
->rx_std_max_post
= 8;
13566 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
)
13567 tp
->pwrmgmt_thresh
= tr32(PCIE_PWR_MGMT_THRESH
) &
13568 PCIE_PWR_MGMT_L1_THRESH_MSK
;
13573 #ifdef CONFIG_SPARC
13574 static int __devinit
tg3_get_macaddr_sparc(struct tg3
*tp
)
13576 struct net_device
*dev
= tp
->dev
;
13577 struct pci_dev
*pdev
= tp
->pdev
;
13578 struct device_node
*dp
= pci_device_to_OF_node(pdev
);
13579 const unsigned char *addr
;
13582 addr
= of_get_property(dp
, "local-mac-address", &len
);
13583 if (addr
&& len
== 6) {
13584 memcpy(dev
->dev_addr
, addr
, 6);
13585 memcpy(dev
->perm_addr
, dev
->dev_addr
, 6);
13591 static int __devinit
tg3_get_default_macaddr_sparc(struct tg3
*tp
)
13593 struct net_device
*dev
= tp
->dev
;
13595 memcpy(dev
->dev_addr
, idprom
->id_ethaddr
, 6);
13596 memcpy(dev
->perm_addr
, idprom
->id_ethaddr
, 6);
13601 static int __devinit
tg3_get_device_address(struct tg3
*tp
)
13603 struct net_device
*dev
= tp
->dev
;
13604 u32 hi
, lo
, mac_offset
;
13607 #ifdef CONFIG_SPARC
13608 if (!tg3_get_macaddr_sparc(tp
))
13613 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) ||
13614 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
13615 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
13617 if (tg3_nvram_lock(tp
))
13618 tw32_f(NVRAM_CMD
, NVRAM_CMD_RESET
);
13620 tg3_nvram_unlock(tp
);
13621 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13622 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
) {
13623 if (PCI_FUNC(tp
->pdev
->devfn
) & 1)
13625 if (PCI_FUNC(tp
->pdev
->devfn
) > 1)
13626 mac_offset
+= 0x18c;
13627 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13630 /* First try to get it from MAC address mailbox. */
13631 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_HIGH_MBOX
, &hi
);
13632 if ((hi
>> 16) == 0x484b) {
13633 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
13634 dev
->dev_addr
[1] = (hi
>> 0) & 0xff;
13636 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_LOW_MBOX
, &lo
);
13637 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
13638 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
13639 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
13640 dev
->dev_addr
[5] = (lo
>> 0) & 0xff;
13642 /* Some old bootcode may report a 0 MAC address in SRAM */
13643 addr_ok
= is_valid_ether_addr(&dev
->dev_addr
[0]);
13646 /* Next, try NVRAM. */
13647 if (!(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) &&
13648 !tg3_nvram_read_be32(tp
, mac_offset
+ 0, &hi
) &&
13649 !tg3_nvram_read_be32(tp
, mac_offset
+ 4, &lo
)) {
13650 memcpy(&dev
->dev_addr
[0], ((char *)&hi
) + 2, 2);
13651 memcpy(&dev
->dev_addr
[2], (char *)&lo
, sizeof(lo
));
13653 /* Finally just fetch it out of the MAC control regs. */
13655 hi
= tr32(MAC_ADDR_0_HIGH
);
13656 lo
= tr32(MAC_ADDR_0_LOW
);
13658 dev
->dev_addr
[5] = lo
& 0xff;
13659 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
13660 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
13661 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
13662 dev
->dev_addr
[1] = hi
& 0xff;
13663 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
13667 if (!is_valid_ether_addr(&dev
->dev_addr
[0])) {
13668 #ifdef CONFIG_SPARC
13669 if (!tg3_get_default_macaddr_sparc(tp
))
13674 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
13678 #define BOUNDARY_SINGLE_CACHELINE 1
13679 #define BOUNDARY_MULTI_CACHELINE 2
13681 static u32 __devinit
tg3_calc_dma_bndry(struct tg3
*tp
, u32 val
)
13683 int cacheline_size
;
13687 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
, &byte
);
13689 cacheline_size
= 1024;
13691 cacheline_size
= (int) byte
* 4;
13693 /* On 5703 and later chips, the boundary bits have no
13696 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
13697 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
&&
13698 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
13701 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13702 goal
= BOUNDARY_MULTI_CACHELINE
;
13704 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13705 goal
= BOUNDARY_SINGLE_CACHELINE
;
13711 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) {
13712 val
= goal
? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT
;
13719 /* PCI controllers on most RISC systems tend to disconnect
13720 * when a device tries to burst across a cache-line boundary.
13721 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13723 * Unfortunately, for PCI-E there are only limited
13724 * write-side controls for this, and thus for reads
13725 * we will still get the disconnects. We'll also waste
13726 * these PCI cycles for both read and write for chips
13727 * other than 5700 and 5701 which do not implement the
13730 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
13731 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
13732 switch (cacheline_size
) {
13737 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13738 val
|= (DMA_RWCTRL_READ_BNDRY_128_PCIX
|
13739 DMA_RWCTRL_WRITE_BNDRY_128_PCIX
);
13741 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
13742 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
13747 val
|= (DMA_RWCTRL_READ_BNDRY_256_PCIX
|
13748 DMA_RWCTRL_WRITE_BNDRY_256_PCIX
);
13752 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
13753 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
13756 } else if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
13757 switch (cacheline_size
) {
13761 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13762 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
13763 val
|= DMA_RWCTRL_WRITE_BNDRY_64_PCIE
;
13769 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
13770 val
|= DMA_RWCTRL_WRITE_BNDRY_128_PCIE
;
13774 switch (cacheline_size
) {
13776 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13777 val
|= (DMA_RWCTRL_READ_BNDRY_16
|
13778 DMA_RWCTRL_WRITE_BNDRY_16
);
13783 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13784 val
|= (DMA_RWCTRL_READ_BNDRY_32
|
13785 DMA_RWCTRL_WRITE_BNDRY_32
);
13790 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13791 val
|= (DMA_RWCTRL_READ_BNDRY_64
|
13792 DMA_RWCTRL_WRITE_BNDRY_64
);
13797 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13798 val
|= (DMA_RWCTRL_READ_BNDRY_128
|
13799 DMA_RWCTRL_WRITE_BNDRY_128
);
13804 val
|= (DMA_RWCTRL_READ_BNDRY_256
|
13805 DMA_RWCTRL_WRITE_BNDRY_256
);
13808 val
|= (DMA_RWCTRL_READ_BNDRY_512
|
13809 DMA_RWCTRL_WRITE_BNDRY_512
);
13813 val
|= (DMA_RWCTRL_READ_BNDRY_1024
|
13814 DMA_RWCTRL_WRITE_BNDRY_1024
);
13823 static int __devinit
tg3_do_test_dma(struct tg3
*tp
, u32
*buf
, dma_addr_t buf_dma
, int size
, int to_device
)
13825 struct tg3_internal_buffer_desc test_desc
;
13826 u32 sram_dma_descs
;
13829 sram_dma_descs
= NIC_SRAM_DMA_DESC_POOL_BASE
;
13831 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
, 0);
13832 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
, 0);
13833 tw32(RDMAC_STATUS
, 0);
13834 tw32(WDMAC_STATUS
, 0);
13836 tw32(BUFMGR_MODE
, 0);
13837 tw32(FTQ_RESET
, 0);
13839 test_desc
.addr_hi
= ((u64
) buf_dma
) >> 32;
13840 test_desc
.addr_lo
= buf_dma
& 0xffffffff;
13841 test_desc
.nic_mbuf
= 0x00002100;
13842 test_desc
.len
= size
;
13845 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13846 * the *second* time the tg3 driver was getting loaded after an
13849 * Broadcom tells me:
13850 * ...the DMA engine is connected to the GRC block and a DMA
13851 * reset may affect the GRC block in some unpredictable way...
13852 * The behavior of resets to individual blocks has not been tested.
13854 * Broadcom noted the GRC reset will also reset all sub-components.
13857 test_desc
.cqid_sqid
= (13 << 8) | 2;
13859 tw32_f(RDMAC_MODE
, RDMAC_MODE_ENABLE
);
13862 test_desc
.cqid_sqid
= (16 << 8) | 7;
13864 tw32_f(WDMAC_MODE
, WDMAC_MODE_ENABLE
);
13867 test_desc
.flags
= 0x00000005;
13869 for (i
= 0; i
< (sizeof(test_desc
) / sizeof(u32
)); i
++) {
13872 val
= *(((u32
*)&test_desc
) + i
);
13873 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
,
13874 sram_dma_descs
+ (i
* sizeof(u32
)));
13875 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
13877 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
13880 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ
, sram_dma_descs
);
13882 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ
, sram_dma_descs
);
13885 for (i
= 0; i
< 40; i
++) {
13889 val
= tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
);
13891 val
= tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
);
13892 if ((val
& 0xffff) == sram_dma_descs
) {
13903 #define TEST_BUFFER_SIZE 0x2000
13905 static int __devinit
tg3_test_dma(struct tg3
*tp
)
13907 dma_addr_t buf_dma
;
13908 u32
*buf
, saved_dma_rwctrl
;
13911 buf
= pci_alloc_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, &buf_dma
);
13917 tp
->dma_rwctrl
= ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT
) |
13918 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT
));
13920 tp
->dma_rwctrl
= tg3_calc_dma_bndry(tp
, tp
->dma_rwctrl
);
13922 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)
13925 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
13926 /* DMA read watermark not used on PCIE */
13927 tp
->dma_rwctrl
|= 0x00180000;
13928 } else if (!(tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
13929 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
||
13930 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)
13931 tp
->dma_rwctrl
|= 0x003f0000;
13933 tp
->dma_rwctrl
|= 0x003f000f;
13935 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
13936 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
13937 u32 ccval
= (tr32(TG3PCI_CLOCK_CTRL
) & 0x1f);
13938 u32 read_water
= 0x7;
13940 /* If the 5704 is behind the EPB bridge, we can
13941 * do the less restrictive ONE_DMA workaround for
13942 * better performance.
13944 if ((tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) &&
13945 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
13946 tp
->dma_rwctrl
|= 0x8000;
13947 else if (ccval
== 0x6 || ccval
== 0x7)
13948 tp
->dma_rwctrl
|= DMA_RWCTRL_ONE_DMA
;
13950 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
)
13952 /* Set bit 23 to enable PCIX hw bug fix */
13954 (read_water
<< DMA_RWCTRL_READ_WATER_SHIFT
) |
13955 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT
) |
13957 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
) {
13958 /* 5780 always in PCIX mode */
13959 tp
->dma_rwctrl
|= 0x00144000;
13960 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
13961 /* 5714 always in PCIX mode */
13962 tp
->dma_rwctrl
|= 0x00148000;
13964 tp
->dma_rwctrl
|= 0x001b000f;
13968 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
13969 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
13970 tp
->dma_rwctrl
&= 0xfffffff0;
13972 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13973 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
13974 /* Remove this if it causes problems for some boards. */
13975 tp
->dma_rwctrl
|= DMA_RWCTRL_USE_MEM_READ_MULT
;
13977 /* On 5700/5701 chips, we need to set this bit.
13978 * Otherwise the chip will issue cacheline transactions
13979 * to streamable DMA memory with not all the byte
13980 * enables turned on. This is an error on several
13981 * RISC PCI controllers, in particular sparc64.
13983 * On 5703/5704 chips, this bit has been reassigned
13984 * a different meaning. In particular, it is used
13985 * on those chips to enable a PCI-X workaround.
13987 tp
->dma_rwctrl
|= DMA_RWCTRL_ASSERT_ALL_BE
;
13990 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
13993 /* Unneeded, already done by tg3_get_invariants. */
13994 tg3_switch_clocks(tp
);
13997 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
13998 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
14001 /* It is best to perform DMA test with maximum write burst size
14002 * to expose the 5700/5701 write DMA bug.
14004 saved_dma_rwctrl
= tp
->dma_rwctrl
;
14005 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
14006 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
14011 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++)
14014 /* Send the buffer to the chip. */
14015 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 1);
14017 dev_err(&tp
->pdev
->dev
,
14018 "%s: Buffer write failed. err = %d\n",
14024 /* validate data reached card RAM correctly. */
14025 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
14027 tg3_read_mem(tp
, 0x2100 + (i
*4), &val
);
14028 if (le32_to_cpu(val
) != p
[i
]) {
14029 dev_err(&tp
->pdev
->dev
,
14030 "%s: Buffer corrupted on device! "
14031 "(%d != %d)\n", __func__
, val
, i
);
14032 /* ret = -ENODEV here? */
14037 /* Now read it back. */
14038 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 0);
14040 dev_err(&tp
->pdev
->dev
, "%s: Buffer read failed. "
14041 "err = %d\n", __func__
, ret
);
14046 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
14050 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
14051 DMA_RWCTRL_WRITE_BNDRY_16
) {
14052 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
14053 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
14054 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
14057 dev_err(&tp
->pdev
->dev
,
14058 "%s: Buffer corrupted on read back! "
14059 "(%d != %d)\n", __func__
, p
[i
], i
);
14065 if (i
== (TEST_BUFFER_SIZE
/ sizeof(u32
))) {
14071 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
14072 DMA_RWCTRL_WRITE_BNDRY_16
) {
14073 static struct pci_device_id dma_wait_state_chipsets
[] = {
14074 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
,
14075 PCI_DEVICE_ID_APPLE_UNI_N_PCI15
) },
14079 /* DMA test passed without adjusting DMA boundary,
14080 * now look for chipsets that are known to expose the
14081 * DMA bug without failing the test.
14083 if (pci_dev_present(dma_wait_state_chipsets
)) {
14084 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
14085 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
14087 /* Safe to use the calculated DMA boundary. */
14088 tp
->dma_rwctrl
= saved_dma_rwctrl
;
14091 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
14095 pci_free_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, buf
, buf_dma
);
14100 static void __devinit
tg3_init_link_config(struct tg3
*tp
)
14102 tp
->link_config
.advertising
=
14103 (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
14104 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
14105 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
|
14106 ADVERTISED_Autoneg
| ADVERTISED_MII
);
14107 tp
->link_config
.speed
= SPEED_INVALID
;
14108 tp
->link_config
.duplex
= DUPLEX_INVALID
;
14109 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
14110 tp
->link_config
.active_speed
= SPEED_INVALID
;
14111 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
14112 tp
->link_config
.orig_speed
= SPEED_INVALID
;
14113 tp
->link_config
.orig_duplex
= DUPLEX_INVALID
;
14114 tp
->link_config
.orig_autoneg
= AUTONEG_INVALID
;
14117 static void __devinit
tg3_init_bufmgr_config(struct tg3
*tp
)
14119 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) {
14120 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
14121 DEFAULT_MB_RDMA_LOW_WATER_5705
;
14122 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14123 DEFAULT_MB_MACRX_LOW_WATER_57765
;
14124 tp
->bufmgr_config
.mbuf_high_water
=
14125 DEFAULT_MB_HIGH_WATER_57765
;
14127 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
14128 DEFAULT_MB_RDMA_LOW_WATER_5705
;
14129 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
14130 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765
;
14131 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
14132 DEFAULT_MB_HIGH_WATER_JUMBO_57765
;
14133 } else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
14134 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
14135 DEFAULT_MB_RDMA_LOW_WATER_5705
;
14136 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14137 DEFAULT_MB_MACRX_LOW_WATER_5705
;
14138 tp
->bufmgr_config
.mbuf_high_water
=
14139 DEFAULT_MB_HIGH_WATER_5705
;
14140 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
14141 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14142 DEFAULT_MB_MACRX_LOW_WATER_5906
;
14143 tp
->bufmgr_config
.mbuf_high_water
=
14144 DEFAULT_MB_HIGH_WATER_5906
;
14147 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
14148 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780
;
14149 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
14150 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780
;
14151 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
14152 DEFAULT_MB_HIGH_WATER_JUMBO_5780
;
14154 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
14155 DEFAULT_MB_RDMA_LOW_WATER
;
14156 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14157 DEFAULT_MB_MACRX_LOW_WATER
;
14158 tp
->bufmgr_config
.mbuf_high_water
=
14159 DEFAULT_MB_HIGH_WATER
;
14161 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
14162 DEFAULT_MB_RDMA_LOW_WATER_JUMBO
;
14163 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
14164 DEFAULT_MB_MACRX_LOW_WATER_JUMBO
;
14165 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
14166 DEFAULT_MB_HIGH_WATER_JUMBO
;
14169 tp
->bufmgr_config
.dma_low_water
= DEFAULT_DMA_LOW_WATER
;
14170 tp
->bufmgr_config
.dma_high_water
= DEFAULT_DMA_HIGH_WATER
;
14173 static char * __devinit
tg3_phy_string(struct tg3
*tp
)
14175 switch (tp
->phy_id
& TG3_PHY_ID_MASK
) {
14176 case TG3_PHY_ID_BCM5400
: return "5400";
14177 case TG3_PHY_ID_BCM5401
: return "5401";
14178 case TG3_PHY_ID_BCM5411
: return "5411";
14179 case TG3_PHY_ID_BCM5701
: return "5701";
14180 case TG3_PHY_ID_BCM5703
: return "5703";
14181 case TG3_PHY_ID_BCM5704
: return "5704";
14182 case TG3_PHY_ID_BCM5705
: return "5705";
14183 case TG3_PHY_ID_BCM5750
: return "5750";
14184 case TG3_PHY_ID_BCM5752
: return "5752";
14185 case TG3_PHY_ID_BCM5714
: return "5714";
14186 case TG3_PHY_ID_BCM5780
: return "5780";
14187 case TG3_PHY_ID_BCM5755
: return "5755";
14188 case TG3_PHY_ID_BCM5787
: return "5787";
14189 case TG3_PHY_ID_BCM5784
: return "5784";
14190 case TG3_PHY_ID_BCM5756
: return "5722/5756";
14191 case TG3_PHY_ID_BCM5906
: return "5906";
14192 case TG3_PHY_ID_BCM5761
: return "5761";
14193 case TG3_PHY_ID_BCM5718C
: return "5718C";
14194 case TG3_PHY_ID_BCM5718S
: return "5718S";
14195 case TG3_PHY_ID_BCM57765
: return "57765";
14196 case TG3_PHY_ID_BCM5719C
: return "5719C";
14197 case TG3_PHY_ID_BCM8002
: return "8002/serdes";
14198 case 0: return "serdes";
14199 default: return "unknown";
14203 static char * __devinit
tg3_bus_string(struct tg3
*tp
, char *str
)
14205 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
14206 strcpy(str
, "PCI Express");
14208 } else if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
14209 u32 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
) & 0x1f;
14211 strcpy(str
, "PCIX:");
14213 if ((clock_ctrl
== 7) ||
14214 ((tr32(GRC_MISC_CFG
) & GRC_MISC_CFG_BOARD_ID_MASK
) ==
14215 GRC_MISC_CFG_BOARD_ID_5704CIOBE
))
14216 strcat(str
, "133MHz");
14217 else if (clock_ctrl
== 0)
14218 strcat(str
, "33MHz");
14219 else if (clock_ctrl
== 2)
14220 strcat(str
, "50MHz");
14221 else if (clock_ctrl
== 4)
14222 strcat(str
, "66MHz");
14223 else if (clock_ctrl
== 6)
14224 strcat(str
, "100MHz");
14226 strcpy(str
, "PCI:");
14227 if (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
)
14228 strcat(str
, "66MHz");
14230 strcat(str
, "33MHz");
14232 if (tp
->tg3_flags
& TG3_FLAG_PCI_32BIT
)
14233 strcat(str
, ":32-bit");
14235 strcat(str
, ":64-bit");
14239 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*tp
)
14241 struct pci_dev
*peer
;
14242 unsigned int func
, devnr
= tp
->pdev
->devfn
& ~7;
14244 for (func
= 0; func
< 8; func
++) {
14245 peer
= pci_get_slot(tp
->pdev
->bus
, devnr
| func
);
14246 if (peer
&& peer
!= tp
->pdev
)
14250 /* 5704 can be configured in single-port mode, set peer to
14251 * tp->pdev in that case.
14259 * We don't need to keep the refcount elevated; there's no way
14260 * to remove one half of this device without removing the other
14267 static void __devinit
tg3_init_coal(struct tg3
*tp
)
14269 struct ethtool_coalesce
*ec
= &tp
->coal
;
14271 memset(ec
, 0, sizeof(*ec
));
14272 ec
->cmd
= ETHTOOL_GCOALESCE
;
14273 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS
;
14274 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS
;
14275 ec
->rx_max_coalesced_frames
= LOW_RXMAX_FRAMES
;
14276 ec
->tx_max_coalesced_frames
= LOW_TXMAX_FRAMES
;
14277 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT
;
14278 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT
;
14279 ec
->rx_max_coalesced_frames_irq
= DEFAULT_RXCOAL_MAXF_INT
;
14280 ec
->tx_max_coalesced_frames_irq
= DEFAULT_TXCOAL_MAXF_INT
;
14281 ec
->stats_block_coalesce_usecs
= DEFAULT_STAT_COAL_TICKS
;
14283 if (tp
->coalesce_mode
& (HOSTCC_MODE_CLRTICK_RXBD
|
14284 HOSTCC_MODE_CLRTICK_TXBD
)) {
14285 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS_CLRTCKS
;
14286 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT_CLRTCKS
;
14287 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS_CLRTCKS
;
14288 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT_CLRTCKS
;
14291 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
14292 ec
->rx_coalesce_usecs_irq
= 0;
14293 ec
->tx_coalesce_usecs_irq
= 0;
14294 ec
->stats_block_coalesce_usecs
= 0;
14298 static const struct net_device_ops tg3_netdev_ops
= {
14299 .ndo_open
= tg3_open
,
14300 .ndo_stop
= tg3_close
,
14301 .ndo_start_xmit
= tg3_start_xmit
,
14302 .ndo_get_stats64
= tg3_get_stats64
,
14303 .ndo_validate_addr
= eth_validate_addr
,
14304 .ndo_set_multicast_list
= tg3_set_rx_mode
,
14305 .ndo_set_mac_address
= tg3_set_mac_addr
,
14306 .ndo_do_ioctl
= tg3_ioctl
,
14307 .ndo_tx_timeout
= tg3_tx_timeout
,
14308 .ndo_change_mtu
= tg3_change_mtu
,
14309 #if TG3_VLAN_TAG_USED
14310 .ndo_vlan_rx_register
= tg3_vlan_rx_register
,
14312 #ifdef CONFIG_NET_POLL_CONTROLLER
14313 .ndo_poll_controller
= tg3_poll_controller
,
14317 static const struct net_device_ops tg3_netdev_ops_dma_bug
= {
14318 .ndo_open
= tg3_open
,
14319 .ndo_stop
= tg3_close
,
14320 .ndo_start_xmit
= tg3_start_xmit_dma_bug
,
14321 .ndo_get_stats64
= tg3_get_stats64
,
14322 .ndo_validate_addr
= eth_validate_addr
,
14323 .ndo_set_multicast_list
= tg3_set_rx_mode
,
14324 .ndo_set_mac_address
= tg3_set_mac_addr
,
14325 .ndo_do_ioctl
= tg3_ioctl
,
14326 .ndo_tx_timeout
= tg3_tx_timeout
,
14327 .ndo_change_mtu
= tg3_change_mtu
,
14328 #if TG3_VLAN_TAG_USED
14329 .ndo_vlan_rx_register
= tg3_vlan_rx_register
,
14331 #ifdef CONFIG_NET_POLL_CONTROLLER
14332 .ndo_poll_controller
= tg3_poll_controller
,
14336 static int __devinit
tg3_init_one(struct pci_dev
*pdev
,
14337 const struct pci_device_id
*ent
)
14339 struct net_device
*dev
;
14341 int i
, err
, pm_cap
;
14342 u32 sndmbx
, rcvmbx
, intmbx
;
14344 u64 dma_mask
, persist_dma_mask
;
14346 printk_once(KERN_INFO
"%s\n", version
);
14348 err
= pci_enable_device(pdev
);
14350 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
14354 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
14356 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
14357 goto err_out_disable_pdev
;
14360 pci_set_master(pdev
);
14362 /* Find power-management capability. */
14363 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
14365 dev_err(&pdev
->dev
,
14366 "Cannot find Power Management capability, aborting\n");
14368 goto err_out_free_res
;
14371 dev
= alloc_etherdev_mq(sizeof(*tp
), TG3_IRQ_MAX_VECS
);
14373 dev_err(&pdev
->dev
, "Etherdev alloc failed, aborting\n");
14375 goto err_out_free_res
;
14378 SET_NETDEV_DEV(dev
, &pdev
->dev
);
14380 #if TG3_VLAN_TAG_USED
14381 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
14384 tp
= netdev_priv(dev
);
14387 tp
->pm_cap
= pm_cap
;
14388 tp
->rx_mode
= TG3_DEF_RX_MODE
;
14389 tp
->tx_mode
= TG3_DEF_TX_MODE
;
14392 tp
->msg_enable
= tg3_debug
;
14394 tp
->msg_enable
= TG3_DEF_MSG_ENABLE
;
14396 /* The word/byte swap controls here control register access byte
14397 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14400 tp
->misc_host_ctrl
=
14401 MISC_HOST_CTRL_MASK_PCI_INT
|
14402 MISC_HOST_CTRL_WORD_SWAP
|
14403 MISC_HOST_CTRL_INDIR_ACCESS
|
14404 MISC_HOST_CTRL_PCISTATE_RW
;
14406 /* The NONFRM (non-frame) byte/word swap controls take effect
14407 * on descriptor entries, anything which isn't packet data.
14409 * The StrongARM chips on the board (one for tx, one for rx)
14410 * are running in big-endian mode.
14412 tp
->grc_mode
= (GRC_MODE_WSWAP_DATA
| GRC_MODE_BSWAP_DATA
|
14413 GRC_MODE_WSWAP_NONFRM_DATA
);
14414 #ifdef __BIG_ENDIAN
14415 tp
->grc_mode
|= GRC_MODE_BSWAP_NONFRM_DATA
;
14417 spin_lock_init(&tp
->lock
);
14418 spin_lock_init(&tp
->indirect_lock
);
14419 INIT_WORK(&tp
->reset_task
, tg3_reset_task
);
14421 tp
->regs
= pci_ioremap_bar(pdev
, BAR_0
);
14423 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
14425 goto err_out_free_dev
;
14428 tg3_init_link_config(tp
);
14430 tp
->rx_pending
= TG3_DEF_RX_RING_PENDING
;
14431 tp
->rx_jumbo_pending
= TG3_DEF_RX_JUMBO_RING_PENDING
;
14433 dev
->ethtool_ops
= &tg3_ethtool_ops
;
14434 dev
->watchdog_timeo
= TG3_TX_TIMEOUT
;
14435 dev
->irq
= pdev
->irq
;
14437 err
= tg3_get_invariants(tp
);
14439 dev_err(&pdev
->dev
,
14440 "Problem fetching invariants of chip, aborting\n");
14441 goto err_out_iounmap
;
14444 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) &&
14445 tp
->pci_chip_rev_id
!= CHIPREV_ID_5717_A0
&&
14446 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5719
)
14447 dev
->netdev_ops
= &tg3_netdev_ops
;
14449 dev
->netdev_ops
= &tg3_netdev_ops_dma_bug
;
14452 /* The EPB bridge inside 5714, 5715, and 5780 and any
14453 * device behind the EPB cannot support DMA addresses > 40-bit.
14454 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14455 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14456 * do DMA address check in tg3_start_xmit().
14458 if (tp
->tg3_flags2
& TG3_FLG2_IS_5788
)
14459 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(32);
14460 else if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) {
14461 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(40);
14462 #ifdef CONFIG_HIGHMEM
14463 dma_mask
= DMA_BIT_MASK(64);
14466 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(64);
14468 /* Configure DMA attributes. */
14469 if (dma_mask
> DMA_BIT_MASK(32)) {
14470 err
= pci_set_dma_mask(pdev
, dma_mask
);
14472 dev
->features
|= NETIF_F_HIGHDMA
;
14473 err
= pci_set_consistent_dma_mask(pdev
,
14476 dev_err(&pdev
->dev
, "Unable to obtain 64 bit "
14477 "DMA for consistent allocations\n");
14478 goto err_out_iounmap
;
14482 if (err
|| dma_mask
== DMA_BIT_MASK(32)) {
14483 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
14485 dev_err(&pdev
->dev
,
14486 "No usable DMA configuration, aborting\n");
14487 goto err_out_iounmap
;
14491 tg3_init_bufmgr_config(tp
);
14493 /* Selectively allow TSO based on operating conditions */
14494 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) ||
14495 (tp
->fw_needed
&& !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)))
14496 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
14498 tp
->tg3_flags2
&= ~(TG3_FLG2_TSO_CAPABLE
| TG3_FLG2_TSO_BUG
);
14499 tp
->fw_needed
= NULL
;
14502 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
)
14503 tp
->fw_needed
= FIRMWARE_TG3
;
14505 /* TSO is on by default on chips that support hardware TSO.
14506 * Firmware TSO on older chips gives lower performance, so it
14507 * is off by default, but can be enabled using ethtool.
14509 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) &&
14510 (dev
->features
& NETIF_F_IP_CSUM
)) {
14511 dev
->features
|= NETIF_F_TSO
;
14512 vlan_features_add(dev
, NETIF_F_TSO
);
14514 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
) ||
14515 (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
)) {
14516 if (dev
->features
& NETIF_F_IPV6_CSUM
) {
14517 dev
->features
|= NETIF_F_TSO6
;
14518 vlan_features_add(dev
, NETIF_F_TSO6
);
14520 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) ||
14521 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
14522 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
14523 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) ||
14524 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
14525 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
14526 dev
->features
|= NETIF_F_TSO_ECN
;
14527 vlan_features_add(dev
, NETIF_F_TSO_ECN
);
14531 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
&&
14532 !(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
14533 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
)) {
14534 tp
->tg3_flags2
|= TG3_FLG2_MAX_RXPEND_64
;
14535 tp
->rx_pending
= 63;
14538 err
= tg3_get_device_address(tp
);
14540 dev_err(&pdev
->dev
,
14541 "Could not obtain valid ethernet address, aborting\n");
14542 goto err_out_iounmap
;
14545 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
14546 tp
->aperegs
= pci_ioremap_bar(pdev
, BAR_2
);
14547 if (!tp
->aperegs
) {
14548 dev_err(&pdev
->dev
,
14549 "Cannot map APE registers, aborting\n");
14551 goto err_out_iounmap
;
14554 tg3_ape_lock_init(tp
);
14556 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
14557 tg3_read_dash_ver(tp
);
14561 * Reset chip in case UNDI or EFI driver did not shutdown
14562 * DMA self test will enable WDMAC and we'll see (spurious)
14563 * pending DMA on the PCI bus at that point.
14565 if ((tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
) ||
14566 (tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
14567 tw32(MEMARB_MODE
, MEMARB_MODE_ENABLE
);
14568 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
14571 err
= tg3_test_dma(tp
);
14573 dev_err(&pdev
->dev
, "DMA engine test failed, aborting\n");
14574 goto err_out_apeunmap
;
14577 /* flow control autonegotiation is default behavior */
14578 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
14579 tp
->link_config
.flowctrl
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
14581 intmbx
= MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
;
14582 rcvmbx
= MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
;
14583 sndmbx
= MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
;
14584 for (i
= 0; i
< TG3_IRQ_MAX_VECS
; i
++) {
14585 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
14588 tnapi
->tx_pending
= TG3_DEF_TX_RING_PENDING
;
14590 tnapi
->int_mbox
= intmbx
;
14596 tnapi
->consmbox
= rcvmbx
;
14597 tnapi
->prodmbox
= sndmbx
;
14600 tnapi
->coal_now
= HOSTCC_MODE_COAL_VEC1_NOW
<< (i
- 1);
14601 netif_napi_add(dev
, &tnapi
->napi
, tg3_poll_msix
, 64);
14603 tnapi
->coal_now
= HOSTCC_MODE_NOW
;
14604 netif_napi_add(dev
, &tnapi
->napi
, tg3_poll
, 64);
14607 if (!(tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
))
14611 * If we support MSIX, we'll be using RSS. If we're using
14612 * RSS, the first vector only handles link interrupts and the
14613 * remaining vectors handle rx and tx interrupts. Reuse the
14614 * mailbox values for the next iteration. The values we setup
14615 * above are still useful for the single vectored mode.
14630 pci_set_drvdata(pdev
, dev
);
14632 err
= register_netdev(dev
);
14634 dev_err(&pdev
->dev
, "Cannot register net device, aborting\n");
14635 goto err_out_apeunmap
;
14638 netdev_info(dev
, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14639 tp
->board_part_number
,
14640 tp
->pci_chip_rev_id
,
14641 tg3_bus_string(tp
, str
),
14644 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) {
14645 struct phy_device
*phydev
;
14646 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
14648 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14649 phydev
->drv
->name
, dev_name(&phydev
->dev
));
14653 if (tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)
14654 ethtype
= "10/100Base-TX";
14655 else if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
14656 ethtype
= "1000Base-SX";
14658 ethtype
= "10/100/1000Base-T";
14660 netdev_info(dev
, "attached PHY is %s (%s Ethernet) "
14661 "(WireSpeed[%d])\n", tg3_phy_string(tp
), ethtype
,
14662 (tp
->phy_flags
& TG3_PHYFLG_NO_ETH_WIRE_SPEED
) == 0);
14665 netdev_info(dev
, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14666 (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0,
14667 (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) != 0,
14668 (tp
->phy_flags
& TG3_PHYFLG_USE_MI_INTERRUPT
) != 0,
14669 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0,
14670 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) != 0);
14671 netdev_info(dev
, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14673 pdev
->dma_mask
== DMA_BIT_MASK(32) ? 32 :
14674 ((u64
)pdev
->dma_mask
) == DMA_BIT_MASK(40) ? 40 : 64);
14680 iounmap(tp
->aperegs
);
14681 tp
->aperegs
= NULL
;
14694 pci_release_regions(pdev
);
14696 err_out_disable_pdev
:
14697 pci_disable_device(pdev
);
14698 pci_set_drvdata(pdev
, NULL
);
14702 static void __devexit
tg3_remove_one(struct pci_dev
*pdev
)
14704 struct net_device
*dev
= pci_get_drvdata(pdev
);
14707 struct tg3
*tp
= netdev_priv(dev
);
14710 release_firmware(tp
->fw
);
14712 flush_scheduled_work();
14714 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
14719 unregister_netdev(dev
);
14721 iounmap(tp
->aperegs
);
14722 tp
->aperegs
= NULL
;
14729 pci_release_regions(pdev
);
14730 pci_disable_device(pdev
);
14731 pci_set_drvdata(pdev
, NULL
);
14735 static int tg3_suspend(struct pci_dev
*pdev
, pm_message_t state
)
14737 struct net_device
*dev
= pci_get_drvdata(pdev
);
14738 struct tg3
*tp
= netdev_priv(dev
);
14739 pci_power_t target_state
;
14742 /* PCI register 4 needs to be saved whether netif_running() or not.
14743 * MSI address and data need to be saved if using MSI and
14746 pci_save_state(pdev
);
14748 if (!netif_running(dev
))
14751 flush_scheduled_work();
14753 tg3_netif_stop(tp
);
14755 del_timer_sync(&tp
->timer
);
14757 tg3_full_lock(tp
, 1);
14758 tg3_disable_ints(tp
);
14759 tg3_full_unlock(tp
);
14761 netif_device_detach(dev
);
14763 tg3_full_lock(tp
, 0);
14764 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
14765 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
14766 tg3_full_unlock(tp
);
14768 target_state
= pdev
->pm_cap
? pci_target_state(pdev
) : PCI_D3hot
;
14770 err
= tg3_set_power_state(tp
, target_state
);
14774 tg3_full_lock(tp
, 0);
14776 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
14777 err2
= tg3_restart_hw(tp
, 1);
14781 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
14782 add_timer(&tp
->timer
);
14784 netif_device_attach(dev
);
14785 tg3_netif_start(tp
);
14788 tg3_full_unlock(tp
);
14797 static int tg3_resume(struct pci_dev
*pdev
)
14799 struct net_device
*dev
= pci_get_drvdata(pdev
);
14800 struct tg3
*tp
= netdev_priv(dev
);
14803 pci_restore_state(tp
->pdev
);
14805 if (!netif_running(dev
))
14808 err
= tg3_set_power_state(tp
, PCI_D0
);
14812 netif_device_attach(dev
);
14814 tg3_full_lock(tp
, 0);
14816 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
14817 err
= tg3_restart_hw(tp
, 1);
14821 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
14822 add_timer(&tp
->timer
);
14824 tg3_netif_start(tp
);
14827 tg3_full_unlock(tp
);
14835 static struct pci_driver tg3_driver
= {
14836 .name
= DRV_MODULE_NAME
,
14837 .id_table
= tg3_pci_tbl
,
14838 .probe
= tg3_init_one
,
14839 .remove
= __devexit_p(tg3_remove_one
),
14840 .suspend
= tg3_suspend
,
14841 .resume
= tg3_resume
14844 static int __init
tg3_init(void)
14846 return pci_register_driver(&tg3_driver
);
14849 static void __exit
tg3_cleanup(void)
14851 pci_unregister_driver(&tg3_driver
);
14854 module_init(tg3_init
);
14855 module_exit(tg3_cleanup
);