arch/x86/oprofile/nmi_int.c

   1 /**
   2  * @file nmi_int.c
   3  *
   4  * @remark Copyright 2002-2009 OProfile authors
   5  * @remark Read the file COPYING
   6  *
   7  * @author John Levon <levon@movementarian.org>
   8  * @author Robert Richter <robert.richter@amd.com>
   9  * @author Barry Kasindorf <barry.kasindorf@amd.com>
  10  * @author Jason Yeh <jason.yeh@amd.com>
  11  * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/notifier.h>
  16 #include <linux/smp.h>
  17 #include <linux/oprofile.h>
  18 #include <linux/sysdev.h>
  19 #include <linux/slab.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/cpu.h>
  23 #include <asm/nmi.h>
  24 #include <asm/msr.h>
  25 #include <asm/apic.h>
  26
  27 #include "op_counter.h"
  28 #include "op_x86_model.h"
  29
  30 static struct op_x86_model_spec *model;
  31 static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
  32 static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
  33
  34 /* 0 == registered but off, 1 == registered and on */
  35 static int nmi_enabled = 0;
  36
  37 struct op_counter_config counter_config[OP_MAX_COUNTER];
  38
  39 /* common functions */
  40
  41 u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
  42                     struct op_counter_config *counter_config)
  43 {
  44         u64 val = 0;
  45         u16 event = (u16)counter_config->event;
  46
  47         val |= ARCH_PERFMON_EVENTSEL_INT;
  48         val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0;
  49         val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0;
  50         val |= (counter_config->unit_mask & 0xFF) << 8;
  51         event &= model->event_mask ? model->event_mask : 0xFF;
  52         val |= event & 0xFF;
  53         val |= (event & 0x0F00) << 24;
  54
  55         return val;
  56 }
  57
  58
  59 static int profile_exceptions_notify(struct notifier_block *self,
  60                                      unsigned long val, void *data)
  61 {
  62         struct die_args *args = (struct die_args *)data;
  63         int ret = NOTIFY_DONE;
  64         int cpu = smp_processor_id();
  65
  66         switch (val) {
  67         case DIE_NMI:
  68         case DIE_NMI_IPI:
  69                 model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu));
  70                 ret = NOTIFY_STOP;
  71                 break;
  72         default:
  73                 break;
  74         }
  75         return ret;
  76 }
  77
  78 static void nmi_cpu_save_registers(struct op_msrs *msrs)
  79 {
  80         struct op_msr *counters = msrs->counters;
  81         struct op_msr *controls = msrs->controls;
  82         unsigned int i;
  83
  84         for (i = 0; i < model->num_counters; ++i) {
  85                 if (counters[i].addr)
  86                         rdmsrl(counters[i].addr, counters[i].saved);
  87         }
  88
  89         for (i = 0; i < model->num_controls; ++i) {
  90                 if (controls[i].addr)
  91                         rdmsrl(controls[i].addr, controls[i].saved);
  92         }
  93 }
  94
  95 static void nmi_cpu_start(void *dummy)
  96 {
  97         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
  98         model->start(msrs);
  99 }
 100
 101 static int nmi_start(void)
 102 {
 103         on_each_cpu(nmi_cpu_start, NULL, 1);
 104         return 0;
 105 }
 106
 107 static void nmi_cpu_stop(void *dummy)
 108 {
 109         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
 110         model->stop(msrs);
 111 }
 112
 113 static void nmi_stop(void)
 114 {
 115         on_each_cpu(nmi_cpu_stop, NULL, 1);
 116 }
 117
 118 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 119
 120 static DEFINE_PER_CPU(int, switch_index);
 121
 122 static inline int has_mux(void)
 123 {
 124         return !!model->switch_ctrl;
 125 }
 126
 127 inline int op_x86_phys_to_virt(int phys)
 128 {
 129         return __get_cpu_var(switch_index) + phys;
 130 }
 131
 132 inline int op_x86_virt_to_phys(int virt)
 133 {
 134         return virt % model->num_counters;
 135 }
 136
 137 static void nmi_shutdown_mux(void)
 138 {
 139         int i;
 140
 141         if (!has_mux())
 142                 return;
 143
 144         for_each_possible_cpu(i) {
 145                 kfree(per_cpu(cpu_msrs, i).multiplex);
 146                 per_cpu(cpu_msrs, i).multiplex = NULL;
 147                 per_cpu(switch_index, i) = 0;
 148         }
 149 }
 150
 151 static int nmi_setup_mux(void)
 152 {
 153         size_t multiplex_size =
 154                 sizeof(struct op_msr) * model->num_virt_counters;
 155         int i;
 156
 157         if (!has_mux())
 158                 return 1;
 159
 160         for_each_possible_cpu(i) {
 161                 per_cpu(cpu_msrs, i).multiplex =
 162                         kzalloc(multiplex_size, GFP_KERNEL);
 163                 if (!per_cpu(cpu_msrs, i).multiplex)
 164                         return 0;
 165         }
 166
 167         return 1;
 168 }
 169
 170 static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
 171 {
 172         int i;
 173         struct op_msr *multiplex = msrs->multiplex;
 174
 175         if (!has_mux())
 176                 return;
 177
 178         for (i = 0; i < model->num_virt_counters; ++i) {
 179                 if (counter_config[i].enabled) {
 180                         multiplex[i].saved = -(u64)counter_config[i].count;
 181                 } else {
 182                         multiplex[i].saved = 0;
 183                 }
 184         }
 185
 186         per_cpu(switch_index, cpu) = 0;
 187 }
 188
 189 static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
 190 {
 191         struct op_msr *counters = msrs->counters;
 192         struct op_msr *multiplex = msrs->multiplex;
 193         int i;
 194
 195         for (i = 0; i < model->num_counters; ++i) {
 196                 int virt = op_x86_phys_to_virt(i);
 197                 if (counters[i].addr)
 198                         rdmsrl(counters[i].addr, multiplex[virt].saved);
 199         }
 200 }
 201
 202 static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
 203 {
 204         struct op_msr *counters = msrs->counters;
 205         struct op_msr *multiplex = msrs->multiplex;
 206         int i;
 207
 208         for (i = 0; i < model->num_counters; ++i) {
 209                 int virt = op_x86_phys_to_virt(i);
 210                 if (counters[i].addr)
 211                         wrmsrl(counters[i].addr, multiplex[virt].saved);
 212         }
 213 }
 214
 215 static void nmi_cpu_switch(void *dummy)
 216 {
 217         int cpu = smp_processor_id();
 218         int si = per_cpu(switch_index, cpu);
 219         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 220
 221         nmi_cpu_stop(NULL);
 222         nmi_cpu_save_mpx_registers(msrs);
 223
 224         /* move to next set */
 225         si += model->num_counters;
 226         if ((si >= model->num_virt_counters) || (counter_config[si].count == 0))
 227                 per_cpu(switch_index, cpu) = 0;
 228         else
 229                 per_cpu(switch_index, cpu) = si;
 230
 231         model->switch_ctrl(model, msrs);
 232         nmi_cpu_restore_mpx_registers(msrs);
 233
 234         nmi_cpu_start(NULL);
 235 }
 236
 237
 238 /*
 239  * Quick check to see if multiplexing is necessary.
 240  * The check should be sufficient since counters are used
 241  * in ordre.
 242  */
 243 static int nmi_multiplex_on(void)
 244 {
 245         return counter_config[model->num_counters].count ? 0 : -EINVAL;
 246 }
 247
 248 static int nmi_switch_event(void)
 249 {
 250         if (!has_mux())
 251                 return -ENOSYS;         /* not implemented */
 252         if (nmi_multiplex_on() < 0)
 253                 return -EINVAL;         /* not necessary */
 254
 255         on_each_cpu(nmi_cpu_switch, NULL, 1);
 256
 257         return 0;
 258 }
 259
 260 static inline void mux_init(struct oprofile_operations *ops)
 261 {
 262         if (has_mux())
 263                 ops->switch_events = nmi_switch_event;
 264 }
 265
 266 static void mux_clone(int cpu)
 267 {
 268         if (!has_mux())
 269                 return;
 270
 271         memcpy(per_cpu(cpu_msrs, cpu).multiplex,
 272                per_cpu(cpu_msrs, 0).multiplex,
 273                sizeof(struct op_msr) * model->num_virt_counters);
 274 }
 275
 276 #else
 277
 278 inline int op_x86_phys_to_virt(int phys) { return phys; }
 279 inline int op_x86_virt_to_phys(int virt) { return virt; }
 280 static inline void nmi_shutdown_mux(void) { }
 281 static inline int nmi_setup_mux(void) { return 1; }
 282 static inline void
 283 nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { }
 284 static inline void mux_init(struct oprofile_operations *ops) { }
 285 static void mux_clone(int cpu) { }
 286
 287 #endif
 288
 289 static void free_msrs(void)
 290 {
 291         int i;
 292         for_each_possible_cpu(i) {
 293                 kfree(per_cpu(cpu_msrs, i).counters);
 294                 per_cpu(cpu_msrs, i).counters = NULL;
 295                 kfree(per_cpu(cpu_msrs, i).controls);
 296                 per_cpu(cpu_msrs, i).controls = NULL;
 297         }
 298 }
 299
 300 static int allocate_msrs(void)
 301 {
 302         size_t controls_size = sizeof(struct op_msr) * model->num_controls;
 303         size_t counters_size = sizeof(struct op_msr) * model->num_counters;
 304
 305         int i;
 306         for_each_possible_cpu(i) {
 307                 per_cpu(cpu_msrs, i).counters = kzalloc(counters_size,
 308                                                         GFP_KERNEL);
 309                 if (!per_cpu(cpu_msrs, i).counters)
 310                         return 0;
 311                 per_cpu(cpu_msrs, i).controls = kzalloc(controls_size,
 312                                                         GFP_KERNEL);
 313                 if (!per_cpu(cpu_msrs, i).controls)
 314                         return 0;
 315         }
 316
 317         return 1;
 318 }
 319
 320 static void nmi_cpu_setup(void *dummy)
 321 {
 322         int cpu = smp_processor_id();
 323         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 324         nmi_cpu_save_registers(msrs);
 325         spin_lock(&oprofilefs_lock);
 326         model->setup_ctrs(model, msrs);
 327         nmi_cpu_setup_mux(cpu, msrs);
 328         spin_unlock(&oprofilefs_lock);
 329         per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
 330         apic_write(APIC_LVTPC, APIC_DM_NMI);
 331 }
 332
 333 static struct notifier_block profile_exceptions_nb = {
 334         .notifier_call = profile_exceptions_notify,
 335         .next = NULL,
 336         .priority = 2
 337 };
 338
 339 static int nmi_setup(void)
 340 {
 341         int err = 0;
 342         int cpu;
 343
 344         if (!allocate_msrs())
 345                 err = -ENOMEM;
 346         else if (!nmi_setup_mux())
 347                 err = -ENOMEM;
 348         else
 349                 err = register_die_notifier(&profile_exceptions_nb);
 350
 351         if (err) {
 352                 free_msrs();
 353                 nmi_shutdown_mux();
 354                 return err;
 355         }
 356
 357         /* We need to serialize save and setup for HT because the subset
 358          * of msrs are distinct for save and setup operations
 359          */
 360
 361         /* Assume saved/restored counters are the same on all CPUs */
 362         model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
 363         for_each_possible_cpu(cpu) {
 364                 if (!cpu)
 365                         continue;
 366
 367                 memcpy(per_cpu(cpu_msrs, cpu).counters,
 368                        per_cpu(cpu_msrs, 0).counters,
 369                        sizeof(struct op_msr) * model->num_counters);
 370
 371                 memcpy(per_cpu(cpu_msrs, cpu).controls,
 372                        per_cpu(cpu_msrs, 0).controls,
 373                        sizeof(struct op_msr) * model->num_controls);
 374
 375                 mux_clone(cpu);
 376         }
 377         on_each_cpu(nmi_cpu_setup, NULL, 1);
 378         nmi_enabled = 1;
 379         return 0;
 380 }
 381
 382 static void nmi_cpu_restore_registers(struct op_msrs *msrs)
 383 {
 384         struct op_msr *counters = msrs->counters;
 385         struct op_msr *controls = msrs->controls;
 386         unsigned int i;
 387
 388         for (i = 0; i < model->num_controls; ++i) {
 389                 if (controls[i].addr)
 390                         wrmsrl(controls[i].addr, controls[i].saved);
 391         }
 392
 393         for (i = 0; i < model->num_counters; ++i) {
 394                 if (counters[i].addr)
 395                         wrmsrl(counters[i].addr, counters[i].saved);
 396         }
 397 }
 398
 399 static void nmi_cpu_shutdown(void *dummy)
 400 {
 401         unsigned int v;
 402         int cpu = smp_processor_id();
 403         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 404
 405         /* restoring APIC_LVTPC can trigger an apic error because the delivery
 406          * mode and vector nr combination can be illegal. That's by design: on
 407          * power on apic lvt contain a zero vector nr which are legal only for
 408          * NMI delivery mode. So inhibit apic err before restoring lvtpc
 409          */
 410         v = apic_read(APIC_LVTERR);
 411         apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
 412         apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
 413         apic_write(APIC_LVTERR, v);
 414         nmi_cpu_restore_registers(msrs);
 415 }
 416
 417 static void nmi_shutdown(void)
 418 {
 419         struct op_msrs *msrs;
 420
 421         nmi_enabled = 0;
 422         on_each_cpu(nmi_cpu_shutdown, NULL, 1);
 423         unregister_die_notifier(&profile_exceptions_nb);
 424         nmi_shutdown_mux();
 425         msrs = &get_cpu_var(cpu_msrs);
 426         model->shutdown(msrs);
 427         free_msrs();
 428         put_cpu_var(cpu_msrs);
 429 }
 430
 431 static int nmi_create_files(struct super_block *sb, struct dentry *root)
 432 {
 433         unsigned int i;
 434
 435         for (i = 0; i < model->num_virt_counters; ++i) {
 436                 struct dentry *dir;
 437                 char buf[4];
 438
 439                 /* quick little hack to _not_ expose a counter if it is not
 440                  * available for use.  This should protect userspace app.
 441                  * NOTE:  assumes 1:1 mapping here (that counters are organized
 442                  *        sequentially in their struct assignment).
 443                  */
 444                 if (!avail_to_resrv_perfctr_nmi_bit(op_x86_virt_to_phys(i)))
 445                         continue;
 446
 447                 snprintf(buf,  sizeof(buf), "%d", i);
 448                 dir = oprofilefs_mkdir(sb, root, buf);
 449                 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
 450                 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
 451                 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
 452                 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
 453                 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
 454                 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
 455         }
 456
 457         return 0;
 458 }
 459
 460 #ifdef CONFIG_SMP
 461 static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
 462                                  void *data)
 463 {
 464         int cpu = (unsigned long)data;
 465         switch (action) {
 466         case CPU_DOWN_FAILED:
 467         case CPU_ONLINE:
 468                 smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
 469                 break;
 470         case CPU_DOWN_PREPARE:
 471                 smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
 472                 break;
 473         }
 474         return NOTIFY_DONE;
 475 }
 476
 477 static struct notifier_block oprofile_cpu_nb = {
 478         .notifier_call = oprofile_cpu_notifier
 479 };
 480 #endif
 481
 482 #ifdef CONFIG_PM
 483
 484 static int nmi_suspend(struct sys_device *dev, pm_message_t state)
 485 {
 486         /* Only one CPU left, just stop that one */
 487         if (nmi_enabled == 1)
 488                 nmi_cpu_stop(NULL);
 489         return 0;
 490 }
 491
 492 static int nmi_resume(struct sys_device *dev)
 493 {
 494         if (nmi_enabled == 1)
 495                 nmi_cpu_start(NULL);
 496         return 0;
 497 }
 498
 499 static struct sysdev_class oprofile_sysclass = {
 500         .name           = "oprofile",
 501         .resume         = nmi_resume,
 502         .suspend        = nmi_suspend,
 503 };
 504
 505 static struct sys_device device_oprofile = {
 506         .id     = 0,
 507         .cls    = &oprofile_sysclass,
 508 };
 509
 510 static int __init init_sysfs(void)
 511 {
 512         int error;
 513
 514         error = sysdev_class_register(&oprofile_sysclass);
 515         if (!error)
 516                 error = sysdev_register(&device_oprofile);
 517         return error;
 518 }
 519
 520 static void exit_sysfs(void)
 521 {
 522         sysdev_unregister(&device_oprofile);
 523         sysdev_class_unregister(&oprofile_sysclass);
 524 }
 525
 526 #else
 527 #define init_sysfs() do { } while (0)
 528 #define exit_sysfs() do { } while (0)
 529 #endif /* CONFIG_PM */
 530
 531 static int __init p4_init(char **cpu_type)
 532 {
 533         __u8 cpu_model = boot_cpu_data.x86_model;
 534
 535         if (cpu_model > 6 || cpu_model == 5)
 536                 return 0;
 537
 538 #ifndef CONFIG_SMP
 539         *cpu_type = "i386/p4";
 540         model = &op_p4_spec;
 541         return 1;
 542 #else
 543         switch (smp_num_siblings) {
 544         case 1:
 545                 *cpu_type = "i386/p4";
 546                 model = &op_p4_spec;
 547                 return 1;
 548
 549         case 2:
 550                 *cpu_type = "i386/p4-ht";
 551                 model = &op_p4_ht2_spec;
 552                 return 1;
 553         }
 554 #endif
 555
 556         printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
 557         printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
 558         return 0;
 559 }
 560
 561 static int force_arch_perfmon;
 562 static int force_cpu_type(const char *str, struct kernel_param *kp)
 563 {
 564         if (!strcmp(str, "arch_perfmon")) {
 565                 force_arch_perfmon = 1;
 566                 printk(KERN_INFO "oprofile: forcing architectural perfmon\n");
 567         }
 568
 569         return 0;
 570 }
 571 module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0);
 572
 573 static int __init ppro_init(char **cpu_type)
 574 {
 575         __u8 cpu_model = boot_cpu_data.x86_model;
 576         struct op_x86_model_spec *spec = &op_ppro_spec; /* default */
 577
 578         if (force_arch_perfmon && cpu_has_arch_perfmon)
 579                 return 0;
 580
 581         switch (cpu_model) {
 582         case 0 ... 2:
 583                 *cpu_type = "i386/ppro";
 584                 break;
 585         case 3 ... 5:
 586                 *cpu_type = "i386/pii";
 587                 break;
 588         case 6 ... 8:
 589         case 10 ... 11:
 590                 *cpu_type = "i386/piii";
 591                 break;
 592         case 9:
 593         case 13:
 594                 *cpu_type = "i386/p6_mobile";
 595                 break;
 596         case 14:
 597                 *cpu_type = "i386/core";
 598                 break;
 599         case 15: case 23:
 600                 *cpu_type = "i386/core_2";
 601                 break;
 602         case 0x2e:
 603         case 26:
 604                 spec = &op_arch_perfmon_spec;
 605                 *cpu_type = "i386/core_i7";
 606                 break;
 607         case 28:
 608                 *cpu_type = "i386/atom";
 609                 break;
 610         default:
 611                 /* Unknown */
 612                 return 0;
 613         }
 614
 615         model = spec;
 616         return 1;
 617 }
 618
 619 /* in order to get sysfs right */
 620 static int using_nmi;
 621
 622 int __init op_nmi_init(struct oprofile_operations *ops)
 623 {
 624         __u8 vendor = boot_cpu_data.x86_vendor;
 625         __u8 family = boot_cpu_data.x86;
 626         char *cpu_type = NULL;
 627         int ret = 0;
 628
 629         if (!cpu_has_apic)
 630                 return -ENODEV;
 631
 632         switch (vendor) {
 633         case X86_VENDOR_AMD:
 634                 /* Needs to be at least an Athlon (or hammer in 32bit mode) */
 635
 636                 switch (family) {
 637                 case 6:
 638                         cpu_type = "i386/athlon";
 639                         break;
 640                 case 0xf:
 641                         /*
 642                          * Actually it could be i386/hammer too, but
 643                          * give user space an consistent name.
 644                          */
 645                         cpu_type = "x86-64/hammer";
 646                         break;
 647                 case 0x10:
 648                         cpu_type = "x86-64/family10";
 649                         break;
 650                 case 0x11:
 651                         cpu_type = "x86-64/family11h";
 652                         break;
 653                 default:
 654                         return -ENODEV;
 655                 }
 656                 model = &op_amd_spec;
 657                 break;
 658
 659         case X86_VENDOR_INTEL:
 660                 switch (family) {
 661                         /* Pentium IV */
 662                 case 0xf:
 663                         p4_init(&cpu_type);
 664                         break;
 665
 666                         /* A P6-class processor */
 667                 case 6:
 668                         ppro_init(&cpu_type);
 669                         break;
 670
 671                 default:
 672                         break;
 673                 }
 674
 675                 if (cpu_type)
 676                         break;
 677
 678                 if (!cpu_has_arch_perfmon)
 679                         return -ENODEV;
 680
 681                 /* use arch perfmon as fallback */
 682                 cpu_type = "i386/arch_perfmon";
 683                 model = &op_arch_perfmon_spec;
 684                 break;
 685
 686         default:
 687                 return -ENODEV;
 688         }
 689
 690 #ifdef CONFIG_SMP
 691         register_cpu_notifier(&oprofile_cpu_nb);
 692 #endif
 693         /* default values, can be overwritten by model */
 694         ops->create_files       = nmi_create_files;
 695         ops->setup              = nmi_setup;
 696         ops->shutdown           = nmi_shutdown;
 697         ops->start              = nmi_start;
 698         ops->stop               = nmi_stop;
 699         ops->cpu_type           = cpu_type;
 700
 701         if (model->init)
 702                 ret = model->init(ops);
 703         if (ret)
 704                 return ret;
 705
 706         if (!model->num_virt_counters)
 707                 model->num_virt_counters = model->num_counters;
 708
 709         mux_init(ops);
 710
 711         init_sysfs();
 712         using_nmi = 1;
 713         printk(KERN_INFO "oprofile: using NMI interrupt.\n");
 714         return 0;
 715 }
 716
 717 void op_nmi_exit(void)
 718 {
 719         if (using_nmi) {
 720                 exit_sysfs();
 721 #ifdef CONFIG_SMP
 722                 unregister_cpu_notifier(&oprofile_cpu_nb);
 723 #endif
 724         }
 725         if (model->exit)
 726                 model->exit();
 727 }