drivers/mtd/maps/intel_vr_nor.c

   1 /*
   2  * drivers/mtd/maps/intel_vr_nor.c
   3  *
   4  * An MTD map driver for a NOR flash bank on the Expansion Bus of the Intel
   5  * Vermilion Range chipset.
   6  *
   7  * The Vermilion Range Expansion Bus supports four chip selects, each of which
   8  * has 64MiB of address space.  The 2nd BAR of the Expansion Bus PCI Device
   9  * is a 256MiB memory region containing the address spaces for all four of the
  10  * chip selects, with start addresses hardcoded on 64MiB boundaries.
  11  *
  12  * This map driver only supports NOR flash on chip select 0.  The buswidth
  13  * (either 8 bits or 16 bits) is determined by reading the Expansion Bus Timing
  14  * and Control Register for Chip Select 0 (EXP_TIMING_CS0).  This driver does
  15  * not modify the value in the EXP_TIMING_CS0 register except to enable writing
  16  * and disable boot acceleration.  The timing parameters in the register are
  17  * assumed to have been properly initialized by the BIOS.  The reset default
  18  * timing parameters are maximally conservative (slow), so access to the flash
  19  * will be slower than it should be if the BIOS has not initialized the timing
  20  * parameters.
  21  *
  22  * Author: Andy Lowe <alowe@mvista.com>
  23  *
  24  * 2006 (c) MontaVista Software, Inc. This file is licensed under
  25  * the terms of the GNU General Public License version 2. This program
  26  * is licensed "as is" without any warranty of any kind, whether express
  27  * or implied.
  28  */
  29
  30 #include <linux/module.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/pci.h>
  34 #include <linux/init.h>
  35 #include <linux/mtd/mtd.h>
  36 #include <linux/mtd/map.h>
  37 #include <linux/mtd/partitions.h>
  38 #include <linux/mtd/cfi.h>
  39 #include <linux/mtd/flashchip.h>
  40
  41 #define DRV_NAME "vr_nor"
  42
  43 struct vr_nor_mtd {
  44         void __iomem *csr_base;
  45         struct map_info map;
  46         struct mtd_info *info;
  47         struct pci_dev *dev;
  48 };
  49
  50 /* Expansion Bus Configuration and Status Registers are in BAR 0 */
  51 #define EXP_CSR_MBAR 0
  52 /* Expansion Bus Memory Window is BAR 1 */
  53 #define EXP_WIN_MBAR 1
  54 /* Maximum address space for Chip Select 0 is 64MiB */
  55 #define CS0_SIZE 0x04000000
  56 /* Chip Select 0 is at offset 0 in the Memory Window */
  57 #define CS0_START 0x0
  58 /* Chip Select 0 Timing Register is at offset 0 in CSR */
  59 #define EXP_TIMING_CS0 0x00
  60 #define TIMING_CS_EN            (1 << 31)       /* Chip Select Enable */
  61 #define TIMING_BOOT_ACCEL_DIS   (1 <<  8)       /* Boot Acceleration Disable */
  62 #define TIMING_WR_EN            (1 <<  1)       /* Write Enable */
  63 #define TIMING_BYTE_EN          (1 <<  0)       /* 8-bit vs 16-bit bus */
  64 #define TIMING_MASK             0x3FFF0000
  65
  66 static void __devexit vr_nor_destroy_partitions(struct vr_nor_mtd *p)
  67 {
  68         mtd_device_unregister(p->info);
  69 }
  70
  71 static int __devinit vr_nor_init_partitions(struct vr_nor_mtd *p)
  72 {
  73         /* register the flash bank */
  74         /* partition the flash bank */
  75         return mtd_device_parse_register(p->info, NULL, NULL, NULL, 0);
  76 }
  77
  78 static void __devexit vr_nor_destroy_mtd_setup(struct vr_nor_mtd *p)
  79 {
  80         map_destroy(p->info);
  81 }
  82
  83 static int __devinit vr_nor_mtd_setup(struct vr_nor_mtd *p)
  84 {
  85         static const char *probe_types[] =
  86             { "cfi_probe", "jedec_probe", NULL };
  87         const char **type;
  88
  89         for (type = probe_types; !p->info && *type; type++)
  90                 p->info = do_map_probe(*type, &p->map);
  91         if (!p->info)
  92                 return -ENODEV;
  93
  94         p->info->owner = THIS_MODULE;
  95
  96         return 0;
  97 }
  98
  99 static void __devexit vr_nor_destroy_maps(struct vr_nor_mtd *p)
 100 {
 101         unsigned int exp_timing_cs0;
 102
 103         /* write-protect the flash bank */
 104         exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0);
 105         exp_timing_cs0 &= ~TIMING_WR_EN;
 106         writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0);
 107
 108         /* unmap the flash window */
 109         iounmap(p->map.virt);
 110
 111         /* unmap the csr window */
 112         iounmap(p->csr_base);
 113 }
 114
 115 /*
 116  * Initialize the map_info structure and map the flash.
 117  * Returns 0 on success, nonzero otherwise.
 118  */
 119 static int __devinit vr_nor_init_maps(struct vr_nor_mtd *p)
 120 {
 121         unsigned long csr_phys, csr_len;
 122         unsigned long win_phys, win_len;
 123         unsigned int exp_timing_cs0;
 124         int err;
 125
 126         csr_phys = pci_resource_start(p->dev, EXP_CSR_MBAR);
 127         csr_len = pci_resource_len(p->dev, EXP_CSR_MBAR);
 128         win_phys = pci_resource_start(p->dev, EXP_WIN_MBAR);
 129         win_len = pci_resource_len(p->dev, EXP_WIN_MBAR);
 130
 131         if (!csr_phys || !csr_len || !win_phys || !win_len)
 132                 return -ENODEV;
 133
 134         if (win_len < (CS0_START + CS0_SIZE))
 135                 return -ENXIO;
 136
 137         p->csr_base = ioremap_nocache(csr_phys, csr_len);
 138         if (!p->csr_base)
 139                 return -ENOMEM;
 140
 141         exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0);
 142         if (!(exp_timing_cs0 & TIMING_CS_EN)) {
 143                 dev_warn(&p->dev->dev, "Expansion Bus Chip Select 0 "
 144                        "is disabled.\n");
 145                 err = -ENODEV;
 146                 goto release;
 147         }
 148         if ((exp_timing_cs0 & TIMING_MASK) == TIMING_MASK) {
 149                 dev_warn(&p->dev->dev, "Expansion Bus Chip Select 0 "
 150                        "is configured for maximally slow access times.\n");
 151         }
 152         p->map.name = DRV_NAME;
 153         p->map.bankwidth = (exp_timing_cs0 & TIMING_BYTE_EN) ? 1 : 2;
 154         p->map.phys = win_phys + CS0_START;
 155         p->map.size = CS0_SIZE;
 156         p->map.virt = ioremap_nocache(p->map.phys, p->map.size);
 157         if (!p->map.virt) {
 158                 err = -ENOMEM;
 159                 goto release;
 160         }
 161         simple_map_init(&p->map);
 162
 163         /* Enable writes to flash bank */
 164         exp_timing_cs0 |= TIMING_BOOT_ACCEL_DIS | TIMING_WR_EN;
 165         writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0);
 166
 167         return 0;
 168
 169       release:
 170         iounmap(p->csr_base);
 171         return err;
 172 }
 173
 174 static struct pci_device_id vr_nor_pci_ids[] = {
 175         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x500D)},
 176         {0,}
 177 };
 178
 179 static void __devexit vr_nor_pci_remove(struct pci_dev *dev)
 180 {
 181         struct vr_nor_mtd *p = pci_get_drvdata(dev);
 182
 183         pci_set_drvdata(dev, NULL);
 184         vr_nor_destroy_partitions(p);
 185         vr_nor_destroy_mtd_setup(p);
 186         vr_nor_destroy_maps(p);
 187         kfree(p);
 188         pci_release_regions(dev);
 189         pci_disable_device(dev);
 190 }
 191
 192 static int __devinit
 193 vr_nor_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 194 {
 195         struct vr_nor_mtd *p = NULL;
 196         unsigned int exp_timing_cs0;
 197         int err;
 198
 199         err = pci_enable_device(dev);
 200         if (err)
 201                 goto out;
 202
 203         err = pci_request_regions(dev, DRV_NAME);
 204         if (err)
 205                 goto disable_dev;
 206
 207         p = kzalloc(sizeof(*p), GFP_KERNEL);
 208         err = -ENOMEM;
 209         if (!p)
 210                 goto release;
 211
 212         p->dev = dev;
 213
 214         err = vr_nor_init_maps(p);
 215         if (err)
 216                 goto release;
 217
 218         err = vr_nor_mtd_setup(p);
 219         if (err)
 220                 goto destroy_maps;
 221
 222         err = vr_nor_init_partitions(p);
 223         if (err)
 224                 goto destroy_mtd_setup;
 225
 226         pci_set_drvdata(dev, p);
 227
 228         return 0;
 229
 230       destroy_mtd_setup:
 231         map_destroy(p->info);
 232
 233       destroy_maps:
 234         /* write-protect the flash bank */
 235         exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0);
 236         exp_timing_cs0 &= ~TIMING_WR_EN;
 237         writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0);
 238
 239         /* unmap the flash window */
 240         iounmap(p->map.virt);
 241
 242         /* unmap the csr window */
 243         iounmap(p->csr_base);
 244
 245       release:
 246         kfree(p);
 247         pci_release_regions(dev);
 248
 249       disable_dev:
 250         pci_disable_device(dev);
 251
 252       out:
 253         return err;
 254 }
 255
 256 static struct pci_driver vr_nor_pci_driver = {
 257         .name = DRV_NAME,
 258         .probe = vr_nor_pci_probe,
 259         .remove = __devexit_p(vr_nor_pci_remove),
 260         .id_table = vr_nor_pci_ids,
 261 };
 262
 263 static int __init vr_nor_mtd_init(void)
 264 {
 265         return pci_register_driver(&vr_nor_pci_driver);
 266 }
 267
 268 static void __exit vr_nor_mtd_exit(void)
 269 {
 270         pci_unregister_driver(&vr_nor_pci_driver);
 271 }
 272
 273 module_init(vr_nor_mtd_init);
 274 module_exit(vr_nor_mtd_exit);
 275
 276 MODULE_AUTHOR("Andy Lowe");
 277 MODULE_DESCRIPTION("MTD map driver for NOR flash on Intel Vermilion Range");
 278 MODULE_LICENSE("GPL");
 279 MODULE_DEVICE_TABLE(pci, vr_nor_pci_ids);