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netxen: fix mac list management
[linux-2.6/btrfs-unstable.git] / drivers / net / netxen / netxen_nic.h
blobd368e24c023594758c0cf2a921c37261ff91a5a7
1 /*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen Inc,
26 * 18922 Forge Drive
27 * Cupertino, CA 95014-0701
28 *
29 */
30
31 #ifndef _NETXEN_NIC_H_
32 #define _NETXEN_NIC_H_
33
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/types.h>
37 #include <linux/ioport.h>
38 #include <linux/pci.h>
39 #include <linux/netdevice.h>
40 #include <linux/etherdevice.h>
41 #include <linux/ip.h>
42 #include <linux/in.h>
43 #include <linux/tcp.h>
44 #include <linux/skbuff.h>
45 #include <linux/firmware.h>
46
47 #include <linux/ethtool.h>
48 #include <linux/mii.h>
49 #include <linux/timer.h>
50
51 #include <linux/vmalloc.h>
52
53 #include <asm/io.h>
54 #include <asm/byteorder.h>
55
56 #include "netxen_nic_hw.h"
57
58 #define _NETXEN_NIC_LINUX_MAJOR 4
59 #define _NETXEN_NIC_LINUX_MINOR 0
60 #define _NETXEN_NIC_LINUX_SUBVERSION 30
61 #define NETXEN_NIC_LINUX_VERSIONID "4.0.30"
62
63 #define NETXEN_VERSION_CODE(a, b, c) (((a) << 16) + ((b) << 8) + (c))
64
65 #define NETXEN_NUM_FLASH_SECTORS (64)
66 #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
67 #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \
68 * NETXEN_FLASH_SECTOR_SIZE)
69
70 #define PHAN_VENDOR_ID 0x4040
71
72 #define RCV_DESC_RINGSIZE(rds_ring) \
73 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
74 #define RCV_BUFF_RINGSIZE(rds_ring) \
75 (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc)
76 #define STATUS_DESC_RINGSIZE(sds_ring) \
77 (sizeof(struct status_desc) * (sds_ring)->num_desc)
78 #define TX_BUFF_RINGSIZE(tx_ring) \
79 (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc)
80 #define TX_DESC_RINGSIZE(tx_ring) \
81 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
82
83 #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
84
85 #define NETXEN_RCV_PRODUCER_OFFSET 0
86 #define NETXEN_RCV_PEG_DB_ID 2
87 #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
88 #define FLASH_SUCCESS 0
89
90 #define ADDR_IN_WINDOW1(off) \
91 ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
92
93 /*
94 * normalize a 64MB crb address to 32MB PCI window
95 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
96 */
97 #define NETXEN_CRB_NORMAL(reg) \
98 ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
99
100 #define NETXEN_CRB_NORMALIZE(adapter, reg) \
101 pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
102
103 #define DB_NORMALIZE(adapter, off) \
104 (adapter->ahw.db_base + (off))
105
106 #define NX_P2_C0 0x24
107 #define NX_P2_C1 0x25
108 #define NX_P3_A0 0x30
109 #define NX_P3_A2 0x30
110 #define NX_P3_B0 0x40
111 #define NX_P3_B1 0x41
112 #define NX_P3_B2 0x42
113
114 #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1)
115 #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
116
117 #define FIRST_PAGE_GROUP_START 0
118 #define FIRST_PAGE_GROUP_END 0x100000
119
120 #define SECOND_PAGE_GROUP_START 0x6000000
121 #define SECOND_PAGE_GROUP_END 0x68BC000
122
123 #define THIRD_PAGE_GROUP_START 0x70E4000
124 #define THIRD_PAGE_GROUP_END 0x8000000
125
126 #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
127 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
128 #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
129
130 #define P2_MAX_MTU (8000)
131 #define P3_MAX_MTU (9600)
132 #define NX_ETHERMTU 1500
133 #define NX_MAX_ETHERHDR 32 /* This contains some padding */
134
135 #define NX_RX_NORMAL_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU)
136 #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU)
137 #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU)
138 #define NX_CT_DEFAULT_RX_BUF_LEN 2048
139
140 #define MAX_RX_BUFFER_LENGTH 1760
141 #define MAX_RX_JUMBO_BUFFER_LENGTH 8062
142 #define MAX_RX_LRO_BUFFER_LENGTH (8062)
143 #define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - 2)
144 #define RX_JUMBO_DMA_MAP_LEN \
145 (MAX_RX_JUMBO_BUFFER_LENGTH - 2)
146 #define RX_LRO_DMA_MAP_LEN (MAX_RX_LRO_BUFFER_LENGTH - 2)
147
148 /*
149 * Maximum number of ring contexts
150 */
151 #define MAX_RING_CTX 1
152
153 /* Opcodes to be used with the commands */
154 #define TX_ETHER_PKT 0x01
155 #define TX_TCP_PKT 0x02
156 #define TX_UDP_PKT 0x03
157 #define TX_IP_PKT 0x04
158 #define TX_TCP_LSO 0x05
159 #define TX_TCP_LSO6 0x06
160 #define TX_IPSEC 0x07
161 #define TX_IPSEC_CMD 0x0a
162 #define TX_TCPV6_PKT 0x0b
163 #define TX_UDPV6_PKT 0x0c
164
165 /* The following opcodes are for internal consumption. */
166 #define NETXEN_CONTROL_OP 0x10
167 #define PEGNET_REQUEST 0x11
168
169 #define MAX_NUM_CARDS 4
170
171 #define MAX_BUFFERS_PER_CMD 32
172
173 /*
174 * Following are the states of the Phantom. Phantom will set them and
175 * Host will read to check if the fields are correct.
176 */
177 #define PHAN_INITIALIZE_START 0xff00
178 #define PHAN_INITIALIZE_FAILED 0xffff
179 #define PHAN_INITIALIZE_COMPLETE 0xff01
180
181 /* Host writes the following to notify that it has done the init-handshake */
182 #define PHAN_INITIALIZE_ACK 0xf00f
183
184 #define NUM_RCV_DESC_RINGS 3
185 #define NUM_STS_DESC_RINGS 4
186
187 #define RCV_RING_NORMAL 0
188 #define RCV_RING_JUMBO 1
189 #define RCV_RING_LRO 2
190
191 #define MAX_CMD_DESCRIPTORS 4096
192 #define MAX_RCV_DESCRIPTORS 16384
193 #define MAX_CMD_DESCRIPTORS_HOST 1024
194 #define MAX_RCV_DESCRIPTORS_1G 2048
195 #define MAX_RCV_DESCRIPTORS_10G 4096
196 #define MAX_JUMBO_RCV_DESCRIPTORS 1024
197 #define MAX_LRO_RCV_DESCRIPTORS 8
198 #define NETXEN_CTX_SIGNATURE 0xdee0
199 #define NETXEN_CTX_SIGNATURE_V2 0x0002dee0
200 #define NETXEN_CTX_RESET 0xbad0
201 #define NETXEN_RCV_PRODUCER(ringid) (ringid)
202
203 #define PHAN_PEG_RCV_INITIALIZED 0xff01
204 #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
205
206 #define get_next_index(index, length) \
207 (((index) + 1) & ((length) - 1))
208
209 #define get_index_range(index,length,count) \
210 (((index) + (count)) & ((length) - 1))
211
212 #define MPORT_SINGLE_FUNCTION_MODE 0x1111
213 #define MPORT_MULTI_FUNCTION_MODE 0x2222
214
215 #include "netxen_nic_phan_reg.h"
216
217 /*
218 * NetXen host-peg signal message structure
219 *
220 * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx
221 * Bit 2 : priv_id => must be 1
222 * Bit 3-17 : count => for doorbell
223 * Bit 18-27 : ctx_id => Context id
224 * Bit 28-31 : opcode
225 */
226
227 typedef u32 netxen_ctx_msg;
228
229 #define netxen_set_msg_peg_id(config_word, val) \
230 ((config_word) &= ~3, (config_word) |= val & 3)
231 #define netxen_set_msg_privid(config_word) \
232 ((config_word) |= 1 << 2)
233 #define netxen_set_msg_count(config_word, val) \
234 ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
235 #define netxen_set_msg_ctxid(config_word, val) \
236 ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
237 #define netxen_set_msg_opcode(config_word, val) \
238 ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
239
240 struct netxen_rcv_ring {
241 __le64 addr;
242 __le32 size;
243 __le32 rsrvd;
244 };
245
246 struct netxen_sts_ring {
247 __le64 addr;
248 __le32 size;
249 __le16 msi_index;
250 __le16 rsvd;
251 } ;
252
253 struct netxen_ring_ctx {
254
255 /* one command ring */
256 __le64 cmd_consumer_offset;
257 __le64 cmd_ring_addr;
258 __le32 cmd_ring_size;
259 __le32 rsrvd;
260
261 /* three receive rings */
262 struct netxen_rcv_ring rcv_rings[NUM_RCV_DESC_RINGS];
263
264 __le64 sts_ring_addr;
265 __le32 sts_ring_size;
266
267 __le32 ctx_id;
268
269 __le64 rsrvd_2[3];
270 __le32 sts_ring_count;
271 __le32 rsrvd_3;
272 struct netxen_sts_ring sts_rings[NUM_STS_DESC_RINGS];
273
274 } __attribute__ ((aligned(64)));
275
276 /*
277 * Following data structures describe the descriptors that will be used.
278 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
279 * we are doing LSO (above the 1500 size packet) only.
280 */
281
282 /*
283 * The size of reference handle been changed to 16 bits to pass the MSS fields
284 * for the LSO packet
285 */
286
287 #define FLAGS_CHECKSUM_ENABLED 0x01
288 #define FLAGS_LSO_ENABLED 0x02
289 #define FLAGS_IPSEC_SA_ADD 0x04
290 #define FLAGS_IPSEC_SA_DELETE 0x08
291 #define FLAGS_VLAN_TAGGED 0x10
292
293 #define netxen_set_cmd_desc_port(cmd_desc, var) \
294 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
295 #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \
296 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
297
298 #define netxen_set_tx_port(_desc, _port) \
299 (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)
300
301 #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \
302 (_desc)->flags_opcode = \
303 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))
304
305 #define netxen_set_tx_frags_len(_desc, _frags, _len) \
306 (_desc)->num_of_buffers_total_length = \
307 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))
308
309 struct cmd_desc_type0 {
310 u8 tcp_hdr_offset; /* For LSO only */
311 u8 ip_hdr_offset; /* For LSO only */
312 /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */
313 __le16 flags_opcode;
314 /* Bit pattern: 0-7 total number of segments,
315 8-31 Total size of the packet */
316 __le32 num_of_buffers_total_length;
317 union {
318 struct {
319 __le32 addr_low_part2;
320 __le32 addr_high_part2;
321 };
322 __le64 addr_buffer2;
323 };
324
325 __le16 reference_handle; /* changed to u16 to add mss */
326 __le16 mss; /* passed by NDIS_PACKET for LSO */
327 /* Bit pattern 0-3 port, 0-3 ctx id */
328 u8 port_ctxid;
329 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
330 __le16 conn_id; /* IPSec offoad only */
331
332 union {
333 struct {
334 __le32 addr_low_part3;
335 __le32 addr_high_part3;
336 };
337 __le64 addr_buffer3;
338 };
339 union {
340 struct {
341 __le32 addr_low_part1;
342 __le32 addr_high_part1;
343 };
344 __le64 addr_buffer1;
345 };
346
347 __le16 buffer_length[4];
348
349 union {
350 struct {
351 __le32 addr_low_part4;
352 __le32 addr_high_part4;
353 };
354 __le64 addr_buffer4;
355 };
356
357 __le64 unused;
358
359 } __attribute__ ((aligned(64)));
360
361 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
362 struct rcv_desc {
363 __le16 reference_handle;
364 __le16 reserved;
365 __le32 buffer_length; /* allocated buffer length (usually 2K) */
366 __le64 addr_buffer;
367 };
368
369 /* opcode field in status_desc */
370 #define NETXEN_NIC_RXPKT_DESC 0x04
371 #define NETXEN_OLD_RXPKT_DESC 0x3f
372 #define NETXEN_NIC_RESPONSE_DESC 0x05
373
374 /* for status field in status_desc */
375 #define STATUS_NEED_CKSUM (1)
376 #define STATUS_CKSUM_OK (2)
377
378 /* owner bits of status_desc */
379 #define STATUS_OWNER_HOST (0x1ULL << 56)
380 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
381
382 /* Status descriptor:
383 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
384 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
385 53-55 desc_cnt, 56-57 owner, 58-63 opcode
386 */
387 #define netxen_get_sts_port(sts_data) \
388 ((sts_data) & 0x0F)
389 #define netxen_get_sts_status(sts_data) \
390 (((sts_data) >> 4) & 0x0F)
391 #define netxen_get_sts_type(sts_data) \
392 (((sts_data) >> 8) & 0x0F)
393 #define netxen_get_sts_totallength(sts_data) \
394 (((sts_data) >> 12) & 0xFFFF)
395 #define netxen_get_sts_refhandle(sts_data) \
396 (((sts_data) >> 28) & 0xFFFF)
397 #define netxen_get_sts_prot(sts_data) \
398 (((sts_data) >> 44) & 0x0F)
399 #define netxen_get_sts_pkt_offset(sts_data) \
400 (((sts_data) >> 48) & 0x1F)
401 #define netxen_get_sts_desc_cnt(sts_data) \
402 (((sts_data) >> 53) & 0x7)
403 #define netxen_get_sts_opcode(sts_data) \
404 (((sts_data) >> 58) & 0x03F)
405
406 struct status_desc {
407 __le64 status_desc_data[2];
408 } __attribute__ ((aligned(16)));
409
410 /* The version of the main data structure */
411 #define NETXEN_BDINFO_VERSION 1
412
413 /* Magic number to let user know flash is programmed */
414 #define NETXEN_BDINFO_MAGIC 0x12345678
415
416 /* Max number of Gig ports on a Phantom board */
417 #define NETXEN_MAX_PORTS 4
418
419 #define NETXEN_BRDTYPE_P1_BD 0x0000
420 #define NETXEN_BRDTYPE_P1_SB 0x0001
421 #define NETXEN_BRDTYPE_P1_SMAX 0x0002
422 #define NETXEN_BRDTYPE_P1_SOCK 0x0003
423
424 #define NETXEN_BRDTYPE_P2_SOCK_31 0x0008
425 #define NETXEN_BRDTYPE_P2_SOCK_35 0x0009
426 #define NETXEN_BRDTYPE_P2_SB35_4G 0x000a
427 #define NETXEN_BRDTYPE_P2_SB31_10G 0x000b
428 #define NETXEN_BRDTYPE_P2_SB31_2G 0x000c
429
430 #define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ 0x000d
431 #define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ 0x000e
432 #define NETXEN_BRDTYPE_P2_SB31_10G_CX4 0x000f
433
434 #define NETXEN_BRDTYPE_P3_REF_QG 0x0021
435 #define NETXEN_BRDTYPE_P3_HMEZ 0x0022
436 #define NETXEN_BRDTYPE_P3_10G_CX4_LP 0x0023
437 #define NETXEN_BRDTYPE_P3_4_GB 0x0024
438 #define NETXEN_BRDTYPE_P3_IMEZ 0x0025
439 #define NETXEN_BRDTYPE_P3_10G_SFP_PLUS 0x0026
440 #define NETXEN_BRDTYPE_P3_10000_BASE_T 0x0027
441 #define NETXEN_BRDTYPE_P3_XG_LOM 0x0028
442 #define NETXEN_BRDTYPE_P3_4_GB_MM 0x0029
443 #define NETXEN_BRDTYPE_P3_10G_SFP_CT 0x002a
444 #define NETXEN_BRDTYPE_P3_10G_SFP_QT 0x002b
445 #define NETXEN_BRDTYPE_P3_10G_CX4 0x0031
446 #define NETXEN_BRDTYPE_P3_10G_XFP 0x0032
447 #define NETXEN_BRDTYPE_P3_10G_TP 0x0080
448
449 struct netxen_board_info {
450 u32 header_version;
451
452 u32 board_mfg;
453 u32 board_type;
454 u32 board_num;
455 u32 chip_id;
456 u32 chip_minor;
457 u32 chip_major;
458 u32 chip_pkg;
459 u32 chip_lot;
460
461 u32 port_mask; /* available niu ports */
462 u32 peg_mask; /* available pegs */
463 u32 icache_ok; /* can we run with icache? */
464 u32 dcache_ok; /* can we run with dcache? */
465 u32 casper_ok;
466
467 u32 mac_addr_lo_0;
468 u32 mac_addr_lo_1;
469 u32 mac_addr_lo_2;
470 u32 mac_addr_lo_3;
471
472 /* MN-related config */
473 u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */
474 u32 mn_sync_shift_cclk;
475 u32 mn_sync_shift_mclk;
476 u32 mn_wb_en;
477 u32 mn_crystal_freq; /* in MHz */
478 u32 mn_speed; /* in MHz */
479 u32 mn_org;
480 u32 mn_depth;
481 u32 mn_ranks_0; /* ranks per slot */
482 u32 mn_ranks_1; /* ranks per slot */
483 u32 mn_rd_latency_0;
484 u32 mn_rd_latency_1;
485 u32 mn_rd_latency_2;
486 u32 mn_rd_latency_3;
487 u32 mn_rd_latency_4;
488 u32 mn_rd_latency_5;
489 u32 mn_rd_latency_6;
490 u32 mn_rd_latency_7;
491 u32 mn_rd_latency_8;
492 u32 mn_dll_val[18];
493 u32 mn_mode_reg; /* MIU DDR Mode Register */
494 u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */
495 u32 mn_timing_0; /* MIU Memory Control Timing Rgister */
496 u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */
497 u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */
498
499 /* SN-related config */
500 u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */
501 u32 sn_pt_mode; /* pass through mode */
502 u32 sn_ecc_en;
503 u32 sn_wb_en;
504 u32 sn_crystal_freq;
505 u32 sn_speed;
506 u32 sn_org;
507 u32 sn_depth;
508 u32 sn_dll_tap;
509 u32 sn_rd_latency;
510
511 u32 mac_addr_hi_0;
512 u32 mac_addr_hi_1;
513 u32 mac_addr_hi_2;
514 u32 mac_addr_hi_3;
515
516 u32 magic; /* indicates flash has been initialized */
517
518 u32 mn_rdimm;
519 u32 mn_dll_override;
520
521 };
522
523 #define FLASH_NUM_PORTS (4)
524
525 struct netxen_flash_mac_addr {
526 u32 flash_addr[32];
527 };
528
529 struct netxen_user_old_info {
530 u8 flash_md5[16];
531 u8 crbinit_md5[16];
532 u8 brdcfg_md5[16];
533 /* bootloader */
534 u32 bootld_version;
535 u32 bootld_size;
536 u8 bootld_md5[16];
537 /* image */
538 u32 image_version;
539 u32 image_size;
540 u8 image_md5[16];
541 /* primary image status */
542 u32 primary_status;
543 u32 secondary_present;
544
545 /* MAC address , 4 ports */
546 struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
547 };
548 #define FLASH_NUM_MAC_PER_PORT 32
549 struct netxen_user_info {
550 u8 flash_md5[16 * 64];
551 /* bootloader */
552 u32 bootld_version;
553 u32 bootld_size;
554 /* image */
555 u32 image_version;
556 u32 image_size;
557 /* primary image status */
558 u32 primary_status;
559 u32 secondary_present;
560
561 /* MAC address , 4 ports, 32 address per port */
562 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
563 u32 sub_sys_id;
564 u8 serial_num[32];
565
566 /* Any user defined data */
567 };
568
569 /*
570 * Flash Layout - new format.
571 */
572 struct netxen_new_user_info {
573 u8 flash_md5[16 * 64];
574 /* bootloader */
575 u32 bootld_version;
576 u32 bootld_size;
577 /* image */
578 u32 image_version;
579 u32 image_size;
580 /* primary image status */
581 u32 primary_status;
582 u32 secondary_present;
583
584 /* MAC address , 4 ports, 32 address per port */
585 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
586 u32 sub_sys_id;
587 u8 serial_num[32];
588
589 /* Any user defined data */
590 };
591
592 #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
593 #define SECONDARY_IMAGE_ABSENT 0xffffffff
594 #define PRIMARY_IMAGE_GOOD 0x5a5a5a5a
595 #define PRIMARY_IMAGE_BAD 0xffffffff
596
597 /* Flash memory map */
598 #define NETXEN_CRBINIT_START 0 /* crbinit section */
599 #define NETXEN_BRDCFG_START 0x4000 /* board config */
600 #define NETXEN_INITCODE_START 0x6000 /* pegtune code */
601 #define NETXEN_BOOTLD_START 0x10000 /* bootld */
602 #define NETXEN_IMAGE_START 0x43000 /* compressed image */
603 #define NETXEN_SECONDARY_START 0x200000 /* backup images */
604 #define NETXEN_PXE_START 0x3E0000 /* PXE boot rom */
605 #define NETXEN_USER_START 0x3E8000 /* Firmare info */
606 #define NETXEN_FIXED_START 0x3F0000 /* backup of crbinit */
607
608 #define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408)
609 #define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c)
610 #define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c)
611 #define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128)
612 #define NX_FW_MIN_SIZE (0x3fffff)
613 #define NX_P2_MN_ROMIMAGE 0
614 #define NX_P3_CT_ROMIMAGE 1
615 #define NX_P3_MN_ROMIMAGE 2
616
617 #define NETXEN_USER_START_OLD NETXEN_PXE_START /* for backward compatibility */
618
619 #define NETXEN_FLASH_START (NETXEN_CRBINIT_START)
620 #define NETXEN_INIT_SECTOR (0)
621 #define NETXEN_PRIMARY_START (NETXEN_BOOTLD_START)
622 #define NETXEN_FLASH_CRBINIT_SIZE (0x4000)
623 #define NETXEN_FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info))
624 #define NETXEN_FLASH_USER_SIZE (sizeof(struct netxen_user_info)/sizeof(u32))
625 #define NETXEN_FLASH_SECONDARY_SIZE (NETXEN_USER_START-NETXEN_SECONDARY_START)
626 #define NETXEN_NUM_PRIMARY_SECTORS (0x20)
627 #define NETXEN_NUM_CONFIG_SECTORS (1)
628 extern char netxen_nic_driver_name[];
629
630 /* Number of status descriptors to handle per interrupt */
631 #define MAX_STATUS_HANDLE (64)
632
633 /*
634 * netxen_skb_frag{} is to contain mapping info for each SG list. This
635 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
636 */
637 struct netxen_skb_frag {
638 u64 dma;
639 u64 length;
640 };
641
642 #define _netxen_set_bits(config_word, start, bits, val) {\
643 unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\
644 unsigned long long __tvalue = (val); \
645 (config_word) &= ~__tmask; \
646 (config_word) |= (((__tvalue) << (start)) & __tmask); \
647 }
648
649 #define _netxen_clear_bits(config_word, start, bits) {\
650 unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start)); \
651 (config_word) &= ~__tmask; \
652 }
653
654 /* Following defines are for the state of the buffers */
655 #define NETXEN_BUFFER_FREE 0
656 #define NETXEN_BUFFER_BUSY 1
657
658 /*
659 * There will be one netxen_buffer per skb packet. These will be
660 * used to save the dma info for pci_unmap_page()
661 */
662 struct netxen_cmd_buffer {
663 struct sk_buff *skb;
664 struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
665 u32 frag_count;
666 };
667
668 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
669 struct netxen_rx_buffer {
670 struct list_head list;
671 struct sk_buff *skb;
672 u64 dma;
673 u16 ref_handle;
674 u16 state;
675 };
676
677 /* Board types */
678 #define NETXEN_NIC_GBE 0x01
679 #define NETXEN_NIC_XGBE 0x02
680
681 /*
682 * One hardware_context{} per adapter
683 * contains interrupt info as well shared hardware info.
684 */
685 struct netxen_hardware_context {
686 void __iomem *pci_base0;
687 void __iomem *pci_base1;
688 void __iomem *pci_base2;
689 void __iomem *db_base;
690 unsigned long db_len;
691 unsigned long pci_len0;
692
693 int qdr_sn_window;
694 int ddr_mn_window;
695 unsigned long mn_win_crb;
696 unsigned long ms_win_crb;
697
698 u8 cut_through;
699 u8 revision_id;
700 u8 pci_func;
701 u8 linkup;
702 u16 port_type;
703 u16 board_type;
704 };
705
706 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
707 #define ETHERNET_FCS_SIZE 4
708
709 struct netxen_adapter_stats {
710 u64 xmitcalled;
711 u64 xmitfinished;
712 u64 rxdropped;
713 u64 txdropped;
714 u64 csummed;
715 u64 no_rcv;
716 u64 rxbytes;
717 u64 txbytes;
718 };
719
720 /*
721 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
722 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
723 */
724 struct nx_host_rds_ring {
725 u32 producer;
726 u32 crb_rcv_producer;
727 u32 num_desc;
728 u32 dma_size;
729 u32 skb_size;
730 u32 flags;
731 struct rcv_desc *desc_head;
732 struct netxen_rx_buffer *rx_buf_arr;
733 struct list_head free_list;
734 spinlock_t lock;
735 dma_addr_t phys_addr;
736 };
737
738 struct nx_host_sds_ring {
739 u32 consumer;
740 u32 crb_sts_consumer;
741 u32 crb_intr_mask;
742 u32 num_desc;
743
744 struct status_desc *desc_head;
745 struct netxen_adapter *adapter;
746 struct napi_struct napi;
747 struct list_head free_list[NUM_RCV_DESC_RINGS];
748
749 int irq;
750
751 dma_addr_t phys_addr;
752 char name[IFNAMSIZ+4];
753 };
754
755 struct nx_host_tx_ring {
756 u32 producer;
757 __le32 *hw_consumer;
758 u32 sw_consumer;
759 u32 crb_cmd_producer;
760 u32 crb_cmd_consumer;
761 u32 num_desc;
762
763 struct netxen_cmd_buffer *cmd_buf_arr;
764 struct cmd_desc_type0 *desc_head;
765 dma_addr_t phys_addr;
766 };
767
768 /*
769 * Receive context. There is one such structure per instance of the
770 * receive processing. Any state information that is relevant to
771 * the receive, and is must be in this structure. The global data may be
772 * present elsewhere.
773 */
774 struct netxen_recv_context {
775 u32 state;
776 u16 context_id;
777 u16 virt_port;
778
779 struct nx_host_rds_ring *rds_rings;
780 struct nx_host_sds_ring *sds_rings;
781
782 struct netxen_ring_ctx *hwctx;
783 dma_addr_t phys_addr;
784 };
785
786 /* New HW context creation */
787
788 #define NX_OS_CRB_RETRY_COUNT 4000
789 #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
790 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
791
792 #define NX_CDRP_CLEAR 0x00000000
793 #define NX_CDRP_CMD_BIT 0x80000000
794
795 /*
796 * All responses must have the NX_CDRP_CMD_BIT cleared
797 * in the crb NX_CDRP_CRB_OFFSET.
798 */
799 #define NX_CDRP_FORM_RSP(rsp) (rsp)
800 #define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0)
801
802 #define NX_CDRP_RSP_OK 0x00000001
803 #define NX_CDRP_RSP_FAIL 0x00000002
804 #define NX_CDRP_RSP_TIMEOUT 0x00000003
805
806 /*
807 * All commands must have the NX_CDRP_CMD_BIT set in
808 * the crb NX_CDRP_CRB_OFFSET.
809 */
810 #define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd))
811 #define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0)
812
813 #define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
814 #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
815 #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
816 #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
817 #define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
818 #define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
819 #define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007
820 #define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008
821 #define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009
822 #define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
823 #define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e
824 #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
825 #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
826 #define NX_CDRP_CMD_SET_MTU 0x00000012
827 #define NX_CDRP_CMD_MAX 0x00000013
828
829 #define NX_RCODE_SUCCESS 0
830 #define NX_RCODE_NO_HOST_MEM 1
831 #define NX_RCODE_NO_HOST_RESOURCE 2
832 #define NX_RCODE_NO_CARD_CRB 3
833 #define NX_RCODE_NO_CARD_MEM 4
834 #define NX_RCODE_NO_CARD_RESOURCE 5
835 #define NX_RCODE_INVALID_ARGS 6
836 #define NX_RCODE_INVALID_ACTION 7
837 #define NX_RCODE_INVALID_STATE 8
838 #define NX_RCODE_NOT_SUPPORTED 9
839 #define NX_RCODE_NOT_PERMITTED 10
840 #define NX_RCODE_NOT_READY 11
841 #define NX_RCODE_DOES_NOT_EXIST 12
842 #define NX_RCODE_ALREADY_EXISTS 13
843 #define NX_RCODE_BAD_SIGNATURE 14
844 #define NX_RCODE_CMD_NOT_IMPL 15
845 #define NX_RCODE_CMD_INVALID 16
846 #define NX_RCODE_TIMEOUT 17
847 #define NX_RCODE_CMD_FAILED 18
848 #define NX_RCODE_MAX_EXCEEDED 19
849 #define NX_RCODE_MAX 20
850
851 #define NX_DESTROY_CTX_RESET 0
852 #define NX_DESTROY_CTX_D3_RESET 1
853 #define NX_DESTROY_CTX_MAX 2
854
855 /*
856 * Capabilities
857 */
858 #define NX_CAP_BIT(class, bit) (1 << bit)
859 #define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0)
860 #define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1)
861 #define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2)
862 #define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3)
863 #define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4)
864 #define NX_CAP0_LRO NX_CAP_BIT(0, 5)
865 #define NX_CAP0_LSO NX_CAP_BIT(0, 6)
866 #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7)
867 #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8)
868
869 /*
870 * Context state
871 */
872 #define NX_HOST_CTX_STATE_FREED 0
873 #define NX_HOST_CTX_STATE_ALLOCATED 1
874 #define NX_HOST_CTX_STATE_ACTIVE 2
875 #define NX_HOST_CTX_STATE_DISABLED 3
876 #define NX_HOST_CTX_STATE_QUIESCED 4
877 #define NX_HOST_CTX_STATE_MAX 5
878
879 /*
880 * Rx context
881 */
882
883 typedef struct {
884 __le64 host_phys_addr; /* Ring base addr */
885 __le32 ring_size; /* Ring entries */
886 __le16 msi_index;
887 __le16 rsvd; /* Padding */
888 } nx_hostrq_sds_ring_t;
889
890 typedef struct {
891 __le64 host_phys_addr; /* Ring base addr */
892 __le64 buff_size; /* Packet buffer size */
893 __le32 ring_size; /* Ring entries */
894 __le32 ring_kind; /* Class of ring */
895 } nx_hostrq_rds_ring_t;
896
897 typedef struct {
898 __le64 host_rsp_dma_addr; /* Response dma'd here */
899 __le32 capabilities[4]; /* Flag bit vector */
900 __le32 host_int_crb_mode; /* Interrupt crb usage */
901 __le32 host_rds_crb_mode; /* RDS crb usage */
902 /* These ring offsets are relative to data[0] below */
903 __le32 rds_ring_offset; /* Offset to RDS config */
904 __le32 sds_ring_offset; /* Offset to SDS config */
905 __le16 num_rds_rings; /* Count of RDS rings */
906 __le16 num_sds_rings; /* Count of SDS rings */
907 __le16 rsvd1; /* Padding */
908 __le16 rsvd2; /* Padding */
909 u8 reserved[128]; /* reserve space for future expansion*/
910 /* MUST BE 64-bit aligned.
911 The following is packed:
912 - N hostrq_rds_rings
913 - N hostrq_sds_rings */
914 char data[0];
915 } nx_hostrq_rx_ctx_t;
916
917 typedef struct {
918 __le32 host_producer_crb; /* Crb to use */
919 __le32 rsvd1; /* Padding */
920 } nx_cardrsp_rds_ring_t;
921
922 typedef struct {
923 __le32 host_consumer_crb; /* Crb to use */
924 __le32 interrupt_crb; /* Crb to use */
925 } nx_cardrsp_sds_ring_t;
926
927 typedef struct {
928 /* These ring offsets are relative to data[0] below */
929 __le32 rds_ring_offset; /* Offset to RDS config */
930 __le32 sds_ring_offset; /* Offset to SDS config */
931 __le32 host_ctx_state; /* Starting State */
932 __le32 num_fn_per_port; /* How many PCI fn share the port */
933 __le16 num_rds_rings; /* Count of RDS rings */
934 __le16 num_sds_rings; /* Count of SDS rings */
935 __le16 context_id; /* Handle for context */
936 u8 phys_port; /* Physical id of port */
937 u8 virt_port; /* Virtual/Logical id of port */
938 u8 reserved[128]; /* save space for future expansion */
939 /* MUST BE 64-bit aligned.
940 The following is packed:
941 - N cardrsp_rds_rings
942 - N cardrs_sds_rings */
943 char data[0];
944 } nx_cardrsp_rx_ctx_t;
945
946 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
947 (sizeof(HOSTRQ_RX) + \
948 (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \
949 (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
950
951 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
952 (sizeof(CARDRSP_RX) + \
953 (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \
954 (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
955
956 /*
957 * Tx context
958 */
959
960 typedef struct {
961 __le64 host_phys_addr; /* Ring base addr */
962 __le32 ring_size; /* Ring entries */
963 __le32 rsvd; /* Padding */
964 } nx_hostrq_cds_ring_t;
965
966 typedef struct {
967 __le64 host_rsp_dma_addr; /* Response dma'd here */
968 __le64 cmd_cons_dma_addr; /* */
969 __le64 dummy_dma_addr; /* */
970 __le32 capabilities[4]; /* Flag bit vector */
971 __le32 host_int_crb_mode; /* Interrupt crb usage */
972 __le32 rsvd1; /* Padding */
973 __le16 rsvd2; /* Padding */
974 __le16 interrupt_ctl;
975 __le16 msi_index;
976 __le16 rsvd3; /* Padding */
977 nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */
978 u8 reserved[128]; /* future expansion */
979 } nx_hostrq_tx_ctx_t;
980
981 typedef struct {
982 __le32 host_producer_crb; /* Crb to use */
983 __le32 interrupt_crb; /* Crb to use */
984 } nx_cardrsp_cds_ring_t;
985
986 typedef struct {
987 __le32 host_ctx_state; /* Starting state */
988 __le16 context_id; /* Handle for context */
989 u8 phys_port; /* Physical id of port */
990 u8 virt_port; /* Virtual/Logical id of port */
991 nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
992 u8 reserved[128]; /* future expansion */
993 } nx_cardrsp_tx_ctx_t;
994
995 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
996 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
997
998 /* CRB */
999
1000 #define NX_HOST_RDS_CRB_MODE_UNIQUE 0
1001 #define NX_HOST_RDS_CRB_MODE_SHARED 1
1002 #define NX_HOST_RDS_CRB_MODE_CUSTOM 2
1003 #define NX_HOST_RDS_CRB_MODE_MAX 3
1004
1005 #define NX_HOST_INT_CRB_MODE_UNIQUE 0
1006 #define NX_HOST_INT_CRB_MODE_SHARED 1
1007 #define NX_HOST_INT_CRB_MODE_NORX 2
1008 #define NX_HOST_INT_CRB_MODE_NOTX 3
1009 #define NX_HOST_INT_CRB_MODE_NORXTX 4
1010
1011
1012 /* MAC */
1013
1014 #define MC_COUNT_P2 16
1015 #define MC_COUNT_P3 38
1016
1017 #define NETXEN_MAC_NOOP 0
1018 #define NETXEN_MAC_ADD 1
1019 #define NETXEN_MAC_DEL 2
1020
1021 typedef struct nx_mac_list_s {
1022 struct list_head list;
1023 uint8_t mac_addr[ETH_ALEN+2];
1024 } nx_mac_list_t;
1025
1026 /*
1027 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
1028 * adjusted based on configured MTU.
1029 */
1030 #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
1031 #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
1032 #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
1033 #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
1034
1035 #define NETXEN_NIC_INTR_DEFAULT 0x04
1036
1037 typedef union {
1038 struct {
1039 uint16_t rx_packets;
1040 uint16_t rx_time_us;
1041 uint16_t tx_packets;
1042 uint16_t tx_time_us;
1043 } data;
1044 uint64_t word;
1045 } nx_nic_intr_coalesce_data_t;
1046
1047 typedef struct {
1048 uint16_t stats_time_us;
1049 uint16_t rate_sample_time;
1050 uint16_t flags;
1051 uint16_t rsvd_1;
1052 uint32_t low_threshold;
1053 uint32_t high_threshold;
1054 nx_nic_intr_coalesce_data_t normal;
1055 nx_nic_intr_coalesce_data_t low;
1056 nx_nic_intr_coalesce_data_t high;
1057 nx_nic_intr_coalesce_data_t irq;
1058 } nx_nic_intr_coalesce_t;
1059
1060 #define NX_HOST_REQUEST 0x13
1061 #define NX_NIC_REQUEST 0x14
1062
1063 #define NX_MAC_EVENT 0x1
1064
1065 /*
1066 * Driver --> Firmware
1067 */
1068 #define NX_NIC_H2C_OPCODE_START 0
1069 #define NX_NIC_H2C_OPCODE_CONFIG_RSS 1
1070 #define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL 2
1071 #define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
1072 #define NX_NIC_H2C_OPCODE_CONFIG_LED 4
1073 #define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
1074 #define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC 6
1075 #define NX_NIC_H2C_OPCODE_LRO_REQUEST 7
1076 #define NX_NIC_H2C_OPCODE_GET_SNMP_STATS 8
1077 #define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST 9
1078 #define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
1079 #define NX_NIC_H2C_OPCODE_PROXY_SET_MTU 11
1080 #define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
1081 #define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
1082 #define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
1083 #define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
1084 #define NX_NIC_H2C_OPCODE_GET_NET_STATS 16
1085 #define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
1086 #define NX_NIC_H2C_OPCODE_CONFIG_IPADDR 18
1087 #define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK 19
1088 #define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE 20
1089 #define NX_NIC_H2C_OPCODE_GET_LINKEVENT 21
1090 #define NX_NIC_C2C_OPCODE 22
1091 #define NX_NIC_H2C_OPCODE_LAST 23
1092
1093 /*
1094 * Firmware --> Driver
1095 */
1096
1097 #define NX_NIC_C2H_OPCODE_START 128
1098 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
1099 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
1100 #define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
1101 #define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
1102 #define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
1103 #define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
1104 #define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
1105 #define NX_NIC_C2H_OPCODE_GET_SNMP_STATS 136
1106 #define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
1107 #define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
1108 #define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
1109 #define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
1110 #define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
1111 #define NX_NIC_C2H_OPCODE_LAST 142
1112
1113 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
1114 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
1115 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
1116
1117 #define NX_FW_CAPABILITY_LINK_NOTIFICATION (1 << 5)
1118 #define NX_FW_CAPABILITY_SWITCHING (1 << 6)
1119
1120 /* module types */
1121 #define LINKEVENT_MODULE_NOT_PRESENT 1
1122 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
1123 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
1124 #define LINKEVENT_MODULE_OPTICAL_LRM 4
1125 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
1126 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
1127 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
1128 #define LINKEVENT_MODULE_TWINAX 8
1129
1130 #define LINKSPEED_10GBPS 10000
1131 #define LINKSPEED_1GBPS 1000
1132 #define LINKSPEED_100MBPS 100
1133 #define LINKSPEED_10MBPS 10
1134
1135 #define LINKSPEED_ENCODED_10MBPS 0
1136 #define LINKSPEED_ENCODED_100MBPS 1
1137 #define LINKSPEED_ENCODED_1GBPS 2
1138
1139 #define LINKEVENT_AUTONEG_DISABLED 0
1140 #define LINKEVENT_AUTONEG_ENABLED 1
1141
1142 #define LINKEVENT_HALF_DUPLEX 0
1143 #define LINKEVENT_FULL_DUPLEX 1
1144
1145 #define LINKEVENT_LINKSPEED_MBPS 0
1146 #define LINKEVENT_LINKSPEED_ENCODED 1
1147
1148 /* firmware response header:
1149 * 63:58 - message type
1150 * 57:56 - owner
1151 * 55:53 - desc count
1152 * 52:48 - reserved
1153 * 47:40 - completion id
1154 * 39:32 - opcode
1155 * 31:16 - error code
1156 * 15:00 - reserved
1157 */
1158 #define netxen_get_nic_msgtype(msg_hdr) \
1159 ((msg_hdr >> 58) & 0x3F)
1160 #define netxen_get_nic_msg_compid(msg_hdr) \
1161 ((msg_hdr >> 40) & 0xFF)
1162 #define netxen_get_nic_msg_opcode(msg_hdr) \
1163 ((msg_hdr >> 32) & 0xFF)
1164 #define netxen_get_nic_msg_errcode(msg_hdr) \
1165 ((msg_hdr >> 16) & 0xFFFF)
1166
1167 typedef struct {
1168 union {
1169 struct {
1170 u64 hdr;
1171 u64 body[7];
1172 };
1173 u64 words[8];
1174 };
1175 } nx_fw_msg_t;
1176
1177 typedef struct {
1178 __le64 qhdr;
1179 __le64 req_hdr;
1180 __le64 words[6];
1181 } nx_nic_req_t;
1182
1183 typedef struct {
1184 u8 op;
1185 u8 tag;
1186 u8 mac_addr[6];
1187 } nx_mac_req_t;
1188
1189 #define MAX_PENDING_DESC_BLOCK_SIZE 64
1190
1191 #define NETXEN_NIC_MSI_ENABLED 0x02
1192 #define NETXEN_NIC_MSIX_ENABLED 0x04
1193 #define NETXEN_IS_MSI_FAMILY(adapter) \
1194 ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
1195
1196 #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
1197 #define NETXEN_MSIX_TBL_SPACE 8192
1198 #define NETXEN_PCI_REG_MSIX_TBL 0x44
1199
1200 #define NETXEN_DB_MAPSIZE_BYTES 0x1000
1201
1202 #define NETXEN_NETDEV_WEIGHT 128
1203 #define NETXEN_ADAPTER_UP_MAGIC 777
1204 #define NETXEN_NIC_PEG_TUNE 0
1205
1206 struct netxen_dummy_dma {
1207 void *addr;
1208 dma_addr_t phys_addr;
1209 };
1210
1211 struct netxen_adapter {
1212 struct netxen_hardware_context ahw;
1213
1214 struct net_device *netdev;
1215 struct pci_dev *pdev;
1216 struct list_head mac_list;
1217
1218 u32 curr_window;
1219 u32 crb_win;
1220 rwlock_t adapter_lock;
1221
1222 spinlock_t tx_clean_lock;
1223
1224 u16 num_txd;
1225 u16 num_rxd;
1226 u16 num_jumbo_rxd;
1227 u16 num_lro_rxd;
1228
1229 u8 max_rds_rings;
1230 u8 max_sds_rings;
1231 u8 driver_mismatch;
1232 u8 msix_supported;
1233 u8 rx_csum;
1234 u8 pci_using_dac;
1235 u8 portnum;
1236 u8 physical_port;
1237
1238 u8 mc_enabled;
1239 u8 max_mc_count;
1240 u8 rss_supported;
1241 u8 resv2;
1242 u32 resv3;
1243
1244 u8 has_link_events;
1245 u8 resv1;
1246 u16 tx_context_id;
1247 u16 mtu;
1248 u16 is_up;
1249
1250 u16 link_speed;
1251 u16 link_duplex;
1252 u16 link_autoneg;
1253 u16 module_type;
1254
1255 u32 capabilities;
1256 u32 flags;
1257 u32 irq;
1258 u32 temp;
1259
1260 struct netxen_adapter_stats stats;
1261
1262 struct netxen_recv_context recv_ctx;
1263 struct nx_host_tx_ring *tx_ring;
1264
1265 int (*enable_phy_interrupts) (struct netxen_adapter *);
1266 int (*disable_phy_interrupts) (struct netxen_adapter *);
1267 int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t);
1268 int (*set_mtu) (struct netxen_adapter *, int);
1269 int (*set_promisc) (struct netxen_adapter *, u32);
1270 int (*phy_read) (struct netxen_adapter *, long reg, u32 *);
1271 int (*phy_write) (struct netxen_adapter *, long reg, u32 val);
1272 int (*init_port) (struct netxen_adapter *, int);
1273 int (*stop_port) (struct netxen_adapter *);
1274
1275 u32 (*hw_read_wx)(struct netxen_adapter *, ulong);
1276 int (*hw_write_wx)(struct netxen_adapter *, ulong, u32);
1277 int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int);
1278 int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int);
1279 int (*pci_write_immediate)(struct netxen_adapter *, u64, u32);
1280 u32 (*pci_read_immediate)(struct netxen_adapter *, u64);
1281 unsigned long (*pci_set_window)(struct netxen_adapter *,
1282 unsigned long long);
1283
1284 struct netxen_legacy_intr_set legacy_intr;
1285
1286 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1287
1288 struct netxen_dummy_dma dummy_dma;
1289
1290 struct work_struct watchdog_task;
1291 struct timer_list watchdog_timer;
1292 struct work_struct tx_timeout_task;
1293
1294 struct net_device_stats net_stats;
1295
1296 nx_nic_intr_coalesce_t coal;
1297
1298 u32 fw_major;
1299 u32 fw_version;
1300 const struct firmware *fw;
1301 };
1302
1303 /*
1304 * NetXen dma watchdog control structure
1305 *
1306 * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
1307 * Bit 1 : disable_request => 1 req disable dma watchdog
1308 * Bit 2 : enable_request => 1 req enable dma watchdog
1309 * Bit 3-31 : unused
1310 */
1311
1312 #define netxen_set_dma_watchdog_disable_req(config_word) \
1313 _netxen_set_bits(config_word, 1, 1, 1)
1314 #define netxen_set_dma_watchdog_enable_req(config_word) \
1315 _netxen_set_bits(config_word, 2, 1, 1)
1316 #define netxen_get_dma_watchdog_enabled(config_word) \
1317 ((config_word) & 0x1)
1318 #define netxen_get_dma_watchdog_disabled(config_word) \
1319 (((config_word) >> 1) & 0x1)
1320
1321 int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1322 int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1323 int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1324 int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1325 int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
1326 __u32 * readval);
1327 int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
1328 long reg, __u32 val);
1329
1330 /* Functions available from netxen_nic_hw.c */
1331 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
1332 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
1333
1334 #define NXRD32(adapter, off) \
1335 (adapter->hw_read_wx(adapter, off))
1336 #define NXWR32(adapter, off, val) \
1337 (adapter->hw_write_wx(adapter, off, val))
1338
1339 int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1340 void netxen_nic_get_firmware_info(struct netxen_adapter *adapter);
1341 int netxen_nic_wol_supported(struct netxen_adapter *adapter);
1342
1343 u32 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off);
1344 int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1345 ulong off, u32 data);
1346 int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1347 u64 off, void *data, int size);
1348 int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1349 u64 off, void *data, int size);
1350 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1351 u64 off, u32 data);
1352 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off);
1353 void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1354 u64 off, u32 data);
1355 u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off);
1356 unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1357 unsigned long long addr);
1358 void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter,
1359 u32 wndw);
1360
1361 u32 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off);
1362 int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1363 ulong off, u32 data);
1364 int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1365 u64 off, void *data, int size);
1366 int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1367 u64 off, void *data, int size);
1368 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1369 u64 off, u32 data);
1370 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off);
1371 void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1372 u64 off, u32 data);
1373 u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off);
1374 unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1375 unsigned long long addr);
1376
1377 /* Functions from netxen_nic_init.c */
1378 void netxen_free_adapter_offload(struct netxen_adapter *adapter);
1379 int netxen_initialize_adapter_offload(struct netxen_adapter *adapter);
1380 int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1381 int netxen_load_firmware(struct netxen_adapter *adapter);
1382 void netxen_request_firmware(struct netxen_adapter *adapter);
1383 void netxen_release_firmware(struct netxen_adapter *adapter);
1384 int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
1385
1386 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1387 int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1388 u8 *bytes, size_t size);
1389 int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1390 u8 *bytes, size_t size);
1391 int netxen_flash_unlock(struct netxen_adapter *adapter);
1392 int netxen_backup_crbinit(struct netxen_adapter *adapter);
1393 int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1394 int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1395 void netxen_halt_pegs(struct netxen_adapter *adapter);
1396
1397 int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1398
1399 int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
1400 void netxen_free_sw_resources(struct netxen_adapter *adapter);
1401
1402 int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
1403 void netxen_free_hw_resources(struct netxen_adapter *adapter);
1404
1405 void netxen_release_rx_buffers(struct netxen_adapter *adapter);
1406 void netxen_release_tx_buffers(struct netxen_adapter *adapter);
1407
1408 void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
1409 int netxen_init_firmware(struct netxen_adapter *adapter);
1410 void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1411 void netxen_watchdog_task(struct work_struct *work);
1412 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1413 struct nx_host_rds_ring *rds_ring);
1414 int netxen_process_cmd_ring(struct netxen_adapter *adapter);
1415 int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max);
1416 void netxen_p2_nic_set_multi(struct net_device *netdev);
1417 void netxen_p3_nic_set_multi(struct net_device *netdev);
1418 void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
1419 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32);
1420 int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
1421 int netxen_config_rss(struct netxen_adapter *adapter, int enable);
1422 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable);
1423 void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup);
1424
1425 int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
1426 int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1427
1428 int netxen_nic_set_mac(struct net_device *netdev, void *p);
1429 struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
1430
1431 void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1432 struct nx_host_tx_ring *tx_ring, uint32_t crb_producer);
1433
1434 /*
1435 * NetXen Board information
1436 */
1437
1438 #define NETXEN_MAX_SHORT_NAME 32
1439 struct netxen_brdinfo {
1440 int brdtype; /* type of board */
1441 long ports; /* max no of physical ports */
1442 char short_name[NETXEN_MAX_SHORT_NAME];
1443 };
1444
1445 static const struct netxen_brdinfo netxen_boards[] = {
1446 {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1447 {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1448 {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1449 {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1450 {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1451 {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1452 {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "},
1453 {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"},
1454 {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"},
1455 {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"},
1456 {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"},
1457 {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1458 {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1459 {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"},
1460 {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
1461 {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
1462 {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
1463 {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1464 {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1465 };
1466
1467 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1468
1469 static inline void get_brd_name_by_type(u32 type, char *name)
1470 {
1471 int i, found = 0;
1472 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1473 if (netxen_boards[i].brdtype == type) {
1474 strcpy(name, netxen_boards[i].short_name);
1475 found = 1;
1476 break;
1477 }
1478
1479 }
1480 if (!found)
1481 name = "Unknown";
1482 }
1483
1484 static inline int
1485 dma_watchdog_shutdown_request(struct netxen_adapter *adapter)
1486 {
1487 u32 ctrl;
1488
1489 /* check if already inactive */
1490 ctrl = adapter->hw_read_wx(adapter,
1491 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL));
1492
1493 if (netxen_get_dma_watchdog_enabled(ctrl) == 0)
1494 return 1;
1495
1496 /* Send the disable request */
1497 netxen_set_dma_watchdog_disable_req(ctrl);
1498 NXWR32(adapter, NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1499
1500 return 0;
1501 }
1502
1503 static inline int
1504 dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter)
1505 {
1506 u32 ctrl;
1507
1508 ctrl = adapter->hw_read_wx(adapter,
1509 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL));
1510
1511 return (netxen_get_dma_watchdog_enabled(ctrl) == 0);
1512 }
1513
1514 static inline int
1515 dma_watchdog_wakeup(struct netxen_adapter *adapter)
1516 {
1517 u32 ctrl;
1518
1519 ctrl = adapter->hw_read_wx(adapter,
1520 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL));
1521
1522 if (netxen_get_dma_watchdog_enabled(ctrl))
1523 return 1;
1524
1525 /* send the wakeup request */
1526 netxen_set_dma_watchdog_enable_req(ctrl);
1527
1528 NXWR32(adapter, NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1529
1530 return 0;
1531 }
1532
1533
1534 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1535 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1536 extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1537 extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1538 int *valp);
1539
1540 extern struct ethtool_ops netxen_nic_ethtool_ops;
1541
1542 #endif /* __NETXEN_NIC_H_ */
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