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vxlan: Fix to enable UDP checksums on interface
[linux-2.6/btrfs-unstable.git] / arch / tile / kernel / pci_gx.c
blobe39f9c542807c0cae9e329c4641e6c9429c263f1
1 /*
2 * Copyright 2012 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/mmzone.h>
17 #include <linux/pci.h>
18 #include <linux/delay.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/capability.h>
22 #include <linux/sched.h>
23 #include <linux/errno.h>
24 #include <linux/irq.h>
25 #include <linux/msi.h>
26 #include <linux/io.h>
27 #include <linux/uaccess.h>
28 #include <linux/ctype.h>
29
30 #include <asm/processor.h>
31 #include <asm/sections.h>
32 #include <asm/byteorder.h>
33
34 #include <gxio/iorpc_globals.h>
35 #include <gxio/kiorpc.h>
36 #include <gxio/trio.h>
37 #include <gxio/iorpc_trio.h>
38 #include <hv/drv_trio_intf.h>
39
40 #include <arch/sim.h>
41
42 /*
43 * This file containes the routines to search for PCI buses,
44 * enumerate the buses, and configure any attached devices.
45 */
46
47 #define DEBUG_PCI_CFG 0
48
49 #if DEBUG_PCI_CFG
50 #define TRACE_CFG_WR(size, val, bus, dev, func, offset) \
51 pr_info("CFG WR %d-byte VAL %#x to bus %d dev %d func %d addr %u\n", \
52 size, val, bus, dev, func, offset & 0xFFF);
53 #define TRACE_CFG_RD(size, val, bus, dev, func, offset) \
54 pr_info("CFG RD %d-byte VAL %#x from bus %d dev %d func %d addr %u\n", \
55 size, val, bus, dev, func, offset & 0xFFF);
56 #else
57 #define TRACE_CFG_WR(...)
58 #define TRACE_CFG_RD(...)
59 #endif
60
61 static int pci_probe = 1;
62
63 /* Information on the PCIe RC ports configuration. */
64 static int pcie_rc[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES];
65
66 /*
67 * On some platforms with one or more Gx endpoint ports, we need to
68 * delay the PCIe RC port probe for a few seconds to work around
69 * a HW PCIe link-training bug. The exact delay is specified with
70 * a kernel boot argument in the form of "pcie_rc_delay=T,P,S",
71 * where T is the TRIO instance number, P is the port number and S is
72 * the delay in seconds. If the argument is specified, but the delay is
73 * not provided, the value will be DEFAULT_RC_DELAY.
74 */
75 static int rc_delay[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES];
76
77 /* Default number of seconds that the PCIe RC port probe can be delayed. */
78 #define DEFAULT_RC_DELAY 10
79
80 /* The PCI I/O space size in each PCI domain. */
81 #define IO_SPACE_SIZE 0x10000
82
83 /* Provide shorter versions of some very long constant names. */
84 #define AUTO_CONFIG_RC \
85 TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC
86 #define AUTO_CONFIG_RC_G1 \
87 TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC_G1
88 #define AUTO_CONFIG_EP \
89 TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT
90 #define AUTO_CONFIG_EP_G1 \
91 TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT_G1
92
93 /* Array of the PCIe ports configuration info obtained from the BIB. */
94 struct pcie_trio_ports_property pcie_ports[TILEGX_NUM_TRIO];
95
96 /* Number of configured TRIO instances. */
97 int num_trio_shims;
98
99 /* All drivers share the TRIO contexts defined here. */
100 gxio_trio_context_t trio_contexts[TILEGX_NUM_TRIO];
101
102 /* Pointer to an array of PCIe RC controllers. */
103 struct pci_controller pci_controllers[TILEGX_NUM_TRIO * TILEGX_TRIO_PCIES];
104 int num_rc_controllers;
105
106 static struct pci_ops tile_cfg_ops;
107
108 /* Mask of CPUs that should receive PCIe interrupts. */
109 static struct cpumask intr_cpus_map;
110
111 /* We don't need to worry about the alignment of resources. */
112 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
113 resource_size_t size,
114 resource_size_t align)
115 {
116 return res->start;
117 }
118 EXPORT_SYMBOL(pcibios_align_resource);
119
120 /*
121 * Pick a CPU to receive and handle the PCIe interrupts, based on the IRQ #.
122 * For now, we simply send interrupts to non-dataplane CPUs.
123 * We may implement methods to allow user to specify the target CPUs,
124 * e.g. via boot arguments.
125 */
126 static int tile_irq_cpu(int irq)
127 {
128 unsigned int count;
129 int i = 0;
130 int cpu;
131
132 count = cpumask_weight(&intr_cpus_map);
133 if (unlikely(count == 0)) {
134 pr_warning("intr_cpus_map empty, interrupts will be"
135 " delievered to dataplane tiles\n");
136 return irq % (smp_height * smp_width);
137 }
138
139 count = irq % count;
140 for_each_cpu(cpu, &intr_cpus_map) {
141 if (i++ == count)
142 break;
143 }
144 return cpu;
145 }
146
147 /* Open a file descriptor to the TRIO shim. */
148 static int tile_pcie_open(int trio_index)
149 {
150 gxio_trio_context_t *context = &trio_contexts[trio_index];
151 int ret;
152 int mac;
153
154 /* This opens a file descriptor to the TRIO shim. */
155 ret = gxio_trio_init(context, trio_index);
156 if (ret < 0)
157 goto gxio_trio_init_failure;
158
159 /* Allocate an ASID for the kernel. */
160 ret = gxio_trio_alloc_asids(context, 1, 0, 0);
161 if (ret < 0) {
162 pr_err("PCI: ASID alloc failure on TRIO %d, give up\n",
163 trio_index);
164 goto asid_alloc_failure;
165 }
166
167 context->asid = ret;
168
169 #ifdef USE_SHARED_PCIE_CONFIG_REGION
170 /*
171 * Alloc a PIO region for config access, shared by all MACs per TRIO.
172 * This shouldn't fail since the kernel is supposed to the first
173 * client of the TRIO's PIO regions.
174 */
175 ret = gxio_trio_alloc_pio_regions(context, 1, 0, 0);
176 if (ret < 0) {
177 pr_err("PCI: CFG PIO alloc failure on TRIO %d, give up\n",
178 trio_index);
179 goto pio_alloc_failure;
180 }
181
182 context->pio_cfg_index = ret;
183
184 /*
185 * For PIO CFG, the bus_address_hi parameter is 0. The mac parameter
186 * is also 0 because it is specified in PIO_REGION_SETUP_CFG_ADDR.
187 */
188 ret = gxio_trio_init_pio_region_aux(context, context->pio_cfg_index,
189 0, 0, HV_TRIO_PIO_FLAG_CONFIG_SPACE);
190 if (ret < 0) {
191 pr_err("PCI: CFG PIO init failure on TRIO %d, give up\n",
192 trio_index);
193 goto pio_alloc_failure;
194 }
195 #endif
196
197 /* Get the properties of the PCIe ports on this TRIO instance. */
198 ret = gxio_trio_get_port_property(context, &pcie_ports[trio_index]);
199 if (ret < 0) {
200 pr_err("PCI: PCIE_GET_PORT_PROPERTY failure, error %d,"
201 " on TRIO %d\n", ret, trio_index);
202 goto get_port_property_failure;
203 }
204
205 context->mmio_base_mac =
206 iorpc_ioremap(context->fd, 0, HV_TRIO_CONFIG_IOREMAP_SIZE);
207 if (context->mmio_base_mac == NULL) {
208 pr_err("PCI: TRIO config space mapping failure, error %d,"
209 " on TRIO %d\n", ret, trio_index);
210 ret = -ENOMEM;
211
212 goto trio_mmio_mapping_failure;
213 }
214
215 /* Check the port strap state which will override the BIB setting. */
216 for (mac = 0; mac < TILEGX_TRIO_PCIES; mac++) {
217 TRIO_PCIE_INTFC_PORT_CONFIG_t port_config;
218 unsigned int reg_offset;
219
220 /* Ignore ports that are not specified in the BIB. */
221 if (!pcie_ports[trio_index].ports[mac].allow_rc &&
222 !pcie_ports[trio_index].ports[mac].allow_ep)
223 continue;
224
225 reg_offset =
226 (TRIO_PCIE_INTFC_PORT_CONFIG <<
227 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
228 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
229 TRIO_CFG_REGION_ADDR__INTFC_SHIFT) |
230 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
231
232 port_config.word =
233 __gxio_mmio_read(context->mmio_base_mac + reg_offset);
234
235 if (port_config.strap_state != AUTO_CONFIG_RC &&
236 port_config.strap_state != AUTO_CONFIG_RC_G1) {
237 /*
238 * If this is really intended to be an EP port, record
239 * it so that the endpoint driver will know about it.
240 */
241 if (port_config.strap_state == AUTO_CONFIG_EP ||
242 port_config.strap_state == AUTO_CONFIG_EP_G1)
243 pcie_ports[trio_index].ports[mac].allow_ep = 1;
244 }
245 }
246
247 return ret;
248
249 trio_mmio_mapping_failure:
250 get_port_property_failure:
251 asid_alloc_failure:
252 #ifdef USE_SHARED_PCIE_CONFIG_REGION
253 pio_alloc_failure:
254 #endif
255 hv_dev_close(context->fd);
256 gxio_trio_init_failure:
257 context->fd = -1;
258
259 return ret;
260 }
261
262 static int __init tile_trio_init(void)
263 {
264 int i;
265
266 /* We loop over all the TRIO shims. */
267 for (i = 0; i < TILEGX_NUM_TRIO; i++) {
268 if (tile_pcie_open(i) < 0)
269 continue;
270 num_trio_shims++;
271 }
272
273 return 0;
274 }
275 postcore_initcall(tile_trio_init);
276
277 static void tilegx_legacy_irq_ack(struct irq_data *d)
278 {
279 __insn_mtspr(SPR_IPI_EVENT_RESET_K, 1UL << d->irq);
280 }
281
282 static void tilegx_legacy_irq_mask(struct irq_data *d)
283 {
284 __insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq);
285 }
286
287 static void tilegx_legacy_irq_unmask(struct irq_data *d)
288 {
289 __insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq);
290 }
291
292 static struct irq_chip tilegx_legacy_irq_chip = {
293 .name = "tilegx_legacy_irq",
294 .irq_ack = tilegx_legacy_irq_ack,
295 .irq_mask = tilegx_legacy_irq_mask,
296 .irq_unmask = tilegx_legacy_irq_unmask,
297
298 /* TBD: support set_affinity. */
299 };
300
301 /*
302 * This is a wrapper function of the kernel level-trigger interrupt
303 * handler handle_level_irq() for PCI legacy interrupts. The TRIO
304 * is configured such that only INTx Assert interrupts are proxied
305 * to Linux which just calls handle_level_irq() after clearing the
306 * MAC INTx Assert status bit associated with this interrupt.
307 */
308 static void trio_handle_level_irq(unsigned int irq, struct irq_desc *desc)
309 {
310 struct pci_controller *controller = irq_desc_get_handler_data(desc);
311 gxio_trio_context_t *trio_context = controller->trio;
312 uint64_t intx = (uint64_t)irq_desc_get_chip_data(desc);
313 int mac = controller->mac;
314 unsigned int reg_offset;
315 uint64_t level_mask;
316
317 handle_level_irq(irq, desc);
318
319 /*
320 * Clear the INTx Level status, otherwise future interrupts are
321 * not sent.
322 */
323 reg_offset = (TRIO_PCIE_INTFC_MAC_INT_STS <<
324 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
325 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
326 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
327 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
328
329 level_mask = TRIO_PCIE_INTFC_MAC_INT_STS__INT_LEVEL_MASK << intx;
330
331 __gxio_mmio_write(trio_context->mmio_base_mac + reg_offset, level_mask);
332 }
333
334 /*
335 * Create kernel irqs and set up the handlers for the legacy interrupts.
336 * Also some minimum initialization for the MSI support.
337 */
338 static int tile_init_irqs(struct pci_controller *controller)
339 {
340 int i;
341 int j;
342 int irq;
343 int result;
344
345 cpumask_copy(&intr_cpus_map, cpu_online_mask);
346
347
348 for (i = 0; i < 4; i++) {
349 gxio_trio_context_t *context = controller->trio;
350 int cpu;
351
352 /* Ask the kernel to allocate an IRQ. */
353 irq = irq_alloc_hwirq(-1);
354 if (!irq) {
355 pr_err("PCI: no free irq vectors, failed for %d\n", i);
356 goto free_irqs;
357 }
358 controller->irq_intx_table[i] = irq;
359
360 /* Distribute the 4 IRQs to different tiles. */
361 cpu = tile_irq_cpu(irq);
362
363 /* Configure the TRIO intr binding for this IRQ. */
364 result = gxio_trio_config_legacy_intr(context, cpu_x(cpu),
365 cpu_y(cpu), KERNEL_PL,
366 irq, controller->mac, i);
367 if (result < 0) {
368 pr_err("PCI: MAC intx config failed for %d\n", i);
369
370 goto free_irqs;
371 }
372
373 /* Register the IRQ handler with the kernel. */
374 irq_set_chip_and_handler(irq, &tilegx_legacy_irq_chip,
375 trio_handle_level_irq);
376 irq_set_chip_data(irq, (void *)(uint64_t)i);
377 irq_set_handler_data(irq, controller);
378 }
379
380 return 0;
381
382 free_irqs:
383 for (j = 0; j < i; j++)
384 irq_free_hwirq(controller->irq_intx_table[j]);
385
386 return -1;
387 }
388
389 /*
390 * Return 1 if the port is strapped to operate in RC mode.
391 */
392 static int
393 strapped_for_rc(gxio_trio_context_t *trio_context, int mac)
394 {
395 TRIO_PCIE_INTFC_PORT_CONFIG_t port_config;
396 unsigned int reg_offset;
397
398 /* Check the port configuration. */
399 reg_offset =
400 (TRIO_PCIE_INTFC_PORT_CONFIG <<
401 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
402 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
403 TRIO_CFG_REGION_ADDR__INTFC_SHIFT) |
404 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
405 port_config.word =
406 __gxio_mmio_read(trio_context->mmio_base_mac + reg_offset);
407
408 if (port_config.strap_state == AUTO_CONFIG_RC ||
409 port_config.strap_state == AUTO_CONFIG_RC_G1)
410 return 1;
411 else
412 return 0;
413 }
414
415 /*
416 * Find valid controllers and fill in pci_controller structs for each
417 * of them.
418 *
419 * Return the number of controllers discovered.
420 */
421 int __init tile_pci_init(void)
422 {
423 int ctl_index = 0;
424 int i, j;
425
426 if (!pci_probe) {
427 pr_info("PCI: disabled by boot argument\n");
428 return 0;
429 }
430
431 pr_info("PCI: Searching for controllers...\n");
432
433 if (num_trio_shims == 0 || sim_is_simulator())
434 return 0;
435
436 /*
437 * Now determine which PCIe ports are configured to operate in RC
438 * mode. There is a differece in the port configuration capability
439 * between the Gx36 and Gx72 devices.
440 *
441 * The Gx36 has configuration capability for each of the 3 PCIe
442 * interfaces (disable, auto endpoint, auto RC, etc.).
443 * On the Gx72, you can only select one of the 3 PCIe interfaces per
444 * TRIO to train automatically. Further, the allowable training modes
445 * are reduced to four options (auto endpoint, auto RC, stream x1,
446 * stream x4).
447 *
448 * For Gx36 ports, it must be allowed to be in RC mode by the
449 * Board Information Block, and the hardware strapping pins must be
450 * set to RC mode.
451 *
452 * For Gx72 ports, the port will operate in RC mode if either of the
453 * following is true:
454 * 1. It is allowed to be in RC mode by the Board Information Block,
455 * and the BIB doesn't allow the EP mode.
456 * 2. It is allowed to be in either the RC or the EP mode by the BIB,
457 * and the hardware strapping pin is set to RC mode.
458 */
459 for (i = 0; i < TILEGX_NUM_TRIO; i++) {
460 gxio_trio_context_t *context = &trio_contexts[i];
461
462 if (context->fd < 0)
463 continue;
464
465 for (j = 0; j < TILEGX_TRIO_PCIES; j++) {
466 int is_rc = 0;
467
468 if (pcie_ports[i].is_gx72 &&
469 pcie_ports[i].ports[j].allow_rc) {
470 if (!pcie_ports[i].ports[j].allow_ep ||
471 strapped_for_rc(context, j))
472 is_rc = 1;
473 } else if (pcie_ports[i].ports[j].allow_rc &&
474 strapped_for_rc(context, j)) {
475 is_rc = 1;
476 }
477 if (is_rc) {
478 pcie_rc[i][j] = 1;
479 num_rc_controllers++;
480 }
481 }
482 }
483
484 /* Return if no PCIe ports are configured to operate in RC mode. */
485 if (num_rc_controllers == 0)
486 return 0;
487
488 /* Set the TRIO pointer and MAC index for each PCIe RC port. */
489 for (i = 0; i < TILEGX_NUM_TRIO; i++) {
490 for (j = 0; j < TILEGX_TRIO_PCIES; j++) {
491 if (pcie_rc[i][j]) {
492 pci_controllers[ctl_index].trio =
493 &trio_contexts[i];
494 pci_controllers[ctl_index].mac = j;
495 pci_controllers[ctl_index].trio_index = i;
496 ctl_index++;
497 if (ctl_index == num_rc_controllers)
498 goto out;
499 }
500 }
501 }
502
503 out:
504 /* Configure each PCIe RC port. */
505 for (i = 0; i < num_rc_controllers; i++) {
506
507 /* Configure the PCIe MAC to run in RC mode. */
508 struct pci_controller *controller = &pci_controllers[i];
509
510 controller->index = i;
511 controller->ops = &tile_cfg_ops;
512
513 controller->io_space.start = PCIBIOS_MIN_IO +
514 (i * IO_SPACE_SIZE);
515 controller->io_space.end = controller->io_space.start +
516 IO_SPACE_SIZE - 1;
517 BUG_ON(controller->io_space.end > IO_SPACE_LIMIT);
518 controller->io_space.flags = IORESOURCE_IO;
519 snprintf(controller->io_space_name,
520 sizeof(controller->io_space_name),
521 "PCI I/O domain %d", i);
522 controller->io_space.name = controller->io_space_name;
523
524 /*
525 * The PCI memory resource is located above the PA space.
526 * For every host bridge, the BAR window or the MMIO aperture
527 * is in range [3GB, 4GB - 1] of a 4GB space beyond the
528 * PA space.
529 */
530 controller->mem_offset = TILE_PCI_MEM_START +
531 (i * TILE_PCI_BAR_WINDOW_TOP);
532 controller->mem_space.start = controller->mem_offset +
533 TILE_PCI_BAR_WINDOW_TOP - TILE_PCI_BAR_WINDOW_SIZE;
534 controller->mem_space.end = controller->mem_offset +
535 TILE_PCI_BAR_WINDOW_TOP - 1;
536 controller->mem_space.flags = IORESOURCE_MEM;
537 snprintf(controller->mem_space_name,
538 sizeof(controller->mem_space_name),
539 "PCI mem domain %d", i);
540 controller->mem_space.name = controller->mem_space_name;
541 }
542
543 return num_rc_controllers;
544 }
545
546 /*
547 * (pin - 1) converts from the PCI standard's [1:4] convention to
548 * a normal [0:3] range.
549 */
550 static int tile_map_irq(const struct pci_dev *dev, u8 device, u8 pin)
551 {
552 struct pci_controller *controller =
553 (struct pci_controller *)dev->sysdata;
554 return controller->irq_intx_table[pin - 1];
555 }
556
557 static void fixup_read_and_payload_sizes(struct pci_controller *controller)
558 {
559 gxio_trio_context_t *trio_context = controller->trio;
560 struct pci_bus *root_bus = controller->root_bus;
561 TRIO_PCIE_RC_DEVICE_CONTROL_t dev_control;
562 TRIO_PCIE_RC_DEVICE_CAP_t rc_dev_cap;
563 unsigned int reg_offset;
564 struct pci_bus *child;
565 int mac;
566 int err;
567
568 mac = controller->mac;
569
570 /* Set our max read request size to be 4KB. */
571 reg_offset =
572 (TRIO_PCIE_RC_DEVICE_CONTROL <<
573 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
574 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
575 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
576 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
577
578 dev_control.word = __gxio_mmio_read32(trio_context->mmio_base_mac +
579 reg_offset);
580 dev_control.max_read_req_sz = 5;
581 __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,
582 dev_control.word);
583
584 /*
585 * Set the max payload size supported by this Gx PCIe MAC.
586 * Though Gx PCIe supports Max Payload Size of up to 1024 bytes,
587 * experiments have shown that setting MPS to 256 yields the
588 * best performance.
589 */
590 reg_offset =
591 (TRIO_PCIE_RC_DEVICE_CAP <<
592 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
593 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
594 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
595 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
596
597 rc_dev_cap.word = __gxio_mmio_read32(trio_context->mmio_base_mac +
598 reg_offset);
599 rc_dev_cap.mps_sup = 1;
600 __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,
601 rc_dev_cap.word);
602
603 /* Configure PCI Express MPS setting. */
604 list_for_each_entry(child, &root_bus->children, node)
605 pcie_bus_configure_settings(child);
606
607 /*
608 * Set the mac_config register in trio based on the MPS/MRS of the link.
609 */
610 reg_offset =
611 (TRIO_PCIE_RC_DEVICE_CONTROL <<
612 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
613 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
614 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
615 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
616
617 dev_control.word = __gxio_mmio_read32(trio_context->mmio_base_mac +
618 reg_offset);
619
620 err = gxio_trio_set_mps_mrs(trio_context,
621 dev_control.max_payload_size,
622 dev_control.max_read_req_sz,
623 mac);
624 if (err < 0) {
625 pr_err("PCI: PCIE_CONFIGURE_MAC_MPS_MRS failure, "
626 "MAC %d on TRIO %d\n",
627 mac, controller->trio_index);
628 }
629 }
630
631 static int setup_pcie_rc_delay(char *str)
632 {
633 unsigned long delay = 0;
634 unsigned long trio_index;
635 unsigned long mac;
636
637 if (str == NULL || !isdigit(*str))
638 return -EINVAL;
639 trio_index = simple_strtoul(str, (char **)&str, 10);
640 if (trio_index >= TILEGX_NUM_TRIO)
641 return -EINVAL;
642
643 if (*str != ',')
644 return -EINVAL;
645
646 str++;
647 if (!isdigit(*str))
648 return -EINVAL;
649 mac = simple_strtoul(str, (char **)&str, 10);
650 if (mac >= TILEGX_TRIO_PCIES)
651 return -EINVAL;
652
653 if (*str != '\0') {
654 if (*str != ',')
655 return -EINVAL;
656
657 str++;
658 if (!isdigit(*str))
659 return -EINVAL;
660 delay = simple_strtoul(str, (char **)&str, 10);
661 }
662
663 rc_delay[trio_index][mac] = delay ? : DEFAULT_RC_DELAY;
664 return 0;
665 }
666 early_param("pcie_rc_delay", setup_pcie_rc_delay);
667
668 /* PCI initialization entry point, called by subsys_initcall. */
669 int __init pcibios_init(void)
670 {
671 resource_size_t offset;
672 LIST_HEAD(resources);
673 int next_busno;
674 int i;
675
676 tile_pci_init();
677
678 if (num_rc_controllers == 0)
679 return 0;
680
681 /*
682 * Delay a bit in case devices aren't ready. Some devices are
683 * known to require at least 20ms here, but we use a more
684 * conservative value.
685 */
686 msleep(250);
687
688 /* Scan all of the recorded PCI controllers. */
689 for (next_busno = 0, i = 0; i < num_rc_controllers; i++) {
690 struct pci_controller *controller = &pci_controllers[i];
691 gxio_trio_context_t *trio_context = controller->trio;
692 TRIO_PCIE_INTFC_PORT_STATUS_t port_status;
693 TRIO_PCIE_INTFC_TX_FIFO_CTL_t tx_fifo_ctl;
694 struct pci_bus *bus;
695 unsigned int reg_offset;
696 unsigned int class_code_revision;
697 int trio_index;
698 int mac;
699 int ret;
700
701 if (trio_context->fd < 0)
702 continue;
703
704 trio_index = controller->trio_index;
705 mac = controller->mac;
706
707 /*
708 * Check for PCIe link-up status to decide if we need
709 * to force the link to come up.
710 */
711 reg_offset =
712 (TRIO_PCIE_INTFC_PORT_STATUS <<
713 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
714 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
715 TRIO_CFG_REGION_ADDR__INTFC_SHIFT) |
716 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
717
718 port_status.word =
719 __gxio_mmio_read(trio_context->mmio_base_mac +
720 reg_offset);
721 if (!port_status.dl_up) {
722 if (rc_delay[trio_index][mac]) {
723 pr_info("Delaying PCIe RC TRIO init %d sec"
724 " on MAC %d on TRIO %d\n",
725 rc_delay[trio_index][mac], mac,
726 trio_index);
727 msleep(rc_delay[trio_index][mac] * 1000);
728 }
729 ret = gxio_trio_force_rc_link_up(trio_context, mac);
730 if (ret < 0)
731 pr_err("PCI: PCIE_FORCE_LINK_UP failure, "
732 "MAC %d on TRIO %d\n", mac, trio_index);
733 }
734
735 pr_info("PCI: Found PCI controller #%d on TRIO %d MAC %d\n", i,
736 trio_index, controller->mac);
737
738 /* Delay the bus probe if needed. */
739 if (rc_delay[trio_index][mac]) {
740 pr_info("Delaying PCIe RC bus enumerating %d sec"
741 " on MAC %d on TRIO %d\n",
742 rc_delay[trio_index][mac], mac,
743 trio_index);
744 msleep(rc_delay[trio_index][mac] * 1000);
745 } else {
746 /*
747 * Wait a bit here because some EP devices
748 * take longer to come up.
749 */
750 msleep(1000);
751 }
752
753 /* Check for PCIe link-up status again. */
754 port_status.word =
755 __gxio_mmio_read(trio_context->mmio_base_mac +
756 reg_offset);
757 if (!port_status.dl_up) {
758 if (pcie_ports[trio_index].ports[mac].removable) {
759 pr_info("PCI: link is down, MAC %d on TRIO %d\n",
760 mac, trio_index);
761 pr_info("This is expected if no PCIe card"
762 " is connected to this link\n");
763 } else
764 pr_err("PCI: link is down, MAC %d on TRIO %d\n",
765 mac, trio_index);
766 continue;
767 }
768
769 /*
770 * Ensure that the link can come out of L1 power down state.
771 * Strictly speaking, this is needed only in the case of
772 * heavy RC-initiated DMAs.
773 */
774 reg_offset =
775 (TRIO_PCIE_INTFC_TX_FIFO_CTL <<
776 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
777 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
778 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
779 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
780 tx_fifo_ctl.word =
781 __gxio_mmio_read(trio_context->mmio_base_mac +
782 reg_offset);
783 tx_fifo_ctl.min_p_credits = 0;
784 __gxio_mmio_write(trio_context->mmio_base_mac + reg_offset,
785 tx_fifo_ctl.word);
786
787 /*
788 * Change the device ID so that Linux bus crawl doesn't confuse
789 * the internal bridge with any Tilera endpoints.
790 */
791 reg_offset =
792 (TRIO_PCIE_RC_DEVICE_ID_VEN_ID <<
793 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
794 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
795 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
796 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
797
798 __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,
799 (TILERA_GX36_RC_DEV_ID <<
800 TRIO_PCIE_RC_DEVICE_ID_VEN_ID__DEV_ID_SHIFT) |
801 TILERA_VENDOR_ID);
802
803 /* Set the internal P2P bridge class code. */
804 reg_offset =
805 (TRIO_PCIE_RC_REVISION_ID <<
806 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
807 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
808 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
809 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
810
811 class_code_revision =
812 __gxio_mmio_read32(trio_context->mmio_base_mac +
813 reg_offset);
814 class_code_revision = (class_code_revision & 0xff) |
815 (PCI_CLASS_BRIDGE_PCI << 16);
816
817 __gxio_mmio_write32(trio_context->mmio_base_mac +
818 reg_offset, class_code_revision);
819
820 #ifdef USE_SHARED_PCIE_CONFIG_REGION
821
822 /* Map in the MMIO space for the PIO region. */
823 offset = HV_TRIO_PIO_OFFSET(trio_context->pio_cfg_index) |
824 (((unsigned long long)mac) <<
825 TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT);
826
827 #else
828
829 /* Alloc a PIO region for PCI config access per MAC. */
830 ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0);
831 if (ret < 0) {
832 pr_err("PCI: PCI CFG PIO alloc failure for mac %d "
833 "on TRIO %d, give up\n", mac, trio_index);
834
835 continue;
836 }
837
838 trio_context->pio_cfg_index[mac] = ret;
839
840 /* For PIO CFG, the bus_address_hi parameter is 0. */
841 ret = gxio_trio_init_pio_region_aux(trio_context,
842 trio_context->pio_cfg_index[mac],
843 mac, 0, HV_TRIO_PIO_FLAG_CONFIG_SPACE);
844 if (ret < 0) {
845 pr_err("PCI: PCI CFG PIO init failure for mac %d "
846 "on TRIO %d, give up\n", mac, trio_index);
847
848 continue;
849 }
850
851 offset = HV_TRIO_PIO_OFFSET(trio_context->pio_cfg_index[mac]) |
852 (((unsigned long long)mac) <<
853 TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT);
854
855 #endif
856
857 /*
858 * To save VMALLOC space, we take advantage of the fact that
859 * bit 29 in the PIO CFG address format is reserved 0. With
860 * TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT being 30,
861 * this cuts VMALLOC space usage from 1GB to 512MB per mac.
862 */
863 trio_context->mmio_base_pio_cfg[mac] =
864 iorpc_ioremap(trio_context->fd, offset, (1UL <<
865 (TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT - 1)));
866 if (trio_context->mmio_base_pio_cfg[mac] == NULL) {
867 pr_err("PCI: PIO map failure for mac %d on TRIO %d\n",
868 mac, trio_index);
869
870 continue;
871 }
872
873 /* Initialize the PCIe interrupts. */
874 if (tile_init_irqs(controller)) {
875 pr_err("PCI: IRQs init failure for mac %d on TRIO %d\n",
876 mac, trio_index);
877
878 continue;
879 }
880
881 /*
882 * The PCI memory resource is located above the PA space.
883 * The memory range for the PCI root bus should not overlap
884 * with the physical RAM.
885 */
886 pci_add_resource_offset(&resources, &controller->mem_space,
887 controller->mem_offset);
888 pci_add_resource(&resources, &controller->io_space);
889 controller->first_busno = next_busno;
890 bus = pci_scan_root_bus(NULL, next_busno, controller->ops,
891 controller, &resources);
892 controller->root_bus = bus;
893 next_busno = bus->busn_res.end + 1;
894 }
895
896 /* Do machine dependent PCI interrupt routing */
897 pci_fixup_irqs(pci_common_swizzle, tile_map_irq);
898
899 /*
900 * This comes from the generic Linux PCI driver.
901 *
902 * It allocates all of the resources (I/O memory, etc)
903 * associated with the devices read in above.
904 */
905 pci_assign_unassigned_resources();
906
907 /* Record the I/O resources in the PCI controller structure. */
908 for (i = 0; i < num_rc_controllers; i++) {
909 struct pci_controller *controller = &pci_controllers[i];
910 gxio_trio_context_t *trio_context = controller->trio;
911 struct pci_bus *root_bus = pci_controllers[i].root_bus;
912 int ret;
913 int j;
914
915 /*
916 * Skip controllers that are not properly initialized or
917 * have down links.
918 */
919 if (root_bus == NULL)
920 continue;
921
922 /* Configure the max_payload_size values for this domain. */
923 fixup_read_and_payload_sizes(controller);
924
925 /* Alloc a PIO region for PCI memory access for each RC port. */
926 ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0);
927 if (ret < 0) {
928 pr_err("PCI: MEM PIO alloc failure on TRIO %d mac %d, "
929 "give up\n", controller->trio_index,
930 controller->mac);
931
932 continue;
933 }
934
935 controller->pio_mem_index = ret;
936
937 /*
938 * For PIO MEM, the bus_address_hi parameter is hard-coded 0
939 * because we always assign 32-bit PCI bus BAR ranges.
940 */
941 ret = gxio_trio_init_pio_region_aux(trio_context,
942 controller->pio_mem_index,
943 controller->mac,
944 0,
945 0);
946 if (ret < 0) {
947 pr_err("PCI: MEM PIO init failure on TRIO %d mac %d, "
948 "give up\n", controller->trio_index,
949 controller->mac);
950
951 continue;
952 }
953
954 #ifdef CONFIG_TILE_PCI_IO
955 /*
956 * Alloc a PIO region for PCI I/O space access for each RC port.
957 */
958 ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0);
959 if (ret < 0) {
960 pr_err("PCI: I/O PIO alloc failure on TRIO %d mac %d, "
961 "give up\n", controller->trio_index,
962 controller->mac);
963
964 continue;
965 }
966
967 controller->pio_io_index = ret;
968
969 /*
970 * For PIO IO, the bus_address_hi parameter is hard-coded 0
971 * because PCI I/O address space is 32-bit.
972 */
973 ret = gxio_trio_init_pio_region_aux(trio_context,
974 controller->pio_io_index,
975 controller->mac,
976 0,
977 HV_TRIO_PIO_FLAG_IO_SPACE);
978 if (ret < 0) {
979 pr_err("PCI: I/O PIO init failure on TRIO %d mac %d, "
980 "give up\n", controller->trio_index,
981 controller->mac);
982
983 continue;
984 }
985 #endif
986
987 /*
988 * Configure a Mem-Map region for each memory controller so
989 * that Linux can map all of its PA space to the PCI bus.
990 * Use the IOMMU to handle hash-for-home memory.
991 */
992 for_each_online_node(j) {
993 unsigned long start_pfn = node_start_pfn[j];
994 unsigned long end_pfn = node_end_pfn[j];
995 unsigned long nr_pages = end_pfn - start_pfn;
996
997 ret = gxio_trio_alloc_memory_maps(trio_context, 1, 0,
998 0);
999 if (ret < 0) {
1000 pr_err("PCI: Mem-Map alloc failure on TRIO %d "
1001 "mac %d for MC %d, give up\n",
1002 controller->trio_index,
1003 controller->mac, j);
1004
1005 goto alloc_mem_map_failed;
1006 }
1007
1008 controller->mem_maps[j] = ret;
1009
1010 /*
1011 * Initialize the Mem-Map and the I/O MMU so that all
1012 * the physical memory can be accessed by the endpoint
1013 * devices. The base bus address is set to the base CPA
1014 * of this memory controller plus an offset (see pci.h).
1015 * The region's base VA is set to the base CPA. The
1016 * I/O MMU table essentially translates the CPA to
1017 * the real PA. Implicitly, for node 0, we create
1018 * a separate Mem-Map region that serves as the inbound
1019 * window for legacy 32-bit devices. This is a direct
1020 * map of the low 4GB CPA space.
1021 */
1022 ret = gxio_trio_init_memory_map_mmu_aux(trio_context,
1023 controller->mem_maps[j],
1024 start_pfn << PAGE_SHIFT,
1025 nr_pages << PAGE_SHIFT,
1026 trio_context->asid,
1027 controller->mac,
1028 (start_pfn << PAGE_SHIFT) +
1029 TILE_PCI_MEM_MAP_BASE_OFFSET,
1030 j,
1031 GXIO_TRIO_ORDER_MODE_UNORDERED);
1032 if (ret < 0) {
1033 pr_err("PCI: Mem-Map init failure on TRIO %d "
1034 "mac %d for MC %d, give up\n",
1035 controller->trio_index,
1036 controller->mac, j);
1037
1038 goto alloc_mem_map_failed;
1039 }
1040 continue;
1041
1042 alloc_mem_map_failed:
1043 break;
1044 }
1045 }
1046
1047 return 0;
1048 }
1049 subsys_initcall(pcibios_init);
1050
1051 /* No bus fixups needed. */
1052 void pcibios_fixup_bus(struct pci_bus *bus)
1053 {
1054 }
1055
1056 /* Process any "pci=" kernel boot arguments. */
1057 char *__init pcibios_setup(char *str)
1058 {
1059 if (!strcmp(str, "off")) {
1060 pci_probe = 0;
1061 return NULL;
1062 }
1063 return str;
1064 }
1065
1066 /*
1067 * Called for each device after PCI setup is done.
1068 * We initialize the PCI device capabilities conservatively, assuming that
1069 * all devices can only address the 32-bit DMA space. The exception here is
1070 * that the device dma_offset is set to the value that matches the 64-bit
1071 * capable devices. This is OK because dma_offset is not used by legacy
1072 * dma_ops, nor by the hybrid dma_ops's streaming DMAs, which are 64-bit ops.
1073 * This implementation matches the kernel design of setting PCI devices'
1074 * coherent_dma_mask to 0xffffffffull by default, allowing the device drivers
1075 * to skip calling pci_set_consistent_dma_mask(DMA_BIT_MASK(32)).
1076 */
1077 static void pcibios_fixup_final(struct pci_dev *pdev)
1078 {
1079 set_dma_ops(&pdev->dev, gx_legacy_pci_dma_map_ops);
1080 set_dma_offset(&pdev->dev, TILE_PCI_MEM_MAP_BASE_OFFSET);
1081 pdev->dev.archdata.max_direct_dma_addr =
1082 TILE_PCI_MAX_DIRECT_DMA_ADDRESS;
1083 pdev->dev.coherent_dma_mask = TILE_PCI_MAX_DIRECT_DMA_ADDRESS;
1084 }
1085 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);
1086
1087 /* Map a PCI MMIO bus address into VA space. */
1088 void __iomem *ioremap(resource_size_t phys_addr, unsigned long size)
1089 {
1090 struct pci_controller *controller = NULL;
1091 resource_size_t bar_start;
1092 resource_size_t bar_end;
1093 resource_size_t offset;
1094 resource_size_t start;
1095 resource_size_t end;
1096 int trio_fd;
1097 int i;
1098
1099 start = phys_addr;
1100 end = phys_addr + size - 1;
1101
1102 /*
1103 * By searching phys_addr in each controller's mem_space, we can
1104 * determine the controller that should accept the PCI memory access.
1105 */
1106 for (i = 0; i < num_rc_controllers; i++) {
1107 /*
1108 * Skip controllers that are not properly initialized or
1109 * have down links.
1110 */
1111 if (pci_controllers[i].root_bus == NULL)
1112 continue;
1113
1114 bar_start = pci_controllers[i].mem_space.start;
1115 bar_end = pci_controllers[i].mem_space.end;
1116
1117 if ((start >= bar_start) && (end <= bar_end)) {
1118 controller = &pci_controllers[i];
1119 break;
1120 }
1121 }
1122
1123 if (controller == NULL)
1124 return NULL;
1125
1126 trio_fd = controller->trio->fd;
1127
1128 /* Convert the resource start to the bus address offset. */
1129 start = phys_addr - controller->mem_offset;
1130
1131 offset = HV_TRIO_PIO_OFFSET(controller->pio_mem_index) + start;
1132
1133 /* We need to keep the PCI bus address's in-page offset in the VA. */
1134 return iorpc_ioremap(trio_fd, offset, size) +
1135 (start & (PAGE_SIZE - 1));
1136 }
1137 EXPORT_SYMBOL(ioremap);
1138
1139 #ifdef CONFIG_TILE_PCI_IO
1140 /* Map a PCI I/O address into VA space. */
1141 void __iomem *ioport_map(unsigned long port, unsigned int size)
1142 {
1143 struct pci_controller *controller = NULL;
1144 resource_size_t bar_start;
1145 resource_size_t bar_end;
1146 resource_size_t offset;
1147 resource_size_t start;
1148 resource_size_t end;
1149 int trio_fd;
1150 int i;
1151
1152 start = port;
1153 end = port + size - 1;
1154
1155 /*
1156 * By searching the port in each controller's io_space, we can
1157 * determine the controller that should accept the PCI I/O access.
1158 */
1159 for (i = 0; i < num_rc_controllers; i++) {
1160 /*
1161 * Skip controllers that are not properly initialized or
1162 * have down links.
1163 */
1164 if (pci_controllers[i].root_bus == NULL)
1165 continue;
1166
1167 bar_start = pci_controllers[i].io_space.start;
1168 bar_end = pci_controllers[i].io_space.end;
1169
1170 if ((start >= bar_start) && (end <= bar_end)) {
1171 controller = &pci_controllers[i];
1172 break;
1173 }
1174 }
1175
1176 if (controller == NULL)
1177 return NULL;
1178
1179 trio_fd = controller->trio->fd;
1180
1181 /* Convert the resource start to the bus address offset. */
1182 port -= controller->io_space.start;
1183
1184 offset = HV_TRIO_PIO_OFFSET(controller->pio_io_index) + port;
1185
1186 /* We need to keep the PCI bus address's in-page offset in the VA. */
1187 return iorpc_ioremap(trio_fd, offset, size) + (port & (PAGE_SIZE - 1));
1188 }
1189 EXPORT_SYMBOL(ioport_map);
1190
1191 void ioport_unmap(void __iomem *addr)
1192 {
1193 iounmap(addr);
1194 }
1195 EXPORT_SYMBOL(ioport_unmap);
1196 #endif
1197
1198 void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
1199 {
1200 iounmap(addr);
1201 }
1202 EXPORT_SYMBOL(pci_iounmap);
1203
1204 /****************************************************************
1205 *
1206 * Tile PCI config space read/write routines
1207 *
1208 ****************************************************************/
1209
1210 /*
1211 * These are the normal read and write ops
1212 * These are expanded with macros from pci_bus_read_config_byte() etc.
1213 *
1214 * devfn is the combined PCI device & function.
1215 *
1216 * offset is in bytes, from the start of config space for the
1217 * specified bus & device.
1218 */
1219 static int tile_cfg_read(struct pci_bus *bus, unsigned int devfn, int offset,
1220 int size, u32 *val)
1221 {
1222 struct pci_controller *controller = bus->sysdata;
1223 gxio_trio_context_t *trio_context = controller->trio;
1224 int busnum = bus->number & 0xff;
1225 int device = PCI_SLOT(devfn);
1226 int function = PCI_FUNC(devfn);
1227 int config_type = 1;
1228 TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR_t cfg_addr;
1229 void *mmio_addr;
1230
1231 /*
1232 * Map all accesses to the local device on root bus into the
1233 * MMIO space of the MAC. Accesses to the downstream devices
1234 * go to the PIO space.
1235 */
1236 if (pci_is_root_bus(bus)) {
1237 if (device == 0) {
1238 /*
1239 * This is the internal downstream P2P bridge,
1240 * access directly.
1241 */
1242 unsigned int reg_offset;
1243
1244 reg_offset = ((offset & 0xFFF) <<
1245 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
1246 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED
1247 << TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
1248 (controller->mac <<
1249 TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
1250
1251 mmio_addr = trio_context->mmio_base_mac + reg_offset;
1252
1253 goto valid_device;
1254
1255 } else {
1256 /*
1257 * We fake an empty device for (device > 0),
1258 * since there is only one device on bus 0.
1259 */
1260 goto invalid_device;
1261 }
1262 }
1263
1264 /*
1265 * Accesses to the directly attached device have to be
1266 * sent as type-0 configs.
1267 */
1268 if (busnum == (controller->first_busno + 1)) {
1269 /*
1270 * There is only one device off of our built-in P2P bridge.
1271 */
1272 if (device != 0)
1273 goto invalid_device;
1274
1275 config_type = 0;
1276 }
1277
1278 cfg_addr.word = 0;
1279 cfg_addr.reg_addr = (offset & 0xFFF);
1280 cfg_addr.fn = function;
1281 cfg_addr.dev = device;
1282 cfg_addr.bus = busnum;
1283 cfg_addr.type = config_type;
1284
1285 /*
1286 * Note that we don't set the mac field in cfg_addr because the
1287 * mapping is per port.
1288 */
1289 mmio_addr = trio_context->mmio_base_pio_cfg[controller->mac] +
1290 cfg_addr.word;
1291
1292 valid_device:
1293
1294 switch (size) {
1295 case 4:
1296 *val = __gxio_mmio_read32(mmio_addr);
1297 break;
1298
1299 case 2:
1300 *val = __gxio_mmio_read16(mmio_addr);
1301 break;
1302
1303 case 1:
1304 *val = __gxio_mmio_read8(mmio_addr);
1305 break;
1306
1307 default:
1308 return PCIBIOS_FUNC_NOT_SUPPORTED;
1309 }
1310
1311 TRACE_CFG_RD(size, *val, busnum, device, function, offset);
1312
1313 return 0;
1314
1315 invalid_device:
1316
1317 switch (size) {
1318 case 4:
1319 *val = 0xFFFFFFFF;
1320 break;
1321
1322 case 2:
1323 *val = 0xFFFF;
1324 break;
1325
1326 case 1:
1327 *val = 0xFF;
1328 break;
1329
1330 default:
1331 return PCIBIOS_FUNC_NOT_SUPPORTED;
1332 }
1333
1334 return 0;
1335 }
1336
1337
1338 /*
1339 * See tile_cfg_read() for relevent comments.
1340 * Note that "val" is the value to write, not a pointer to that value.
1341 */
1342 static int tile_cfg_write(struct pci_bus *bus, unsigned int devfn, int offset,
1343 int size, u32 val)
1344 {
1345 struct pci_controller *controller = bus->sysdata;
1346 gxio_trio_context_t *trio_context = controller->trio;
1347 int busnum = bus->number & 0xff;
1348 int device = PCI_SLOT(devfn);
1349 int function = PCI_FUNC(devfn);
1350 int config_type = 1;
1351 TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR_t cfg_addr;
1352 void *mmio_addr;
1353 u32 val_32 = (u32)val;
1354 u16 val_16 = (u16)val;
1355 u8 val_8 = (u8)val;
1356
1357 /*
1358 * Map all accesses to the local device on root bus into the
1359 * MMIO space of the MAC. Accesses to the downstream devices
1360 * go to the PIO space.
1361 */
1362 if (pci_is_root_bus(bus)) {
1363 if (device == 0) {
1364 /*
1365 * This is the internal downstream P2P bridge,
1366 * access directly.
1367 */
1368 unsigned int reg_offset;
1369
1370 reg_offset = ((offset & 0xFFF) <<
1371 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
1372 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED
1373 << TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
1374 (controller->mac <<
1375 TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
1376
1377 mmio_addr = trio_context->mmio_base_mac + reg_offset;
1378
1379 goto valid_device;
1380
1381 } else {
1382 /*
1383 * We fake an empty device for (device > 0),
1384 * since there is only one device on bus 0.
1385 */
1386 goto invalid_device;
1387 }
1388 }
1389
1390 /*
1391 * Accesses to the directly attached device have to be
1392 * sent as type-0 configs.
1393 */
1394 if (busnum == (controller->first_busno + 1)) {
1395 /*
1396 * There is only one device off of our built-in P2P bridge.
1397 */
1398 if (device != 0)
1399 goto invalid_device;
1400
1401 config_type = 0;
1402 }
1403
1404 cfg_addr.word = 0;
1405 cfg_addr.reg_addr = (offset & 0xFFF);
1406 cfg_addr.fn = function;
1407 cfg_addr.dev = device;
1408 cfg_addr.bus = busnum;
1409 cfg_addr.type = config_type;
1410
1411 /*
1412 * Note that we don't set the mac field in cfg_addr because the
1413 * mapping is per port.
1414 */
1415 mmio_addr = trio_context->mmio_base_pio_cfg[controller->mac] +
1416 cfg_addr.word;
1417
1418 valid_device:
1419
1420 switch (size) {
1421 case 4:
1422 __gxio_mmio_write32(mmio_addr, val_32);
1423 TRACE_CFG_WR(size, val_32, busnum, device, function, offset);
1424 break;
1425
1426 case 2:
1427 __gxio_mmio_write16(mmio_addr, val_16);
1428 TRACE_CFG_WR(size, val_16, busnum, device, function, offset);
1429 break;
1430
1431 case 1:
1432 __gxio_mmio_write8(mmio_addr, val_8);
1433 TRACE_CFG_WR(size, val_8, busnum, device, function, offset);
1434 break;
1435
1436 default:
1437 return PCIBIOS_FUNC_NOT_SUPPORTED;
1438 }
1439
1440 invalid_device:
1441
1442 return 0;
1443 }
1444
1445
1446 static struct pci_ops tile_cfg_ops = {
1447 .read = tile_cfg_read,
1448 .write = tile_cfg_write,
1449 };
1450
1451
1452 /* MSI support starts here. */
1453 static unsigned int tilegx_msi_startup(struct irq_data *d)
1454 {
1455 if (d->msi_desc)
1456 unmask_msi_irq(d);
1457
1458 return 0;
1459 }
1460
1461 static void tilegx_msi_ack(struct irq_data *d)
1462 {
1463 __insn_mtspr(SPR_IPI_EVENT_RESET_K, 1UL << d->irq);
1464 }
1465
1466 static void tilegx_msi_mask(struct irq_data *d)
1467 {
1468 mask_msi_irq(d);
1469 __insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq);
1470 }
1471
1472 static void tilegx_msi_unmask(struct irq_data *d)
1473 {
1474 __insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq);
1475 unmask_msi_irq(d);
1476 }
1477
1478 static struct irq_chip tilegx_msi_chip = {
1479 .name = "tilegx_msi",
1480 .irq_startup = tilegx_msi_startup,
1481 .irq_ack = tilegx_msi_ack,
1482 .irq_mask = tilegx_msi_mask,
1483 .irq_unmask = tilegx_msi_unmask,
1484
1485 /* TBD: support set_affinity. */
1486 };
1487
1488 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
1489 {
1490 struct pci_controller *controller;
1491 gxio_trio_context_t *trio_context;
1492 struct msi_msg msg;
1493 int default_irq;
1494 uint64_t mem_map_base;
1495 uint64_t mem_map_limit;
1496 u64 msi_addr;
1497 int mem_map;
1498 int cpu;
1499 int irq;
1500 int ret;
1501
1502 irq = irq_alloc_hwirq(-1);
1503 if (!irq)
1504 return -ENOSPC;
1505
1506 /*
1507 * Since we use a 64-bit Mem-Map to accept the MSI write, we fail
1508 * devices that are not capable of generating a 64-bit message address.
1509 * These devices will fall back to using the legacy interrupts.
1510 * Most PCIe endpoint devices do support 64-bit message addressing.
1511 */
1512 if (desc->msi_attrib.is_64 == 0) {
1513 dev_printk(KERN_INFO, &pdev->dev,
1514 "64-bit MSI message address not supported, "
1515 "falling back to legacy interrupts.\n");
1516
1517 ret = -ENOMEM;
1518 goto is_64_failure;
1519 }
1520
1521 default_irq = desc->msi_attrib.default_irq;
1522 controller = irq_get_handler_data(default_irq);
1523
1524 BUG_ON(!controller);
1525
1526 trio_context = controller->trio;
1527
1528 /*
1529 * Allocate a scatter-queue that will accept the MSI write and
1530 * trigger the TILE-side interrupts. We use the scatter-queue regions
1531 * before the mem map regions, because the latter are needed by more
1532 * applications.
1533 */
1534 mem_map = gxio_trio_alloc_scatter_queues(trio_context, 1, 0, 0);
1535 if (mem_map >= 0) {
1536 TRIO_MAP_SQ_DOORBELL_FMT_t doorbell_template = {{
1537 .pop = 0,
1538 .doorbell = 1,
1539 }};
1540
1541 mem_map += TRIO_NUM_MAP_MEM_REGIONS;
1542 mem_map_base = MEM_MAP_INTR_REGIONS_BASE +
1543 mem_map * MEM_MAP_INTR_REGION_SIZE;
1544 mem_map_limit = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 1;
1545
1546 msi_addr = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 8;
1547 msg.data = (unsigned int)doorbell_template.word;
1548 } else {
1549 /* SQ regions are out, allocate from map mem regions. */
1550 mem_map = gxio_trio_alloc_memory_maps(trio_context, 1, 0, 0);
1551 if (mem_map < 0) {
1552 dev_printk(KERN_INFO, &pdev->dev,
1553 "%s Mem-Map alloc failure. "
1554 "Failed to initialize MSI interrupts. "
1555 "Falling back to legacy interrupts.\n",
1556 desc->msi_attrib.is_msix ? "MSI-X" : "MSI");
1557 ret = -ENOMEM;
1558 goto msi_mem_map_alloc_failure;
1559 }
1560
1561 mem_map_base = MEM_MAP_INTR_REGIONS_BASE +
1562 mem_map * MEM_MAP_INTR_REGION_SIZE;
1563 mem_map_limit = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 1;
1564
1565 msi_addr = mem_map_base + TRIO_MAP_MEM_REG_INT3 -
1566 TRIO_MAP_MEM_REG_INT0;
1567
1568 msg.data = mem_map;
1569 }
1570
1571 /* We try to distribute different IRQs to different tiles. */
1572 cpu = tile_irq_cpu(irq);
1573
1574 /*
1575 * Now call up to the HV to configure the MSI interrupt and
1576 * set up the IPI binding.
1577 */
1578 ret = gxio_trio_config_msi_intr(trio_context, cpu_x(cpu), cpu_y(cpu),
1579 KERNEL_PL, irq, controller->mac,
1580 mem_map, mem_map_base, mem_map_limit,
1581 trio_context->asid);
1582 if (ret < 0) {
1583 dev_printk(KERN_INFO, &pdev->dev, "HV MSI config failed.\n");
1584
1585 goto hv_msi_config_failure;
1586 }
1587
1588 irq_set_msi_desc(irq, desc);
1589
1590 msg.address_hi = msi_addr >> 32;
1591 msg.address_lo = msi_addr & 0xffffffff;
1592
1593 write_msi_msg(irq, &msg);
1594 irq_set_chip_and_handler(irq, &tilegx_msi_chip, handle_level_irq);
1595 irq_set_handler_data(irq, controller);
1596
1597 return 0;
1598
1599 hv_msi_config_failure:
1600 /* Free mem-map */
1601 msi_mem_map_alloc_failure:
1602 is_64_failure:
1603 irq_free_hwirq(irq);
1604 return ret;
1605 }
1606
1607 void arch_teardown_msi_irq(unsigned int irq)
1608 {
1609 irq_free_hwirq(irq);
1610 }
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