2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
5 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 /***********************\
22 * PHY related functions *
23 \***********************/
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <asm/unaligned.h>
37 * DOC: PHY related functions
39 * Here we handle the low-level functions related to baseband
40 * and analog frontend (RF) parts. This is by far the most complex
41 * part of the hw code so make sure you know what you are doing.
43 * Here is a list of what this is all about:
45 * - Channel setting/switching
47 * - Automatic Gain Control (AGC) calibration
49 * - Noise Floor calibration
51 * - I/Q imbalance calibration (QAM correction)
53 * - Calibration due to thermal changes (gain_F)
55 * - Spur noise mitigation
57 * - RF/PHY initialization for the various operating modes and bwmodes
61 * - TX power control per channel/rate/packet type
63 * Also have in mind we never got documentation for most of these
64 * functions, what we have comes mostly from Atheros's code, reverse
65 * engineering and patent docs/presentations etc.
74 * ath5k_hw_radio_revision() - Get the PHY Chip revision
75 * @ah: The &struct ath5k_hw
76 * @band: One of enum ieee80211_band
78 * Returns the revision number of a 2GHz, 5GHz or single chip
82 ath5k_hw_radio_revision(struct ath5k_hw
*ah
, enum ieee80211_band band
)
89 * Set the radio chip access register
92 case IEEE80211_BAND_2GHZ
:
93 ath5k_hw_reg_write(ah
, AR5K_PHY_SHIFT_2GHZ
, AR5K_PHY(0));
95 case IEEE80211_BAND_5GHZ
:
96 ath5k_hw_reg_write(ah
, AR5K_PHY_SHIFT_5GHZ
, AR5K_PHY(0));
102 usleep_range(2000, 2500);
104 /* ...wait until PHY is ready and read the selected radio revision */
105 ath5k_hw_reg_write(ah
, 0x00001c16, AR5K_PHY(0x34));
107 for (i
= 0; i
< 8; i
++)
108 ath5k_hw_reg_write(ah
, 0x00010000, AR5K_PHY(0x20));
110 if (ah
->ah_version
== AR5K_AR5210
) {
111 srev
= ath5k_hw_reg_read(ah
, AR5K_PHY(256) >> 28) & 0xf;
112 ret
= (u16
)ath5k_hw_bitswap(srev
, 4) + 1;
114 srev
= (ath5k_hw_reg_read(ah
, AR5K_PHY(0x100)) >> 24) & 0xff;
115 ret
= (u16
)ath5k_hw_bitswap(((srev
& 0xf0) >> 4) |
116 ((srev
& 0x0f) << 4), 8);
119 /* Reset to the 5GHz mode */
120 ath5k_hw_reg_write(ah
, AR5K_PHY_SHIFT_5GHZ
, AR5K_PHY(0));
126 * ath5k_channel_ok() - Check if a channel is supported by the hw
127 * @ah: The &struct ath5k_hw
128 * @channel: The &struct ieee80211_channel
130 * Note: We don't do any regulatory domain checks here, it's just
134 ath5k_channel_ok(struct ath5k_hw
*ah
, struct ieee80211_channel
*channel
)
136 u16 freq
= channel
->center_freq
;
138 /* Check if the channel is in our supported range */
139 if (channel
->band
== IEEE80211_BAND_2GHZ
) {
140 if ((freq
>= ah
->ah_capabilities
.cap_range
.range_2ghz_min
) &&
141 (freq
<= ah
->ah_capabilities
.cap_range
.range_2ghz_max
))
143 } else if (channel
->band
== IEEE80211_BAND_5GHZ
)
144 if ((freq
>= ah
->ah_capabilities
.cap_range
.range_5ghz_min
) &&
145 (freq
<= ah
->ah_capabilities
.cap_range
.range_5ghz_max
))
152 * ath5k_hw_chan_has_spur_noise() - Check if channel is sensitive to spur noise
153 * @ah: The &struct ath5k_hw
154 * @channel: The &struct ieee80211_channel
157 ath5k_hw_chan_has_spur_noise(struct ath5k_hw
*ah
,
158 struct ieee80211_channel
*channel
)
162 if ((ah
->ah_radio
== AR5K_RF5112
) ||
163 (ah
->ah_radio
== AR5K_RF5413
) ||
164 (ah
->ah_radio
== AR5K_RF2413
) ||
165 (ah
->ah_mac_version
== (AR5K_SREV_AR2417
>> 4)))
170 if ((channel
->center_freq
% refclk_freq
!= 0) &&
171 ((channel
->center_freq
% refclk_freq
< 10) ||
172 (channel
->center_freq
% refclk_freq
> 22)))
179 * ath5k_hw_rfb_op() - Perform an operation on the given RF Buffer
180 * @ah: The &struct ath5k_hw
181 * @rf_regs: The struct ath5k_rf_reg
183 * @reg_id: RF register ID
184 * @set: Indicate we need to swap data
186 * This is an internal function used to modify RF Banks before
187 * writing them to AR5K_RF_BUFFER. Check out rfbuffer.h for more
191 ath5k_hw_rfb_op(struct ath5k_hw
*ah
, const struct ath5k_rf_reg
*rf_regs
,
192 u32 val
, u8 reg_id
, bool set
)
194 const struct ath5k_rf_reg
*rfreg
= NULL
;
195 u8 offset
, bank
, num_bits
, col
, position
;
197 u32 mask
, data
, last_bit
, bits_shifted
, first_bit
;
203 rfb
= ah
->ah_rf_banks
;
205 for (i
= 0; i
< ah
->ah_rf_regs_count
; i
++) {
206 if (rf_regs
[i
].index
== reg_id
) {
212 if (rfb
== NULL
|| rfreg
== NULL
) {
213 ATH5K_PRINTF("Rf register not found!\n");
214 /* should not happen */
219 num_bits
= rfreg
->field
.len
;
220 first_bit
= rfreg
->field
.pos
;
221 col
= rfreg
->field
.col
;
223 /* first_bit is an offset from bank's
224 * start. Since we have all banks on
225 * the same array, we use this offset
226 * to mark each bank's start */
227 offset
= ah
->ah_offset
[bank
];
230 if (!(col
<= 3 && num_bits
<= 32 && first_bit
+ num_bits
<= 319)) {
231 ATH5K_PRINTF("invalid values at offset %u\n", offset
);
235 entry
= ((first_bit
- 1) / 8) + offset
;
236 position
= (first_bit
- 1) % 8;
239 data
= ath5k_hw_bitswap(val
, num_bits
);
241 for (bits_shifted
= 0, bits_left
= num_bits
; bits_left
> 0;
242 position
= 0, entry
++) {
244 last_bit
= (position
+ bits_left
> 8) ? 8 :
245 position
+ bits_left
;
247 mask
= (((1 << last_bit
) - 1) ^ ((1 << position
) - 1)) <<
252 rfb
[entry
] |= ((data
<< position
) << (col
* 8)) & mask
;
253 data
>>= (8 - position
);
255 data
|= (((rfb
[entry
] & mask
) >> (col
* 8)) >> position
)
257 bits_shifted
+= last_bit
- position
;
260 bits_left
-= 8 - position
;
263 data
= set
? 1 : ath5k_hw_bitswap(data
, num_bits
);
269 * ath5k_hw_write_ofdm_timings() - set OFDM timings on AR5212
270 * @ah: the &struct ath5k_hw
271 * @channel: the currently set channel upon reset
273 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM
274 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_phy_init.
276 * Since delta slope is floating point we split it on its exponent and
277 * mantissa and provide these values on hw.
279 * For more infos i think this patent is related
280 * "http://www.freepatentsonline.com/7184495.html"
283 ath5k_hw_write_ofdm_timings(struct ath5k_hw
*ah
,
284 struct ieee80211_channel
*channel
)
286 /* Get exponent and mantissa and set it */
287 u32 coef_scaled
, coef_exp
, coef_man
,
288 ds_coef_exp
, ds_coef_man
, clock
;
290 BUG_ON(!(ah
->ah_version
== AR5K_AR5212
) ||
291 (channel
->hw_value
== AR5K_MODE_11B
));
294 * ALGO: coef = (5 * clock / carrier_freq) / 2
295 * we scale coef by shifting clock value by 24 for
296 * better precision since we use integers */
297 switch (ah
->ah_bwmode
) {
298 case AR5K_BWMODE_40MHZ
:
301 case AR5K_BWMODE_10MHZ
:
304 case AR5K_BWMODE_5MHZ
:
311 coef_scaled
= ((5 * (clock
<< 24)) / 2) / channel
->center_freq
;
314 * ALGO: coef_exp = 14 - highest set bit position */
315 coef_exp
= ilog2(coef_scaled
);
317 /* Doesn't make sense if it's zero*/
318 if (!coef_scaled
|| !coef_exp
)
321 /* Note: we've shifted coef_scaled by 24 */
322 coef_exp
= 14 - (coef_exp
- 24);
325 /* Get mantissa (significant digits)
326 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */
327 coef_man
= coef_scaled
+
328 (1 << (24 - coef_exp
- 1));
330 /* Calculate delta slope coefficient exponent
331 * and mantissa (remove scaling) and set them on hw */
332 ds_coef_man
= coef_man
>> (24 - coef_exp
);
333 ds_coef_exp
= coef_exp
- 16;
335 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_TIMING_3
,
336 AR5K_PHY_TIMING_3_DSC_MAN
, ds_coef_man
);
337 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_TIMING_3
,
338 AR5K_PHY_TIMING_3_DSC_EXP
, ds_coef_exp
);
344 * ath5k_hw_phy_disable() - Disable PHY
345 * @ah: The &struct ath5k_hw
347 int ath5k_hw_phy_disable(struct ath5k_hw
*ah
)
350 ath5k_hw_reg_write(ah
, AR5K_PHY_ACT_DISABLE
, AR5K_PHY_ACT
);
356 * ath5k_hw_wait_for_synth() - Wait for synth to settle
357 * @ah: The &struct ath5k_hw
358 * @channel: The &struct ieee80211_channel
361 ath5k_hw_wait_for_synth(struct ath5k_hw
*ah
,
362 struct ieee80211_channel
*channel
)
365 * On 5211+ read activation -> rx delay
366 * and use it (100ns steps).
368 if (ah
->ah_version
!= AR5K_AR5210
) {
370 delay
= ath5k_hw_reg_read(ah
, AR5K_PHY_RX_DELAY
) &
372 delay
= (channel
->hw_value
== AR5K_MODE_11B
) ?
373 ((delay
<< 2) / 22) : (delay
/ 10);
374 if (ah
->ah_bwmode
== AR5K_BWMODE_10MHZ
)
376 if (ah
->ah_bwmode
== AR5K_BWMODE_5MHZ
)
378 /* XXX: /2 on turbo ? Let's be safe
380 usleep_range(100 + delay
, 100 + (2 * delay
));
382 usleep_range(1000, 1500);
387 /**********************\
388 * RF Gain optimization *
389 \**********************/
392 * DOC: RF Gain optimization
394 * This code is used to optimize RF gain on different environments
395 * (temperature mostly) based on feedback from a power detector.
397 * It's only used on RF5111 and RF5112, later RF chips seem to have
398 * auto adjustment on hw -notice they have a much smaller BANK 7 and
399 * no gain optimization ladder-.
401 * For more infos check out this patent doc
402 * "http://www.freepatentsonline.com/7400691.html"
404 * This paper describes power drops as seen on the receiver due to
406 * "http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
407 * %20of%20Power%20Control.pdf"
409 * And this is the MadWiFi bug entry related to the above
410 * "http://madwifi-project.org/ticket/1659"
411 * with various measurements and diagrams
415 * ath5k_hw_rfgain_opt_init() - Initialize ah_gain during attach
416 * @ah: The &struct ath5k_hw
418 int ath5k_hw_rfgain_opt_init(struct ath5k_hw
*ah
)
420 /* Initialize the gain optimization values */
421 switch (ah
->ah_radio
) {
423 ah
->ah_gain
.g_step_idx
= rfgain_opt_5111
.go_default
;
424 ah
->ah_gain
.g_low
= 20;
425 ah
->ah_gain
.g_high
= 35;
426 ah
->ah_gain
.g_state
= AR5K_RFGAIN_ACTIVE
;
429 ah
->ah_gain
.g_step_idx
= rfgain_opt_5112
.go_default
;
430 ah
->ah_gain
.g_low
= 20;
431 ah
->ah_gain
.g_high
= 85;
432 ah
->ah_gain
.g_state
= AR5K_RFGAIN_ACTIVE
;
442 * ath5k_hw_request_rfgain_probe() - Request a PAPD probe packet
443 * @ah: The &struct ath5k_hw
445 * Schedules a gain probe check on the next transmitted packet.
446 * That means our next packet is going to be sent with lower
447 * tx power and a Peak to Average Power Detector (PAPD) will try
448 * to measure the gain.
450 * TODO: Force a tx packet (bypassing PCU arbitrator etc)
451 * just after we enable the probe so that we don't mess with
455 ath5k_hw_request_rfgain_probe(struct ath5k_hw
*ah
)
458 /* Skip if gain calibration is inactive or
459 * we already handle a probe request */
460 if (ah
->ah_gain
.g_state
!= AR5K_RFGAIN_ACTIVE
)
463 /* Send the packet with 2dB below max power as
464 * patent doc suggest */
465 ath5k_hw_reg_write(ah
, AR5K_REG_SM(ah
->ah_txpower
.txp_ofdm
- 4,
466 AR5K_PHY_PAPD_PROBE_TXPOWER
) |
467 AR5K_PHY_PAPD_PROBE_TX_NEXT
, AR5K_PHY_PAPD_PROBE
);
469 ah
->ah_gain
.g_state
= AR5K_RFGAIN_READ_REQUESTED
;
474 * ath5k_hw_rf_gainf_corr() - Calculate Gain_F measurement correction
475 * @ah: The &struct ath5k_hw
477 * Calculate Gain_F measurement correction
478 * based on the current step for RF5112 rev. 2
481 ath5k_hw_rf_gainf_corr(struct ath5k_hw
*ah
)
485 const struct ath5k_gain_opt
*go
;
486 const struct ath5k_gain_opt_step
*g_step
;
487 const struct ath5k_rf_reg
*rf_regs
;
489 /* Only RF5112 Rev. 2 supports it */
490 if ((ah
->ah_radio
!= AR5K_RF5112
) ||
491 (ah
->ah_radio_5ghz_revision
<= AR5K_SREV_RAD_5112A
))
494 go
= &rfgain_opt_5112
;
495 rf_regs
= rf_regs_5112a
;
496 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_5112a
);
498 g_step
= &go
->go_step
[ah
->ah_gain
.g_step_idx
];
500 if (ah
->ah_rf_banks
== NULL
)
503 rf
= ah
->ah_rf_banks
;
504 ah
->ah_gain
.g_f_corr
= 0;
506 /* No VGA (Variable Gain Amplifier) override, skip */
507 if (ath5k_hw_rfb_op(ah
, rf_regs
, 0, AR5K_RF_MIXVGA_OVR
, false) != 1)
510 /* Mix gain stepping */
511 step
= ath5k_hw_rfb_op(ah
, rf_regs
, 0, AR5K_RF_MIXGAIN_STEP
, false);
513 /* Mix gain override */
514 mix
= g_step
->gos_param
[0];
518 ah
->ah_gain
.g_f_corr
= step
* 2;
521 ah
->ah_gain
.g_f_corr
= (step
- 5) * 2;
524 ah
->ah_gain
.g_f_corr
= step
;
527 ah
->ah_gain
.g_f_corr
= 0;
531 return ah
->ah_gain
.g_f_corr
;
535 * ath5k_hw_rf_check_gainf_readback() - Validate Gain_F feedback from detector
536 * @ah: The &struct ath5k_hw
538 * Check if current gain_F measurement is in the range of our
539 * power detector windows. If we get a measurement outside range
540 * we know it's not accurate (detectors can't measure anything outside
541 * their detection window) so we must ignore it.
543 * Returns true if readback was O.K. or false on failure
546 ath5k_hw_rf_check_gainf_readback(struct ath5k_hw
*ah
)
548 const struct ath5k_rf_reg
*rf_regs
;
549 u32 step
, mix_ovr
, level
[4];
552 if (ah
->ah_rf_banks
== NULL
)
555 rf
= ah
->ah_rf_banks
;
557 if (ah
->ah_radio
== AR5K_RF5111
) {
559 rf_regs
= rf_regs_5111
;
560 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_5111
);
562 step
= ath5k_hw_rfb_op(ah
, rf_regs
, 0, AR5K_RF_RFGAIN_STEP
,
566 level
[1] = (step
== 63) ? 50 : step
+ 4;
567 level
[2] = (step
!= 63) ? 64 : level
[0];
568 level
[3] = level
[2] + 50;
570 ah
->ah_gain
.g_high
= level
[3] -
571 (step
== 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN
: -5);
572 ah
->ah_gain
.g_low
= level
[0] +
573 (step
== 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN
: 0);
576 rf_regs
= rf_regs_5112
;
577 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_5112
);
579 mix_ovr
= ath5k_hw_rfb_op(ah
, rf_regs
, 0, AR5K_RF_MIXVGA_OVR
,
582 level
[0] = level
[2] = 0;
585 level
[1] = level
[3] = 83;
587 level
[1] = level
[3] = 107;
588 ah
->ah_gain
.g_high
= 55;
592 return (ah
->ah_gain
.g_current
>= level
[0] &&
593 ah
->ah_gain
.g_current
<= level
[1]) ||
594 (ah
->ah_gain
.g_current
>= level
[2] &&
595 ah
->ah_gain
.g_current
<= level
[3]);
599 * ath5k_hw_rf_gainf_adjust() - Perform Gain_F adjustment
600 * @ah: The &struct ath5k_hw
602 * Choose the right target gain based on current gain
603 * and RF gain optimization ladder
606 ath5k_hw_rf_gainf_adjust(struct ath5k_hw
*ah
)
608 const struct ath5k_gain_opt
*go
;
609 const struct ath5k_gain_opt_step
*g_step
;
612 switch (ah
->ah_radio
) {
614 go
= &rfgain_opt_5111
;
617 go
= &rfgain_opt_5112
;
623 g_step
= &go
->go_step
[ah
->ah_gain
.g_step_idx
];
625 if (ah
->ah_gain
.g_current
>= ah
->ah_gain
.g_high
) {
627 /* Reached maximum */
628 if (ah
->ah_gain
.g_step_idx
== 0)
631 for (ah
->ah_gain
.g_target
= ah
->ah_gain
.g_current
;
632 ah
->ah_gain
.g_target
>= ah
->ah_gain
.g_high
&&
633 ah
->ah_gain
.g_step_idx
> 0;
634 g_step
= &go
->go_step
[ah
->ah_gain
.g_step_idx
])
635 ah
->ah_gain
.g_target
-= 2 *
636 (go
->go_step
[--(ah
->ah_gain
.g_step_idx
)].gos_gain
-
643 if (ah
->ah_gain
.g_current
<= ah
->ah_gain
.g_low
) {
645 /* Reached minimum */
646 if (ah
->ah_gain
.g_step_idx
== (go
->go_steps_count
- 1))
649 for (ah
->ah_gain
.g_target
= ah
->ah_gain
.g_current
;
650 ah
->ah_gain
.g_target
<= ah
->ah_gain
.g_low
&&
651 ah
->ah_gain
.g_step_idx
< go
->go_steps_count
- 1;
652 g_step
= &go
->go_step
[ah
->ah_gain
.g_step_idx
])
653 ah
->ah_gain
.g_target
-= 2 *
654 (go
->go_step
[++ah
->ah_gain
.g_step_idx
].gos_gain
-
662 ATH5K_DBG(ah
, ATH5K_DEBUG_CALIBRATE
,
663 "ret %d, gain step %u, current gain %u, target gain %u\n",
664 ret
, ah
->ah_gain
.g_step_idx
, ah
->ah_gain
.g_current
,
665 ah
->ah_gain
.g_target
);
671 * ath5k_hw_gainf_calibrate() - Do a gain_F calibration
672 * @ah: The &struct ath5k_hw
674 * Main callback for thermal RF gain calibration engine
675 * Check for a new gain reading and schedule an adjustment
678 * Returns one of enum ath5k_rfgain codes
681 ath5k_hw_gainf_calibrate(struct ath5k_hw
*ah
)
684 struct ath5k_eeprom_info
*ee
= &ah
->ah_capabilities
.cap_eeprom
;
686 if (ah
->ah_rf_banks
== NULL
||
687 ah
->ah_gain
.g_state
== AR5K_RFGAIN_INACTIVE
)
688 return AR5K_RFGAIN_INACTIVE
;
690 /* No check requested, either engine is inactive
691 * or an adjustment is already requested */
692 if (ah
->ah_gain
.g_state
!= AR5K_RFGAIN_READ_REQUESTED
)
695 /* Read the PAPD (Peak to Average Power Detector)
697 data
= ath5k_hw_reg_read(ah
, AR5K_PHY_PAPD_PROBE
);
699 /* No probe is scheduled, read gain_F measurement */
700 if (!(data
& AR5K_PHY_PAPD_PROBE_TX_NEXT
)) {
701 ah
->ah_gain
.g_current
= data
>> AR5K_PHY_PAPD_PROBE_GAINF_S
;
702 type
= AR5K_REG_MS(data
, AR5K_PHY_PAPD_PROBE_TYPE
);
704 /* If tx packet is CCK correct the gain_F measurement
705 * by cck ofdm gain delta */
706 if (type
== AR5K_PHY_PAPD_PROBE_TYPE_CCK
) {
707 if (ah
->ah_radio_5ghz_revision
>= AR5K_SREV_RAD_5112A
)
708 ah
->ah_gain
.g_current
+=
709 ee
->ee_cck_ofdm_gain_delta
;
711 ah
->ah_gain
.g_current
+=
712 AR5K_GAIN_CCK_PROBE_CORR
;
715 /* Further correct gain_F measurement for
717 if (ah
->ah_radio_5ghz_revision
>= AR5K_SREV_RAD_5112A
) {
718 ath5k_hw_rf_gainf_corr(ah
);
719 ah
->ah_gain
.g_current
=
720 ah
->ah_gain
.g_current
>= ah
->ah_gain
.g_f_corr
?
721 (ah
->ah_gain
.g_current
- ah
->ah_gain
.g_f_corr
) :
725 /* Check if measurement is ok and if we need
726 * to adjust gain, schedule a gain adjustment,
727 * else switch back to the active state */
728 if (ath5k_hw_rf_check_gainf_readback(ah
) &&
729 AR5K_GAIN_CHECK_ADJUST(&ah
->ah_gain
) &&
730 ath5k_hw_rf_gainf_adjust(ah
)) {
731 ah
->ah_gain
.g_state
= AR5K_RFGAIN_NEED_CHANGE
;
733 ah
->ah_gain
.g_state
= AR5K_RFGAIN_ACTIVE
;
738 return ah
->ah_gain
.g_state
;
742 * ath5k_hw_rfgain_init() - Write initial RF gain settings to hw
743 * @ah: The &struct ath5k_hw
744 * @band: One of enum ieee80211_band
746 * Write initial RF gain table to set the RF sensitivity.
748 * NOTE: This one works on all RF chips and has nothing to do
749 * with Gain_F calibration
752 ath5k_hw_rfgain_init(struct ath5k_hw
*ah
, enum ieee80211_band band
)
754 const struct ath5k_ini_rfgain
*ath5k_rfg
;
755 unsigned int i
, size
, index
;
757 switch (ah
->ah_radio
) {
759 ath5k_rfg
= rfgain_5111
;
760 size
= ARRAY_SIZE(rfgain_5111
);
763 ath5k_rfg
= rfgain_5112
;
764 size
= ARRAY_SIZE(rfgain_5112
);
767 ath5k_rfg
= rfgain_2413
;
768 size
= ARRAY_SIZE(rfgain_2413
);
771 ath5k_rfg
= rfgain_2316
;
772 size
= ARRAY_SIZE(rfgain_2316
);
775 ath5k_rfg
= rfgain_5413
;
776 size
= ARRAY_SIZE(rfgain_5413
);
780 ath5k_rfg
= rfgain_2425
;
781 size
= ARRAY_SIZE(rfgain_2425
);
787 index
= (band
== IEEE80211_BAND_2GHZ
) ? 1 : 0;
789 for (i
= 0; i
< size
; i
++) {
791 ath5k_hw_reg_write(ah
, ath5k_rfg
[i
].rfg_value
[index
],
792 (u32
)ath5k_rfg
[i
].rfg_register
);
799 /********************\
800 * RF Registers setup *
801 \********************/
804 * ath5k_hw_rfregs_init() - Initialize RF register settings
805 * @ah: The &struct ath5k_hw
806 * @channel: The &struct ieee80211_channel
807 * @mode: One of enum ath5k_driver_mode
809 * Setup RF registers by writing RF buffer on hw. For
810 * more infos on this, check out rfbuffer.h
813 ath5k_hw_rfregs_init(struct ath5k_hw
*ah
,
814 struct ieee80211_channel
*channel
,
817 const struct ath5k_rf_reg
*rf_regs
;
818 const struct ath5k_ini_rfbuffer
*ini_rfb
;
819 const struct ath5k_gain_opt
*go
= NULL
;
820 const struct ath5k_gain_opt_step
*g_step
;
821 struct ath5k_eeprom_info
*ee
= &ah
->ah_capabilities
.cap_eeprom
;
824 int i
, obdb
= -1, bank
= -1;
826 switch (ah
->ah_radio
) {
828 rf_regs
= rf_regs_5111
;
829 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_5111
);
831 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_5111
);
832 go
= &rfgain_opt_5111
;
835 if (ah
->ah_radio_5ghz_revision
>= AR5K_SREV_RAD_5112A
) {
836 rf_regs
= rf_regs_5112a
;
837 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_5112a
);
839 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_5112a
);
841 rf_regs
= rf_regs_5112
;
842 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_5112
);
844 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_5112
);
846 go
= &rfgain_opt_5112
;
849 rf_regs
= rf_regs_2413
;
850 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_2413
);
852 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_2413
);
855 rf_regs
= rf_regs_2316
;
856 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_2316
);
858 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_2316
);
861 rf_regs
= rf_regs_5413
;
862 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_5413
);
864 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_5413
);
867 rf_regs
= rf_regs_2425
;
868 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_2425
);
870 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_2317
);
873 rf_regs
= rf_regs_2425
;
874 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_2425
);
875 if (ah
->ah_mac_srev
< AR5K_SREV_AR2417
) {
877 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_2425
);
880 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_2417
);
887 /* If it's the first time we set RF buffer, allocate
888 * ah->ah_rf_banks based on ah->ah_rf_banks_size
890 if (ah
->ah_rf_banks
== NULL
) {
891 ah
->ah_rf_banks
= kmalloc(sizeof(u32
) * ah
->ah_rf_banks_size
,
893 if (ah
->ah_rf_banks
== NULL
) {
894 ATH5K_ERR(ah
, "out of memory\n");
899 /* Copy values to modify them */
900 rfb
= ah
->ah_rf_banks
;
902 for (i
= 0; i
< ah
->ah_rf_banks_size
; i
++) {
903 if (ini_rfb
[i
].rfb_bank
>= AR5K_MAX_RF_BANKS
) {
904 ATH5K_ERR(ah
, "invalid bank\n");
908 /* Bank changed, write down the offset */
909 if (bank
!= ini_rfb
[i
].rfb_bank
) {
910 bank
= ini_rfb
[i
].rfb_bank
;
911 ah
->ah_offset
[bank
] = i
;
914 rfb
[i
] = ini_rfb
[i
].rfb_mode_data
[mode
];
917 /* Set Output and Driver bias current (OB/DB) */
918 if (channel
->band
== IEEE80211_BAND_2GHZ
) {
920 if (channel
->hw_value
== AR5K_MODE_11B
)
921 ee_mode
= AR5K_EEPROM_MODE_11B
;
923 ee_mode
= AR5K_EEPROM_MODE_11G
;
925 /* For RF511X/RF211X combination we
926 * use b_OB and b_DB parameters stored
927 * in eeprom on ee->ee_ob[ee_mode][0]
929 * For all other chips we use OB/DB for 2GHz
930 * stored in the b/g modal section just like
931 * 802.11a on ee->ee_ob[ee_mode][1] */
932 if ((ah
->ah_radio
== AR5K_RF5111
) ||
933 (ah
->ah_radio
== AR5K_RF5112
))
938 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_ob
[ee_mode
][obdb
],
939 AR5K_RF_OB_2GHZ
, true);
941 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_db
[ee_mode
][obdb
],
942 AR5K_RF_DB_2GHZ
, true);
944 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
945 } else if ((channel
->band
== IEEE80211_BAND_5GHZ
) ||
946 (ah
->ah_radio
== AR5K_RF5111
)) {
948 /* For 11a, Turbo and XR we need to choose
949 * OB/DB based on frequency range */
950 ee_mode
= AR5K_EEPROM_MODE_11A
;
951 obdb
= channel
->center_freq
>= 5725 ? 3 :
952 (channel
->center_freq
>= 5500 ? 2 :
953 (channel
->center_freq
>= 5260 ? 1 :
954 (channel
->center_freq
> 4000 ? 0 : -1)));
959 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_ob
[ee_mode
][obdb
],
960 AR5K_RF_OB_5GHZ
, true);
962 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_db
[ee_mode
][obdb
],
963 AR5K_RF_DB_5GHZ
, true);
966 g_step
= &go
->go_step
[ah
->ah_gain
.g_step_idx
];
968 /* Set turbo mode (N/A on RF5413) */
969 if ((ah
->ah_bwmode
== AR5K_BWMODE_40MHZ
) &&
970 (ah
->ah_radio
!= AR5K_RF5413
))
971 ath5k_hw_rfb_op(ah
, rf_regs
, 1, AR5K_RF_TURBO
, false);
973 /* Bank Modifications (chip-specific) */
974 if (ah
->ah_radio
== AR5K_RF5111
) {
976 /* Set gain_F settings according to current step */
977 if (channel
->hw_value
!= AR5K_MODE_11B
) {
979 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_FRAME_CTL
,
980 AR5K_PHY_FRAME_CTL_TX_CLIP
,
981 g_step
->gos_param
[0]);
983 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[1],
984 AR5K_RF_PWD_90
, true);
986 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[2],
987 AR5K_RF_PWD_84
, true);
989 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[3],
990 AR5K_RF_RFGAIN_SEL
, true);
992 /* We programmed gain_F parameters, switch back
994 ah
->ah_gain
.g_state
= AR5K_RFGAIN_ACTIVE
;
1000 ath5k_hw_rfb_op(ah
, rf_regs
, !ee
->ee_xpd
[ee_mode
],
1001 AR5K_RF_PWD_XPD
, true);
1003 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_x_gain
[ee_mode
],
1004 AR5K_RF_XPD_GAIN
, true);
1006 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_i_gain
[ee_mode
],
1007 AR5K_RF_GAIN_I
, true);
1009 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_xpd
[ee_mode
],
1010 AR5K_RF_PLO_SEL
, true);
1012 /* Tweak power detectors for half/quarter rate support */
1013 if (ah
->ah_bwmode
== AR5K_BWMODE_5MHZ
||
1014 ah
->ah_bwmode
== AR5K_BWMODE_10MHZ
) {
1017 ath5k_hw_rfb_op(ah
, rf_regs
, 0x1f,
1018 AR5K_RF_WAIT_S
, true);
1020 wait_i
= (ah
->ah_bwmode
== AR5K_BWMODE_5MHZ
) ?
1023 ath5k_hw_rfb_op(ah
, rf_regs
, wait_i
,
1024 AR5K_RF_WAIT_I
, true);
1025 ath5k_hw_rfb_op(ah
, rf_regs
, 3,
1026 AR5K_RF_MAX_TIME
, true);
1031 if (ah
->ah_radio
== AR5K_RF5112
) {
1033 /* Set gain_F settings according to current step */
1034 if (channel
->hw_value
!= AR5K_MODE_11B
) {
1036 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[0],
1037 AR5K_RF_MIXGAIN_OVR
, true);
1039 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[1],
1040 AR5K_RF_PWD_138
, true);
1042 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[2],
1043 AR5K_RF_PWD_137
, true);
1045 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[3],
1046 AR5K_RF_PWD_136
, true);
1048 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[4],
1049 AR5K_RF_PWD_132
, true);
1051 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[5],
1052 AR5K_RF_PWD_131
, true);
1054 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[6],
1055 AR5K_RF_PWD_130
, true);
1057 /* We programmed gain_F parameters, switch back
1058 * to active state */
1059 ah
->ah_gain
.g_state
= AR5K_RFGAIN_ACTIVE
;
1062 /* Bank 6/7 setup */
1064 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_xpd
[ee_mode
],
1065 AR5K_RF_XPD_SEL
, true);
1067 if (ah
->ah_radio_5ghz_revision
< AR5K_SREV_RAD_5112A
) {
1068 /* Rev. 1 supports only one xpd */
1069 ath5k_hw_rfb_op(ah
, rf_regs
,
1070 ee
->ee_x_gain
[ee_mode
],
1071 AR5K_RF_XPD_GAIN
, true);
1074 u8
*pdg_curve_to_idx
= ee
->ee_pdc_to_idx
[ee_mode
];
1075 if (ee
->ee_pd_gains
[ee_mode
] > 1) {
1076 ath5k_hw_rfb_op(ah
, rf_regs
,
1077 pdg_curve_to_idx
[0],
1078 AR5K_RF_PD_GAIN_LO
, true);
1079 ath5k_hw_rfb_op(ah
, rf_regs
,
1080 pdg_curve_to_idx
[1],
1081 AR5K_RF_PD_GAIN_HI
, true);
1083 ath5k_hw_rfb_op(ah
, rf_regs
,
1084 pdg_curve_to_idx
[0],
1085 AR5K_RF_PD_GAIN_LO
, true);
1086 ath5k_hw_rfb_op(ah
, rf_regs
,
1087 pdg_curve_to_idx
[0],
1088 AR5K_RF_PD_GAIN_HI
, true);
1091 /* Lower synth voltage on Rev 2 */
1092 if (ah
->ah_radio
== AR5K_RF5112
&&
1093 (ah
->ah_radio_5ghz_revision
& AR5K_SREV_REV
) > 0) {
1094 ath5k_hw_rfb_op(ah
, rf_regs
, 2,
1095 AR5K_RF_HIGH_VC_CP
, true);
1097 ath5k_hw_rfb_op(ah
, rf_regs
, 2,
1098 AR5K_RF_MID_VC_CP
, true);
1100 ath5k_hw_rfb_op(ah
, rf_regs
, 2,
1101 AR5K_RF_LOW_VC_CP
, true);
1103 ath5k_hw_rfb_op(ah
, rf_regs
, 2,
1104 AR5K_RF_PUSH_UP
, true);
1107 /* Decrease power consumption on 5213+ BaseBand */
1108 if (ah
->ah_phy_revision
>= AR5K_SREV_PHY_5212A
) {
1109 ath5k_hw_rfb_op(ah
, rf_regs
, 1,
1110 AR5K_RF_PAD2GND
, true);
1112 ath5k_hw_rfb_op(ah
, rf_regs
, 1,
1113 AR5K_RF_XB2_LVL
, true);
1115 ath5k_hw_rfb_op(ah
, rf_regs
, 1,
1116 AR5K_RF_XB5_LVL
, true);
1118 ath5k_hw_rfb_op(ah
, rf_regs
, 1,
1119 AR5K_RF_PWD_167
, true);
1121 ath5k_hw_rfb_op(ah
, rf_regs
, 1,
1122 AR5K_RF_PWD_166
, true);
1126 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_i_gain
[ee_mode
],
1127 AR5K_RF_GAIN_I
, true);
1129 /* Tweak power detector for half/quarter rates */
1130 if (ah
->ah_bwmode
== AR5K_BWMODE_5MHZ
||
1131 ah
->ah_bwmode
== AR5K_BWMODE_10MHZ
) {
1134 pd_delay
= (ah
->ah_bwmode
== AR5K_BWMODE_5MHZ
) ?
1137 ath5k_hw_rfb_op(ah
, rf_regs
, pd_delay
,
1138 AR5K_RF_PD_PERIOD_A
, true);
1139 ath5k_hw_rfb_op(ah
, rf_regs
, 0xf,
1140 AR5K_RF_PD_DELAY_A
, true);
1145 if (ah
->ah_radio
== AR5K_RF5413
&&
1146 channel
->band
== IEEE80211_BAND_2GHZ
) {
1148 ath5k_hw_rfb_op(ah
, rf_regs
, 1, AR5K_RF_DERBY_CHAN_SEL_MODE
,
1151 /* Set optimum value for early revisions (on pci-e chips) */
1152 if (ah
->ah_mac_srev
>= AR5K_SREV_AR5424
&&
1153 ah
->ah_mac_srev
< AR5K_SREV_AR5413
)
1154 ath5k_hw_rfb_op(ah
, rf_regs
, ath5k_hw_bitswap(6, 3),
1155 AR5K_RF_PWD_ICLOBUF_2G
, true);
1159 /* Write RF banks on hw */
1160 for (i
= 0; i
< ah
->ah_rf_banks_size
; i
++) {
1162 ath5k_hw_reg_write(ah
, rfb
[i
], ini_rfb
[i
].rfb_ctrl_register
);
1169 /**************************\
1170 PHY/RF channel functions
1171 \**************************/
1174 * ath5k_hw_rf5110_chan2athchan() - Convert channel freq on RF5110
1175 * @channel: The &struct ieee80211_channel
1177 * Map channel frequency to IEEE channel number and convert it
1178 * to an internal channel value used by the RF5110 chipset.
1181 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel
*channel
)
1185 athchan
= (ath5k_hw_bitswap(
1186 (ieee80211_frequency_to_channel(
1187 channel
->center_freq
) - 24) / 2, 5)
1188 << 1) | (1 << 6) | 0x1;
1193 * ath5k_hw_rf5110_channel() - Set channel frequency on RF5110
1194 * @ah: The &struct ath5k_hw
1195 * @channel: The &struct ieee80211_channel
1198 ath5k_hw_rf5110_channel(struct ath5k_hw
*ah
,
1199 struct ieee80211_channel
*channel
)
1204 * Set the channel and wait
1206 data
= ath5k_hw_rf5110_chan2athchan(channel
);
1207 ath5k_hw_reg_write(ah
, data
, AR5K_RF_BUFFER
);
1208 ath5k_hw_reg_write(ah
, 0, AR5K_RF_BUFFER_CONTROL_0
);
1209 usleep_range(1000, 1500);
1215 * ath5k_hw_rf5111_chan2athchan() - Handle 2GHz channels on RF5111/2111
1216 * @ieee: IEEE channel number
1217 * @athchan: The &struct ath5k_athchan_2ghz
1219 * In order to enable the RF2111 frequency converter on RF5111/2111 setups
1220 * we need to add some offsets and extra flags to the data values we pass
1221 * on to the PHY. So for every 2GHz channel this function gets called
1222 * to do the conversion.
1225 ath5k_hw_rf5111_chan2athchan(unsigned int ieee
,
1226 struct ath5k_athchan_2ghz
*athchan
)
1230 /* Cast this value to catch negative channel numbers (>= -19) */
1231 channel
= (int)ieee
;
1234 * Map 2GHz IEEE channel to 5GHz Atheros channel
1236 if (channel
<= 13) {
1237 athchan
->a2_athchan
= 115 + channel
;
1238 athchan
->a2_flags
= 0x46;
1239 } else if (channel
== 14) {
1240 athchan
->a2_athchan
= 124;
1241 athchan
->a2_flags
= 0x44;
1242 } else if (channel
>= 15 && channel
<= 26) {
1243 athchan
->a2_athchan
= ((channel
- 14) * 4) + 132;
1244 athchan
->a2_flags
= 0x46;
1252 * ath5k_hw_rf5111_channel() - Set channel frequency on RF5111/2111
1253 * @ah: The &struct ath5k_hw
1254 * @channel: The &struct ieee80211_channel
1257 ath5k_hw_rf5111_channel(struct ath5k_hw
*ah
,
1258 struct ieee80211_channel
*channel
)
1260 struct ath5k_athchan_2ghz ath5k_channel_2ghz
;
1261 unsigned int ath5k_channel
=
1262 ieee80211_frequency_to_channel(channel
->center_freq
);
1263 u32 data0
, data1
, clock
;
1267 * Set the channel on the RF5111 radio
1271 if (channel
->band
== IEEE80211_BAND_2GHZ
) {
1272 /* Map 2GHz channel to 5GHz Atheros channel ID */
1273 ret
= ath5k_hw_rf5111_chan2athchan(
1274 ieee80211_frequency_to_channel(channel
->center_freq
),
1275 &ath5k_channel_2ghz
);
1279 ath5k_channel
= ath5k_channel_2ghz
.a2_athchan
;
1280 data0
= ((ath5k_hw_bitswap(ath5k_channel_2ghz
.a2_flags
, 8) & 0xff)
1284 if (ath5k_channel
< 145 || !(ath5k_channel
& 1)) {
1286 data1
= ((ath5k_hw_bitswap(ath5k_channel
- 24, 8) & 0xff) << 2) |
1287 (clock
<< 1) | (1 << 10) | 1;
1290 data1
= ((ath5k_hw_bitswap((ath5k_channel
- 24) / 2, 8) & 0xff)
1291 << 2) | (clock
<< 1) | (1 << 10) | 1;
1294 ath5k_hw_reg_write(ah
, (data1
& 0xff) | ((data0
& 0xff) << 8),
1296 ath5k_hw_reg_write(ah
, ((data1
>> 8) & 0xff) | (data0
& 0xff00),
1297 AR5K_RF_BUFFER_CONTROL_3
);
1303 * ath5k_hw_rf5112_channel() - Set channel frequency on 5112 and newer
1304 * @ah: The &struct ath5k_hw
1305 * @channel: The &struct ieee80211_channel
1307 * On RF5112/2112 and newer we don't need to do any conversion.
1308 * We pass the frequency value after a few modifications to the
1311 * NOTE: Make sure channel frequency given is within our range or else
1312 * we might damage the chip ! Use ath5k_channel_ok before calling this one.
1315 ath5k_hw_rf5112_channel(struct ath5k_hw
*ah
,
1316 struct ieee80211_channel
*channel
)
1318 u32 data
, data0
, data1
, data2
;
1321 data
= data0
= data1
= data2
= 0;
1322 c
= channel
->center_freq
;
1324 /* My guess based on code:
1325 * 2GHz RF has 2 synth modes, one with a Local Oscillator
1326 * at 2224Hz and one with a LO at 2192Hz. IF is 1520Hz
1327 * (3040/2). data0 is used to set the PLL divider and data1
1328 * selects synth mode. */
1330 /* Channel 14 and all frequencies with 2Hz spacing
1331 * below/above (non-standard channels) */
1332 if (!((c
- 2224) % 5)) {
1333 /* Same as (c - 2224) / 5 */
1334 data0
= ((2 * (c
- 704)) - 3040) / 10;
1336 /* Channel 1 and all frequencies with 5Hz spacing
1337 * below/above (standard channels without channel 14) */
1338 } else if (!((c
- 2192) % 5)) {
1339 /* Same as (c - 2192) / 5 */
1340 data0
= ((2 * (c
- 672)) - 3040) / 10;
1345 data0
= ath5k_hw_bitswap((data0
<< 2) & 0xff, 8);
1346 /* This is more complex, we have a single synthesizer with
1347 * 4 reference clock settings (?) based on frequency spacing
1348 * and set using data2. LO is at 4800Hz and data0 is again used
1349 * to set some divider.
1351 * NOTE: There is an old atheros presentation at Stanford
1352 * that mentions a method called dual direct conversion
1353 * with 1GHz sliding IF for RF5110. Maybe that's what we
1354 * have here, or an updated version. */
1355 } else if ((c
% 5) != 2 || c
> 5435) {
1356 if (!(c
% 20) && c
>= 5120) {
1357 data0
= ath5k_hw_bitswap(((c
- 4800) / 20 << 2), 8);
1358 data2
= ath5k_hw_bitswap(3, 2);
1359 } else if (!(c
% 10)) {
1360 data0
= ath5k_hw_bitswap(((c
- 4800) / 10 << 1), 8);
1361 data2
= ath5k_hw_bitswap(2, 2);
1362 } else if (!(c
% 5)) {
1363 data0
= ath5k_hw_bitswap((c
- 4800) / 5, 8);
1364 data2
= ath5k_hw_bitswap(1, 2);
1368 data0
= ath5k_hw_bitswap((10 * (c
- 2 - 4800)) / 25 + 1, 8);
1369 data2
= ath5k_hw_bitswap(0, 2);
1372 data
= (data0
<< 4) | (data1
<< 1) | (data2
<< 2) | 0x1001;
1374 ath5k_hw_reg_write(ah
, data
& 0xff, AR5K_RF_BUFFER
);
1375 ath5k_hw_reg_write(ah
, (data
>> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5
);
1381 * ath5k_hw_rf2425_channel() - Set channel frequency on RF2425
1382 * @ah: The &struct ath5k_hw
1383 * @channel: The &struct ieee80211_channel
1385 * AR2425/2417 have a different 2GHz RF so code changes
1386 * a little bit from RF5112.
1389 ath5k_hw_rf2425_channel(struct ath5k_hw
*ah
,
1390 struct ieee80211_channel
*channel
)
1392 u32 data
, data0
, data2
;
1395 data
= data0
= data2
= 0;
1396 c
= channel
->center_freq
;
1399 data0
= ath5k_hw_bitswap((c
- 2272), 8);
1402 } else if ((c
% 5) != 2 || c
> 5435) {
1403 if (!(c
% 20) && c
< 5120)
1404 data0
= ath5k_hw_bitswap(((c
- 4800) / 20 << 2), 8);
1406 data0
= ath5k_hw_bitswap(((c
- 4800) / 10 << 1), 8);
1408 data0
= ath5k_hw_bitswap((c
- 4800) / 5, 8);
1411 data2
= ath5k_hw_bitswap(1, 2);
1413 data0
= ath5k_hw_bitswap((10 * (c
- 2 - 4800)) / 25 + 1, 8);
1414 data2
= ath5k_hw_bitswap(0, 2);
1417 data
= (data0
<< 4) | data2
<< 2 | 0x1001;
1419 ath5k_hw_reg_write(ah
, data
& 0xff, AR5K_RF_BUFFER
);
1420 ath5k_hw_reg_write(ah
, (data
>> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5
);
1426 * ath5k_hw_channel() - Set a channel on the radio chip
1427 * @ah: The &struct ath5k_hw
1428 * @channel: The &struct ieee80211_channel
1430 * This is the main function called to set a channel on the
1431 * radio chip based on the radio chip version.
1434 ath5k_hw_channel(struct ath5k_hw
*ah
,
1435 struct ieee80211_channel
*channel
)
1439 * Check bounds supported by the PHY (we don't care about regulatory
1440 * restrictions at this point).
1442 if (!ath5k_channel_ok(ah
, channel
)) {
1444 "channel frequency (%u MHz) out of supported "
1446 channel
->center_freq
);
1451 * Set the channel and wait
1453 switch (ah
->ah_radio
) {
1455 ret
= ath5k_hw_rf5110_channel(ah
, channel
);
1458 ret
= ath5k_hw_rf5111_channel(ah
, channel
);
1462 ret
= ath5k_hw_rf2425_channel(ah
, channel
);
1465 ret
= ath5k_hw_rf5112_channel(ah
, channel
);
1472 /* Set JAPAN setting for channel 14 */
1473 if (channel
->center_freq
== 2484) {
1474 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_CCKTXCTL
,
1475 AR5K_PHY_CCKTXCTL_JAPAN
);
1477 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_CCKTXCTL
,
1478 AR5K_PHY_CCKTXCTL_WORLD
);
1481 ah
->ah_current_channel
= channel
;
1492 * DOC: PHY Calibration routines
1494 * Noise floor calibration: When we tell the hardware to
1495 * perform a noise floor calibration by setting the
1496 * AR5K_PHY_AGCCTL_NF bit on AR5K_PHY_AGCCTL, it will periodically
1497 * sample-and-hold the minimum noise level seen at the antennas.
1498 * This value is then stored in a ring buffer of recently measured
1499 * noise floor values so we have a moving window of the last few
1500 * samples. The median of the values in the history is then loaded
1501 * into the hardware for its own use for RSSI and CCA measurements.
1502 * This type of calibration doesn't interfere with traffic.
1504 * AGC calibration: When we tell the hardware to perform
1505 * an AGC (Automatic Gain Control) calibration by setting the
1506 * AR5K_PHY_AGCCTL_CAL, hw disconnects the antennas and does
1507 * a calibration on the DC offsets of ADCs. During this period
1508 * rx/tx gets disabled so we have to deal with it on the driver
1511 * I/Q calibration: When we tell the hardware to perform
1512 * an I/Q calibration, it tries to correct I/Q imbalance and
1513 * fix QAM constellation by sampling data from rxed frames.
1514 * It doesn't interfere with traffic.
1516 * For more infos on AGC and I/Q calibration check out patent doc
1521 * ath5k_hw_read_measured_noise_floor() - Read measured NF from hw
1522 * @ah: The &struct ath5k_hw
1525 ath5k_hw_read_measured_noise_floor(struct ath5k_hw
*ah
)
1529 val
= ath5k_hw_reg_read(ah
, AR5K_PHY_NF
);
1530 return sign_extend32(AR5K_REG_MS(val
, AR5K_PHY_NF_MINCCA_PWR
), 8);
1534 * ath5k_hw_init_nfcal_hist() - Initialize NF calibration history buffer
1535 * @ah: The &struct ath5k_hw
1538 ath5k_hw_init_nfcal_hist(struct ath5k_hw
*ah
)
1542 ah
->ah_nfcal_hist
.index
= 0;
1543 for (i
= 0; i
< ATH5K_NF_CAL_HIST_MAX
; i
++)
1544 ah
->ah_nfcal_hist
.nfval
[i
] = AR5K_TUNE_CCA_MAX_GOOD_VALUE
;
1548 * ath5k_hw_update_nfcal_hist() - Update NF calibration history buffer
1549 * @ah: The &struct ath5k_hw
1550 * @noise_floor: The NF we got from hw
1552 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw
*ah
, s16 noise_floor
)
1554 struct ath5k_nfcal_hist
*hist
= &ah
->ah_nfcal_hist
;
1555 hist
->index
= (hist
->index
+ 1) & (ATH5K_NF_CAL_HIST_MAX
- 1);
1556 hist
->nfval
[hist
->index
] = noise_floor
;
1560 * ath5k_hw_get_median_noise_floor() - Get median NF from history buffer
1561 * @ah: The &struct ath5k_hw
1564 ath5k_hw_get_median_noise_floor(struct ath5k_hw
*ah
)
1566 s16 sort
[ATH5K_NF_CAL_HIST_MAX
];
1570 memcpy(sort
, ah
->ah_nfcal_hist
.nfval
, sizeof(sort
));
1571 for (i
= 0; i
< ATH5K_NF_CAL_HIST_MAX
- 1; i
++) {
1572 for (j
= 1; j
< ATH5K_NF_CAL_HIST_MAX
- i
; j
++) {
1573 if (sort
[j
] > sort
[j
- 1]) {
1575 sort
[j
] = sort
[j
- 1];
1580 for (i
= 0; i
< ATH5K_NF_CAL_HIST_MAX
; i
++) {
1581 ATH5K_DBG(ah
, ATH5K_DEBUG_CALIBRATE
,
1582 "cal %d:%d\n", i
, sort
[i
]);
1584 return sort
[(ATH5K_NF_CAL_HIST_MAX
- 1) / 2];
1588 * ath5k_hw_update_noise_floor() - Update NF on hardware
1589 * @ah: The &struct ath5k_hw
1591 * This is the main function we call to perform a NF calibration,
1592 * it reads NF from hardware, calculates the median and updates
1596 ath5k_hw_update_noise_floor(struct ath5k_hw
*ah
)
1598 struct ath5k_eeprom_info
*ee
= &ah
->ah_capabilities
.cap_eeprom
;
1603 /* keep last value if calibration hasn't completed */
1604 if (ath5k_hw_reg_read(ah
, AR5K_PHY_AGCCTL
) & AR5K_PHY_AGCCTL_NF
) {
1605 ATH5K_DBG(ah
, ATH5K_DEBUG_CALIBRATE
,
1606 "NF did not complete in calibration window\n");
1611 ah
->ah_cal_mask
|= AR5K_CALIBRATION_NF
;
1613 ee_mode
= ath5k_eeprom_mode_from_channel(ah
->ah_current_channel
);
1615 /* completed NF calibration, test threshold */
1616 nf
= ath5k_hw_read_measured_noise_floor(ah
);
1617 threshold
= ee
->ee_noise_floor_thr
[ee_mode
];
1619 if (nf
> threshold
) {
1620 ATH5K_DBG(ah
, ATH5K_DEBUG_CALIBRATE
,
1621 "noise floor failure detected; "
1622 "read %d, threshold %d\n",
1625 nf
= AR5K_TUNE_CCA_MAX_GOOD_VALUE
;
1628 ath5k_hw_update_nfcal_hist(ah
, nf
);
1629 nf
= ath5k_hw_get_median_noise_floor(ah
);
1631 /* load noise floor (in .5 dBm) so the hardware will use it */
1632 val
= ath5k_hw_reg_read(ah
, AR5K_PHY_NF
) & ~AR5K_PHY_NF_M
;
1633 val
|= (nf
* 2) & AR5K_PHY_NF_M
;
1634 ath5k_hw_reg_write(ah
, val
, AR5K_PHY_NF
);
1636 AR5K_REG_MASKED_BITS(ah
, AR5K_PHY_AGCCTL
, AR5K_PHY_AGCCTL_NF
,
1637 ~(AR5K_PHY_AGCCTL_NF_EN
| AR5K_PHY_AGCCTL_NF_NOUPDATE
));
1639 ath5k_hw_register_timeout(ah
, AR5K_PHY_AGCCTL
, AR5K_PHY_AGCCTL_NF
,
1643 * Load a high max CCA Power value (-50 dBm in .5 dBm units)
1644 * so that we're not capped by the median we just loaded.
1645 * This will be used as the initial value for the next noise
1646 * floor calibration.
1648 val
= (val
& ~AR5K_PHY_NF_M
) | ((-50 * 2) & AR5K_PHY_NF_M
);
1649 ath5k_hw_reg_write(ah
, val
, AR5K_PHY_NF
);
1650 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_AGCCTL
,
1651 AR5K_PHY_AGCCTL_NF_EN
|
1652 AR5K_PHY_AGCCTL_NF_NOUPDATE
|
1653 AR5K_PHY_AGCCTL_NF
);
1655 ah
->ah_noise_floor
= nf
;
1657 ah
->ah_cal_mask
&= ~AR5K_CALIBRATION_NF
;
1659 ATH5K_DBG(ah
, ATH5K_DEBUG_CALIBRATE
,
1660 "noise floor calibrated: %d\n", nf
);
1664 * ath5k_hw_rf5110_calibrate() - Perform a PHY calibration on RF5110
1665 * @ah: The &struct ath5k_hw
1666 * @channel: The &struct ieee80211_channel
1668 * Do a complete PHY calibration (AGC + NF + I/Q) on RF5110
1671 ath5k_hw_rf5110_calibrate(struct ath5k_hw
*ah
,
1672 struct ieee80211_channel
*channel
)
1674 u32 phy_sig
, phy_agc
, phy_sat
, beacon
;
1677 if (!(ah
->ah_cal_mask
& AR5K_CALIBRATION_FULL
))
1681 * Disable beacons and RX/TX queues, wait
1683 AR5K_REG_ENABLE_BITS(ah
, AR5K_DIAG_SW_5210
,
1684 AR5K_DIAG_SW_DIS_TX_5210
| AR5K_DIAG_SW_DIS_RX_5210
);
1685 beacon
= ath5k_hw_reg_read(ah
, AR5K_BEACON_5210
);
1686 ath5k_hw_reg_write(ah
, beacon
& ~AR5K_BEACON_ENABLE
, AR5K_BEACON_5210
);
1688 usleep_range(2000, 2500);
1691 * Set the channel (with AGC turned off)
1693 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_AGC
, AR5K_PHY_AGC_DISABLE
);
1695 ret
= ath5k_hw_channel(ah
, channel
);
1698 * Activate PHY and wait
1700 ath5k_hw_reg_write(ah
, AR5K_PHY_ACT_ENABLE
, AR5K_PHY_ACT
);
1701 usleep_range(1000, 1500);
1703 AR5K_REG_DISABLE_BITS(ah
, AR5K_PHY_AGC
, AR5K_PHY_AGC_DISABLE
);
1709 * Calibrate the radio chip
1712 /* Remember normal state */
1713 phy_sig
= ath5k_hw_reg_read(ah
, AR5K_PHY_SIG
);
1714 phy_agc
= ath5k_hw_reg_read(ah
, AR5K_PHY_AGCCOARSE
);
1715 phy_sat
= ath5k_hw_reg_read(ah
, AR5K_PHY_ADCSAT
);
1717 /* Update radio registers */
1718 ath5k_hw_reg_write(ah
, (phy_sig
& ~(AR5K_PHY_SIG_FIRPWR
)) |
1719 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR
), AR5K_PHY_SIG
);
1721 ath5k_hw_reg_write(ah
, (phy_agc
& ~(AR5K_PHY_AGCCOARSE_HI
|
1722 AR5K_PHY_AGCCOARSE_LO
)) |
1723 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI
) |
1724 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO
), AR5K_PHY_AGCCOARSE
);
1726 ath5k_hw_reg_write(ah
, (phy_sat
& ~(AR5K_PHY_ADCSAT_ICNT
|
1727 AR5K_PHY_ADCSAT_THR
)) |
1728 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT
) |
1729 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR
), AR5K_PHY_ADCSAT
);
1733 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_AGC
, AR5K_PHY_AGC_DISABLE
);
1735 ath5k_hw_reg_write(ah
, AR5K_PHY_RFSTG_DISABLE
, AR5K_PHY_RFSTG
);
1736 AR5K_REG_DISABLE_BITS(ah
, AR5K_PHY_AGC
, AR5K_PHY_AGC_DISABLE
);
1738 usleep_range(1000, 1500);
1741 * Enable calibration and wait until completion
1743 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_AGCCTL
, AR5K_PHY_AGCCTL_CAL
);
1745 ret
= ath5k_hw_register_timeout(ah
, AR5K_PHY_AGCCTL
,
1746 AR5K_PHY_AGCCTL_CAL
, 0, false);
1748 /* Reset to normal state */
1749 ath5k_hw_reg_write(ah
, phy_sig
, AR5K_PHY_SIG
);
1750 ath5k_hw_reg_write(ah
, phy_agc
, AR5K_PHY_AGCCOARSE
);
1751 ath5k_hw_reg_write(ah
, phy_sat
, AR5K_PHY_ADCSAT
);
1754 ATH5K_ERR(ah
, "calibration timeout (%uMHz)\n",
1755 channel
->center_freq
);
1760 * Re-enable RX/TX and beacons
1762 AR5K_REG_DISABLE_BITS(ah
, AR5K_DIAG_SW_5210
,
1763 AR5K_DIAG_SW_DIS_TX_5210
| AR5K_DIAG_SW_DIS_RX_5210
);
1764 ath5k_hw_reg_write(ah
, beacon
, AR5K_BEACON_5210
);
1770 * ath5k_hw_rf511x_iq_calibrate() - Perform I/Q calibration on RF5111 and newer
1771 * @ah: The &struct ath5k_hw
1774 ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw
*ah
)
1777 s32 iq_corr
, i_coff
, i_coffd
, q_coff
, q_coffd
;
1780 /* Skip if I/Q calibration is not needed or if it's still running */
1781 if (!ah
->ah_iq_cal_needed
)
1783 else if (ath5k_hw_reg_read(ah
, AR5K_PHY_IQ
) & AR5K_PHY_IQ_RUN
) {
1784 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_CALIBRATE
,
1785 "I/Q calibration still running");
1789 /* Calibration has finished, get the results and re-run */
1791 /* Work around for empty results which can apparently happen on 5212:
1792 * Read registers up to 10 times until we get both i_pr and q_pwr */
1793 for (i
= 0; i
<= 10; i
++) {
1794 iq_corr
= ath5k_hw_reg_read(ah
, AR5K_PHY_IQRES_CAL_CORR
);
1795 i_pwr
= ath5k_hw_reg_read(ah
, AR5K_PHY_IQRES_CAL_PWR_I
);
1796 q_pwr
= ath5k_hw_reg_read(ah
, AR5K_PHY_IQRES_CAL_PWR_Q
);
1797 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_CALIBRATE
,
1798 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr
, i_pwr
, q_pwr
);
1803 i_coffd
= ((i_pwr
>> 1) + (q_pwr
>> 1)) >> 7;
1805 if (ah
->ah_version
== AR5K_AR5211
)
1806 q_coffd
= q_pwr
>> 6;
1808 q_coffd
= q_pwr
>> 7;
1810 /* In case i_coffd became zero, cancel calibration
1811 * not only it's too small, it'll also result a divide
1812 * by zero later on. */
1813 if (i_coffd
== 0 || q_coffd
< 2)
1816 /* Protect against loss of sign bits */
1818 i_coff
= (-iq_corr
) / i_coffd
;
1819 i_coff
= clamp(i_coff
, -32, 31); /* signed 6 bit */
1821 if (ah
->ah_version
== AR5K_AR5211
)
1822 q_coff
= (i_pwr
/ q_coffd
) - 64;
1824 q_coff
= (i_pwr
/ q_coffd
) - 128;
1825 q_coff
= clamp(q_coff
, -16, 15); /* signed 5 bit */
1827 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_CALIBRATE
,
1828 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)",
1829 i_coff
, q_coff
, i_coffd
, q_coffd
);
1831 /* Commit new I/Q values (set enable bit last to match HAL sources) */
1832 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_IQ
, AR5K_PHY_IQ_CORR_Q_I_COFF
, i_coff
);
1833 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_IQ
, AR5K_PHY_IQ_CORR_Q_Q_COFF
, q_coff
);
1834 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_IQ
, AR5K_PHY_IQ_CORR_ENABLE
);
1836 /* Re-enable calibration -if we don't we'll commit
1837 * the same values again and again */
1838 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_IQ
,
1839 AR5K_PHY_IQ_CAL_NUM_LOG_MAX
, 15);
1840 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_IQ
, AR5K_PHY_IQ_RUN
);
1846 * ath5k_hw_phy_calibrate() - Perform a PHY calibration
1847 * @ah: The &struct ath5k_hw
1848 * @channel: The &struct ieee80211_channel
1850 * The main function we call from above to perform
1851 * a short or full PHY calibration based on RF chip
1852 * and current channel
1855 ath5k_hw_phy_calibrate(struct ath5k_hw
*ah
,
1856 struct ieee80211_channel
*channel
)
1860 if (ah
->ah_radio
== AR5K_RF5110
)
1861 return ath5k_hw_rf5110_calibrate(ah
, channel
);
1863 ret
= ath5k_hw_rf511x_iq_calibrate(ah
);
1865 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_CALIBRATE
,
1866 "No I/Q correction performed (%uMHz)\n",
1867 channel
->center_freq
);
1869 /* Happens all the time if there is not much
1870 * traffic, consider it normal behaviour. */
1874 /* On full calibration request a PAPD probe for
1875 * gainf calibration if needed */
1876 if ((ah
->ah_cal_mask
& AR5K_CALIBRATION_FULL
) &&
1877 (ah
->ah_radio
== AR5K_RF5111
||
1878 ah
->ah_radio
== AR5K_RF5112
) &&
1879 channel
->hw_value
!= AR5K_MODE_11B
)
1880 ath5k_hw_request_rfgain_probe(ah
);
1882 /* Update noise floor */
1883 if (!(ah
->ah_cal_mask
& AR5K_CALIBRATION_NF
))
1884 ath5k_hw_update_noise_floor(ah
);
1890 /***************************\
1891 * Spur mitigation functions *
1892 \***************************/
1895 * ath5k_hw_set_spur_mitigation_filter() - Configure SPUR filter
1896 * @ah: The &struct ath5k_hw
1897 * @channel: The &struct ieee80211_channel
1899 * This function gets called during PHY initialization to
1900 * configure the spur filter for the given channel. Spur is noise
1901 * generated due to "reflection" effects, for more information on this
1902 * method check out patent US7643810
1905 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw
*ah
,
1906 struct ieee80211_channel
*channel
)
1908 struct ath5k_eeprom_info
*ee
= &ah
->ah_capabilities
.cap_eeprom
;
1909 u32 mag_mask
[4] = {0, 0, 0, 0};
1910 u32 pilot_mask
[2] = {0, 0};
1911 /* Note: fbin values are scaled up by 2 */
1912 u16 spur_chan_fbin
, chan_fbin
, symbol_width
, spur_detection_window
;
1913 s32 spur_delta_phase
, spur_freq_sigma_delta
;
1914 s32 spur_offset
, num_symbols_x16
;
1915 u8 num_symbol_offsets
, i
, freq_band
;
1917 /* Convert current frequency to fbin value (the same way channels
1918 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale
1919 * up by 2 so we can compare it later */
1920 if (channel
->band
== IEEE80211_BAND_2GHZ
) {
1921 chan_fbin
= (channel
->center_freq
- 2300) * 10;
1922 freq_band
= AR5K_EEPROM_BAND_2GHZ
;
1924 chan_fbin
= (channel
->center_freq
- 4900) * 10;
1925 freq_band
= AR5K_EEPROM_BAND_5GHZ
;
1928 /* Check if any spur_chan_fbin from EEPROM is
1929 * within our current channel's spur detection range */
1930 spur_chan_fbin
= AR5K_EEPROM_NO_SPUR
;
1931 spur_detection_window
= AR5K_SPUR_CHAN_WIDTH
;
1932 /* XXX: Half/Quarter channels ?*/
1933 if (ah
->ah_bwmode
== AR5K_BWMODE_40MHZ
)
1934 spur_detection_window
*= 2;
1936 for (i
= 0; i
< AR5K_EEPROM_N_SPUR_CHANS
; i
++) {
1937 spur_chan_fbin
= ee
->ee_spur_chans
[i
][freq_band
];
1939 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag
1940 * so it's zero if we got nothing from EEPROM */
1941 if (spur_chan_fbin
== AR5K_EEPROM_NO_SPUR
) {
1942 spur_chan_fbin
&= AR5K_EEPROM_SPUR_CHAN_MASK
;
1946 if ((chan_fbin
- spur_detection_window
<=
1947 (spur_chan_fbin
& AR5K_EEPROM_SPUR_CHAN_MASK
)) &&
1948 (chan_fbin
+ spur_detection_window
>=
1949 (spur_chan_fbin
& AR5K_EEPROM_SPUR_CHAN_MASK
))) {
1950 spur_chan_fbin
&= AR5K_EEPROM_SPUR_CHAN_MASK
;
1955 /* We need to enable spur filter for this channel */
1956 if (spur_chan_fbin
) {
1957 spur_offset
= spur_chan_fbin
- chan_fbin
;
1960 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21
1961 * spur_delta_phase -> spur_offset / chip_freq << 11
1962 * Note: Both values have 100Hz resolution
1964 switch (ah
->ah_bwmode
) {
1965 case AR5K_BWMODE_40MHZ
:
1966 /* Both sample_freq and chip_freq are 80MHz */
1967 spur_delta_phase
= (spur_offset
<< 16) / 25;
1968 spur_freq_sigma_delta
= (spur_delta_phase
>> 10);
1969 symbol_width
= AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz
* 2;
1971 case AR5K_BWMODE_10MHZ
:
1972 /* Both sample_freq and chip_freq are 20MHz (?) */
1973 spur_delta_phase
= (spur_offset
<< 18) / 25;
1974 spur_freq_sigma_delta
= (spur_delta_phase
>> 10);
1975 symbol_width
= AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz
/ 2;
1976 case AR5K_BWMODE_5MHZ
:
1977 /* Both sample_freq and chip_freq are 10MHz (?) */
1978 spur_delta_phase
= (spur_offset
<< 19) / 25;
1979 spur_freq_sigma_delta
= (spur_delta_phase
>> 10);
1980 symbol_width
= AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz
/ 4;
1982 if (channel
->band
== IEEE80211_BAND_5GHZ
) {
1983 /* Both sample_freq and chip_freq are 40MHz */
1984 spur_delta_phase
= (spur_offset
<< 17) / 25;
1985 spur_freq_sigma_delta
=
1986 (spur_delta_phase
>> 10);
1988 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz
;
1990 /* sample_freq -> 40MHz chip_freq -> 44MHz
1991 * (for b compatibility) */
1992 spur_delta_phase
= (spur_offset
<< 17) / 25;
1993 spur_freq_sigma_delta
=
1994 (spur_offset
<< 8) / 55;
1996 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz
;
2001 /* Calculate pilot and magnitude masks */
2003 /* Scale up spur_offset by 1000 to switch to 100HZ resolution
2004 * and divide by symbol_width to find how many symbols we have
2005 * Note: number of symbols is scaled up by 16 */
2006 num_symbols_x16
= ((spur_offset
* 1000) << 4) / symbol_width
;
2008 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */
2009 if (!(num_symbols_x16
& 0xF))
2011 num_symbol_offsets
= 3;
2014 num_symbol_offsets
= 4;
2016 for (i
= 0; i
< num_symbol_offsets
; i
++) {
2018 /* Calculate pilot mask */
2020 (num_symbols_x16
/ 16) + i
+ 25;
2022 /* Pilot magnitude mask seems to be a way to
2023 * declare the boundaries for our detection
2024 * window or something, it's 2 for the middle
2025 * value(s) where the symbol is expected to be
2026 * and 1 on the boundary values */
2028 (i
== 0 || i
== (num_symbol_offsets
- 1))
2031 if (curr_sym_off
>= 0 && curr_sym_off
<= 32) {
2032 if (curr_sym_off
<= 25)
2033 pilot_mask
[0] |= 1 << curr_sym_off
;
2034 else if (curr_sym_off
>= 27)
2035 pilot_mask
[0] |= 1 << (curr_sym_off
- 1);
2036 } else if (curr_sym_off
>= 33 && curr_sym_off
<= 52)
2037 pilot_mask
[1] |= 1 << (curr_sym_off
- 33);
2039 /* Calculate magnitude mask (for viterbi decoder) */
2040 if (curr_sym_off
>= -1 && curr_sym_off
<= 14)
2042 plt_mag_map
<< (curr_sym_off
+ 1) * 2;
2043 else if (curr_sym_off
>= 15 && curr_sym_off
<= 30)
2045 plt_mag_map
<< (curr_sym_off
- 15) * 2;
2046 else if (curr_sym_off
>= 31 && curr_sym_off
<= 46)
2048 plt_mag_map
<< (curr_sym_off
- 31) * 2;
2049 else if (curr_sym_off
>= 47 && curr_sym_off
<= 53)
2051 plt_mag_map
<< (curr_sym_off
- 47) * 2;
2055 /* Write settings on hw to enable spur filter */
2056 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_BIN_MASK_CTL
,
2057 AR5K_PHY_BIN_MASK_CTL_RATE
, 0xff);
2058 /* XXX: Self correlator also ? */
2059 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_IQ
,
2060 AR5K_PHY_IQ_PILOT_MASK_EN
|
2061 AR5K_PHY_IQ_CHAN_MASK_EN
|
2062 AR5K_PHY_IQ_SPUR_FILT_EN
);
2064 /* Set delta phase and freq sigma delta */
2065 ath5k_hw_reg_write(ah
,
2066 AR5K_REG_SM(spur_delta_phase
,
2067 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE
) |
2068 AR5K_REG_SM(spur_freq_sigma_delta
,
2069 AR5K_PHY_TIMING_11_SPUR_FREQ_SD
) |
2070 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC
,
2071 AR5K_PHY_TIMING_11
);
2073 /* Write pilot masks */
2074 ath5k_hw_reg_write(ah
, pilot_mask
[0], AR5K_PHY_TIMING_7
);
2075 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_TIMING_8
,
2076 AR5K_PHY_TIMING_8_PILOT_MASK_2
,
2079 ath5k_hw_reg_write(ah
, pilot_mask
[0], AR5K_PHY_TIMING_9
);
2080 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_TIMING_10
,
2081 AR5K_PHY_TIMING_10_PILOT_MASK_2
,
2084 /* Write magnitude masks */
2085 ath5k_hw_reg_write(ah
, mag_mask
[0], AR5K_PHY_BIN_MASK_1
);
2086 ath5k_hw_reg_write(ah
, mag_mask
[1], AR5K_PHY_BIN_MASK_2
);
2087 ath5k_hw_reg_write(ah
, mag_mask
[2], AR5K_PHY_BIN_MASK_3
);
2088 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_BIN_MASK_CTL
,
2089 AR5K_PHY_BIN_MASK_CTL_MASK_4
,
2092 ath5k_hw_reg_write(ah
, mag_mask
[0], AR5K_PHY_BIN_MASK2_1
);
2093 ath5k_hw_reg_write(ah
, mag_mask
[1], AR5K_PHY_BIN_MASK2_2
);
2094 ath5k_hw_reg_write(ah
, mag_mask
[2], AR5K_PHY_BIN_MASK2_3
);
2095 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_BIN_MASK2_4
,
2096 AR5K_PHY_BIN_MASK2_4_MASK_4
,
2099 } else if (ath5k_hw_reg_read(ah
, AR5K_PHY_IQ
) &
2100 AR5K_PHY_IQ_SPUR_FILT_EN
) {
2101 /* Clean up spur mitigation settings and disable filter */
2102 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_BIN_MASK_CTL
,
2103 AR5K_PHY_BIN_MASK_CTL_RATE
, 0);
2104 AR5K_REG_DISABLE_BITS(ah
, AR5K_PHY_IQ
,
2105 AR5K_PHY_IQ_PILOT_MASK_EN
|
2106 AR5K_PHY_IQ_CHAN_MASK_EN
|
2107 AR5K_PHY_IQ_SPUR_FILT_EN
);
2108 ath5k_hw_reg_write(ah
, 0, AR5K_PHY_TIMING_11
);
2110 /* Clear pilot masks */
2111 ath5k_hw_reg_write(ah
, 0, AR5K_PHY_TIMING_7
);
2112 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_TIMING_8
,
2113 AR5K_PHY_TIMING_8_PILOT_MASK_2
,
2116 ath5k_hw_reg_write(ah
, 0, AR5K_PHY_TIMING_9
);
2117 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_TIMING_10
,
2118 AR5K_PHY_TIMING_10_PILOT_MASK_2
,
2121 /* Clear magnitude masks */
2122 ath5k_hw_reg_write(ah
, 0, AR5K_PHY_BIN_MASK_1
);
2123 ath5k_hw_reg_write(ah
, 0, AR5K_PHY_BIN_MASK_2
);
2124 ath5k_hw_reg_write(ah
, 0, AR5K_PHY_BIN_MASK_3
);
2125 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_BIN_MASK_CTL
,
2126 AR5K_PHY_BIN_MASK_CTL_MASK_4
,
2129 ath5k_hw_reg_write(ah
, 0, AR5K_PHY_BIN_MASK2_1
);
2130 ath5k_hw_reg_write(ah
, 0, AR5K_PHY_BIN_MASK2_2
);
2131 ath5k_hw_reg_write(ah
, 0, AR5K_PHY_BIN_MASK2_3
);
2132 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_BIN_MASK2_4
,
2133 AR5K_PHY_BIN_MASK2_4_MASK_4
,
2144 * DOC: Antenna control
2146 * Hw supports up to 14 antennas ! I haven't found any card that implements
2147 * that. The maximum number of antennas I've seen is up to 4 (2 for 2GHz and 2
2148 * for 5GHz). Antenna 1 (MAIN) should be omnidirectional, 2 (AUX)
2149 * omnidirectional or sectorial and antennas 3-14 sectorial (or directional).
2151 * We can have a single antenna for RX and multiple antennas for TX.
2152 * RX antenna is our "default" antenna (usually antenna 1) set on
2153 * DEFAULT_ANTENNA register and TX antenna is set on each TX control descriptor
2154 * (0 for automatic selection, 1 - 14 antenna number).
2156 * We can let hw do all the work doing fast antenna diversity for both
2157 * tx and rx or we can do things manually. Here are the options we have
2158 * (all are bits of STA_ID1 register):
2160 * AR5K_STA_ID1_DEFAULT_ANTENNA -> When 0 is set as the TX antenna on TX
2161 * control descriptor, use the default antenna to transmit or else use the last
2162 * antenna on which we received an ACK.
2164 * AR5K_STA_ID1_DESC_ANTENNA -> Update default antenna after each TX frame to
2165 * the antenna on which we got the ACK for that frame.
2167 * AR5K_STA_ID1_RTS_DEF_ANTENNA -> Use default antenna for RTS or else use the
2168 * one on the TX descriptor.
2170 * AR5K_STA_ID1_SELFGEN_DEF_ANT -> Use default antenna for self generated frames
2171 * (ACKs etc), or else use current antenna (the one we just used for TX).
2173 * Using the above we support the following scenarios:
2175 * AR5K_ANTMODE_DEFAULT -> Hw handles antenna diversity etc automatically
2177 * AR5K_ANTMODE_FIXED_A -> Only antenna A (MAIN) is present
2179 * AR5K_ANTMODE_FIXED_B -> Only antenna B (AUX) is present
2181 * AR5K_ANTMODE_SINGLE_AP -> Sta locked on a single ap
2183 * AR5K_ANTMODE_SECTOR_AP -> AP with tx antenna set on tx desc
2185 * AR5K_ANTMODE_SECTOR_STA -> STA with tx antenna set on tx desc
2187 * AR5K_ANTMODE_DEBUG Debug mode -A -> Rx, B-> Tx-
2189 * Also note that when setting antenna to F on tx descriptor card inverts
2190 * current tx antenna.
2194 * ath5k_hw_set_def_antenna() - Set default rx antenna on AR5211/5212 and newer
2195 * @ah: The &struct ath5k_hw
2196 * @ant: Antenna number
2199 ath5k_hw_set_def_antenna(struct ath5k_hw
*ah
, u8 ant
)
2201 if (ah
->ah_version
!= AR5K_AR5210
)
2202 ath5k_hw_reg_write(ah
, ant
& 0x7, AR5K_DEFAULT_ANTENNA
);
2206 * ath5k_hw_set_fast_div() - Enable/disable fast rx antenna diversity
2207 * @ah: The &struct ath5k_hw
2208 * @ee_mode: One of enum ath5k_driver_mode
2209 * @enable: True to enable, false to disable
2212 ath5k_hw_set_fast_div(struct ath5k_hw
*ah
, u8 ee_mode
, bool enable
)
2215 case AR5K_EEPROM_MODE_11G
:
2216 /* XXX: This is set to
2217 * disabled on initvals !!! */
2218 case AR5K_EEPROM_MODE_11A
:
2220 AR5K_REG_DISABLE_BITS(ah
, AR5K_PHY_AGCCTL
,
2221 AR5K_PHY_AGCCTL_OFDM_DIV_DIS
);
2223 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_AGCCTL
,
2224 AR5K_PHY_AGCCTL_OFDM_DIV_DIS
);
2226 case AR5K_EEPROM_MODE_11B
:
2227 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_AGCCTL
,
2228 AR5K_PHY_AGCCTL_OFDM_DIV_DIS
);
2235 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_RESTART
,
2236 AR5K_PHY_RESTART_DIV_GC
, 4);
2238 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_FAST_ANT_DIV
,
2239 AR5K_PHY_FAST_ANT_DIV_EN
);
2241 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_RESTART
,
2242 AR5K_PHY_RESTART_DIV_GC
, 0);
2244 AR5K_REG_DISABLE_BITS(ah
, AR5K_PHY_FAST_ANT_DIV
,
2245 AR5K_PHY_FAST_ANT_DIV_EN
);
2250 * ath5k_hw_set_antenna_switch() - Set up antenna switch table
2251 * @ah: The &struct ath5k_hw
2252 * @ee_mode: One of enum ath5k_driver_mode
2254 * Switch table comes from EEPROM and includes information on controlling
2255 * the 2 antenna RX attenuators
2258 ath5k_hw_set_antenna_switch(struct ath5k_hw
*ah
, u8 ee_mode
)
2263 * In case a fixed antenna was set as default
2264 * use the same switch table twice.
2266 if (ah
->ah_ant_mode
== AR5K_ANTMODE_FIXED_A
)
2267 ant0
= ant1
= AR5K_ANT_SWTABLE_A
;
2268 else if (ah
->ah_ant_mode
== AR5K_ANTMODE_FIXED_B
)
2269 ant0
= ant1
= AR5K_ANT_SWTABLE_B
;
2271 ant0
= AR5K_ANT_SWTABLE_A
;
2272 ant1
= AR5K_ANT_SWTABLE_B
;
2275 /* Set antenna idle switch table */
2276 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_ANT_CTL
,
2277 AR5K_PHY_ANT_CTL_SWTABLE_IDLE
,
2278 (ah
->ah_ant_ctl
[ee_mode
][AR5K_ANT_CTL
] |
2279 AR5K_PHY_ANT_CTL_TXRX_EN
));
2281 /* Set antenna switch tables */
2282 ath5k_hw_reg_write(ah
, ah
->ah_ant_ctl
[ee_mode
][ant0
],
2283 AR5K_PHY_ANT_SWITCH_TABLE_0
);
2284 ath5k_hw_reg_write(ah
, ah
->ah_ant_ctl
[ee_mode
][ant1
],
2285 AR5K_PHY_ANT_SWITCH_TABLE_1
);
2289 * ath5k_hw_set_antenna_mode() - Set antenna operating mode
2290 * @ah: The &struct ath5k_hw
2291 * @ant_mode: One of enum ath5k_ant_mode
2294 ath5k_hw_set_antenna_mode(struct ath5k_hw
*ah
, u8 ant_mode
)
2296 struct ieee80211_channel
*channel
= ah
->ah_current_channel
;
2297 bool use_def_for_tx
, update_def_on_tx
, use_def_for_rts
, fast_div
;
2298 bool use_def_for_sg
;
2303 /* if channel is not initialized yet we can't set the antennas
2304 * so just store the mode. it will be set on the next reset */
2305 if (channel
== NULL
) {
2306 ah
->ah_ant_mode
= ant_mode
;
2310 def_ant
= ah
->ah_def_ant
;
2312 ee_mode
= ath5k_eeprom_mode_from_channel(channel
);
2315 "invalid channel: %d\n", channel
->center_freq
);
2320 case AR5K_ANTMODE_DEFAULT
:
2322 use_def_for_tx
= false;
2323 update_def_on_tx
= false;
2324 use_def_for_rts
= false;
2325 use_def_for_sg
= false;
2328 case AR5K_ANTMODE_FIXED_A
:
2331 use_def_for_tx
= true;
2332 update_def_on_tx
= false;
2333 use_def_for_rts
= true;
2334 use_def_for_sg
= true;
2337 case AR5K_ANTMODE_FIXED_B
:
2340 use_def_for_tx
= true;
2341 update_def_on_tx
= false;
2342 use_def_for_rts
= true;
2343 use_def_for_sg
= true;
2346 case AR5K_ANTMODE_SINGLE_AP
:
2347 def_ant
= 1; /* updated on tx */
2349 use_def_for_tx
= true;
2350 update_def_on_tx
= true;
2351 use_def_for_rts
= true;
2352 use_def_for_sg
= true;
2355 case AR5K_ANTMODE_SECTOR_AP
:
2356 tx_ant
= 1; /* variable */
2357 use_def_for_tx
= false;
2358 update_def_on_tx
= false;
2359 use_def_for_rts
= true;
2360 use_def_for_sg
= false;
2363 case AR5K_ANTMODE_SECTOR_STA
:
2364 tx_ant
= 1; /* variable */
2365 use_def_for_tx
= true;
2366 update_def_on_tx
= false;
2367 use_def_for_rts
= true;
2368 use_def_for_sg
= false;
2371 case AR5K_ANTMODE_DEBUG
:
2374 use_def_for_tx
= false;
2375 update_def_on_tx
= false;
2376 use_def_for_rts
= false;
2377 use_def_for_sg
= false;
2384 ah
->ah_tx_ant
= tx_ant
;
2385 ah
->ah_ant_mode
= ant_mode
;
2386 ah
->ah_def_ant
= def_ant
;
2388 sta_id1
|= use_def_for_tx
? AR5K_STA_ID1_DEFAULT_ANTENNA
: 0;
2389 sta_id1
|= update_def_on_tx
? AR5K_STA_ID1_DESC_ANTENNA
: 0;
2390 sta_id1
|= use_def_for_rts
? AR5K_STA_ID1_RTS_DEF_ANTENNA
: 0;
2391 sta_id1
|= use_def_for_sg
? AR5K_STA_ID1_SELFGEN_DEF_ANT
: 0;
2393 AR5K_REG_DISABLE_BITS(ah
, AR5K_STA_ID1
, AR5K_STA_ID1_ANTENNA_SETTINGS
);
2396 AR5K_REG_ENABLE_BITS(ah
, AR5K_STA_ID1
, sta_id1
);
2398 ath5k_hw_set_antenna_switch(ah
, ee_mode
);
2399 /* Note: set diversity before default antenna
2400 * because it won't work correctly */
2401 ath5k_hw_set_fast_div(ah
, ee_mode
, fast_div
);
2402 ath5k_hw_set_def_antenna(ah
, def_ant
);
2415 * ath5k_get_interpolated_value() - Get interpolated Y val between two points
2416 * @target: X value of the middle point
2417 * @x_left: X value of the left point
2418 * @x_right: X value of the right point
2419 * @y_left: Y value of the left point
2420 * @y_right: Y value of the right point
2423 ath5k_get_interpolated_value(s16 target
, s16 x_left
, s16 x_right
,
2424 s16 y_left
, s16 y_right
)
2428 /* Avoid divide by zero and skip interpolation
2429 * if we have the same point */
2430 if ((x_left
== x_right
) || (y_left
== y_right
))
2434 * Since we use ints and not fps, we need to scale up in
2435 * order to get a sane ratio value (or else we 'll eg. get
2436 * always 1 instead of 1.25, 1.75 etc). We scale up by 100
2437 * to have some accuracy both for 0.5 and 0.25 steps.
2439 ratio
= ((100 * y_right
- 100 * y_left
) / (x_right
- x_left
));
2441 /* Now scale down to be in range */
2442 result
= y_left
+ (ratio
* (target
- x_left
) / 100);
2448 * ath5k_get_linear_pcdac_min() - Find vertical boundary (min pwr) for the
2449 * linear PCDAC curve
2450 * @stepL: Left array with y values (pcdac steps)
2451 * @stepR: Right array with y values (pcdac steps)
2452 * @pwrL: Left array with x values (power steps)
2453 * @pwrR: Right array with x values (power steps)
2455 * Since we have the top of the curve and we draw the line below
2456 * until we reach 1 (1 pcdac step) we need to know which point
2457 * (x value) that is so that we don't go below x axis and have negative
2458 * pcdac values when creating the curve, or fill the table with zeros.
2461 ath5k_get_linear_pcdac_min(const u8
*stepL
, const u8
*stepR
,
2462 const s16
*pwrL
, const s16
*pwrR
)
2465 s16 min_pwrL
, min_pwrR
;
2468 /* Some vendors write the same pcdac value twice !!! */
2469 if (stepL
[0] == stepL
[1] || stepR
[0] == stepR
[1])
2470 return max(pwrL
[0], pwrR
[0]);
2472 if (pwrL
[0] == pwrL
[1])
2478 tmp
= (s8
) ath5k_get_interpolated_value(pwr_i
,
2480 stepL
[0], stepL
[1]);
2486 if (pwrR
[0] == pwrR
[1])
2492 tmp
= (s8
) ath5k_get_interpolated_value(pwr_i
,
2494 stepR
[0], stepR
[1]);
2500 /* Keep the right boundary so that it works for both curves */
2501 return max(min_pwrL
, min_pwrR
);
2505 * ath5k_create_power_curve() - Create a Power to PDADC or PCDAC curve
2506 * @pmin: Minimum power value (xmin)
2507 * @pmax: Maximum power value (xmax)
2508 * @pwr: Array of power steps (x values)
2509 * @vpd: Array of matching PCDAC/PDADC steps (y values)
2510 * @num_points: Number of provided points
2511 * @vpd_table: Array to fill with the full PCDAC/PDADC values (y values)
2512 * @type: One of enum ath5k_powertable_type (eeprom.h)
2514 * Interpolate (pwr,vpd) points to create a Power to PDADC or a
2515 * Power to PCDAC curve.
2517 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC
2518 * steps (offsets) on y axis. Power can go up to 31.5dB and max
2519 * PCDAC/PDADC step for each curve is 64 but we can write more than
2520 * one curves on hw so we can go up to 128 (which is the max step we
2521 * can write on the final table).
2523 * We write y values (PCDAC/PDADC steps) on hw.
2526 ath5k_create_power_curve(s16 pmin
, s16 pmax
,
2527 const s16
*pwr
, const u8
*vpd
,
2529 u8
*vpd_table
, u8 type
)
2531 u8 idx
[2] = { 0, 1 };
2532 s16 pwr_i
= 2 * pmin
;
2538 /* We want the whole line, so adjust boundaries
2539 * to cover the entire power range. Note that
2540 * power values are already 0.25dB so no need
2541 * to multiply pwr_i by 2 */
2542 if (type
== AR5K_PWRTABLE_LINEAR_PCDAC
) {
2548 /* Find surrounding turning points (TPs)
2549 * and interpolate between them */
2550 for (i
= 0; (i
<= (u16
) (pmax
- pmin
)) &&
2551 (i
< AR5K_EEPROM_POWER_TABLE_SIZE
); i
++) {
2553 /* We passed the right TP, move to the next set of TPs
2554 * if we pass the last TP, extrapolate above using the last
2555 * two TPs for ratio */
2556 if ((pwr_i
> pwr
[idx
[1]]) && (idx
[1] < num_points
- 1)) {
2561 vpd_table
[i
] = (u8
) ath5k_get_interpolated_value(pwr_i
,
2562 pwr
[idx
[0]], pwr
[idx
[1]],
2563 vpd
[idx
[0]], vpd
[idx
[1]]);
2565 /* Increase by 0.5dB
2566 * (0.25 dB units) */
2572 * ath5k_get_chan_pcal_surrounding_piers() - Get surrounding calibration piers
2573 * for a given channel.
2574 * @ah: The &struct ath5k_hw
2575 * @channel: The &struct ieee80211_channel
2576 * @pcinfo_l: The &struct ath5k_chan_pcal_info to put the left cal. pier
2577 * @pcinfo_r: The &struct ath5k_chan_pcal_info to put the right cal. pier
2579 * Get the surrounding per-channel power calibration piers
2580 * for a given frequency so that we can interpolate between
2581 * them and come up with an appropriate dataset for our current
2585 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw
*ah
,
2586 struct ieee80211_channel
*channel
,
2587 struct ath5k_chan_pcal_info
**pcinfo_l
,
2588 struct ath5k_chan_pcal_info
**pcinfo_r
)
2590 struct ath5k_eeprom_info
*ee
= &ah
->ah_capabilities
.cap_eeprom
;
2591 struct ath5k_chan_pcal_info
*pcinfo
;
2594 u32 target
= channel
->center_freq
;
2599 switch (channel
->hw_value
) {
2600 case AR5K_EEPROM_MODE_11A
:
2601 pcinfo
= ee
->ee_pwr_cal_a
;
2602 mode
= AR5K_EEPROM_MODE_11A
;
2604 case AR5K_EEPROM_MODE_11B
:
2605 pcinfo
= ee
->ee_pwr_cal_b
;
2606 mode
= AR5K_EEPROM_MODE_11B
;
2608 case AR5K_EEPROM_MODE_11G
:
2610 pcinfo
= ee
->ee_pwr_cal_g
;
2611 mode
= AR5K_EEPROM_MODE_11G
;
2614 max
= ee
->ee_n_piers
[mode
] - 1;
2616 /* Frequency is below our calibrated
2617 * range. Use the lowest power curve
2619 if (target
< pcinfo
[0].freq
) {
2624 /* Frequency is above our calibrated
2625 * range. Use the highest power curve
2627 if (target
> pcinfo
[max
].freq
) {
2628 idx_l
= idx_r
= max
;
2632 /* Frequency is inside our calibrated
2633 * channel range. Pick the surrounding
2634 * calibration piers so that we can
2636 for (i
= 0; i
<= max
; i
++) {
2638 /* Frequency matches one of our calibration
2639 * piers, no need to interpolate, just use
2640 * that calibration pier */
2641 if (pcinfo
[i
].freq
== target
) {
2646 /* We found a calibration pier that's above
2647 * frequency, use this pier and the previous
2648 * one to interpolate */
2649 if (target
< pcinfo
[i
].freq
) {
2657 *pcinfo_l
= &pcinfo
[idx_l
];
2658 *pcinfo_r
= &pcinfo
[idx_r
];
2662 * ath5k_get_rate_pcal_data() - Get the interpolated per-rate power
2664 * @ah: The &struct ath5k_hw *ah,
2665 * @channel: The &struct ieee80211_channel
2666 * @rates: The &struct ath5k_rate_pcal_info to fill
2668 * Get the surrounding per-rate power calibration data
2669 * for a given frequency and interpolate between power
2670 * values to set max target power supported by hw for
2671 * each rate on this frequency.
2674 ath5k_get_rate_pcal_data(struct ath5k_hw
*ah
,
2675 struct ieee80211_channel
*channel
,
2676 struct ath5k_rate_pcal_info
*rates
)
2678 struct ath5k_eeprom_info
*ee
= &ah
->ah_capabilities
.cap_eeprom
;
2679 struct ath5k_rate_pcal_info
*rpinfo
;
2682 u32 target
= channel
->center_freq
;
2687 switch (channel
->hw_value
) {
2689 rpinfo
= ee
->ee_rate_tpwr_a
;
2690 mode
= AR5K_EEPROM_MODE_11A
;
2693 rpinfo
= ee
->ee_rate_tpwr_b
;
2694 mode
= AR5K_EEPROM_MODE_11B
;
2698 rpinfo
= ee
->ee_rate_tpwr_g
;
2699 mode
= AR5K_EEPROM_MODE_11G
;
2702 max
= ee
->ee_rate_target_pwr_num
[mode
] - 1;
2704 /* Get the surrounding calibration
2705 * piers - same as above */
2706 if (target
< rpinfo
[0].freq
) {
2711 if (target
> rpinfo
[max
].freq
) {
2712 idx_l
= idx_r
= max
;
2716 for (i
= 0; i
<= max
; i
++) {
2718 if (rpinfo
[i
].freq
== target
) {
2723 if (target
< rpinfo
[i
].freq
) {
2731 /* Now interpolate power value, based on the frequency */
2732 rates
->freq
= target
;
2734 rates
->target_power_6to24
=
2735 ath5k_get_interpolated_value(target
, rpinfo
[idx_l
].freq
,
2737 rpinfo
[idx_l
].target_power_6to24
,
2738 rpinfo
[idx_r
].target_power_6to24
);
2740 rates
->target_power_36
=
2741 ath5k_get_interpolated_value(target
, rpinfo
[idx_l
].freq
,
2743 rpinfo
[idx_l
].target_power_36
,
2744 rpinfo
[idx_r
].target_power_36
);
2746 rates
->target_power_48
=
2747 ath5k_get_interpolated_value(target
, rpinfo
[idx_l
].freq
,
2749 rpinfo
[idx_l
].target_power_48
,
2750 rpinfo
[idx_r
].target_power_48
);
2752 rates
->target_power_54
=
2753 ath5k_get_interpolated_value(target
, rpinfo
[idx_l
].freq
,
2755 rpinfo
[idx_l
].target_power_54
,
2756 rpinfo
[idx_r
].target_power_54
);
2760 * ath5k_get_max_ctl_power() - Get max edge power for a given frequency
2761 * @ah: the &struct ath5k_hw
2762 * @channel: The &struct ieee80211_channel
2764 * Get the max edge power for this channel if
2765 * we have such data from EEPROM's Conformance Test
2766 * Limits (CTL), and limit max power if needed.
2769 ath5k_get_max_ctl_power(struct ath5k_hw
*ah
,
2770 struct ieee80211_channel
*channel
)
2772 struct ath_regulatory
*regulatory
= ath5k_hw_regulatory(ah
);
2773 struct ath5k_eeprom_info
*ee
= &ah
->ah_capabilities
.cap_eeprom
;
2774 struct ath5k_edge_power
*rep
= ee
->ee_ctl_pwr
;
2775 u8
*ctl_val
= ee
->ee_ctl
;
2776 s16 max_chan_pwr
= ah
->ah_txpower
.txp_max_pwr
/ 4;
2781 u32 target
= channel
->center_freq
;
2783 ctl_mode
= ath_regd_get_band_ctl(regulatory
, channel
->band
);
2785 switch (channel
->hw_value
) {
2787 if (ah
->ah_bwmode
== AR5K_BWMODE_40MHZ
)
2788 ctl_mode
|= AR5K_CTL_TURBO
;
2790 ctl_mode
|= AR5K_CTL_11A
;
2793 if (ah
->ah_bwmode
== AR5K_BWMODE_40MHZ
)
2794 ctl_mode
|= AR5K_CTL_TURBOG
;
2796 ctl_mode
|= AR5K_CTL_11G
;
2799 ctl_mode
|= AR5K_CTL_11B
;
2805 for (i
= 0; i
< ee
->ee_ctls
; i
++) {
2806 if (ctl_val
[i
] == ctl_mode
) {
2812 /* If we have a CTL dataset available grab it and find the
2813 * edge power for our frequency */
2814 if (ctl_idx
== 0xFF)
2817 /* Edge powers are sorted by frequency from lower
2818 * to higher. Each CTL corresponds to 8 edge power
2820 rep_idx
= ctl_idx
* AR5K_EEPROM_N_EDGES
;
2822 /* Don't do boundaries check because we
2823 * might have more that one bands defined
2826 /* Get the edge power that's closer to our
2828 for (i
= 0; i
< AR5K_EEPROM_N_EDGES
; i
++) {
2830 if (target
<= rep
[rep_idx
].freq
)
2831 edge_pwr
= (s16
) rep
[rep_idx
].edge
;
2835 ah
->ah_txpower
.txp_max_pwr
= 4 * min(edge_pwr
, max_chan_pwr
);
2840 * Power to PCDAC table functions
2844 * DOC: Power to PCDAC table functions
2846 * For RF5111 we have an XPD -eXternal Power Detector- curve
2847 * for each calibrated channel. Each curve has 0,5dB Power steps
2848 * on x axis and PCDAC steps (offsets) on y axis and looks like an
2849 * exponential function. To recreate the curve we read 11 points
2850 * from eeprom (eeprom.c) and interpolate here.
2852 * For RF5112 we have 4 XPD -eXternal Power Detector- curves
2853 * for each calibrated channel on 0, -6, -12 and -18dBm but we only
2854 * use the higher (3) and the lower (0) curves. Each curve again has 0.5dB
2855 * power steps on x axis and PCDAC steps on y axis and looks like a
2856 * linear function. To recreate the curve and pass the power values
2857 * on hw, we get 4 points for xpd 0 (lower gain -> max power)
2858 * and 3 points for xpd 3 (higher gain -> lower power) from eeprom (eeprom.c)
2859 * and interpolate here.
2861 * For a given channel we get the calibrated points (piers) for it or
2862 * -if we don't have calibration data for this specific channel- from the
2863 * available surrounding channels we have calibration data for, after we do a
2864 * linear interpolation between them. Then since we have our calibrated points
2865 * for this channel, we do again a linear interpolation between them to get the
2868 * We finally write the Y values of the curve(s) (the PCDAC values) on hw
2872 * ath5k_fill_pwr_to_pcdac_table() - Fill Power to PCDAC table on RF5111
2873 * @ah: The &struct ath5k_hw
2874 * @table_min: Minimum power (x min)
2875 * @table_max: Maximum power (x max)
2877 * No further processing is needed for RF5111, the only thing we have to
2878 * do is fill the values below and above calibration range since eeprom data
2879 * may not cover the entire PCDAC table.
2882 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw
*ah
, s16
* table_min
,
2885 u8
*pcdac_out
= ah
->ah_txpower
.txp_pd_table
;
2886 u8
*pcdac_tmp
= ah
->ah_txpower
.tmpL
[0];
2887 u8 pcdac_0
, pcdac_n
, pcdac_i
, pwr_idx
, i
;
2888 s16 min_pwr
, max_pwr
;
2890 /* Get table boundaries */
2891 min_pwr
= table_min
[0];
2892 pcdac_0
= pcdac_tmp
[0];
2894 max_pwr
= table_max
[0];
2895 pcdac_n
= pcdac_tmp
[table_max
[0] - table_min
[0]];
2897 /* Extrapolate below minimum using pcdac_0 */
2899 for (i
= 0; i
< min_pwr
; i
++)
2900 pcdac_out
[pcdac_i
++] = pcdac_0
;
2902 /* Copy values from pcdac_tmp */
2904 for (i
= 0; pwr_idx
<= max_pwr
&&
2905 pcdac_i
< AR5K_EEPROM_POWER_TABLE_SIZE
; i
++) {
2906 pcdac_out
[pcdac_i
++] = pcdac_tmp
[i
];
2910 /* Extrapolate above maximum */
2911 while (pcdac_i
< AR5K_EEPROM_POWER_TABLE_SIZE
)
2912 pcdac_out
[pcdac_i
++] = pcdac_n
;
2917 * ath5k_combine_linear_pcdac_curves() - Combine available PCDAC Curves
2918 * @ah: The &struct ath5k_hw
2919 * @table_min: Minimum power (x min)
2920 * @table_max: Maximum power (x max)
2921 * @pdcurves: Number of pd curves
2923 * Combine available XPD Curves and fill Linear Power to PCDAC table on RF5112
2924 * RFX112 can have up to 2 curves (one for low txpower range and one for
2925 * higher txpower range). We need to put them both on pcdac_out and place
2926 * them in the correct location. In case we only have one curve available
2927 * just fit it on pcdac_out (it's supposed to cover the entire range of
2928 * available pwr levels since it's always the higher power curve). Extrapolate
2929 * below and above final table if needed.
2932 ath5k_combine_linear_pcdac_curves(struct ath5k_hw
*ah
, s16
* table_min
,
2933 s16
*table_max
, u8 pdcurves
)
2935 u8
*pcdac_out
= ah
->ah_txpower
.txp_pd_table
;
2942 s16 mid_pwr_idx
= 0;
2943 /* Edge flag turns on the 7nth bit on the PCDAC
2944 * to declare the higher power curve (force values
2945 * to be greater than 64). If we only have one curve
2946 * we don't need to set this, if we have 2 curves and
2947 * fill the table backwards this can also be used to
2948 * switch from higher power curve to lower power curve */
2952 /* When we have only one curve available
2953 * that's the higher power curve. If we have
2954 * two curves the first is the high power curve
2955 * and the next is the low power curve. */
2957 pcdac_low_pwr
= ah
->ah_txpower
.tmpL
[1];
2958 pcdac_high_pwr
= ah
->ah_txpower
.tmpL
[0];
2959 mid_pwr_idx
= table_max
[1] - table_min
[1] - 1;
2960 max_pwr_idx
= (table_max
[0] - table_min
[0]) / 2;
2962 /* If table size goes beyond 31.5dB, keep the
2963 * upper 31.5dB range when setting tx power.
2964 * Note: 126 = 31.5 dB in quarter dB steps */
2965 if (table_max
[0] - table_min
[1] > 126)
2966 min_pwr_idx
= table_max
[0] - 126;
2968 min_pwr_idx
= table_min
[1];
2970 /* Since we fill table backwards
2971 * start from high power curve */
2972 pcdac_tmp
= pcdac_high_pwr
;
2976 pcdac_low_pwr
= ah
->ah_txpower
.tmpL
[1]; /* Zeroed */
2977 pcdac_high_pwr
= ah
->ah_txpower
.tmpL
[0];
2978 min_pwr_idx
= table_min
[0];
2979 max_pwr_idx
= (table_max
[0] - table_min
[0]) / 2;
2980 pcdac_tmp
= pcdac_high_pwr
;
2984 /* This is used when setting tx power*/
2985 ah
->ah_txpower
.txp_min_idx
= min_pwr_idx
/ 2;
2987 /* Fill Power to PCDAC table backwards */
2989 for (i
= 63; i
>= 0; i
--) {
2990 /* Entering lower power range, reset
2991 * edge flag and set pcdac_tmp to lower
2993 if (edge_flag
== 0x40 &&
2994 (2 * pwr
<= (table_max
[1] - table_min
[0]) || pwr
== 0)) {
2996 pcdac_tmp
= pcdac_low_pwr
;
2997 pwr
= mid_pwr_idx
/ 2;
3000 /* Don't go below 1, extrapolate below if we have
3001 * already switched to the lower power curve -or
3002 * we only have one curve and edge_flag is zero
3004 if (pcdac_tmp
[pwr
] < 1 && (edge_flag
== 0x00)) {
3006 pcdac_out
[i
] = pcdac_out
[i
+ 1];
3012 pcdac_out
[i
] = pcdac_tmp
[pwr
] | edge_flag
;
3014 /* Extrapolate above if pcdac is greater than
3015 * 126 -this can happen because we OR pcdac_out
3016 * value with edge_flag on high power curve */
3017 if (pcdac_out
[i
] > 126)
3020 /* Decrease by a 0.5dB step */
3026 * ath5k_write_pcdac_table() - Write the PCDAC values on hw
3027 * @ah: The &struct ath5k_hw
3030 ath5k_write_pcdac_table(struct ath5k_hw
*ah
)
3032 u8
*pcdac_out
= ah
->ah_txpower
.txp_pd_table
;
3036 * Write TX power values
3038 for (i
= 0; i
< (AR5K_EEPROM_POWER_TABLE_SIZE
/ 2); i
++) {
3039 ath5k_hw_reg_write(ah
,
3040 (((pcdac_out
[2 * i
+ 0] << 8 | 0xff) & 0xffff) << 0) |
3041 (((pcdac_out
[2 * i
+ 1] << 8 | 0xff) & 0xffff) << 16),
3042 AR5K_PHY_PCDAC_TXPOWER(i
));
3048 * Power to PDADC table functions
3052 * DOC: Power to PDADC table functions
3054 * For RF2413 and later we have a Power to PDADC table (Power Detector)
3055 * instead of a PCDAC (Power Control) and 4 pd gain curves for each
3056 * calibrated channel. Each curve has power on x axis in 0.5 db steps and
3057 * PDADC steps on y axis and looks like an exponential function like the
3060 * To recreate the curves we read the points from eeprom (eeprom.c)
3061 * and interpolate here. Note that in most cases only 2 (higher and lower)
3062 * curves are used (like RF5112) but vendors have the opportunity to include
3063 * all 4 curves on eeprom. The final curve (higher power) has an extra
3064 * point for better accuracy like RF5112.
3066 * The process is similar to what we do above for RF5111/5112
3070 * ath5k_combine_pwr_to_pdadc_curves() - Combine the various PDADC curves
3071 * @ah: The &struct ath5k_hw
3072 * @pwr_min: Minimum power (x min)
3073 * @pwr_max: Maximum power (x max)
3074 * @pdcurves: Number of available curves
3076 * Combine the various pd curves and create the final Power to PDADC table
3077 * We can have up to 4 pd curves, we need to do a similar process
3078 * as we do for RF5112. This time we don't have an edge_flag but we
3079 * set the gain boundaries on a separate register.
3082 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw
*ah
,
3083 s16
*pwr_min
, s16
*pwr_max
, u8 pdcurves
)
3085 u8 gain_boundaries
[AR5K_EEPROM_N_PD_GAINS
];
3086 u8
*pdadc_out
= ah
->ah_txpower
.txp_pd_table
;
3089 u8 pdadc_i
, pdadc_n
, pwr_step
, pdg
, max_idx
, table_size
;
3092 /* Note: Register value is initialized on initvals
3093 * there is no feedback from hw.
3094 * XXX: What about pd_gain_overlap from EEPROM ? */
3095 pd_gain_overlap
= (u8
) ath5k_hw_reg_read(ah
, AR5K_PHY_TPC_RG5
) &
3096 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP
;
3098 /* Create final PDADC table */
3099 for (pdg
= 0, pdadc_i
= 0; pdg
< pdcurves
; pdg
++) {
3100 pdadc_tmp
= ah
->ah_txpower
.tmpL
[pdg
];
3102 if (pdg
== pdcurves
- 1)
3103 /* 2 dB boundary stretch for last
3104 * (higher power) curve */
3105 gain_boundaries
[pdg
] = pwr_max
[pdg
] + 4;
3107 /* Set gain boundary in the middle
3108 * between this curve and the next one */
3109 gain_boundaries
[pdg
] =
3110 (pwr_max
[pdg
] + pwr_min
[pdg
+ 1]) / 2;
3112 /* Sanity check in case our 2 db stretch got out of
3114 if (gain_boundaries
[pdg
] > AR5K_TUNE_MAX_TXPOWER
)
3115 gain_boundaries
[pdg
] = AR5K_TUNE_MAX_TXPOWER
;
3117 /* For the first curve (lower power)
3118 * start from 0 dB */
3122 /* For the other curves use the gain overlap */
3123 pdadc_0
= (gain_boundaries
[pdg
- 1] - pwr_min
[pdg
]) -
3126 /* Force each power step to be at least 0.5 dB */
3127 if ((pdadc_tmp
[1] - pdadc_tmp
[0]) > 1)
3128 pwr_step
= pdadc_tmp
[1] - pdadc_tmp
[0];
3132 /* If pdadc_0 is negative, we need to extrapolate
3133 * below this pdgain by a number of pwr_steps */
3134 while ((pdadc_0
< 0) && (pdadc_i
< 128)) {
3135 s16 tmp
= pdadc_tmp
[0] + pdadc_0
* pwr_step
;
3136 pdadc_out
[pdadc_i
++] = (tmp
< 0) ? 0 : (u8
) tmp
;
3140 /* Set last pwr level, using gain boundaries */
3141 pdadc_n
= gain_boundaries
[pdg
] + pd_gain_overlap
- pwr_min
[pdg
];
3142 /* Limit it to be inside pwr range */
3143 table_size
= pwr_max
[pdg
] - pwr_min
[pdg
];
3144 max_idx
= (pdadc_n
< table_size
) ? pdadc_n
: table_size
;
3146 /* Fill pdadc_out table */
3147 while (pdadc_0
< max_idx
&& pdadc_i
< 128)
3148 pdadc_out
[pdadc_i
++] = pdadc_tmp
[pdadc_0
++];
3150 /* Need to extrapolate above this pdgain? */
3151 if (pdadc_n
<= max_idx
)
3154 /* Force each power step to be at least 0.5 dB */
3155 if ((pdadc_tmp
[table_size
- 1] - pdadc_tmp
[table_size
- 2]) > 1)
3156 pwr_step
= pdadc_tmp
[table_size
- 1] -
3157 pdadc_tmp
[table_size
- 2];
3161 /* Extrapolate above */
3162 while ((pdadc_0
< (s16
) pdadc_n
) &&
3163 (pdadc_i
< AR5K_EEPROM_POWER_TABLE_SIZE
* 2)) {
3164 s16 tmp
= pdadc_tmp
[table_size
- 1] +
3165 (pdadc_0
- max_idx
) * pwr_step
;
3166 pdadc_out
[pdadc_i
++] = (tmp
> 127) ? 127 : (u8
) tmp
;
3171 while (pdg
< AR5K_EEPROM_N_PD_GAINS
) {
3172 gain_boundaries
[pdg
] = gain_boundaries
[pdg
- 1];
3176 while (pdadc_i
< AR5K_EEPROM_POWER_TABLE_SIZE
* 2) {
3177 pdadc_out
[pdadc_i
] = pdadc_out
[pdadc_i
- 1];
3181 /* Set gain boundaries */
3182 ath5k_hw_reg_write(ah
,
3183 AR5K_REG_SM(pd_gain_overlap
,
3184 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP
) |
3185 AR5K_REG_SM(gain_boundaries
[0],
3186 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1
) |
3187 AR5K_REG_SM(gain_boundaries
[1],
3188 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2
) |
3189 AR5K_REG_SM(gain_boundaries
[2],
3190 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3
) |
3191 AR5K_REG_SM(gain_boundaries
[3],
3192 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4
),
3195 /* Used for setting rate power table */
3196 ah
->ah_txpower
.txp_min_idx
= pwr_min
[0];
3201 * ath5k_write_pwr_to_pdadc_table() - Write the PDADC values on hw
3202 * @ah: The &struct ath5k_hw
3203 * @ee_mode: One of enum ath5k_driver_mode
3206 ath5k_write_pwr_to_pdadc_table(struct ath5k_hw
*ah
, u8 ee_mode
)
3208 struct ath5k_eeprom_info
*ee
= &ah
->ah_capabilities
.cap_eeprom
;
3209 u8
*pdadc_out
= ah
->ah_txpower
.txp_pd_table
;
3210 u8
*pdg_to_idx
= ee
->ee_pdc_to_idx
[ee_mode
];
3211 u8 pdcurves
= ee
->ee_pd_gains
[ee_mode
];
3215 /* Select the right pdgain curves */
3217 /* Clear current settings */
3218 reg
= ath5k_hw_reg_read(ah
, AR5K_PHY_TPC_RG1
);
3219 reg
&= ~(AR5K_PHY_TPC_RG1_PDGAIN_1
|
3220 AR5K_PHY_TPC_RG1_PDGAIN_2
|
3221 AR5K_PHY_TPC_RG1_PDGAIN_3
|
3222 AR5K_PHY_TPC_RG1_NUM_PD_GAIN
);
3225 * Use pd_gains curve from eeprom
3227 * This overrides the default setting from initvals
3228 * in case some vendors (e.g. Zcomax) don't use the default
3229 * curves. If we don't honor their settings we 'll get a
3230 * 5dB (1 * gain overlap ?) drop.
3232 reg
|= AR5K_REG_SM(pdcurves
, AR5K_PHY_TPC_RG1_NUM_PD_GAIN
);
3236 reg
|= AR5K_REG_SM(pdg_to_idx
[2], AR5K_PHY_TPC_RG1_PDGAIN_3
);
3239 reg
|= AR5K_REG_SM(pdg_to_idx
[1], AR5K_PHY_TPC_RG1_PDGAIN_2
);
3242 reg
|= AR5K_REG_SM(pdg_to_idx
[0], AR5K_PHY_TPC_RG1_PDGAIN_1
);
3245 ath5k_hw_reg_write(ah
, reg
, AR5K_PHY_TPC_RG1
);
3248 * Write TX power values
3250 for (i
= 0; i
< (AR5K_EEPROM_POWER_TABLE_SIZE
/ 2); i
++) {
3251 u32 val
= get_unaligned_le32(&pdadc_out
[4 * i
]);
3252 ath5k_hw_reg_write(ah
, val
, AR5K_PHY_PDADC_TXPOWER(i
));
3258 * Common code for PCDAC/PDADC tables
3262 * ath5k_setup_channel_powertable() - Set up power table for this channel
3263 * @ah: The &struct ath5k_hw
3264 * @channel: The &struct ieee80211_channel
3265 * @ee_mode: One of enum ath5k_driver_mode
3266 * @type: One of enum ath5k_powertable_type (eeprom.h)
3268 * This is the main function that uses all of the above
3269 * to set PCDAC/PDADC table on hw for the current channel.
3270 * This table is used for tx power calibration on the baseband,
3271 * without it we get weird tx power levels and in some cases
3272 * distorted spectral mask
3275 ath5k_setup_channel_powertable(struct ath5k_hw
*ah
,
3276 struct ieee80211_channel
*channel
,
3277 u8 ee_mode
, u8 type
)
3279 struct ath5k_pdgain_info
*pdg_L
, *pdg_R
;
3280 struct ath5k_chan_pcal_info
*pcinfo_L
;
3281 struct ath5k_chan_pcal_info
*pcinfo_R
;
3282 struct ath5k_eeprom_info
*ee
= &ah
->ah_capabilities
.cap_eeprom
;
3283 u8
*pdg_curve_to_idx
= ee
->ee_pdc_to_idx
[ee_mode
];
3284 s16 table_min
[AR5K_EEPROM_N_PD_GAINS
];
3285 s16 table_max
[AR5K_EEPROM_N_PD_GAINS
];
3288 u32 target
= channel
->center_freq
;
3291 /* Get surrounding freq piers for this channel */
3292 ath5k_get_chan_pcal_surrounding_piers(ah
, channel
,
3296 /* Loop over pd gain curves on
3297 * surrounding freq piers by index */
3298 for (pdg
= 0; pdg
< ee
->ee_pd_gains
[ee_mode
]; pdg
++) {
3300 /* Fill curves in reverse order
3301 * from lower power (max gain)
3302 * to higher power. Use curve -> idx
3303 * backmapping we did on eeprom init */
3304 u8 idx
= pdg_curve_to_idx
[pdg
];
3306 /* Grab the needed curves by index */
3307 pdg_L
= &pcinfo_L
->pd_curves
[idx
];
3308 pdg_R
= &pcinfo_R
->pd_curves
[idx
];
3310 /* Initialize the temp tables */
3311 tmpL
= ah
->ah_txpower
.tmpL
[pdg
];
3312 tmpR
= ah
->ah_txpower
.tmpR
[pdg
];
3314 /* Set curve's x boundaries and create
3315 * curves so that they cover the same
3316 * range (if we don't do that one table
3317 * will have values on some range and the
3318 * other one won't have any so interpolation
3320 table_min
[pdg
] = min(pdg_L
->pd_pwr
[0],
3321 pdg_R
->pd_pwr
[0]) / 2;
3323 table_max
[pdg
] = max(pdg_L
->pd_pwr
[pdg_L
->pd_points
- 1],
3324 pdg_R
->pd_pwr
[pdg_R
->pd_points
- 1]) / 2;
3326 /* Now create the curves on surrounding channels
3327 * and interpolate if needed to get the final
3328 * curve for this gain on this channel */
3330 case AR5K_PWRTABLE_LINEAR_PCDAC
:
3331 /* Override min/max so that we don't loose
3332 * accuracy (don't divide by 2) */
3333 table_min
[pdg
] = min(pdg_L
->pd_pwr
[0],
3337 max(pdg_L
->pd_pwr
[pdg_L
->pd_points
- 1],
3338 pdg_R
->pd_pwr
[pdg_R
->pd_points
- 1]);
3340 /* Override minimum so that we don't get
3341 * out of bounds while extrapolating
3342 * below. Don't do this when we have 2
3343 * curves and we are on the high power curve
3344 * because table_min is ok in this case */
3345 if (!(ee
->ee_pd_gains
[ee_mode
] > 1 && pdg
== 0)) {
3348 ath5k_get_linear_pcdac_min(pdg_L
->pd_step
,
3353 /* Don't go too low because we will
3354 * miss the upper part of the curve.
3355 * Note: 126 = 31.5dB (max power supported)
3356 * in 0.25dB units */
3357 if (table_max
[pdg
] - table_min
[pdg
] > 126)
3358 table_min
[pdg
] = table_max
[pdg
] - 126;
3362 case AR5K_PWRTABLE_PWR_TO_PCDAC
:
3363 case AR5K_PWRTABLE_PWR_TO_PDADC
:
3365 ath5k_create_power_curve(table_min
[pdg
],
3369 pdg_L
->pd_points
, tmpL
, type
);
3371 /* We are in a calibration
3372 * pier, no need to interpolate
3373 * between freq piers */
3374 if (pcinfo_L
== pcinfo_R
)
3377 ath5k_create_power_curve(table_min
[pdg
],
3381 pdg_R
->pd_points
, tmpR
, type
);
3387 /* Interpolate between curves
3388 * of surrounding freq piers to
3389 * get the final curve for this
3390 * pd gain. Re-use tmpL for interpolation
3392 for (i
= 0; (i
< (u16
) (table_max
[pdg
] - table_min
[pdg
])) &&
3393 (i
< AR5K_EEPROM_POWER_TABLE_SIZE
); i
++) {
3394 tmpL
[i
] = (u8
) ath5k_get_interpolated_value(target
,
3395 (s16
) pcinfo_L
->freq
,
3396 (s16
) pcinfo_R
->freq
,
3402 /* Now we have a set of curves for this
3403 * channel on tmpL (x range is table_max - table_min
3404 * and y values are tmpL[pdg][]) sorted in the same
3405 * order as EEPROM (because we've used the backmapping).
3406 * So for RF5112 it's from higher power to lower power
3407 * and for RF2413 it's from lower power to higher power.
3408 * For RF5111 we only have one curve. */
3410 /* Fill min and max power levels for this
3411 * channel by interpolating the values on
3412 * surrounding channels to complete the dataset */
3413 ah
->ah_txpower
.txp_min_pwr
= ath5k_get_interpolated_value(target
,
3414 (s16
) pcinfo_L
->freq
,
3415 (s16
) pcinfo_R
->freq
,
3416 pcinfo_L
->min_pwr
, pcinfo_R
->min_pwr
);
3418 ah
->ah_txpower
.txp_max_pwr
= ath5k_get_interpolated_value(target
,
3419 (s16
) pcinfo_L
->freq
,
3420 (s16
) pcinfo_R
->freq
,
3421 pcinfo_L
->max_pwr
, pcinfo_R
->max_pwr
);
3423 /* Fill PCDAC/PDADC table */
3425 case AR5K_PWRTABLE_LINEAR_PCDAC
:
3426 /* For RF5112 we can have one or two curves
3427 * and each curve covers a certain power lvl
3428 * range so we need to do some more processing */
3429 ath5k_combine_linear_pcdac_curves(ah
, table_min
, table_max
,
3430 ee
->ee_pd_gains
[ee_mode
]);
3432 /* Set txp.offset so that we can
3433 * match max power value with max
3435 ah
->ah_txpower
.txp_offset
= 64 - (table_max
[0] / 2);
3437 case AR5K_PWRTABLE_PWR_TO_PCDAC
:
3438 /* We are done for RF5111 since it has only
3439 * one curve, just fit the curve on the table */
3440 ath5k_fill_pwr_to_pcdac_table(ah
, table_min
, table_max
);
3442 /* No rate powertable adjustment for RF5111 */
3443 ah
->ah_txpower
.txp_min_idx
= 0;
3444 ah
->ah_txpower
.txp_offset
= 0;
3446 case AR5K_PWRTABLE_PWR_TO_PDADC
:
3447 /* Set PDADC boundaries and fill
3448 * final PDADC table */
3449 ath5k_combine_pwr_to_pdadc_curves(ah
, table_min
, table_max
,
3450 ee
->ee_pd_gains
[ee_mode
]);
3452 /* Set txp.offset, note that table_min
3453 * can be negative */
3454 ah
->ah_txpower
.txp_offset
= table_min
[0];
3460 ah
->ah_txpower
.txp_setup
= true;
3466 * ath5k_write_channel_powertable() - Set power table for current channel on hw
3467 * @ah: The &struct ath5k_hw
3468 * @ee_mode: One of enum ath5k_driver_mode
3469 * @type: One of enum ath5k_powertable_type (eeprom.h)
3472 ath5k_write_channel_powertable(struct ath5k_hw
*ah
, u8 ee_mode
, u8 type
)
3474 if (type
== AR5K_PWRTABLE_PWR_TO_PDADC
)
3475 ath5k_write_pwr_to_pdadc_table(ah
, ee_mode
);
3477 ath5k_write_pcdac_table(ah
);
3482 * DOC: Per-rate tx power setting
3484 * This is the code that sets the desired tx power limit (below
3485 * maximum) on hw for each rate (we also have TPC that sets
3486 * power per packet type). We do that by providing an index on the
3487 * PCDAC/PDADC table we set up above, for each rate.
3489 * For now we only limit txpower based on maximum tx power
3490 * supported by hw (what's inside rate_info) + conformance test
3491 * limits. We need to limit this even more, based on regulatory domain
3492 * etc to be safe. Normally this is done from above so we don't care
3493 * here, all we care is that the tx power we set will be O.K.
3494 * for the hw (e.g. won't create noise on PA etc).
3496 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps -
3497 * x values) and is indexed as follows:
3498 * rates[0] - rates[7] -> OFDM rates
3499 * rates[8] - rates[14] -> CCK rates
3500 * rates[15] -> XR rates (they all have the same power)
3504 * ath5k_setup_rate_powertable() - Set up rate power table for a given tx power
3505 * @ah: The &struct ath5k_hw
3506 * @max_pwr: The maximum tx power requested in 0.5dB steps
3507 * @rate_info: The &struct ath5k_rate_pcal_info to fill
3508 * @ee_mode: One of enum ath5k_driver_mode
3511 ath5k_setup_rate_powertable(struct ath5k_hw
*ah
, u16 max_pwr
,
3512 struct ath5k_rate_pcal_info
*rate_info
,
3518 /* max_pwr is power level we got from driver/user in 0.5dB
3519 * units, switch to 0.25dB units so we can compare */
3521 max_pwr
= min(max_pwr
, (u16
) ah
->ah_txpower
.txp_max_pwr
) / 2;
3523 /* apply rate limits */
3524 rates
= ah
->ah_txpower
.txp_rates_power_table
;
3526 /* OFDM rates 6 to 24Mb/s */
3527 for (i
= 0; i
< 5; i
++)
3528 rates
[i
] = min(max_pwr
, rate_info
->target_power_6to24
);
3530 /* Rest OFDM rates */
3531 rates
[5] = min(rates
[0], rate_info
->target_power_36
);
3532 rates
[6] = min(rates
[0], rate_info
->target_power_48
);
3533 rates
[7] = min(rates
[0], rate_info
->target_power_54
);
3537 rates
[8] = min(rates
[0], rate_info
->target_power_6to24
);
3539 rates
[9] = min(rates
[0], rate_info
->target_power_36
);
3541 rates
[10] = min(rates
[0], rate_info
->target_power_36
);
3543 rates
[11] = min(rates
[0], rate_info
->target_power_48
);
3545 rates
[12] = min(rates
[0], rate_info
->target_power_48
);
3547 rates
[13] = min(rates
[0], rate_info
->target_power_54
);
3549 rates
[14] = min(rates
[0], rate_info
->target_power_54
);
3552 rates
[15] = min(rates
[0], rate_info
->target_power_6to24
);
3554 /* CCK rates have different peak to average ratio
3555 * so we have to tweak their power so that gainf
3556 * correction works ok. For this we use OFDM to
3557 * CCK delta from eeprom */
3558 if ((ee_mode
== AR5K_EEPROM_MODE_11G
) &&
3559 (ah
->ah_phy_revision
< AR5K_SREV_PHY_5212A
))
3560 for (i
= 8; i
<= 15; i
++)
3561 rates
[i
] -= ah
->ah_txpower
.txp_cck_ofdm_gainf_delta
;
3563 /* Now that we have all rates setup use table offset to
3564 * match the power range set by user with the power indices
3565 * on PCDAC/PDADC table */
3566 for (i
= 0; i
< 16; i
++) {
3567 rates
[i
] += ah
->ah_txpower
.txp_offset
;
3568 /* Don't get out of bounds */
3573 /* Min/max in 0.25dB units */
3574 ah
->ah_txpower
.txp_min_pwr
= 2 * rates
[7];
3575 ah
->ah_txpower
.txp_cur_pwr
= 2 * rates
[0];
3576 ah
->ah_txpower
.txp_ofdm
= rates
[7];
3581 * ath5k_hw_txpower() - Set transmission power limit for a given channel
3582 * @ah: The &struct ath5k_hw
3583 * @channel: The &struct ieee80211_channel
3584 * @txpower: Requested tx power in 0.5dB steps
3586 * Combines all of the above to set the requested tx power limit
3590 ath5k_hw_txpower(struct ath5k_hw
*ah
, struct ieee80211_channel
*channel
,
3593 struct ath5k_rate_pcal_info rate_info
;
3594 struct ieee80211_channel
*curr_channel
= ah
->ah_current_channel
;
3599 if (txpower
> AR5K_TUNE_MAX_TXPOWER
) {
3600 ATH5K_ERR(ah
, "invalid tx power: %u\n", txpower
);
3604 ee_mode
= ath5k_eeprom_mode_from_channel(channel
);
3607 "invalid channel: %d\n", channel
->center_freq
);
3611 /* Initialize TX power table */
3612 switch (ah
->ah_radio
) {
3617 type
= AR5K_PWRTABLE_PWR_TO_PCDAC
;
3620 type
= AR5K_PWRTABLE_LINEAR_PCDAC
;
3627 type
= AR5K_PWRTABLE_PWR_TO_PDADC
;
3634 * If we don't change channel/mode skip tx powertable calculation
3635 * and use the cached one.
3637 if (!ah
->ah_txpower
.txp_setup
||
3638 (channel
->hw_value
!= curr_channel
->hw_value
) ||
3639 (channel
->center_freq
!= curr_channel
->center_freq
)) {
3640 /* Reset TX power values */
3641 memset(&ah
->ah_txpower
, 0, sizeof(ah
->ah_txpower
));
3642 ah
->ah_txpower
.txp_tpc
= AR5K_TUNE_TPC_TXPOWER
;
3644 /* Calculate the powertable */
3645 ret
= ath5k_setup_channel_powertable(ah
, channel
,
3651 /* Write table on hw */
3652 ath5k_write_channel_powertable(ah
, ee_mode
, type
);
3654 /* Limit max power if we have a CTL available */
3655 ath5k_get_max_ctl_power(ah
, channel
);
3657 /* FIXME: Antenna reduction stuff */
3659 /* FIXME: Limit power on turbo modes */
3661 /* FIXME: TPC scale reduction */
3663 /* Get surrounding channels for per-rate power table
3665 ath5k_get_rate_pcal_data(ah
, channel
, &rate_info
);
3667 /* Setup rate power table */
3668 ath5k_setup_rate_powertable(ah
, txpower
, &rate_info
, ee_mode
);
3670 /* Write rate power table on hw */
3671 ath5k_hw_reg_write(ah
, AR5K_TXPOWER_OFDM(3, 24) |
3672 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
3673 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1
);
3675 ath5k_hw_reg_write(ah
, AR5K_TXPOWER_OFDM(7, 24) |
3676 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
3677 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2
);
3679 ath5k_hw_reg_write(ah
, AR5K_TXPOWER_CCK(10, 24) |
3680 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
3681 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3
);
3683 ath5k_hw_reg_write(ah
, AR5K_TXPOWER_CCK(14, 24) |
3684 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
3685 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4
);
3687 /* FIXME: TPC support */
3688 if (ah
->ah_txpower
.txp_tpc
) {
3689 ath5k_hw_reg_write(ah
, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE
|
3690 AR5K_TUNE_MAX_TXPOWER
, AR5K_PHY_TXPOWER_RATE_MAX
);
3692 ath5k_hw_reg_write(ah
,
3693 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER
, AR5K_TPC_ACK
) |
3694 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER
, AR5K_TPC_CTS
) |
3695 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER
, AR5K_TPC_CHIRP
),
3698 ath5k_hw_reg_write(ah
, AR5K_PHY_TXPOWER_RATE_MAX
|
3699 AR5K_TUNE_MAX_TXPOWER
, AR5K_PHY_TXPOWER_RATE_MAX
);
3706 * ath5k_hw_set_txpower_limit() - Set txpower limit for the current channel
3707 * @ah: The &struct ath5k_hw
3708 * @txpower: The requested tx power limit in 0.5dB steps
3710 * This function provides access to ath5k_hw_txpower to the driver in
3711 * case user or an application changes it while PHY is running.
3714 ath5k_hw_set_txpower_limit(struct ath5k_hw
*ah
, u8 txpower
)
3716 ATH5K_DBG(ah
, ATH5K_DEBUG_TXPOWER
,
3717 "changing txpower to %d\n", txpower
);
3719 return ath5k_hw_txpower(ah
, ah
->ah_current_channel
, txpower
);
3728 * ath5k_hw_phy_init() - Initialize PHY
3729 * @ah: The &struct ath5k_hw
3730 * @channel: The @struct ieee80211_channel
3731 * @mode: One of enum ath5k_driver_mode
3732 * @fast: Try a fast channel switch instead
3734 * This is the main function used during reset to initialize PHY
3735 * or do a fast channel change if possible.
3737 * NOTE: Do not call this one from the driver, it assumes PHY is in a
3738 * warm reset state !
3741 ath5k_hw_phy_init(struct ath5k_hw
*ah
, struct ieee80211_channel
*channel
,
3744 struct ieee80211_channel
*curr_channel
;
3750 * Sanity check for fast flag
3751 * Don't try fast channel change when changing modulation
3752 * mode/band. We check for chip compatibility on
3755 curr_channel
= ah
->ah_current_channel
;
3756 if (fast
&& (channel
->hw_value
!= curr_channel
->hw_value
))
3760 * On fast channel change we only set the synth parameters
3761 * while PHY is running, enable calibration and skip the rest.
3764 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_RFBUS_REQ
,
3765 AR5K_PHY_RFBUS_REQ_REQUEST
);
3766 for (i
= 0; i
< 100; i
++) {
3767 if (ath5k_hw_reg_read(ah
, AR5K_PHY_RFBUS_GRANT
))
3775 /* Set channel and wait for synth */
3776 ret
= ath5k_hw_channel(ah
, channel
);
3780 ath5k_hw_wait_for_synth(ah
, channel
);
3786 * Note: We need to do that before we set
3787 * RF buffer settings on 5211/5212+ so that we
3788 * properly set curve indices.
3790 ret
= ath5k_hw_txpower(ah
, channel
, ah
->ah_txpower
.txp_cur_pwr
?
3791 ah
->ah_txpower
.txp_cur_pwr
/ 2 : AR5K_TUNE_MAX_TXPOWER
);
3795 /* Write OFDM timings on 5212*/
3796 if (ah
->ah_version
== AR5K_AR5212
&&
3797 channel
->hw_value
!= AR5K_MODE_11B
) {
3799 ret
= ath5k_hw_write_ofdm_timings(ah
, channel
);
3803 /* Spur info is available only from EEPROM versions
3804 * greater than 5.3, but the EEPROM routines will use
3805 * static values for older versions */
3806 if (ah
->ah_mac_srev
>= AR5K_SREV_AR5424
)
3807 ath5k_hw_set_spur_mitigation_filter(ah
,
3811 /* If we used fast channel switching
3812 * we are done, release RF bus and
3813 * fire up NF calibration.
3815 * Note: Only NF calibration due to
3816 * channel change, not AGC calibration
3817 * since AGC is still running !
3821 * Release RF Bus grant
3823 AR5K_REG_DISABLE_BITS(ah
, AR5K_PHY_RFBUS_REQ
,
3824 AR5K_PHY_RFBUS_REQ_REQUEST
);
3827 * Start NF calibration
3829 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_AGCCTL
,
3830 AR5K_PHY_AGCCTL_NF
);
3836 * For 5210 we do all initialization using
3837 * initvals, so we don't have to modify
3838 * any settings (5210 also only supports
3841 if (ah
->ah_version
!= AR5K_AR5210
) {
3844 * Write initial RF gain settings
3845 * This should work for both 5111/5112
3847 ret
= ath5k_hw_rfgain_init(ah
, channel
->band
);
3851 usleep_range(1000, 1500);
3856 ret
= ath5k_hw_rfregs_init(ah
, channel
, mode
);
3860 /*Enable/disable 802.11b mode on 5111
3861 (enable 2111 frequency converter + CCK)*/
3862 if (ah
->ah_radio
== AR5K_RF5111
) {
3863 if (mode
== AR5K_MODE_11B
)
3864 AR5K_REG_ENABLE_BITS(ah
, AR5K_TXCFG
,
3867 AR5K_REG_DISABLE_BITS(ah
, AR5K_TXCFG
,
3871 } else if (ah
->ah_version
== AR5K_AR5210
) {
3872 usleep_range(1000, 1500);
3873 /* Disable phy and wait */
3874 ath5k_hw_reg_write(ah
, AR5K_PHY_ACT_DISABLE
, AR5K_PHY_ACT
);
3875 usleep_range(1000, 1500);
3878 /* Set channel on PHY */
3879 ret
= ath5k_hw_channel(ah
, channel
);
3884 * Enable the PHY and wait until completion
3885 * This includes BaseBand and Synthesizer
3888 ath5k_hw_reg_write(ah
, AR5K_PHY_ACT_ENABLE
, AR5K_PHY_ACT
);
3890 ath5k_hw_wait_for_synth(ah
, channel
);
3893 * Perform ADC test to see if baseband is ready
3894 * Set tx hold and check adc test register
3896 phy_tst1
= ath5k_hw_reg_read(ah
, AR5K_PHY_TST1
);
3897 ath5k_hw_reg_write(ah
, AR5K_PHY_TST1_TXHOLD
, AR5K_PHY_TST1
);
3898 for (i
= 0; i
<= 20; i
++) {
3899 if (!(ath5k_hw_reg_read(ah
, AR5K_PHY_ADC_TEST
) & 0x10))
3901 usleep_range(200, 250);
3903 ath5k_hw_reg_write(ah
, phy_tst1
, AR5K_PHY_TST1
);
3906 * Start automatic gain control calibration
3908 * During AGC calibration RX path is re-routed to
3909 * a power detector so we don't receive anything.
3911 * This method is used to calibrate some static offsets
3912 * used together with on-the fly I/Q calibration (the
3913 * one performed via ath5k_hw_phy_calibrate), which doesn't
3914 * interrupt rx path.
3916 * While rx path is re-routed to the power detector we also
3917 * start a noise floor calibration to measure the
3918 * card's noise floor (the noise we measure when we are not
3919 * transmitting or receiving anything).
3921 * If we are in a noisy environment, AGC calibration may time
3922 * out and/or noise floor calibration might timeout.
3924 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_AGCCTL
,
3925 AR5K_PHY_AGCCTL_CAL
| AR5K_PHY_AGCCTL_NF
);
3927 /* At the same time start I/Q calibration for QAM constellation
3928 * -no need for CCK- */
3929 ah
->ah_iq_cal_needed
= false;
3930 if (!(mode
== AR5K_MODE_11B
)) {
3931 ah
->ah_iq_cal_needed
= true;
3932 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_IQ
,
3933 AR5K_PHY_IQ_CAL_NUM_LOG_MAX
, 15);
3934 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_IQ
,
3938 /* Wait for gain calibration to finish (we check for I/Q calibration
3939 * during ath5k_phy_calibrate) */
3940 if (ath5k_hw_register_timeout(ah
, AR5K_PHY_AGCCTL
,
3941 AR5K_PHY_AGCCTL_CAL
, 0, false)) {
3942 ATH5K_ERR(ah
, "gain calibration timeout (%uMHz)\n",
3943 channel
->center_freq
);
3946 /* Restore antenna mode */
3947 ath5k_hw_set_antenna_mode(ah
, ah
->ah_ant_mode
);