ARM: at91/dt: at91sam9x5ek: use stdout-path
[linux-2.6/btrfs-unstable.git] / arch / arm / mm / cache-l2x0.c
blobe309c8f35af5af61e1d267bc212d7e4f08fbd786
1 /*
2 * arch/arm/mm/cache-l2x0.c - L210/L220/L310 cache controller support
4 * Copyright (C) 2007 ARM Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/cpu.h>
20 #include <linux/err.h>
21 #include <linux/init.h>
22 #include <linux/smp.h>
23 #include <linux/spinlock.h>
24 #include <linux/log2.h>
25 #include <linux/io.h>
26 #include <linux/of.h>
27 #include <linux/of_address.h>
29 #include <asm/cacheflush.h>
30 #include <asm/cp15.h>
31 #include <asm/cputype.h>
32 #include <asm/hardware/cache-l2x0.h>
33 #include "cache-tauros3.h"
34 #include "cache-aurora-l2.h"
36 struct l2c_init_data {
37 const char *type;
38 unsigned way_size_0;
39 unsigned num_lock;
40 void (*of_parse)(const struct device_node *, u32 *, u32 *);
41 void (*enable)(void __iomem *, u32, unsigned);
42 void (*fixup)(void __iomem *, u32, struct outer_cache_fns *);
43 void (*save)(void __iomem *);
44 void (*configure)(void __iomem *);
45 struct outer_cache_fns outer_cache;
48 #define CACHE_LINE_SIZE 32
50 static void __iomem *l2x0_base;
51 static const struct l2c_init_data *l2x0_data;
52 static DEFINE_RAW_SPINLOCK(l2x0_lock);
53 static u32 l2x0_way_mask; /* Bitmask of active ways */
54 static u32 l2x0_size;
55 static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
57 struct l2x0_regs l2x0_saved_regs;
60 * Common code for all cache controllers.
62 static inline void l2c_wait_mask(void __iomem *reg, unsigned long mask)
64 /* wait for cache operation by line or way to complete */
65 while (readl_relaxed(reg) & mask)
66 cpu_relax();
70 * By default, we write directly to secure registers. Platforms must
71 * override this if they are running non-secure.
73 static void l2c_write_sec(unsigned long val, void __iomem *base, unsigned reg)
75 if (val == readl_relaxed(base + reg))
76 return;
77 if (outer_cache.write_sec)
78 outer_cache.write_sec(val, reg);
79 else
80 writel_relaxed(val, base + reg);
84 * This should only be called when we have a requirement that the
85 * register be written due to a work-around, as platforms running
86 * in non-secure mode may not be able to access this register.
88 static inline void l2c_set_debug(void __iomem *base, unsigned long val)
90 l2c_write_sec(val, base, L2X0_DEBUG_CTRL);
93 static void __l2c_op_way(void __iomem *reg)
95 writel_relaxed(l2x0_way_mask, reg);
96 l2c_wait_mask(reg, l2x0_way_mask);
99 static inline void l2c_unlock(void __iomem *base, unsigned num)
101 unsigned i;
103 for (i = 0; i < num; i++) {
104 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_D_BASE +
105 i * L2X0_LOCKDOWN_STRIDE);
106 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_I_BASE +
107 i * L2X0_LOCKDOWN_STRIDE);
111 static void l2c_configure(void __iomem *base)
113 if (outer_cache.configure) {
114 outer_cache.configure(&l2x0_saved_regs);
115 return;
118 if (l2x0_data->configure)
119 l2x0_data->configure(base);
121 l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTRL);
125 * Enable the L2 cache controller. This function must only be
126 * called when the cache controller is known to be disabled.
128 static void l2c_enable(void __iomem *base, u32 aux, unsigned num_lock)
130 unsigned long flags;
132 /* Do not touch the controller if already enabled. */
133 if (readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)
134 return;
136 l2x0_saved_regs.aux_ctrl = aux;
137 l2c_configure(base);
139 l2c_unlock(base, num_lock);
141 local_irq_save(flags);
142 __l2c_op_way(base + L2X0_INV_WAY);
143 writel_relaxed(0, base + sync_reg_offset);
144 l2c_wait_mask(base + sync_reg_offset, 1);
145 local_irq_restore(flags);
147 l2c_write_sec(L2X0_CTRL_EN, base, L2X0_CTRL);
150 static void l2c_disable(void)
152 void __iomem *base = l2x0_base;
154 outer_cache.flush_all();
155 l2c_write_sec(0, base, L2X0_CTRL);
156 dsb(st);
159 static void l2c_save(void __iomem *base)
161 l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
164 static void l2c_resume(void)
166 l2c_enable(l2x0_base, l2x0_saved_regs.aux_ctrl, l2x0_data->num_lock);
170 * L2C-210 specific code.
172 * The L2C-2x0 PA, set/way and sync operations are atomic, but we must
173 * ensure that no background operation is running. The way operations
174 * are all background tasks.
176 * While a background operation is in progress, any new operation is
177 * ignored (unspecified whether this causes an error.) Thankfully, not
178 * used on SMP.
180 * Never has a different sync register other than L2X0_CACHE_SYNC, but
181 * we use sync_reg_offset here so we can share some of this with L2C-310.
183 static void __l2c210_cache_sync(void __iomem *base)
185 writel_relaxed(0, base + sync_reg_offset);
188 static void __l2c210_op_pa_range(void __iomem *reg, unsigned long start,
189 unsigned long end)
191 while (start < end) {
192 writel_relaxed(start, reg);
193 start += CACHE_LINE_SIZE;
197 static void l2c210_inv_range(unsigned long start, unsigned long end)
199 void __iomem *base = l2x0_base;
201 if (start & (CACHE_LINE_SIZE - 1)) {
202 start &= ~(CACHE_LINE_SIZE - 1);
203 writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA);
204 start += CACHE_LINE_SIZE;
207 if (end & (CACHE_LINE_SIZE - 1)) {
208 end &= ~(CACHE_LINE_SIZE - 1);
209 writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA);
212 __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end);
213 __l2c210_cache_sync(base);
216 static void l2c210_clean_range(unsigned long start, unsigned long end)
218 void __iomem *base = l2x0_base;
220 start &= ~(CACHE_LINE_SIZE - 1);
221 __l2c210_op_pa_range(base + L2X0_CLEAN_LINE_PA, start, end);
222 __l2c210_cache_sync(base);
225 static void l2c210_flush_range(unsigned long start, unsigned long end)
227 void __iomem *base = l2x0_base;
229 start &= ~(CACHE_LINE_SIZE - 1);
230 __l2c210_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA, start, end);
231 __l2c210_cache_sync(base);
234 static void l2c210_flush_all(void)
236 void __iomem *base = l2x0_base;
238 BUG_ON(!irqs_disabled());
240 __l2c_op_way(base + L2X0_CLEAN_INV_WAY);
241 __l2c210_cache_sync(base);
244 static void l2c210_sync(void)
246 __l2c210_cache_sync(l2x0_base);
249 static const struct l2c_init_data l2c210_data __initconst = {
250 .type = "L2C-210",
251 .way_size_0 = SZ_8K,
252 .num_lock = 1,
253 .enable = l2c_enable,
254 .save = l2c_save,
255 .outer_cache = {
256 .inv_range = l2c210_inv_range,
257 .clean_range = l2c210_clean_range,
258 .flush_range = l2c210_flush_range,
259 .flush_all = l2c210_flush_all,
260 .disable = l2c_disable,
261 .sync = l2c210_sync,
262 .resume = l2c_resume,
267 * L2C-220 specific code.
269 * All operations are background operations: they have to be waited for.
270 * Conflicting requests generate a slave error (which will cause an
271 * imprecise abort.) Never uses sync_reg_offset, so we hard-code the
272 * sync register here.
274 * However, we can re-use the l2c210_resume call.
276 static inline void __l2c220_cache_sync(void __iomem *base)
278 writel_relaxed(0, base + L2X0_CACHE_SYNC);
279 l2c_wait_mask(base + L2X0_CACHE_SYNC, 1);
282 static void l2c220_op_way(void __iomem *base, unsigned reg)
284 unsigned long flags;
286 raw_spin_lock_irqsave(&l2x0_lock, flags);
287 __l2c_op_way(base + reg);
288 __l2c220_cache_sync(base);
289 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
292 static unsigned long l2c220_op_pa_range(void __iomem *reg, unsigned long start,
293 unsigned long end, unsigned long flags)
295 raw_spinlock_t *lock = &l2x0_lock;
297 while (start < end) {
298 unsigned long blk_end = start + min(end - start, 4096UL);
300 while (start < blk_end) {
301 l2c_wait_mask(reg, 1);
302 writel_relaxed(start, reg);
303 start += CACHE_LINE_SIZE;
306 if (blk_end < end) {
307 raw_spin_unlock_irqrestore(lock, flags);
308 raw_spin_lock_irqsave(lock, flags);
312 return flags;
315 static void l2c220_inv_range(unsigned long start, unsigned long end)
317 void __iomem *base = l2x0_base;
318 unsigned long flags;
320 raw_spin_lock_irqsave(&l2x0_lock, flags);
321 if ((start | end) & (CACHE_LINE_SIZE - 1)) {
322 if (start & (CACHE_LINE_SIZE - 1)) {
323 start &= ~(CACHE_LINE_SIZE - 1);
324 writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA);
325 start += CACHE_LINE_SIZE;
328 if (end & (CACHE_LINE_SIZE - 1)) {
329 end &= ~(CACHE_LINE_SIZE - 1);
330 l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1);
331 writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA);
335 flags = l2c220_op_pa_range(base + L2X0_INV_LINE_PA,
336 start, end, flags);
337 l2c_wait_mask(base + L2X0_INV_LINE_PA, 1);
338 __l2c220_cache_sync(base);
339 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
342 static void l2c220_clean_range(unsigned long start, unsigned long end)
344 void __iomem *base = l2x0_base;
345 unsigned long flags;
347 start &= ~(CACHE_LINE_SIZE - 1);
348 if ((end - start) >= l2x0_size) {
349 l2c220_op_way(base, L2X0_CLEAN_WAY);
350 return;
353 raw_spin_lock_irqsave(&l2x0_lock, flags);
354 flags = l2c220_op_pa_range(base + L2X0_CLEAN_LINE_PA,
355 start, end, flags);
356 l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1);
357 __l2c220_cache_sync(base);
358 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
361 static void l2c220_flush_range(unsigned long start, unsigned long end)
363 void __iomem *base = l2x0_base;
364 unsigned long flags;
366 start &= ~(CACHE_LINE_SIZE - 1);
367 if ((end - start) >= l2x0_size) {
368 l2c220_op_way(base, L2X0_CLEAN_INV_WAY);
369 return;
372 raw_spin_lock_irqsave(&l2x0_lock, flags);
373 flags = l2c220_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA,
374 start, end, flags);
375 l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1);
376 __l2c220_cache_sync(base);
377 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
380 static void l2c220_flush_all(void)
382 l2c220_op_way(l2x0_base, L2X0_CLEAN_INV_WAY);
385 static void l2c220_sync(void)
387 unsigned long flags;
389 raw_spin_lock_irqsave(&l2x0_lock, flags);
390 __l2c220_cache_sync(l2x0_base);
391 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
394 static void l2c220_enable(void __iomem *base, u32 aux, unsigned num_lock)
397 * Always enable non-secure access to the lockdown registers -
398 * we write to them as part of the L2C enable sequence so they
399 * need to be accessible.
401 aux |= L220_AUX_CTRL_NS_LOCKDOWN;
403 l2c_enable(base, aux, num_lock);
406 static const struct l2c_init_data l2c220_data = {
407 .type = "L2C-220",
408 .way_size_0 = SZ_8K,
409 .num_lock = 1,
410 .enable = l2c220_enable,
411 .save = l2c_save,
412 .outer_cache = {
413 .inv_range = l2c220_inv_range,
414 .clean_range = l2c220_clean_range,
415 .flush_range = l2c220_flush_range,
416 .flush_all = l2c220_flush_all,
417 .disable = l2c_disable,
418 .sync = l2c220_sync,
419 .resume = l2c_resume,
424 * L2C-310 specific code.
426 * Very similar to L2C-210, the PA, set/way and sync operations are atomic,
427 * and the way operations are all background tasks. However, issuing an
428 * operation while a background operation is in progress results in a
429 * SLVERR response. We can reuse:
431 * __l2c210_cache_sync (using sync_reg_offset)
432 * l2c210_sync
433 * l2c210_inv_range (if 588369 is not applicable)
434 * l2c210_clean_range
435 * l2c210_flush_range (if 588369 is not applicable)
436 * l2c210_flush_all (if 727915 is not applicable)
438 * Errata:
439 * 588369: PL310 R0P0->R1P0, fixed R2P0.
440 * Affects: all clean+invalidate operations
441 * clean and invalidate skips the invalidate step, so we need to issue
442 * separate operations. We also require the above debug workaround
443 * enclosing this code fragment on affected parts. On unaffected parts,
444 * we must not use this workaround without the debug register writes
445 * to avoid exposing a problem similar to 727915.
447 * 727915: PL310 R2P0->R3P0, fixed R3P1.
448 * Affects: clean+invalidate by way
449 * clean and invalidate by way runs in the background, and a store can
450 * hit the line between the clean operation and invalidate operation,
451 * resulting in the store being lost.
453 * 752271: PL310 R3P0->R3P1-50REL0, fixed R3P2.
454 * Affects: 8x64-bit (double fill) line fetches
455 * double fill line fetches can fail to cause dirty data to be evicted
456 * from the cache before the new data overwrites the second line.
458 * 753970: PL310 R3P0, fixed R3P1.
459 * Affects: sync
460 * prevents merging writes after the sync operation, until another L2C
461 * operation is performed (or a number of other conditions.)
463 * 769419: PL310 R0P0->R3P1, fixed R3P2.
464 * Affects: store buffer
465 * store buffer is not automatically drained.
467 static void l2c310_inv_range_erratum(unsigned long start, unsigned long end)
469 void __iomem *base = l2x0_base;
471 if ((start | end) & (CACHE_LINE_SIZE - 1)) {
472 unsigned long flags;
474 /* Erratum 588369 for both clean+invalidate operations */
475 raw_spin_lock_irqsave(&l2x0_lock, flags);
476 l2c_set_debug(base, 0x03);
478 if (start & (CACHE_LINE_SIZE - 1)) {
479 start &= ~(CACHE_LINE_SIZE - 1);
480 writel_relaxed(start, base + L2X0_CLEAN_LINE_PA);
481 writel_relaxed(start, base + L2X0_INV_LINE_PA);
482 start += CACHE_LINE_SIZE;
485 if (end & (CACHE_LINE_SIZE - 1)) {
486 end &= ~(CACHE_LINE_SIZE - 1);
487 writel_relaxed(end, base + L2X0_CLEAN_LINE_PA);
488 writel_relaxed(end, base + L2X0_INV_LINE_PA);
491 l2c_set_debug(base, 0x00);
492 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
495 __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end);
496 __l2c210_cache_sync(base);
499 static void l2c310_flush_range_erratum(unsigned long start, unsigned long end)
501 raw_spinlock_t *lock = &l2x0_lock;
502 unsigned long flags;
503 void __iomem *base = l2x0_base;
505 raw_spin_lock_irqsave(lock, flags);
506 while (start < end) {
507 unsigned long blk_end = start + min(end - start, 4096UL);
509 l2c_set_debug(base, 0x03);
510 while (start < blk_end) {
511 writel_relaxed(start, base + L2X0_CLEAN_LINE_PA);
512 writel_relaxed(start, base + L2X0_INV_LINE_PA);
513 start += CACHE_LINE_SIZE;
515 l2c_set_debug(base, 0x00);
517 if (blk_end < end) {
518 raw_spin_unlock_irqrestore(lock, flags);
519 raw_spin_lock_irqsave(lock, flags);
522 raw_spin_unlock_irqrestore(lock, flags);
523 __l2c210_cache_sync(base);
526 static void l2c310_flush_all_erratum(void)
528 void __iomem *base = l2x0_base;
529 unsigned long flags;
531 raw_spin_lock_irqsave(&l2x0_lock, flags);
532 l2c_set_debug(base, 0x03);
533 __l2c_op_way(base + L2X0_CLEAN_INV_WAY);
534 l2c_set_debug(base, 0x00);
535 __l2c210_cache_sync(base);
536 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
539 static void __init l2c310_save(void __iomem *base)
541 unsigned revision;
543 l2c_save(base);
545 l2x0_saved_regs.tag_latency = readl_relaxed(base +
546 L310_TAG_LATENCY_CTRL);
547 l2x0_saved_regs.data_latency = readl_relaxed(base +
548 L310_DATA_LATENCY_CTRL);
549 l2x0_saved_regs.filter_end = readl_relaxed(base +
550 L310_ADDR_FILTER_END);
551 l2x0_saved_regs.filter_start = readl_relaxed(base +
552 L310_ADDR_FILTER_START);
554 revision = readl_relaxed(base + L2X0_CACHE_ID) &
555 L2X0_CACHE_ID_RTL_MASK;
557 /* From r2p0, there is Prefetch offset/control register */
558 if (revision >= L310_CACHE_ID_RTL_R2P0)
559 l2x0_saved_regs.prefetch_ctrl = readl_relaxed(base +
560 L310_PREFETCH_CTRL);
562 /* From r3p0, there is Power control register */
563 if (revision >= L310_CACHE_ID_RTL_R3P0)
564 l2x0_saved_regs.pwr_ctrl = readl_relaxed(base +
565 L310_POWER_CTRL);
568 static void l2c310_configure(void __iomem *base)
570 unsigned revision;
572 /* restore pl310 setup */
573 l2c_write_sec(l2x0_saved_regs.tag_latency, base,
574 L310_TAG_LATENCY_CTRL);
575 l2c_write_sec(l2x0_saved_regs.data_latency, base,
576 L310_DATA_LATENCY_CTRL);
577 l2c_write_sec(l2x0_saved_regs.filter_end, base,
578 L310_ADDR_FILTER_END);
579 l2c_write_sec(l2x0_saved_regs.filter_start, base,
580 L310_ADDR_FILTER_START);
582 revision = readl_relaxed(base + L2X0_CACHE_ID) &
583 L2X0_CACHE_ID_RTL_MASK;
585 if (revision >= L310_CACHE_ID_RTL_R2P0)
586 l2c_write_sec(l2x0_saved_regs.prefetch_ctrl, base,
587 L310_PREFETCH_CTRL);
588 if (revision >= L310_CACHE_ID_RTL_R3P0)
589 l2c_write_sec(l2x0_saved_regs.pwr_ctrl, base,
590 L310_POWER_CTRL);
593 static int l2c310_cpu_enable_flz(struct notifier_block *nb, unsigned long act, void *data)
595 switch (act & ~CPU_TASKS_FROZEN) {
596 case CPU_STARTING:
597 set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1));
598 break;
599 case CPU_DYING:
600 set_auxcr(get_auxcr() & ~(BIT(3) | BIT(2) | BIT(1)));
601 break;
603 return NOTIFY_OK;
606 static void __init l2c310_enable(void __iomem *base, u32 aux, unsigned num_lock)
608 unsigned rev = readl_relaxed(base + L2X0_CACHE_ID) & L2X0_CACHE_ID_RTL_MASK;
609 bool cortex_a9 = read_cpuid_part() == ARM_CPU_PART_CORTEX_A9;
611 if (rev >= L310_CACHE_ID_RTL_R2P0) {
612 if (cortex_a9) {
613 aux |= L310_AUX_CTRL_EARLY_BRESP;
614 pr_info("L2C-310 enabling early BRESP for Cortex-A9\n");
615 } else if (aux & L310_AUX_CTRL_EARLY_BRESP) {
616 pr_warn("L2C-310 early BRESP only supported with Cortex-A9\n");
617 aux &= ~L310_AUX_CTRL_EARLY_BRESP;
621 if (cortex_a9) {
622 u32 aux_cur = readl_relaxed(base + L2X0_AUX_CTRL);
623 u32 acr = get_auxcr();
625 pr_debug("Cortex-A9 ACR=0x%08x\n", acr);
627 if (acr & BIT(3) && !(aux_cur & L310_AUX_CTRL_FULL_LINE_ZERO))
628 pr_err("L2C-310: full line of zeros enabled in Cortex-A9 but not L2C-310 - invalid\n");
630 if (aux & L310_AUX_CTRL_FULL_LINE_ZERO && !(acr & BIT(3)))
631 pr_err("L2C-310: enabling full line of zeros but not enabled in Cortex-A9\n");
633 if (!(aux & L310_AUX_CTRL_FULL_LINE_ZERO) && !outer_cache.write_sec) {
634 aux |= L310_AUX_CTRL_FULL_LINE_ZERO;
635 pr_info("L2C-310 full line of zeros enabled for Cortex-A9\n");
637 } else if (aux & (L310_AUX_CTRL_FULL_LINE_ZERO | L310_AUX_CTRL_EARLY_BRESP)) {
638 pr_err("L2C-310: disabling Cortex-A9 specific feature bits\n");
639 aux &= ~(L310_AUX_CTRL_FULL_LINE_ZERO | L310_AUX_CTRL_EARLY_BRESP);
642 /* r3p0 or later has power control register */
643 if (rev >= L310_CACHE_ID_RTL_R3P0)
644 l2x0_saved_regs.pwr_ctrl = L310_DYNAMIC_CLK_GATING_EN |
645 L310_STNDBY_MODE_EN;
648 * Always enable non-secure access to the lockdown registers -
649 * we write to them as part of the L2C enable sequence so they
650 * need to be accessible.
652 aux |= L310_AUX_CTRL_NS_LOCKDOWN;
654 l2c_enable(base, aux, num_lock);
656 /* Read back resulting AUX_CTRL value as it could have been altered. */
657 aux = readl_relaxed(base + L2X0_AUX_CTRL);
659 if (aux & (L310_AUX_CTRL_DATA_PREFETCH | L310_AUX_CTRL_INSTR_PREFETCH)) {
660 u32 prefetch = readl_relaxed(base + L310_PREFETCH_CTRL);
662 pr_info("L2C-310 %s%s prefetch enabled, offset %u lines\n",
663 aux & L310_AUX_CTRL_INSTR_PREFETCH ? "I" : "",
664 aux & L310_AUX_CTRL_DATA_PREFETCH ? "D" : "",
665 1 + (prefetch & L310_PREFETCH_CTRL_OFFSET_MASK));
668 /* r3p0 or later has power control register */
669 if (rev >= L310_CACHE_ID_RTL_R3P0) {
670 u32 power_ctrl;
672 power_ctrl = readl_relaxed(base + L310_POWER_CTRL);
673 pr_info("L2C-310 dynamic clock gating %sabled, standby mode %sabled\n",
674 power_ctrl & L310_DYNAMIC_CLK_GATING_EN ? "en" : "dis",
675 power_ctrl & L310_STNDBY_MODE_EN ? "en" : "dis");
678 if (aux & L310_AUX_CTRL_FULL_LINE_ZERO) {
679 set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1));
680 cpu_notifier(l2c310_cpu_enable_flz, 0);
684 static void __init l2c310_fixup(void __iomem *base, u32 cache_id,
685 struct outer_cache_fns *fns)
687 unsigned revision = cache_id & L2X0_CACHE_ID_RTL_MASK;
688 const char *errata[8];
689 unsigned n = 0;
691 if (IS_ENABLED(CONFIG_PL310_ERRATA_588369) &&
692 revision < L310_CACHE_ID_RTL_R2P0 &&
693 /* For bcm compatibility */
694 fns->inv_range == l2c210_inv_range) {
695 fns->inv_range = l2c310_inv_range_erratum;
696 fns->flush_range = l2c310_flush_range_erratum;
697 errata[n++] = "588369";
700 if (IS_ENABLED(CONFIG_PL310_ERRATA_727915) &&
701 revision >= L310_CACHE_ID_RTL_R2P0 &&
702 revision < L310_CACHE_ID_RTL_R3P1) {
703 fns->flush_all = l2c310_flush_all_erratum;
704 errata[n++] = "727915";
707 if (revision >= L310_CACHE_ID_RTL_R3P0 &&
708 revision < L310_CACHE_ID_RTL_R3P2) {
709 u32 val = l2x0_saved_regs.prefetch_ctrl;
710 /* I don't think bit23 is required here... but iMX6 does so */
711 if (val & (BIT(30) | BIT(23))) {
712 val &= ~(BIT(30) | BIT(23));
713 l2x0_saved_regs.prefetch_ctrl = val;
714 errata[n++] = "752271";
718 if (IS_ENABLED(CONFIG_PL310_ERRATA_753970) &&
719 revision == L310_CACHE_ID_RTL_R3P0) {
720 sync_reg_offset = L2X0_DUMMY_REG;
721 errata[n++] = "753970";
724 if (IS_ENABLED(CONFIG_PL310_ERRATA_769419))
725 errata[n++] = "769419";
727 if (n) {
728 unsigned i;
730 pr_info("L2C-310 errat%s", n > 1 ? "a" : "um");
731 for (i = 0; i < n; i++)
732 pr_cont(" %s", errata[i]);
733 pr_cont(" enabled\n");
737 static void l2c310_disable(void)
740 * If full-line-of-zeros is enabled, we must first disable it in the
741 * Cortex-A9 auxiliary control register before disabling the L2 cache.
743 if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_FULL_LINE_ZERO)
744 set_auxcr(get_auxcr() & ~(BIT(3) | BIT(2) | BIT(1)));
746 l2c_disable();
749 static void l2c310_resume(void)
751 l2c_resume();
753 /* Re-enable full-line-of-zeros for Cortex-A9 */
754 if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_FULL_LINE_ZERO)
755 set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1));
758 static const struct l2c_init_data l2c310_init_fns __initconst = {
759 .type = "L2C-310",
760 .way_size_0 = SZ_8K,
761 .num_lock = 8,
762 .enable = l2c310_enable,
763 .fixup = l2c310_fixup,
764 .save = l2c310_save,
765 .configure = l2c310_configure,
766 .outer_cache = {
767 .inv_range = l2c210_inv_range,
768 .clean_range = l2c210_clean_range,
769 .flush_range = l2c210_flush_range,
770 .flush_all = l2c210_flush_all,
771 .disable = l2c310_disable,
772 .sync = l2c210_sync,
773 .resume = l2c310_resume,
777 static int __init __l2c_init(const struct l2c_init_data *data,
778 u32 aux_val, u32 aux_mask, u32 cache_id)
780 struct outer_cache_fns fns;
781 unsigned way_size_bits, ways;
782 u32 aux, old_aux;
785 * Save the pointer globally so that callbacks which do not receive
786 * context from callers can access the structure.
788 l2x0_data = kmemdup(data, sizeof(*data), GFP_KERNEL);
789 if (!l2x0_data)
790 return -ENOMEM;
793 * Sanity check the aux values. aux_mask is the bits we preserve
794 * from reading the hardware register, and aux_val is the bits we
795 * set.
797 if (aux_val & aux_mask)
798 pr_alert("L2C: platform provided aux values permit register corruption.\n");
800 old_aux = aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
801 aux &= aux_mask;
802 aux |= aux_val;
804 if (old_aux != aux)
805 pr_warn("L2C: DT/platform modifies aux control register: 0x%08x -> 0x%08x\n",
806 old_aux, aux);
808 /* Determine the number of ways */
809 switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
810 case L2X0_CACHE_ID_PART_L310:
811 if ((aux_val | ~aux_mask) & (L2C_AUX_CTRL_WAY_SIZE_MASK | L310_AUX_CTRL_ASSOCIATIVITY_16))
812 pr_warn("L2C: DT/platform tries to modify or specify cache size\n");
813 if (aux & (1 << 16))
814 ways = 16;
815 else
816 ways = 8;
817 break;
819 case L2X0_CACHE_ID_PART_L210:
820 case L2X0_CACHE_ID_PART_L220:
821 ways = (aux >> 13) & 0xf;
822 break;
824 case AURORA_CACHE_ID:
825 ways = (aux >> 13) & 0xf;
826 ways = 2 << ((ways + 1) >> 2);
827 break;
829 default:
830 /* Assume unknown chips have 8 ways */
831 ways = 8;
832 break;
835 l2x0_way_mask = (1 << ways) - 1;
838 * way_size_0 is the size that a way_size value of zero would be
839 * given the calculation: way_size = way_size_0 << way_size_bits.
840 * So, if way_size_bits=0 is reserved, but way_size_bits=1 is 16k,
841 * then way_size_0 would be 8k.
843 * L2 cache size = number of ways * way size.
845 way_size_bits = (aux & L2C_AUX_CTRL_WAY_SIZE_MASK) >>
846 L2C_AUX_CTRL_WAY_SIZE_SHIFT;
847 l2x0_size = ways * (data->way_size_0 << way_size_bits);
849 fns = data->outer_cache;
850 fns.write_sec = outer_cache.write_sec;
851 fns.configure = outer_cache.configure;
852 if (data->fixup)
853 data->fixup(l2x0_base, cache_id, &fns);
856 * Check if l2x0 controller is already enabled. If we are booting
857 * in non-secure mode accessing the below registers will fault.
859 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN))
860 data->enable(l2x0_base, aux, data->num_lock);
862 outer_cache = fns;
865 * It is strange to save the register state before initialisation,
866 * but hey, this is what the DT implementations decided to do.
868 if (data->save)
869 data->save(l2x0_base);
871 /* Re-read it in case some bits are reserved. */
872 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
874 pr_info("%s cache controller enabled, %d ways, %d kB\n",
875 data->type, ways, l2x0_size >> 10);
876 pr_info("%s: CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
877 data->type, cache_id, aux);
879 return 0;
882 void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
884 const struct l2c_init_data *data;
885 u32 cache_id;
887 l2x0_base = base;
889 cache_id = readl_relaxed(base + L2X0_CACHE_ID);
891 switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
892 default:
893 case L2X0_CACHE_ID_PART_L210:
894 data = &l2c210_data;
895 break;
897 case L2X0_CACHE_ID_PART_L220:
898 data = &l2c220_data;
899 break;
901 case L2X0_CACHE_ID_PART_L310:
902 data = &l2c310_init_fns;
903 break;
906 /* Read back current (default) hardware configuration */
907 if (data->save)
908 data->save(l2x0_base);
910 __l2c_init(data, aux_val, aux_mask, cache_id);
913 #ifdef CONFIG_OF
914 static int l2_wt_override;
916 /* Aurora don't have the cache ID register available, so we have to
917 * pass it though the device tree */
918 static u32 cache_id_part_number_from_dt;
921 * l2x0_cache_size_of_parse() - read cache size parameters from DT
922 * @np: the device tree node for the l2 cache
923 * @aux_val: pointer to machine-supplied auxilary register value, to
924 * be augmented by the call (bits to be set to 1)
925 * @aux_mask: pointer to machine-supplied auxilary register mask, to
926 * be augmented by the call (bits to be set to 0)
927 * @associativity: variable to return the calculated associativity in
928 * @max_way_size: the maximum size in bytes for the cache ways
930 static int __init l2x0_cache_size_of_parse(const struct device_node *np,
931 u32 *aux_val, u32 *aux_mask,
932 u32 *associativity,
933 u32 max_way_size)
935 u32 mask = 0, val = 0;
936 u32 cache_size = 0, sets = 0;
937 u32 way_size_bits = 1;
938 u32 way_size = 0;
939 u32 block_size = 0;
940 u32 line_size = 0;
942 of_property_read_u32(np, "cache-size", &cache_size);
943 of_property_read_u32(np, "cache-sets", &sets);
944 of_property_read_u32(np, "cache-block-size", &block_size);
945 of_property_read_u32(np, "cache-line-size", &line_size);
947 if (!cache_size || !sets)
948 return -ENODEV;
950 /* All these l2 caches have the same line = block size actually */
951 if (!line_size) {
952 if (block_size) {
953 /* If linesize is not given, it is equal to blocksize */
954 line_size = block_size;
955 } else {
956 /* Fall back to known size */
957 pr_warn("L2C OF: no cache block/line size given: "
958 "falling back to default size %d bytes\n",
959 CACHE_LINE_SIZE);
960 line_size = CACHE_LINE_SIZE;
964 if (line_size != CACHE_LINE_SIZE)
965 pr_warn("L2C OF: DT supplied line size %d bytes does "
966 "not match hardware line size of %d bytes\n",
967 line_size,
968 CACHE_LINE_SIZE);
971 * Since:
972 * set size = cache size / sets
973 * ways = cache size / (sets * line size)
974 * way size = cache size / (cache size / (sets * line size))
975 * way size = sets * line size
976 * associativity = ways = cache size / way size
978 way_size = sets * line_size;
979 *associativity = cache_size / way_size;
981 if (way_size > max_way_size) {
982 pr_err("L2C OF: set size %dKB is too large\n", way_size);
983 return -EINVAL;
986 pr_info("L2C OF: override cache size: %d bytes (%dKB)\n",
987 cache_size, cache_size >> 10);
988 pr_info("L2C OF: override line size: %d bytes\n", line_size);
989 pr_info("L2C OF: override way size: %d bytes (%dKB)\n",
990 way_size, way_size >> 10);
991 pr_info("L2C OF: override associativity: %d\n", *associativity);
994 * Calculates the bits 17:19 to set for way size:
995 * 512KB -> 6, 256KB -> 5, ... 16KB -> 1
997 way_size_bits = ilog2(way_size >> 10) - 3;
998 if (way_size_bits < 1 || way_size_bits > 6) {
999 pr_err("L2C OF: cache way size illegal: %dKB is not mapped\n",
1000 way_size);
1001 return -EINVAL;
1004 mask |= L2C_AUX_CTRL_WAY_SIZE_MASK;
1005 val |= (way_size_bits << L2C_AUX_CTRL_WAY_SIZE_SHIFT);
1007 *aux_val &= ~mask;
1008 *aux_val |= val;
1009 *aux_mask &= ~mask;
1011 return 0;
1014 static void __init l2x0_of_parse(const struct device_node *np,
1015 u32 *aux_val, u32 *aux_mask)
1017 u32 data[2] = { 0, 0 };
1018 u32 tag = 0;
1019 u32 dirty = 0;
1020 u32 val = 0, mask = 0;
1021 u32 assoc;
1022 int ret;
1024 of_property_read_u32(np, "arm,tag-latency", &tag);
1025 if (tag) {
1026 mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK;
1027 val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT;
1030 of_property_read_u32_array(np, "arm,data-latency",
1031 data, ARRAY_SIZE(data));
1032 if (data[0] && data[1]) {
1033 mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK |
1034 L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK;
1035 val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) |
1036 ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT);
1039 of_property_read_u32(np, "arm,dirty-latency", &dirty);
1040 if (dirty) {
1041 mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK;
1042 val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
1045 ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_256K);
1046 if (ret)
1047 return;
1049 if (assoc > 8) {
1050 pr_err("l2x0 of: cache setting yield too high associativity\n");
1051 pr_err("l2x0 of: %d calculated, max 8\n", assoc);
1052 } else {
1053 mask |= L2X0_AUX_CTRL_ASSOC_MASK;
1054 val |= (assoc << L2X0_AUX_CTRL_ASSOC_SHIFT);
1057 *aux_val &= ~mask;
1058 *aux_val |= val;
1059 *aux_mask &= ~mask;
1062 static const struct l2c_init_data of_l2c210_data __initconst = {
1063 .type = "L2C-210",
1064 .way_size_0 = SZ_8K,
1065 .num_lock = 1,
1066 .of_parse = l2x0_of_parse,
1067 .enable = l2c_enable,
1068 .save = l2c_save,
1069 .outer_cache = {
1070 .inv_range = l2c210_inv_range,
1071 .clean_range = l2c210_clean_range,
1072 .flush_range = l2c210_flush_range,
1073 .flush_all = l2c210_flush_all,
1074 .disable = l2c_disable,
1075 .sync = l2c210_sync,
1076 .resume = l2c_resume,
1080 static const struct l2c_init_data of_l2c220_data __initconst = {
1081 .type = "L2C-220",
1082 .way_size_0 = SZ_8K,
1083 .num_lock = 1,
1084 .of_parse = l2x0_of_parse,
1085 .enable = l2c220_enable,
1086 .save = l2c_save,
1087 .outer_cache = {
1088 .inv_range = l2c220_inv_range,
1089 .clean_range = l2c220_clean_range,
1090 .flush_range = l2c220_flush_range,
1091 .flush_all = l2c220_flush_all,
1092 .disable = l2c_disable,
1093 .sync = l2c220_sync,
1094 .resume = l2c_resume,
1098 static void __init l2c310_of_parse(const struct device_node *np,
1099 u32 *aux_val, u32 *aux_mask)
1101 u32 data[3] = { 0, 0, 0 };
1102 u32 tag[3] = { 0, 0, 0 };
1103 u32 filter[2] = { 0, 0 };
1104 u32 assoc;
1105 u32 prefetch;
1106 u32 val;
1107 int ret;
1109 of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
1110 if (tag[0] && tag[1] && tag[2])
1111 l2x0_saved_regs.tag_latency =
1112 L310_LATENCY_CTRL_RD(tag[0] - 1) |
1113 L310_LATENCY_CTRL_WR(tag[1] - 1) |
1114 L310_LATENCY_CTRL_SETUP(tag[2] - 1);
1116 of_property_read_u32_array(np, "arm,data-latency",
1117 data, ARRAY_SIZE(data));
1118 if (data[0] && data[1] && data[2])
1119 l2x0_saved_regs.data_latency =
1120 L310_LATENCY_CTRL_RD(data[0] - 1) |
1121 L310_LATENCY_CTRL_WR(data[1] - 1) |
1122 L310_LATENCY_CTRL_SETUP(data[2] - 1);
1124 of_property_read_u32_array(np, "arm,filter-ranges",
1125 filter, ARRAY_SIZE(filter));
1126 if (filter[1]) {
1127 l2x0_saved_regs.filter_end =
1128 ALIGN(filter[0] + filter[1], SZ_1M);
1129 l2x0_saved_regs.filter_start = (filter[0] & ~(SZ_1M - 1))
1130 | L310_ADDR_FILTER_EN;
1133 ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_512K);
1134 if (!ret) {
1135 switch (assoc) {
1136 case 16:
1137 *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK;
1138 *aux_val |= L310_AUX_CTRL_ASSOCIATIVITY_16;
1139 *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK;
1140 break;
1141 case 8:
1142 *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK;
1143 *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK;
1144 break;
1145 default:
1146 pr_err("L2C-310 OF cache associativity %d invalid, only 8 or 16 permitted\n",
1147 assoc);
1148 break;
1152 prefetch = l2x0_saved_regs.prefetch_ctrl;
1154 ret = of_property_read_u32(np, "arm,double-linefill", &val);
1155 if (ret == 0) {
1156 if (val)
1157 prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL;
1158 else
1159 prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL;
1160 } else if (ret != -EINVAL) {
1161 pr_err("L2C-310 OF arm,double-linefill property value is missing\n");
1164 ret = of_property_read_u32(np, "arm,double-linefill-incr", &val);
1165 if (ret == 0) {
1166 if (val)
1167 prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_INCR;
1168 else
1169 prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL_INCR;
1170 } else if (ret != -EINVAL) {
1171 pr_err("L2C-310 OF arm,double-linefill-incr property value is missing\n");
1174 ret = of_property_read_u32(np, "arm,double-linefill-wrap", &val);
1175 if (ret == 0) {
1176 if (!val)
1177 prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP;
1178 else
1179 prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP;
1180 } else if (ret != -EINVAL) {
1181 pr_err("L2C-310 OF arm,double-linefill-wrap property value is missing\n");
1184 ret = of_property_read_u32(np, "arm,prefetch-drop", &val);
1185 if (ret == 0) {
1186 if (val)
1187 prefetch |= L310_PREFETCH_CTRL_PREFETCH_DROP;
1188 else
1189 prefetch &= ~L310_PREFETCH_CTRL_PREFETCH_DROP;
1190 } else if (ret != -EINVAL) {
1191 pr_err("L2C-310 OF arm,prefetch-drop property value is missing\n");
1194 ret = of_property_read_u32(np, "arm,prefetch-offset", &val);
1195 if (ret == 0) {
1196 prefetch &= ~L310_PREFETCH_CTRL_OFFSET_MASK;
1197 prefetch |= val & L310_PREFETCH_CTRL_OFFSET_MASK;
1198 } else if (ret != -EINVAL) {
1199 pr_err("L2C-310 OF arm,prefetch-offset property value is missing\n");
1202 l2x0_saved_regs.prefetch_ctrl = prefetch;
1205 static const struct l2c_init_data of_l2c310_data __initconst = {
1206 .type = "L2C-310",
1207 .way_size_0 = SZ_8K,
1208 .num_lock = 8,
1209 .of_parse = l2c310_of_parse,
1210 .enable = l2c310_enable,
1211 .fixup = l2c310_fixup,
1212 .save = l2c310_save,
1213 .configure = l2c310_configure,
1214 .outer_cache = {
1215 .inv_range = l2c210_inv_range,
1216 .clean_range = l2c210_clean_range,
1217 .flush_range = l2c210_flush_range,
1218 .flush_all = l2c210_flush_all,
1219 .disable = l2c310_disable,
1220 .sync = l2c210_sync,
1221 .resume = l2c310_resume,
1226 * This is a variant of the of_l2c310_data with .sync set to
1227 * NULL. Outer sync operations are not needed when the system is I/O
1228 * coherent, and potentially harmful in certain situations (PCIe/PL310
1229 * deadlock on Armada 375/38x due to hardware I/O coherency). The
1230 * other operations are kept because they are infrequent (therefore do
1231 * not cause the deadlock in practice) and needed for secondary CPU
1232 * boot and other power management activities.
1234 static const struct l2c_init_data of_l2c310_coherent_data __initconst = {
1235 .type = "L2C-310 Coherent",
1236 .way_size_0 = SZ_8K,
1237 .num_lock = 8,
1238 .of_parse = l2c310_of_parse,
1239 .enable = l2c310_enable,
1240 .fixup = l2c310_fixup,
1241 .save = l2c310_save,
1242 .configure = l2c310_configure,
1243 .outer_cache = {
1244 .inv_range = l2c210_inv_range,
1245 .clean_range = l2c210_clean_range,
1246 .flush_range = l2c210_flush_range,
1247 .flush_all = l2c210_flush_all,
1248 .disable = l2c310_disable,
1249 .resume = l2c310_resume,
1254 * Note that the end addresses passed to Linux primitives are
1255 * noninclusive, while the hardware cache range operations use
1256 * inclusive start and end addresses.
1258 static unsigned long aurora_range_end(unsigned long start, unsigned long end)
1261 * Limit the number of cache lines processed at once,
1262 * since cache range operations stall the CPU pipeline
1263 * until completion.
1265 if (end > start + MAX_RANGE_SIZE)
1266 end = start + MAX_RANGE_SIZE;
1269 * Cache range operations can't straddle a page boundary.
1271 if (end > PAGE_ALIGN(start+1))
1272 end = PAGE_ALIGN(start+1);
1274 return end;
1277 static void aurora_pa_range(unsigned long start, unsigned long end,
1278 unsigned long offset)
1280 void __iomem *base = l2x0_base;
1281 unsigned long range_end;
1282 unsigned long flags;
1285 * round start and end adresses up to cache line size
1287 start &= ~(CACHE_LINE_SIZE - 1);
1288 end = ALIGN(end, CACHE_LINE_SIZE);
1291 * perform operation on all full cache lines between 'start' and 'end'
1293 while (start < end) {
1294 range_end = aurora_range_end(start, end);
1296 raw_spin_lock_irqsave(&l2x0_lock, flags);
1297 writel_relaxed(start, base + AURORA_RANGE_BASE_ADDR_REG);
1298 writel_relaxed(range_end - CACHE_LINE_SIZE, base + offset);
1299 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
1301 writel_relaxed(0, base + AURORA_SYNC_REG);
1302 start = range_end;
1305 static void aurora_inv_range(unsigned long start, unsigned long end)
1307 aurora_pa_range(start, end, AURORA_INVAL_RANGE_REG);
1310 static void aurora_clean_range(unsigned long start, unsigned long end)
1313 * If L2 is forced to WT, the L2 will always be clean and we
1314 * don't need to do anything here.
1316 if (!l2_wt_override)
1317 aurora_pa_range(start, end, AURORA_CLEAN_RANGE_REG);
1320 static void aurora_flush_range(unsigned long start, unsigned long end)
1322 if (l2_wt_override)
1323 aurora_pa_range(start, end, AURORA_INVAL_RANGE_REG);
1324 else
1325 aurora_pa_range(start, end, AURORA_FLUSH_RANGE_REG);
1328 static void aurora_flush_all(void)
1330 void __iomem *base = l2x0_base;
1331 unsigned long flags;
1333 /* clean all ways */
1334 raw_spin_lock_irqsave(&l2x0_lock, flags);
1335 __l2c_op_way(base + L2X0_CLEAN_INV_WAY);
1336 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
1338 writel_relaxed(0, base + AURORA_SYNC_REG);
1341 static void aurora_cache_sync(void)
1343 writel_relaxed(0, l2x0_base + AURORA_SYNC_REG);
1346 static void aurora_disable(void)
1348 void __iomem *base = l2x0_base;
1349 unsigned long flags;
1351 raw_spin_lock_irqsave(&l2x0_lock, flags);
1352 __l2c_op_way(base + L2X0_CLEAN_INV_WAY);
1353 writel_relaxed(0, base + AURORA_SYNC_REG);
1354 l2c_write_sec(0, base, L2X0_CTRL);
1355 dsb(st);
1356 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
1359 static void aurora_save(void __iomem *base)
1361 l2x0_saved_regs.ctrl = readl_relaxed(base + L2X0_CTRL);
1362 l2x0_saved_regs.aux_ctrl = readl_relaxed(base + L2X0_AUX_CTRL);
1366 * For Aurora cache in no outer mode, enable via the CP15 coprocessor
1367 * broadcasting of cache commands to L2.
1369 static void __init aurora_enable_no_outer(void __iomem *base, u32 aux,
1370 unsigned num_lock)
1372 u32 u;
1374 asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
1375 u |= AURORA_CTRL_FW; /* Set the FW bit */
1376 asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
1378 isb();
1380 l2c_enable(base, aux, num_lock);
1383 static void __init aurora_fixup(void __iomem *base, u32 cache_id,
1384 struct outer_cache_fns *fns)
1386 sync_reg_offset = AURORA_SYNC_REG;
1389 static void __init aurora_of_parse(const struct device_node *np,
1390 u32 *aux_val, u32 *aux_mask)
1392 u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU;
1393 u32 mask = AURORA_ACR_REPLACEMENT_MASK;
1395 of_property_read_u32(np, "cache-id-part",
1396 &cache_id_part_number_from_dt);
1398 /* Determine and save the write policy */
1399 l2_wt_override = of_property_read_bool(np, "wt-override");
1401 if (l2_wt_override) {
1402 val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY;
1403 mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
1406 *aux_val &= ~mask;
1407 *aux_val |= val;
1408 *aux_mask &= ~mask;
1411 static const struct l2c_init_data of_aurora_with_outer_data __initconst = {
1412 .type = "Aurora",
1413 .way_size_0 = SZ_4K,
1414 .num_lock = 4,
1415 .of_parse = aurora_of_parse,
1416 .enable = l2c_enable,
1417 .fixup = aurora_fixup,
1418 .save = aurora_save,
1419 .outer_cache = {
1420 .inv_range = aurora_inv_range,
1421 .clean_range = aurora_clean_range,
1422 .flush_range = aurora_flush_range,
1423 .flush_all = aurora_flush_all,
1424 .disable = aurora_disable,
1425 .sync = aurora_cache_sync,
1426 .resume = l2c_resume,
1430 static const struct l2c_init_data of_aurora_no_outer_data __initconst = {
1431 .type = "Aurora",
1432 .way_size_0 = SZ_4K,
1433 .num_lock = 4,
1434 .of_parse = aurora_of_parse,
1435 .enable = aurora_enable_no_outer,
1436 .fixup = aurora_fixup,
1437 .save = aurora_save,
1438 .outer_cache = {
1439 .resume = l2c_resume,
1444 * For certain Broadcom SoCs, depending on the address range, different offsets
1445 * need to be added to the address before passing it to L2 for
1446 * invalidation/clean/flush
1448 * Section Address Range Offset EMI
1449 * 1 0x00000000 - 0x3FFFFFFF 0x80000000 VC
1450 * 2 0x40000000 - 0xBFFFFFFF 0x40000000 SYS
1451 * 3 0xC0000000 - 0xFFFFFFFF 0x80000000 VC
1453 * When the start and end addresses have crossed two different sections, we
1454 * need to break the L2 operation into two, each within its own section.
1455 * For example, if we need to invalidate addresses starts at 0xBFFF0000 and
1456 * ends at 0xC0001000, we need do invalidate 1) 0xBFFF0000 - 0xBFFFFFFF and 2)
1457 * 0xC0000000 - 0xC0001000
1459 * Note 1:
1460 * By breaking a single L2 operation into two, we may potentially suffer some
1461 * performance hit, but keep in mind the cross section case is very rare
1463 * Note 2:
1464 * We do not need to handle the case when the start address is in
1465 * Section 1 and the end address is in Section 3, since it is not a valid use
1466 * case
1468 * Note 3:
1469 * Section 1 in practical terms can no longer be used on rev A2. Because of
1470 * that the code does not need to handle section 1 at all.
1473 #define BCM_SYS_EMI_START_ADDR 0x40000000UL
1474 #define BCM_VC_EMI_SEC3_START_ADDR 0xC0000000UL
1476 #define BCM_SYS_EMI_OFFSET 0x40000000UL
1477 #define BCM_VC_EMI_OFFSET 0x80000000UL
1479 static inline int bcm_addr_is_sys_emi(unsigned long addr)
1481 return (addr >= BCM_SYS_EMI_START_ADDR) &&
1482 (addr < BCM_VC_EMI_SEC3_START_ADDR);
1485 static inline unsigned long bcm_l2_phys_addr(unsigned long addr)
1487 if (bcm_addr_is_sys_emi(addr))
1488 return addr + BCM_SYS_EMI_OFFSET;
1489 else
1490 return addr + BCM_VC_EMI_OFFSET;
1493 static void bcm_inv_range(unsigned long start, unsigned long end)
1495 unsigned long new_start, new_end;
1497 BUG_ON(start < BCM_SYS_EMI_START_ADDR);
1499 if (unlikely(end <= start))
1500 return;
1502 new_start = bcm_l2_phys_addr(start);
1503 new_end = bcm_l2_phys_addr(end);
1505 /* normal case, no cross section between start and end */
1506 if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
1507 l2c210_inv_range(new_start, new_end);
1508 return;
1511 /* They cross sections, so it can only be a cross from section
1512 * 2 to section 3
1514 l2c210_inv_range(new_start,
1515 bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
1516 l2c210_inv_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
1517 new_end);
1520 static void bcm_clean_range(unsigned long start, unsigned long end)
1522 unsigned long new_start, new_end;
1524 BUG_ON(start < BCM_SYS_EMI_START_ADDR);
1526 if (unlikely(end <= start))
1527 return;
1529 new_start = bcm_l2_phys_addr(start);
1530 new_end = bcm_l2_phys_addr(end);
1532 /* normal case, no cross section between start and end */
1533 if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
1534 l2c210_clean_range(new_start, new_end);
1535 return;
1538 /* They cross sections, so it can only be a cross from section
1539 * 2 to section 3
1541 l2c210_clean_range(new_start,
1542 bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
1543 l2c210_clean_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
1544 new_end);
1547 static void bcm_flush_range(unsigned long start, unsigned long end)
1549 unsigned long new_start, new_end;
1551 BUG_ON(start < BCM_SYS_EMI_START_ADDR);
1553 if (unlikely(end <= start))
1554 return;
1556 if ((end - start) >= l2x0_size) {
1557 outer_cache.flush_all();
1558 return;
1561 new_start = bcm_l2_phys_addr(start);
1562 new_end = bcm_l2_phys_addr(end);
1564 /* normal case, no cross section between start and end */
1565 if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
1566 l2c210_flush_range(new_start, new_end);
1567 return;
1570 /* They cross sections, so it can only be a cross from section
1571 * 2 to section 3
1573 l2c210_flush_range(new_start,
1574 bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
1575 l2c210_flush_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
1576 new_end);
1579 /* Broadcom L2C-310 start from ARMs R3P2 or later, and require no fixups */
1580 static const struct l2c_init_data of_bcm_l2x0_data __initconst = {
1581 .type = "BCM-L2C-310",
1582 .way_size_0 = SZ_8K,
1583 .num_lock = 8,
1584 .of_parse = l2c310_of_parse,
1585 .enable = l2c310_enable,
1586 .save = l2c310_save,
1587 .configure = l2c310_configure,
1588 .outer_cache = {
1589 .inv_range = bcm_inv_range,
1590 .clean_range = bcm_clean_range,
1591 .flush_range = bcm_flush_range,
1592 .flush_all = l2c210_flush_all,
1593 .disable = l2c310_disable,
1594 .sync = l2c210_sync,
1595 .resume = l2c310_resume,
1599 static void __init tauros3_save(void __iomem *base)
1601 l2c_save(base);
1603 l2x0_saved_regs.aux2_ctrl =
1604 readl_relaxed(base + TAUROS3_AUX2_CTRL);
1605 l2x0_saved_regs.prefetch_ctrl =
1606 readl_relaxed(base + L310_PREFETCH_CTRL);
1609 static void tauros3_configure(void __iomem *base)
1611 writel_relaxed(l2x0_saved_regs.aux2_ctrl,
1612 base + TAUROS3_AUX2_CTRL);
1613 writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
1614 base + L310_PREFETCH_CTRL);
1617 static const struct l2c_init_data of_tauros3_data __initconst = {
1618 .type = "Tauros3",
1619 .way_size_0 = SZ_8K,
1620 .num_lock = 8,
1621 .enable = l2c_enable,
1622 .save = tauros3_save,
1623 .configure = tauros3_configure,
1624 /* Tauros3 broadcasts L1 cache operations to L2 */
1625 .outer_cache = {
1626 .resume = l2c_resume,
1630 #define L2C_ID(name, fns) { .compatible = name, .data = (void *)&fns }
1631 static const struct of_device_id l2x0_ids[] __initconst = {
1632 L2C_ID("arm,l210-cache", of_l2c210_data),
1633 L2C_ID("arm,l220-cache", of_l2c220_data),
1634 L2C_ID("arm,pl310-cache", of_l2c310_data),
1635 L2C_ID("brcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data),
1636 L2C_ID("marvell,aurora-outer-cache", of_aurora_with_outer_data),
1637 L2C_ID("marvell,aurora-system-cache", of_aurora_no_outer_data),
1638 L2C_ID("marvell,tauros3-cache", of_tauros3_data),
1639 /* Deprecated IDs */
1640 L2C_ID("bcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data),
1644 int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
1646 const struct l2c_init_data *data;
1647 struct device_node *np;
1648 struct resource res;
1649 u32 cache_id, old_aux;
1650 u32 cache_level = 2;
1652 np = of_find_matching_node(NULL, l2x0_ids);
1653 if (!np)
1654 return -ENODEV;
1656 if (of_address_to_resource(np, 0, &res))
1657 return -ENODEV;
1659 l2x0_base = ioremap(res.start, resource_size(&res));
1660 if (!l2x0_base)
1661 return -ENOMEM;
1663 l2x0_saved_regs.phy_base = res.start;
1665 data = of_match_node(l2x0_ids, np)->data;
1667 if (of_device_is_compatible(np, "arm,pl310-cache") &&
1668 of_property_read_bool(np, "arm,io-coherent"))
1669 data = &of_l2c310_coherent_data;
1671 old_aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
1672 if (old_aux != ((old_aux & aux_mask) | aux_val)) {
1673 pr_warn("L2C: platform modifies aux control register: 0x%08x -> 0x%08x\n",
1674 old_aux, (old_aux & aux_mask) | aux_val);
1675 } else if (aux_mask != ~0U && aux_val != 0) {
1676 pr_alert("L2C: platform provided aux values match the hardware, so have no effect. Please remove them.\n");
1679 /* All L2 caches are unified, so this property should be specified */
1680 if (!of_property_read_bool(np, "cache-unified"))
1681 pr_err("L2C: device tree omits to specify unified cache\n");
1683 if (of_property_read_u32(np, "cache-level", &cache_level))
1684 pr_err("L2C: device tree omits to specify cache-level\n");
1686 if (cache_level != 2)
1687 pr_err("L2C: device tree specifies invalid cache level\n");
1689 /* Read back current (default) hardware configuration */
1690 if (data->save)
1691 data->save(l2x0_base);
1693 /* L2 configuration can only be changed if the cache is disabled */
1694 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN))
1695 if (data->of_parse)
1696 data->of_parse(np, &aux_val, &aux_mask);
1698 if (cache_id_part_number_from_dt)
1699 cache_id = cache_id_part_number_from_dt;
1700 else
1701 cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
1703 return __l2c_init(data, aux_val, aux_mask, cache_id);
1705 #endif