drm/tegra: dsi: Demidlayer
[linux-2.6/btrfs-unstable.git] / drivers / gpu / drm / tegra / mipi-phy.c
blobba2ae6511957b1752d95cfc6e99f8e2616c596e7
1 /*
2 * Copyright (C) 2013 NVIDIA Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
9 #include <linux/errno.h>
10 #include <linux/kernel.h>
12 #include "mipi-phy.h"
15 * Default D-PHY timings based on MIPI D-PHY specification. Derived from the
16 * valid ranges specified in Section 6.9, Table 14, Page 40 of the D-PHY
17 * specification (v1.2) with minor adjustments.
19 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing,
20 unsigned long period)
22 timing->clkmiss = 0;
23 timing->clkpost = 70 + 52 * period;
24 timing->clkpre = 8;
25 timing->clkprepare = 65;
26 timing->clksettle = 95;
27 timing->clktermen = 0;
28 timing->clktrail = 80;
29 timing->clkzero = 260;
30 timing->dtermen = 0;
31 timing->eot = 0;
32 timing->hsexit = 120;
33 timing->hsprepare = 65 + 5 * period;
34 timing->hszero = 145 + 5 * period;
35 timing->hssettle = 85 + 6 * period;
36 timing->hsskip = 40;
39 * The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40)
40 * contains this formula as:
42 * T_HS-TRAIL = max(n * 8 * period, 60 + n * 4 * period)
44 * where n = 1 for forward-direction HS mode and n = 4 for reverse-
45 * direction HS mode. There's only one setting and this function does
46 * not parameterize on anything other that period, so this code will
47 * assumes that reverse-direction HS mode is supported and uses n = 4.
49 timing->hstrail = max(4 * 8 * period, 60 + 4 * 4 * period);
51 timing->init = 100000;
52 timing->lpx = 60;
53 timing->taget = 5 * timing->lpx;
54 timing->tago = 4 * timing->lpx;
55 timing->tasure = 2 * timing->lpx;
56 timing->wakeup = 1000000;
58 return 0;
62 * Validate D-PHY timing according to MIPI D-PHY specification (v1.2, Section
63 * Section 6.9 "Global Operation Timing Parameters").
65 int mipi_dphy_timing_validate(struct mipi_dphy_timing *timing,
66 unsigned long period)
68 if (timing->clkmiss > 60)
69 return -EINVAL;
71 if (timing->clkpost < (60 + 52 * period))
72 return -EINVAL;
74 if (timing->clkpre < 8)
75 return -EINVAL;
77 if (timing->clkprepare < 38 || timing->clkprepare > 95)
78 return -EINVAL;
80 if (timing->clksettle < 95 || timing->clksettle > 300)
81 return -EINVAL;
83 if (timing->clktermen > 38)
84 return -EINVAL;
86 if (timing->clktrail < 60)
87 return -EINVAL;
89 if (timing->clkprepare + timing->clkzero < 300)
90 return -EINVAL;
92 if (timing->dtermen > 35 + 4 * period)
93 return -EINVAL;
95 if (timing->eot > 105 + 12 * period)
96 return -EINVAL;
98 if (timing->hsexit < 100)
99 return -EINVAL;
101 if (timing->hsprepare < 40 + 4 * period ||
102 timing->hsprepare > 85 + 6 * period)
103 return -EINVAL;
105 if (timing->hsprepare + timing->hszero < 145 + 10 * period)
106 return -EINVAL;
108 if ((timing->hssettle < 85 + 6 * period) ||
109 (timing->hssettle > 145 + 10 * period))
110 return -EINVAL;
112 if (timing->hsskip < 40 || timing->hsskip > 55 + 4 * period)
113 return -EINVAL;
115 if (timing->hstrail < max(8 * period, 60 + 4 * period))
116 return -EINVAL;
118 if (timing->init < 100000)
119 return -EINVAL;
121 if (timing->lpx < 50)
122 return -EINVAL;
124 if (timing->taget != 5 * timing->lpx)
125 return -EINVAL;
127 if (timing->tago != 4 * timing->lpx)
128 return -EINVAL;
130 if (timing->tasure < timing->lpx || timing->tasure > 2 * timing->lpx)
131 return -EINVAL;
133 if (timing->wakeup < 1000000)
134 return -EINVAL;
136 return 0;