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drm/tegra: dsi: Demidlayer
[linux-2.6/btrfs-unstable.git] / drivers / gpu / drm / tegra / dsi.c
blob0b476e1c005a927491de22c78e9a904259b1ff79
1 /*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/debugfs.h>
11 #include <linux/host1x.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_platform.h>
15 #include <linux/platform_device.h>
16 #include <linux/reset.h>
17
18 #include <linux/regulator/consumer.h>
19
20 #include <drm/drm_mipi_dsi.h>
21 #include <drm/drm_panel.h>
22
23 #include <video/mipi_display.h>
24
25 #include "dc.h"
26 #include "drm.h"
27 #include "dsi.h"
28 #include "mipi-phy.h"
29
30 struct tegra_dsi {
31 struct host1x_client client;
32 struct tegra_output output;
33 struct device *dev;
34
35 void __iomem *regs;
36
37 struct reset_control *rst;
38 struct clk *clk_parent;
39 struct clk *clk_lp;
40 struct clk *clk;
41
42 struct drm_info_list *debugfs_files;
43 struct drm_minor *minor;
44 struct dentry *debugfs;
45
46 unsigned long flags;
47 enum mipi_dsi_pixel_format format;
48 unsigned int lanes;
49
50 struct tegra_mipi_device *mipi;
51 struct mipi_dsi_host host;
52
53 struct regulator *vdd;
54
55 unsigned int video_fifo_depth;
56 unsigned int host_fifo_depth;
57
58 /* for ganged-mode support */
59 struct tegra_dsi *master;
60 struct tegra_dsi *slave;
61 };
62
63 static inline struct tegra_dsi *
64 host1x_client_to_dsi(struct host1x_client *client)
65 {
66 return container_of(client, struct tegra_dsi, client);
67 }
68
69 static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
70 {
71 return container_of(host, struct tegra_dsi, host);
72 }
73
74 static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
75 {
76 return container_of(output, struct tegra_dsi, output);
77 }
78
79 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned long reg)
80 {
81 return readl(dsi->regs + (reg << 2));
82 }
83
84 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
85 unsigned long reg)
86 {
87 writel(value, dsi->regs + (reg << 2));
88 }
89
90 static int tegra_dsi_show_regs(struct seq_file *s, void *data)
91 {
92 struct drm_info_node *node = s->private;
93 struct tegra_dsi *dsi = node->info_ent->data;
94
95 #define DUMP_REG(name) \
96 seq_printf(s, "%-32s %#05x %08x\n", #name, name, \
97 tegra_dsi_readl(dsi, name))
98
99 DUMP_REG(DSI_INCR_SYNCPT);
100 DUMP_REG(DSI_INCR_SYNCPT_CONTROL);
101 DUMP_REG(DSI_INCR_SYNCPT_ERROR);
102 DUMP_REG(DSI_CTXSW);
103 DUMP_REG(DSI_RD_DATA);
104 DUMP_REG(DSI_WR_DATA);
105 DUMP_REG(DSI_POWER_CONTROL);
106 DUMP_REG(DSI_INT_ENABLE);
107 DUMP_REG(DSI_INT_STATUS);
108 DUMP_REG(DSI_INT_MASK);
109 DUMP_REG(DSI_HOST_CONTROL);
110 DUMP_REG(DSI_CONTROL);
111 DUMP_REG(DSI_SOL_DELAY);
112 DUMP_REG(DSI_MAX_THRESHOLD);
113 DUMP_REG(DSI_TRIGGER);
114 DUMP_REG(DSI_TX_CRC);
115 DUMP_REG(DSI_STATUS);
116
117 DUMP_REG(DSI_INIT_SEQ_CONTROL);
118 DUMP_REG(DSI_INIT_SEQ_DATA_0);
119 DUMP_REG(DSI_INIT_SEQ_DATA_1);
120 DUMP_REG(DSI_INIT_SEQ_DATA_2);
121 DUMP_REG(DSI_INIT_SEQ_DATA_3);
122 DUMP_REG(DSI_INIT_SEQ_DATA_4);
123 DUMP_REG(DSI_INIT_SEQ_DATA_5);
124 DUMP_REG(DSI_INIT_SEQ_DATA_6);
125 DUMP_REG(DSI_INIT_SEQ_DATA_7);
126
127 DUMP_REG(DSI_PKT_SEQ_0_LO);
128 DUMP_REG(DSI_PKT_SEQ_0_HI);
129 DUMP_REG(DSI_PKT_SEQ_1_LO);
130 DUMP_REG(DSI_PKT_SEQ_1_HI);
131 DUMP_REG(DSI_PKT_SEQ_2_LO);
132 DUMP_REG(DSI_PKT_SEQ_2_HI);
133 DUMP_REG(DSI_PKT_SEQ_3_LO);
134 DUMP_REG(DSI_PKT_SEQ_3_HI);
135 DUMP_REG(DSI_PKT_SEQ_4_LO);
136 DUMP_REG(DSI_PKT_SEQ_4_HI);
137 DUMP_REG(DSI_PKT_SEQ_5_LO);
138 DUMP_REG(DSI_PKT_SEQ_5_HI);
139
140 DUMP_REG(DSI_DCS_CMDS);
141
142 DUMP_REG(DSI_PKT_LEN_0_1);
143 DUMP_REG(DSI_PKT_LEN_2_3);
144 DUMP_REG(DSI_PKT_LEN_4_5);
145 DUMP_REG(DSI_PKT_LEN_6_7);
146
147 DUMP_REG(DSI_PHY_TIMING_0);
148 DUMP_REG(DSI_PHY_TIMING_1);
149 DUMP_REG(DSI_PHY_TIMING_2);
150 DUMP_REG(DSI_BTA_TIMING);
151
152 DUMP_REG(DSI_TIMEOUT_0);
153 DUMP_REG(DSI_TIMEOUT_1);
154 DUMP_REG(DSI_TO_TALLY);
155
156 DUMP_REG(DSI_PAD_CONTROL_0);
157 DUMP_REG(DSI_PAD_CONTROL_CD);
158 DUMP_REG(DSI_PAD_CD_STATUS);
159 DUMP_REG(DSI_VIDEO_MODE_CONTROL);
160 DUMP_REG(DSI_PAD_CONTROL_1);
161 DUMP_REG(DSI_PAD_CONTROL_2);
162 DUMP_REG(DSI_PAD_CONTROL_3);
163 DUMP_REG(DSI_PAD_CONTROL_4);
164
165 DUMP_REG(DSI_GANGED_MODE_CONTROL);
166 DUMP_REG(DSI_GANGED_MODE_START);
167 DUMP_REG(DSI_GANGED_MODE_SIZE);
168
169 DUMP_REG(DSI_RAW_DATA_BYTE_COUNT);
170 DUMP_REG(DSI_ULTRA_LOW_POWER_CONTROL);
171
172 DUMP_REG(DSI_INIT_SEQ_DATA_8);
173 DUMP_REG(DSI_INIT_SEQ_DATA_9);
174 DUMP_REG(DSI_INIT_SEQ_DATA_10);
175 DUMP_REG(DSI_INIT_SEQ_DATA_11);
176 DUMP_REG(DSI_INIT_SEQ_DATA_12);
177 DUMP_REG(DSI_INIT_SEQ_DATA_13);
178 DUMP_REG(DSI_INIT_SEQ_DATA_14);
179 DUMP_REG(DSI_INIT_SEQ_DATA_15);
180
181 #undef DUMP_REG
182
183 return 0;
184 }
185
186 static struct drm_info_list debugfs_files[] = {
187 { "regs", tegra_dsi_show_regs, 0, NULL },
188 };
189
190 static int tegra_dsi_debugfs_init(struct tegra_dsi *dsi,
191 struct drm_minor *minor)
192 {
193 const char *name = dev_name(dsi->dev);
194 unsigned int i;
195 int err;
196
197 dsi->debugfs = debugfs_create_dir(name, minor->debugfs_root);
198 if (!dsi->debugfs)
199 return -ENOMEM;
200
201 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
202 GFP_KERNEL);
203 if (!dsi->debugfs_files) {
204 err = -ENOMEM;
205 goto remove;
206 }
207
208 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
209 dsi->debugfs_files[i].data = dsi;
210
211 err = drm_debugfs_create_files(dsi->debugfs_files,
212 ARRAY_SIZE(debugfs_files),
213 dsi->debugfs, minor);
214 if (err < 0)
215 goto free;
216
217 dsi->minor = minor;
218
219 return 0;
220
221 free:
222 kfree(dsi->debugfs_files);
223 dsi->debugfs_files = NULL;
224 remove:
225 debugfs_remove(dsi->debugfs);
226 dsi->debugfs = NULL;
227
228 return err;
229 }
230
231 static int tegra_dsi_debugfs_exit(struct tegra_dsi *dsi)
232 {
233 drm_debugfs_remove_files(dsi->debugfs_files, ARRAY_SIZE(debugfs_files),
234 dsi->minor);
235 dsi->minor = NULL;
236
237 kfree(dsi->debugfs_files);
238 dsi->debugfs_files = NULL;
239
240 debugfs_remove(dsi->debugfs);
241 dsi->debugfs = NULL;
242
243 return 0;
244 }
245
246 #define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
247 #define PKT_LEN0(len) (((len) & 0x07) << 0)
248 #define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
249 #define PKT_LEN1(len) (((len) & 0x07) << 10)
250 #define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
251 #define PKT_LEN2(len) (((len) & 0x07) << 20)
252
253 #define PKT_LP (1 << 30)
254 #define NUM_PKT_SEQ 12
255
256 /*
257 * non-burst mode with sync pulses
258 */
259 static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
260 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
261 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
262 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
263 PKT_LP,
264 [ 1] = 0,
265 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
266 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
267 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
268 PKT_LP,
269 [ 3] = 0,
270 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
271 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
272 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
273 PKT_LP,
274 [ 5] = 0,
275 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
276 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
277 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
278 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
279 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
280 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
281 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
282 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
283 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
284 PKT_LP,
285 [ 9] = 0,
286 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
287 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
288 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
289 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
290 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
291 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
292 };
293
294 /*
295 * non-burst mode with sync events
296 */
297 static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
298 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
299 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
300 PKT_LP,
301 [ 1] = 0,
302 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
303 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
304 PKT_LP,
305 [ 3] = 0,
306 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
307 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
308 PKT_LP,
309 [ 5] = 0,
310 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
311 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
312 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
313 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
314 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
315 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
316 PKT_LP,
317 [ 9] = 0,
318 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
319 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
320 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
321 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
322 };
323
324 static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
325 [ 0] = 0,
326 [ 1] = 0,
327 [ 2] = 0,
328 [ 3] = 0,
329 [ 4] = 0,
330 [ 5] = 0,
331 [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP,
332 [ 7] = 0,
333 [ 8] = 0,
334 [ 9] = 0,
335 [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
336 [11] = 0,
337 };
338
339 static int tegra_dsi_set_phy_timing(struct tegra_dsi *dsi)
340 {
341 struct mipi_dphy_timing timing;
342 unsigned long period;
343 u32 value;
344 long rate;
345 int err;
346
347 rate = clk_get_rate(dsi->clk);
348 if (rate < 0)
349 return rate;
350
351 period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, rate * 2);
352
353 err = mipi_dphy_timing_get_default(&timing, period);
354 if (err < 0)
355 return err;
356
357 err = mipi_dphy_timing_validate(&timing, period);
358 if (err < 0) {
359 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
360 return err;
361 }
362
363 /*
364 * The D-PHY timing fields below are expressed in byte-clock cycles,
365 * so multiply the period by 8.
366 */
367 period *= 8;
368
369 value = DSI_TIMING_FIELD(timing.hsexit, period, 1) << 24 |
370 DSI_TIMING_FIELD(timing.hstrail, period, 0) << 16 |
371 DSI_TIMING_FIELD(timing.hszero, period, 3) << 8 |
372 DSI_TIMING_FIELD(timing.hsprepare, period, 1);
373 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
374
375 value = DSI_TIMING_FIELD(timing.clktrail, period, 1) << 24 |
376 DSI_TIMING_FIELD(timing.clkpost, period, 1) << 16 |
377 DSI_TIMING_FIELD(timing.clkzero, period, 1) << 8 |
378 DSI_TIMING_FIELD(timing.lpx, period, 1);
379 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
380
381 value = DSI_TIMING_FIELD(timing.clkprepare, period, 1) << 16 |
382 DSI_TIMING_FIELD(timing.clkpre, period, 1) << 8 |
383 DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
384 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
385
386 value = DSI_TIMING_FIELD(timing.taget, period, 1) << 16 |
387 DSI_TIMING_FIELD(timing.tasure, period, 1) << 8 |
388 DSI_TIMING_FIELD(timing.tago, period, 1);
389 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
390
391 if (dsi->slave)
392 return tegra_dsi_set_phy_timing(dsi->slave);
393
394 return 0;
395 }
396
397 static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
398 unsigned int *mulp, unsigned int *divp)
399 {
400 switch (format) {
401 case MIPI_DSI_FMT_RGB666_PACKED:
402 case MIPI_DSI_FMT_RGB888:
403 *mulp = 3;
404 *divp = 1;
405 break;
406
407 case MIPI_DSI_FMT_RGB565:
408 *mulp = 2;
409 *divp = 1;
410 break;
411
412 case MIPI_DSI_FMT_RGB666:
413 *mulp = 9;
414 *divp = 4;
415 break;
416
417 default:
418 return -EINVAL;
419 }
420
421 return 0;
422 }
423
424 static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
425 enum tegra_dsi_format *fmt)
426 {
427 switch (format) {
428 case MIPI_DSI_FMT_RGB888:
429 *fmt = TEGRA_DSI_FORMAT_24P;
430 break;
431
432 case MIPI_DSI_FMT_RGB666:
433 *fmt = TEGRA_DSI_FORMAT_18NP;
434 break;
435
436 case MIPI_DSI_FMT_RGB666_PACKED:
437 *fmt = TEGRA_DSI_FORMAT_18P;
438 break;
439
440 case MIPI_DSI_FMT_RGB565:
441 *fmt = TEGRA_DSI_FORMAT_16P;
442 break;
443
444 default:
445 return -EINVAL;
446 }
447
448 return 0;
449 }
450
451 static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start,
452 unsigned int size)
453 {
454 u32 value;
455
456 tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);
457 tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);
458
459 value = DSI_GANGED_MODE_CONTROL_ENABLE;
460 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
461 }
462
463 static void tegra_dsi_enable(struct tegra_dsi *dsi)
464 {
465 u32 value;
466
467 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
468 value |= DSI_POWER_CONTROL_ENABLE;
469 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
470
471 if (dsi->slave)
472 tegra_dsi_enable(dsi->slave);
473 }
474
475 static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi)
476 {
477 if (dsi->master)
478 return dsi->master->lanes + dsi->lanes;
479
480 if (dsi->slave)
481 return dsi->lanes + dsi->slave->lanes;
482
483 return dsi->lanes;
484 }
485
486 static int tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
487 const struct drm_display_mode *mode)
488 {
489 unsigned int hact, hsw, hbp, hfp, i, mul, div;
490 enum tegra_dsi_format format;
491 const u32 *pkt_seq;
492 u32 value;
493 int err;
494
495 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
496 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
497 pkt_seq = pkt_seq_video_non_burst_sync_pulses;
498 } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
499 DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
500 pkt_seq = pkt_seq_video_non_burst_sync_events;
501 } else {
502 DRM_DEBUG_KMS("Command mode\n");
503 pkt_seq = pkt_seq_command_mode;
504 }
505
506 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
507 if (err < 0)
508 return err;
509
510 err = tegra_dsi_get_format(dsi->format, &format);
511 if (err < 0)
512 return err;
513
514 value = DSI_CONTROL_CHANNEL(0) | DSI_CONTROL_FORMAT(format) |
515 DSI_CONTROL_LANES(dsi->lanes - 1) |
516 DSI_CONTROL_SOURCE(pipe);
517 tegra_dsi_writel(dsi, value, DSI_CONTROL);
518
519 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD);
520
521 value = DSI_HOST_CONTROL_HS;
522 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
523
524 value = tegra_dsi_readl(dsi, DSI_CONTROL);
525
526 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
527 value |= DSI_CONTROL_HS_CLK_CTRL;
528
529 value &= ~DSI_CONTROL_TX_TRIG(3);
530
531 /* enable DCS commands for command mode */
532 if (dsi->flags & MIPI_DSI_MODE_VIDEO)
533 value &= ~DSI_CONTROL_DCS_ENABLE;
534 else
535 value |= DSI_CONTROL_DCS_ENABLE;
536
537 value |= DSI_CONTROL_VIDEO_ENABLE;
538 value &= ~DSI_CONTROL_HOST_ENABLE;
539 tegra_dsi_writel(dsi, value, DSI_CONTROL);
540
541 for (i = 0; i < NUM_PKT_SEQ; i++)
542 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
543
544 if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
545 /* horizontal active pixels */
546 hact = mode->hdisplay * mul / div;
547
548 /* horizontal sync width */
549 hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
550 hsw -= 10;
551
552 /* horizontal back porch */
553 hbp = (mode->htotal - mode->hsync_end) * mul / div;
554 hbp -= 14;
555
556 /* horizontal front porch */
557 hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
558 hfp -= 8;
559
560 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
561 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
562 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
563 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
564
565 /* set SOL delay (for non-burst mode only) */
566 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
567
568 /* TODO: implement ganged mode */
569 } else {
570 u16 bytes;
571
572 if (dsi->master || dsi->slave) {
573 /*
574 * For ganged mode, assume symmetric left-right mode.
575 */
576 bytes = 1 + (mode->hdisplay / 2) * mul / div;
577 } else {
578 /* 1 byte (DCS command) + pixel data */
579 bytes = 1 + mode->hdisplay * mul / div;
580 }
581
582 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1);
583 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3);
584 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5);
585 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7);
586
587 value = MIPI_DCS_WRITE_MEMORY_START << 8 |
588 MIPI_DCS_WRITE_MEMORY_CONTINUE;
589 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
590
591 /* set SOL delay */
592 if (dsi->master || dsi->slave) {
593 unsigned int lanes = tegra_dsi_get_lanes(dsi);
594 unsigned long delay, bclk, bclk_ganged;
595
596 /* SOL to valid, valid to FIFO and FIFO write delay */
597 delay = 4 + 4 + 2;
598 delay = DIV_ROUND_UP(delay * mul, div * lanes);
599 /* FIFO read delay */
600 delay = delay + 6;
601
602 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes);
603 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
604 value = bclk - bclk_ganged + delay + 20;
605 } else {
606 /* TODO: revisit for non-ganged mode */
607 value = 8 * mul / div;
608 }
609
610 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
611 }
612
613 if (dsi->slave) {
614 err = tegra_dsi_configure(dsi->slave, pipe, mode);
615 if (err < 0)
616 return err;
617
618 /*
619 * TODO: Support modes other than symmetrical left-right
620 * split.
621 */
622 tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2);
623 tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2,
624 mode->hdisplay / 2);
625 }
626
627 return 0;
628 }
629
630 static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout)
631 {
632 u32 value;
633
634 timeout = jiffies + msecs_to_jiffies(timeout);
635
636 while (time_before(jiffies, timeout)) {
637 value = tegra_dsi_readl(dsi, DSI_STATUS);
638 if (value & DSI_STATUS_IDLE)
639 return 0;
640
641 usleep_range(1000, 2000);
642 }
643
644 return -ETIMEDOUT;
645 }
646
647 static void tegra_dsi_video_disable(struct tegra_dsi *dsi)
648 {
649 u32 value;
650
651 value = tegra_dsi_readl(dsi, DSI_CONTROL);
652 value &= ~DSI_CONTROL_VIDEO_ENABLE;
653 tegra_dsi_writel(dsi, value, DSI_CONTROL);
654
655 if (dsi->slave)
656 tegra_dsi_video_disable(dsi->slave);
657 }
658
659 static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi)
660 {
661 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
662 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
663 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
664 }
665
666 static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk,
667 unsigned int vrefresh)
668 {
669 unsigned int timeout;
670 u32 value;
671
672 /* one frame high-speed transmission timeout */
673 timeout = (bclk / vrefresh) / 512;
674 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
675 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
676
677 /* 2 ms peripheral timeout for panel */
678 timeout = 2 * bclk / 512 * 1000;
679 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
680 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
681
682 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
683 tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
684
685 if (dsi->slave)
686 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh);
687 }
688
689 static void tegra_dsi_disable(struct tegra_dsi *dsi)
690 {
691 u32 value;
692
693 if (dsi->slave) {
694 tegra_dsi_ganged_disable(dsi->slave);
695 tegra_dsi_ganged_disable(dsi);
696 }
697
698 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
699 value &= ~DSI_POWER_CONTROL_ENABLE;
700 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
701
702 if (dsi->slave)
703 tegra_dsi_disable(dsi->slave);
704
705 usleep_range(5000, 10000);
706 }
707
708 static void tegra_dsi_soft_reset(struct tegra_dsi *dsi)
709 {
710 u32 value;
711
712 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
713 value &= ~DSI_POWER_CONTROL_ENABLE;
714 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
715
716 usleep_range(300, 1000);
717
718 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
719 value |= DSI_POWER_CONTROL_ENABLE;
720 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
721
722 usleep_range(300, 1000);
723
724 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
725 if (value)
726 tegra_dsi_writel(dsi, 0, DSI_TRIGGER);
727
728 if (dsi->slave)
729 tegra_dsi_soft_reset(dsi->slave);
730 }
731
732 static void tegra_dsi_connector_dpms(struct drm_connector *connector, int mode)
733 {
734 }
735
736 static const struct drm_connector_funcs tegra_dsi_connector_funcs = {
737 .dpms = tegra_dsi_connector_dpms,
738 .detect = tegra_output_connector_detect,
739 .fill_modes = drm_helper_probe_single_connector_modes,
740 .destroy = tegra_output_connector_destroy,
741 };
742
743 static enum drm_mode_status
744 tegra_dsi_connector_mode_valid(struct drm_connector *connector,
745 struct drm_display_mode *mode)
746 {
747 return MODE_OK;
748 }
749
750 static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = {
751 .get_modes = tegra_output_connector_get_modes,
752 .mode_valid = tegra_dsi_connector_mode_valid,
753 .best_encoder = tegra_output_connector_best_encoder,
754 };
755
756 static const struct drm_encoder_funcs tegra_dsi_encoder_funcs = {
757 .destroy = tegra_output_encoder_destroy,
758 };
759
760 static void tegra_dsi_encoder_dpms(struct drm_encoder *encoder, int mode)
761 {
762 }
763
764 static bool tegra_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
765 const struct drm_display_mode *mode,
766 struct drm_display_mode *adjusted)
767 {
768 struct tegra_output *output = encoder_to_output(encoder);
769 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
770 unsigned int mul, div, scdiv, vrefresh, lanes;
771 struct tegra_dsi *dsi = to_dsi(output);
772 unsigned long pclk, bclk, plld;
773 int err;
774
775 lanes = tegra_dsi_get_lanes(dsi);
776 pclk = mode->clock * 1000;
777
778 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
779 if (err < 0)
780 return err;
781
782 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", mul, div, lanes);
783 vrefresh = drm_mode_vrefresh(mode);
784 DRM_DEBUG_KMS("vrefresh: %u\n", vrefresh);
785
786 /* compute byte clock */
787 bclk = (pclk * mul) / (div * lanes);
788
789 /*
790 * Compute bit clock and round up to the next MHz.
791 */
792 plld = DIV_ROUND_UP(bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
793
794 /*
795 * We divide the frequency by two here, but we make up for that by
796 * setting the shift clock divider (further below) to half of the
797 * correct value.
798 */
799 plld /= 2;
800
801 /*
802 * Derive pixel clock from bit clock using the shift clock divider.
803 * Note that this is only half of what we would expect, but we need
804 * that to make up for the fact that we divided the bit clock by a
805 * factor of two above.
806 *
807 * It's not clear exactly why this is necessary, but the display is
808 * not working properly otherwise. Perhaps the PLLs cannot generate
809 * frequencies sufficiently high.
810 */
811 scdiv = ((8 * mul) / (div * lanes)) - 2;
812
813 err = tegra_dc_setup_clock(dc, dsi->clk_parent, plld, scdiv);
814 if (err < 0) {
815 dev_err(output->dev, "failed to setup DC clock: %d\n", err);
816 return false;
817 }
818
819 err = clk_set_rate(dsi->clk_parent, plld);
820 if (err < 0) {
821 dev_err(dsi->dev, "failed to set clock rate to %lu Hz\n",
822 plld);
823 return false;
824 }
825
826 tegra_dsi_set_timeout(dsi, bclk, vrefresh);
827
828 err = tegra_dsi_set_phy_timing(dsi);
829 if (err < 0) {
830 dev_err(dsi->dev, "failed to setup D-PHY timing: %d\n", err);
831 return false;
832 }
833
834 return true;
835 }
836
837 static void tegra_dsi_encoder_prepare(struct drm_encoder *encoder)
838 {
839 }
840
841 static void tegra_dsi_encoder_commit(struct drm_encoder *encoder)
842 {
843 }
844
845 static void tegra_dsi_encoder_mode_set(struct drm_encoder *encoder,
846 struct drm_display_mode *mode,
847 struct drm_display_mode *adjusted)
848 {
849 struct tegra_output *output = encoder_to_output(encoder);
850 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
851 struct tegra_dsi *dsi = to_dsi(output);
852 u32 value;
853 int err;
854
855
856 err = tegra_dsi_configure(dsi, dc->pipe, mode);
857 if (err < 0) {
858 dev_err(dsi->dev, "failed to configure DSI: %d\n", err);
859 return;
860 }
861
862 if (output->panel)
863 drm_panel_prepare(output->panel);
864
865 /* enable display controller */
866 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
867 value |= DSI_ENABLE;
868 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
869
870 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
871 value &= ~DISP_CTRL_MODE_MASK;
872 value |= DISP_CTRL_MODE_C_DISPLAY;
873 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
874
875 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
876 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
877 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
878 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
879
880 tegra_dc_commit(dc);
881
882 /* enable DSI controller */
883 tegra_dsi_enable(dsi);
884
885 if (output->panel)
886 drm_panel_enable(output->panel);
887
888 return;
889 }
890
891 static void tegra_dsi_encoder_disable(struct drm_encoder *encoder)
892 {
893 struct tegra_output *output = encoder_to_output(encoder);
894 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
895 struct tegra_dsi *dsi = to_dsi(output);
896 u32 value;
897 int err;
898
899 if (output->panel)
900 drm_panel_disable(output->panel);
901
902 tegra_dsi_video_disable(dsi);
903
904 /*
905 * The following accesses registers of the display controller, so make
906 * sure it's only executed when the output is attached to one.
907 */
908 if (dc) {
909 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
910 value &= ~DSI_ENABLE;
911 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
912
913 tegra_dc_commit(dc);
914 }
915
916 err = tegra_dsi_wait_idle(dsi, 100);
917 if (err < 0)
918 dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err);
919
920 tegra_dsi_soft_reset(dsi);
921
922 if (output->panel)
923 drm_panel_unprepare(output->panel);
924
925 tegra_dsi_disable(dsi);
926
927 return;
928 }
929
930 static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = {
931 .dpms = tegra_dsi_encoder_dpms,
932 .mode_fixup = tegra_dsi_encoder_mode_fixup,
933 .prepare = tegra_dsi_encoder_prepare,
934 .commit = tegra_dsi_encoder_commit,
935 .mode_set = tegra_dsi_encoder_mode_set,
936 .disable = tegra_dsi_encoder_disable,
937 };
938
939 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
940 {
941 u32 value;
942
943 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
944 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
945
946 return 0;
947 }
948
949 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
950 {
951 u32 value;
952
953 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
954 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
955 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
956 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
957 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
958
959 /* start calibration */
960 tegra_dsi_pad_enable(dsi);
961
962 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
963 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
964 DSI_PAD_OUT_CLK(0x0);
965 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
966
967 return tegra_mipi_calibrate(dsi->mipi);
968 }
969
970 static int tegra_dsi_init(struct host1x_client *client)
971 {
972 struct drm_device *drm = dev_get_drvdata(client->parent);
973 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
974 int err;
975
976 reset_control_deassert(dsi->rst);
977
978 err = tegra_dsi_pad_calibrate(dsi);
979 if (err < 0) {
980 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
981 goto reset;
982 }
983
984 /* Gangsters must not register their own outputs. */
985 if (!dsi->master) {
986 dsi->output.dev = client->dev;
987
988 drm_connector_init(drm, &dsi->output.connector,
989 &tegra_dsi_connector_funcs,
990 DRM_MODE_CONNECTOR_DSI);
991 drm_connector_helper_add(&dsi->output.connector,
992 &tegra_dsi_connector_helper_funcs);
993 dsi->output.connector.dpms = DRM_MODE_DPMS_OFF;
994
995 if (dsi->output.panel)
996 drm_panel_attach(dsi->output.panel,
997 &dsi->output.connector);
998
999 drm_encoder_init(drm, &dsi->output.encoder,
1000 &tegra_dsi_encoder_funcs,
1001 DRM_MODE_ENCODER_DSI);
1002 drm_encoder_helper_add(&dsi->output.encoder,
1003 &tegra_dsi_encoder_helper_funcs);
1004
1005 drm_mode_connector_attach_encoder(&dsi->output.connector,
1006 &dsi->output.encoder);
1007 drm_connector_register(&dsi->output.connector);
1008
1009 dsi->output.encoder.possible_crtcs = 0x3;
1010 }
1011
1012 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1013 err = tegra_dsi_debugfs_init(dsi, drm->primary);
1014 if (err < 0)
1015 dev_err(dsi->dev, "debugfs setup failed: %d\n", err);
1016 }
1017
1018 return 0;
1019
1020 reset:
1021 reset_control_assert(dsi->rst);
1022 return err;
1023 }
1024
1025 static int tegra_dsi_exit(struct host1x_client *client)
1026 {
1027 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1028 int err;
1029
1030 tegra_output_exit(&dsi->output);
1031
1032 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1033 err = tegra_dsi_debugfs_exit(dsi);
1034 if (err < 0)
1035 dev_err(dsi->dev, "debugfs cleanup failed: %d\n", err);
1036 }
1037
1038 reset_control_assert(dsi->rst);
1039
1040 return 0;
1041 }
1042
1043 static const struct host1x_client_ops dsi_client_ops = {
1044 .init = tegra_dsi_init,
1045 .exit = tegra_dsi_exit,
1046 };
1047
1048 static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
1049 {
1050 struct clk *parent;
1051 int err;
1052
1053 parent = clk_get_parent(dsi->clk);
1054 if (!parent)
1055 return -EINVAL;
1056
1057 err = clk_set_parent(parent, dsi->clk_parent);
1058 if (err < 0)
1059 return err;
1060
1061 return 0;
1062 }
1063
1064 static const char * const error_report[16] = {
1065 "SoT Error",
1066 "SoT Sync Error",
1067 "EoT Sync Error",
1068 "Escape Mode Entry Command Error",
1069 "Low-Power Transmit Sync Error",
1070 "Peripheral Timeout Error",
1071 "False Control Error",
1072 "Contention Detected",
1073 "ECC Error, single-bit",
1074 "ECC Error, multi-bit",
1075 "Checksum Error",
1076 "DSI Data Type Not Recognized",
1077 "DSI VC ID Invalid",
1078 "Invalid Transmission Length",
1079 "Reserved",
1080 "DSI Protocol Violation",
1081 };
1082
1083 static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi,
1084 const struct mipi_dsi_msg *msg,
1085 size_t count)
1086 {
1087 u8 *rx = msg->rx_buf;
1088 unsigned int i, j, k;
1089 size_t size = 0;
1090 u16 errors;
1091 u32 value;
1092
1093 /* read and parse packet header */
1094 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1095
1096 switch (value & 0x3f) {
1097 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1098 errors = (value >> 8) & 0xffff;
1099 dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n",
1100 errors);
1101 for (i = 0; i < ARRAY_SIZE(error_report); i++)
1102 if (errors & BIT(i))
1103 dev_dbg(dsi->dev, " %2u: %s\n", i,
1104 error_report[i]);
1105 break;
1106
1107 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1108 rx[0] = (value >> 8) & 0xff;
1109 size = 1;
1110 break;
1111
1112 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1113 rx[0] = (value >> 8) & 0xff;
1114 rx[1] = (value >> 16) & 0xff;
1115 size = 2;
1116 break;
1117
1118 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1119 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1120 break;
1121
1122 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1123 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1124 break;
1125
1126 default:
1127 dev_err(dsi->dev, "unhandled response type: %02x\n",
1128 value & 0x3f);
1129 return -EPROTO;
1130 }
1131
1132 size = min(size, msg->rx_len);
1133
1134 if (msg->rx_buf && size > 0) {
1135 for (i = 0, j = 0; i < count - 1; i++, j += 4) {
1136 u8 *rx = msg->rx_buf + j;
1137
1138 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1139
1140 for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
1141 rx[j + k] = (value >> (k << 3)) & 0xff;
1142 }
1143 }
1144
1145 return size;
1146 }
1147
1148 static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout)
1149 {
1150 tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);
1151
1152 timeout = jiffies + msecs_to_jiffies(timeout);
1153
1154 while (time_before(jiffies, timeout)) {
1155 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
1156 if ((value & DSI_TRIGGER_HOST) == 0)
1157 return 0;
1158
1159 usleep_range(1000, 2000);
1160 }
1161
1162 DRM_DEBUG_KMS("timeout waiting for transmission to complete\n");
1163 return -ETIMEDOUT;
1164 }
1165
1166 static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi,
1167 unsigned long timeout)
1168 {
1169 timeout = jiffies + msecs_to_jiffies(250);
1170
1171 while (time_before(jiffies, timeout)) {
1172 u32 value = tegra_dsi_readl(dsi, DSI_STATUS);
1173 u8 count = value & 0x1f;
1174
1175 if (count > 0)
1176 return count;
1177
1178 usleep_range(1000, 2000);
1179 }
1180
1181 DRM_DEBUG_KMS("peripheral returned no data\n");
1182 return -ETIMEDOUT;
1183 }
1184
1185 static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset,
1186 const void *buffer, size_t size)
1187 {
1188 const u8 *buf = buffer;
1189 size_t i, j;
1190 u32 value;
1191
1192 for (j = 0; j < size; j += 4) {
1193 value = 0;
1194
1195 for (i = 0; i < 4 && j + i < size; i++)
1196 value |= buf[j + i] << (i << 3);
1197
1198 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1199 }
1200 }
1201
1202 static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
1203 const struct mipi_dsi_msg *msg)
1204 {
1205 struct tegra_dsi *dsi = host_to_tegra(host);
1206 struct mipi_dsi_packet packet;
1207 const u8 *header;
1208 size_t count;
1209 ssize_t err;
1210 u32 value;
1211
1212 err = mipi_dsi_create_packet(&packet, msg);
1213 if (err < 0)
1214 return err;
1215
1216 header = packet.header;
1217
1218 /* maximum FIFO depth is 1920 words */
1219 if (packet.size > dsi->video_fifo_depth * 4)
1220 return -ENOSPC;
1221
1222 /* reset underflow/overflow flags */
1223 value = tegra_dsi_readl(dsi, DSI_STATUS);
1224 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
1225 value = DSI_HOST_CONTROL_FIFO_RESET;
1226 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1227 usleep_range(10, 20);
1228 }
1229
1230 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
1231 value |= DSI_POWER_CONTROL_ENABLE;
1232 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
1233
1234 usleep_range(5000, 10000);
1235
1236 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
1237 DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
1238
1239 if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
1240 value |= DSI_HOST_CONTROL_HS;
1241
1242 /*
1243 * The host FIFO has a maximum of 64 words, so larger transmissions
1244 * need to use the video FIFO.
1245 */
1246 if (packet.size > dsi->host_fifo_depth * 4)
1247 value |= DSI_HOST_CONTROL_FIFO_SEL;
1248
1249 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1250
1251 /*
1252 * For reads and messages with explicitly requested ACK, generate a
1253 * BTA sequence after the transmission of the packet.
1254 */
1255 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1256 (msg->rx_buf && msg->rx_len > 0)) {
1257 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
1258 value |= DSI_HOST_CONTROL_PKT_BTA;
1259 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1260 }
1261
1262 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
1263 tegra_dsi_writel(dsi, value, DSI_CONTROL);
1264
1265 /* write packet header, ECC is generated by hardware */
1266 value = header[2] << 16 | header[1] << 8 | header[0];
1267 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1268
1269 /* write payload (if any) */
1270 if (packet.payload_length > 0)
1271 tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload,
1272 packet.payload_length);
1273
1274 err = tegra_dsi_transmit(dsi, 250);
1275 if (err < 0)
1276 return err;
1277
1278 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1279 (msg->rx_buf && msg->rx_len > 0)) {
1280 err = tegra_dsi_wait_for_response(dsi, 250);
1281 if (err < 0)
1282 return err;
1283
1284 count = err;
1285
1286 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1287 switch (value) {
1288 case 0x84:
1289 /*
1290 dev_dbg(dsi->dev, "ACK\n");
1291 */
1292 break;
1293
1294 case 0x87:
1295 /*
1296 dev_dbg(dsi->dev, "ESCAPE\n");
1297 */
1298 break;
1299
1300 default:
1301 dev_err(dsi->dev, "unknown status: %08x\n", value);
1302 break;
1303 }
1304
1305 if (count > 1) {
1306 err = tegra_dsi_read_response(dsi, msg, count);
1307 if (err < 0)
1308 dev_err(dsi->dev,
1309 "failed to parse response: %zd\n",
1310 err);
1311 else {
1312 /*
1313 * For read commands, return the number of
1314 * bytes returned by the peripheral.
1315 */
1316 count = err;
1317 }
1318 }
1319 } else {
1320 /*
1321 * For write commands, we have transmitted the 4-byte header
1322 * plus the variable-length payload.
1323 */
1324 count = 4 + packet.payload_length;
1325 }
1326
1327 return count;
1328 }
1329
1330 static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi)
1331 {
1332 struct clk *parent;
1333 int err;
1334
1335 /* make sure both DSI controllers share the same PLL */
1336 parent = clk_get_parent(dsi->slave->clk);
1337 if (!parent)
1338 return -EINVAL;
1339
1340 err = clk_set_parent(parent, dsi->clk_parent);
1341 if (err < 0)
1342 return err;
1343
1344 return 0;
1345 }
1346
1347 static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
1348 struct mipi_dsi_device *device)
1349 {
1350 struct tegra_dsi *dsi = host_to_tegra(host);
1351
1352 dsi->flags = device->mode_flags;
1353 dsi->format = device->format;
1354 dsi->lanes = device->lanes;
1355
1356 if (dsi->slave) {
1357 int err;
1358
1359 dev_dbg(dsi->dev, "attaching dual-channel device %s\n",
1360 dev_name(&device->dev));
1361
1362 err = tegra_dsi_ganged_setup(dsi);
1363 if (err < 0) {
1364 dev_err(dsi->dev, "failed to set up ganged mode: %d\n",
1365 err);
1366 return err;
1367 }
1368 }
1369
1370 /*
1371 * Slaves don't have a panel associated with them, so they provide
1372 * merely the second channel.
1373 */
1374 if (!dsi->master) {
1375 struct tegra_output *output = &dsi->output;
1376
1377 output->panel = of_drm_find_panel(device->dev.of_node);
1378 if (output->panel && output->connector.dev) {
1379 drm_panel_attach(output->panel, &output->connector);
1380 drm_helper_hpd_irq_event(output->connector.dev);
1381 }
1382 }
1383
1384 return 0;
1385 }
1386
1387 static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
1388 struct mipi_dsi_device *device)
1389 {
1390 struct tegra_dsi *dsi = host_to_tegra(host);
1391 struct tegra_output *output = &dsi->output;
1392
1393 if (output->panel && &device->dev == output->panel->dev) {
1394 output->panel = NULL;
1395
1396 if (output->connector.dev)
1397 drm_helper_hpd_irq_event(output->connector.dev);
1398 }
1399
1400 return 0;
1401 }
1402
1403 static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
1404 .attach = tegra_dsi_host_attach,
1405 .detach = tegra_dsi_host_detach,
1406 .transfer = tegra_dsi_host_transfer,
1407 };
1408
1409 static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi)
1410 {
1411 struct device_node *np;
1412
1413 np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0);
1414 if (np) {
1415 struct platform_device *gangster = of_find_device_by_node(np);
1416
1417 dsi->slave = platform_get_drvdata(gangster);
1418 of_node_put(np);
1419
1420 if (!dsi->slave)
1421 return -EPROBE_DEFER;
1422
1423 dsi->slave->master = dsi;
1424 }
1425
1426 return 0;
1427 }
1428
1429 static int tegra_dsi_probe(struct platform_device *pdev)
1430 {
1431 struct tegra_dsi *dsi;
1432 struct resource *regs;
1433 int err;
1434
1435 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1436 if (!dsi)
1437 return -ENOMEM;
1438
1439 dsi->output.dev = dsi->dev = &pdev->dev;
1440 dsi->video_fifo_depth = 1920;
1441 dsi->host_fifo_depth = 64;
1442
1443 err = tegra_dsi_ganged_probe(dsi);
1444 if (err < 0)
1445 return err;
1446
1447 err = tegra_output_probe(&dsi->output);
1448 if (err < 0)
1449 return err;
1450
1451 dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD;
1452
1453 /*
1454 * Assume these values by default. When a DSI peripheral driver
1455 * attaches to the DSI host, the parameters will be taken from
1456 * the attached device.
1457 */
1458 dsi->flags = MIPI_DSI_MODE_VIDEO;
1459 dsi->format = MIPI_DSI_FMT_RGB888;
1460 dsi->lanes = 4;
1461
1462 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
1463 if (IS_ERR(dsi->rst))
1464 return PTR_ERR(dsi->rst);
1465
1466 dsi->clk = devm_clk_get(&pdev->dev, NULL);
1467 if (IS_ERR(dsi->clk)) {
1468 dev_err(&pdev->dev, "cannot get DSI clock\n");
1469 err = PTR_ERR(dsi->clk);
1470 goto reset;
1471 }
1472
1473 err = clk_prepare_enable(dsi->clk);
1474 if (err < 0) {
1475 dev_err(&pdev->dev, "cannot enable DSI clock\n");
1476 goto reset;
1477 }
1478
1479 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
1480 if (IS_ERR(dsi->clk_lp)) {
1481 dev_err(&pdev->dev, "cannot get low-power clock\n");
1482 err = PTR_ERR(dsi->clk_lp);
1483 goto disable_clk;
1484 }
1485
1486 err = clk_prepare_enable(dsi->clk_lp);
1487 if (err < 0) {
1488 dev_err(&pdev->dev, "cannot enable low-power clock\n");
1489 goto disable_clk;
1490 }
1491
1492 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1493 if (IS_ERR(dsi->clk_parent)) {
1494 dev_err(&pdev->dev, "cannot get parent clock\n");
1495 err = PTR_ERR(dsi->clk_parent);
1496 goto disable_clk_lp;
1497 }
1498
1499 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi");
1500 if (IS_ERR(dsi->vdd)) {
1501 dev_err(&pdev->dev, "cannot get VDD supply\n");
1502 err = PTR_ERR(dsi->vdd);
1503 goto disable_clk_lp;
1504 }
1505
1506 err = regulator_enable(dsi->vdd);
1507 if (err < 0) {
1508 dev_err(&pdev->dev, "cannot enable VDD supply\n");
1509 goto disable_clk_lp;
1510 }
1511
1512 err = tegra_dsi_setup_clocks(dsi);
1513 if (err < 0) {
1514 dev_err(&pdev->dev, "cannot setup clocks\n");
1515 goto disable_vdd;
1516 }
1517
1518 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1519 dsi->regs = devm_ioremap_resource(&pdev->dev, regs);
1520 if (IS_ERR(dsi->regs)) {
1521 err = PTR_ERR(dsi->regs);
1522 goto disable_vdd;
1523 }
1524
1525 dsi->mipi = tegra_mipi_request(&pdev->dev);
1526 if (IS_ERR(dsi->mipi)) {
1527 err = PTR_ERR(dsi->mipi);
1528 goto disable_vdd;
1529 }
1530
1531 dsi->host.ops = &tegra_dsi_host_ops;
1532 dsi->host.dev = &pdev->dev;
1533
1534 err = mipi_dsi_host_register(&dsi->host);
1535 if (err < 0) {
1536 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
1537 goto mipi_free;
1538 }
1539
1540 INIT_LIST_HEAD(&dsi->client.list);
1541 dsi->client.ops = &dsi_client_ops;
1542 dsi->client.dev = &pdev->dev;
1543
1544 err = host1x_client_register(&dsi->client);
1545 if (err < 0) {
1546 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1547 err);
1548 goto unregister;
1549 }
1550
1551 platform_set_drvdata(pdev, dsi);
1552
1553 return 0;
1554
1555 unregister:
1556 mipi_dsi_host_unregister(&dsi->host);
1557 mipi_free:
1558 tegra_mipi_free(dsi->mipi);
1559 disable_vdd:
1560 regulator_disable(dsi->vdd);
1561 disable_clk_lp:
1562 clk_disable_unprepare(dsi->clk_lp);
1563 disable_clk:
1564 clk_disable_unprepare(dsi->clk);
1565 reset:
1566 reset_control_assert(dsi->rst);
1567 return err;
1568 }
1569
1570 static int tegra_dsi_remove(struct platform_device *pdev)
1571 {
1572 struct tegra_dsi *dsi = platform_get_drvdata(pdev);
1573 int err;
1574
1575 err = host1x_client_unregister(&dsi->client);
1576 if (err < 0) {
1577 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1578 err);
1579 return err;
1580 }
1581
1582 err = tegra_output_remove(&dsi->output);
1583 if (err < 0) {
1584 dev_err(&pdev->dev, "failed to remove output: %d\n", err);
1585 return err;
1586 }
1587
1588 mipi_dsi_host_unregister(&dsi->host);
1589 tegra_mipi_free(dsi->mipi);
1590
1591 regulator_disable(dsi->vdd);
1592 clk_disable_unprepare(dsi->clk_lp);
1593 clk_disable_unprepare(dsi->clk);
1594 reset_control_assert(dsi->rst);
1595
1596 return 0;
1597 }
1598
1599 static const struct of_device_id tegra_dsi_of_match[] = {
1600 { .compatible = "nvidia,tegra114-dsi", },
1601 { },
1602 };
1603 MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);
1604
1605 struct platform_driver tegra_dsi_driver = {
1606 .driver = {
1607 .name = "tegra-dsi",
1608 .of_match_table = tegra_dsi_of_match,
1609 },
1610 .probe = tegra_dsi_probe,
1611 .remove = tegra_dsi_remove,
1612 };
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