drivers/net/wireless/ath/ath9k/ar9003_mci.h

   1 /*
   2  * Copyright (c) 2010-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef AR9003_MCI_H
  18 #define AR9003_MCI_H
  19
  20 #define MCI_FLAG_DISABLE_TIMESTAMP      0x00000001      /* Disable time stamp */
  21
  22 /* Default remote BT device MCI COEX version */
  23 #define MCI_GPM_COEX_MAJOR_VERSION_DEFAULT  3
  24 #define MCI_GPM_COEX_MINOR_VERSION_DEFAULT  0
  25
  26 /* Local WLAN MCI COEX version */
  27 #define MCI_GPM_COEX_MAJOR_VERSION_WLAN     3
  28 #define MCI_GPM_COEX_MINOR_VERSION_WLAN     0
  29
  30 enum mci_gpm_coex_query_type {
  31         MCI_GPM_COEX_QUERY_BT_ALL_INFO      = BIT(0),
  32         MCI_GPM_COEX_QUERY_BT_TOPOLOGY      = BIT(1),
  33         MCI_GPM_COEX_QUERY_BT_DEBUG         = BIT(2),
  34 };
  35
  36 enum mci_gpm_coex_halt_bt_gpm {
  37         MCI_GPM_COEX_BT_GPM_UNHALT,
  38         MCI_GPM_COEX_BT_GPM_HALT
  39 };
  40
  41 enum mci_gpm_coex_bt_update_flags_op {
  42         MCI_GPM_COEX_BT_FLAGS_READ,
  43         MCI_GPM_COEX_BT_FLAGS_SET,
  44         MCI_GPM_COEX_BT_FLAGS_CLEAR
  45 };
  46
  47 #define MCI_NUM_BT_CHANNELS     79
  48
  49 #define MCI_BT_MCI_FLAGS_UPDATE_CORR          0x00000002
  50 #define MCI_BT_MCI_FLAGS_UPDATE_HDR           0x00000004
  51 #define MCI_BT_MCI_FLAGS_UPDATE_PLD           0x00000008
  52 #define MCI_BT_MCI_FLAGS_LNA_CTRL             0x00000010
  53 #define MCI_BT_MCI_FLAGS_DEBUG                0x00000020
  54 #define MCI_BT_MCI_FLAGS_SCHED_MSG            0x00000040
  55 #define MCI_BT_MCI_FLAGS_CONT_MSG             0x00000080
  56 #define MCI_BT_MCI_FLAGS_COEX_GPM             0x00000100
  57 #define MCI_BT_MCI_FLAGS_CPU_INT_MSG          0x00000200
  58 #define MCI_BT_MCI_FLAGS_MCI_MODE             0x00000400
  59 #define MCI_BT_MCI_FLAGS_AR9462_MODE          0x00001000
  60 #define MCI_BT_MCI_FLAGS_OTHER                0x00010000
  61
  62 #define MCI_DEFAULT_BT_MCI_FLAGS              0x00011dde
  63
  64 #define MCI_TOGGLE_BT_MCI_FLAGS  (MCI_BT_MCI_FLAGS_UPDATE_CORR | \
  65                                   MCI_BT_MCI_FLAGS_UPDATE_HDR  | \
  66                                   MCI_BT_MCI_FLAGS_UPDATE_PLD  | \
  67                                   MCI_BT_MCI_FLAGS_MCI_MODE)
  68
  69 #define MCI_2G_FLAGS_CLEAR_MASK   0x00000000
  70 #define MCI_2G_FLAGS_SET_MASK     MCI_TOGGLE_BT_MCI_FLAGS
  71 #define MCI_2G_FLAGS              MCI_DEFAULT_BT_MCI_FLAGS
  72
  73 #define MCI_5G_FLAGS_CLEAR_MASK   MCI_TOGGLE_BT_MCI_FLAGS
  74 #define MCI_5G_FLAGS_SET_MASK     0x00000000
  75 #define MCI_5G_FLAGS              (MCI_DEFAULT_BT_MCI_FLAGS & \
  76                                    ~MCI_TOGGLE_BT_MCI_FLAGS)
  77
  78 /*
  79  * Default value for AR9462 is 0x00002201
  80  */
  81 #define ATH_MCI_CONFIG_CONCUR_TX            0x00000003
  82 #define ATH_MCI_CONFIG_MCI_OBS_MCI          0x00000004
  83 #define ATH_MCI_CONFIG_MCI_OBS_TXRX         0x00000008
  84 #define ATH_MCI_CONFIG_MCI_OBS_BT           0x00000010
  85 #define ATH_MCI_CONFIG_DISABLE_MCI_CAL      0x00000020
  86 #define ATH_MCI_CONFIG_DISABLE_OSLA         0x00000040
  87 #define ATH_MCI_CONFIG_DISABLE_FTP_STOMP    0x00000080
  88 #define ATH_MCI_CONFIG_AGGR_THRESH          0x00000700
  89 #define ATH_MCI_CONFIG_AGGR_THRESH_S        8
  90 #define ATH_MCI_CONFIG_DISABLE_AGGR_THRESH  0x00000800
  91 #define ATH_MCI_CONFIG_CLK_DIV              0x00003000
  92 #define ATH_MCI_CONFIG_CLK_DIV_S            12
  93 #define ATH_MCI_CONFIG_DISABLE_TUNING       0x00004000
  94 #define ATH_MCI_CONFIG_MCI_WEIGHT_DBG       0x40000000
  95 #define ATH_MCI_CONFIG_DISABLE_MCI          0x80000000
  96
  97 #define ATH_MCI_CONFIG_MCI_OBS_MASK     (ATH_MCI_CONFIG_MCI_OBS_MCI  | \
  98                                          ATH_MCI_CONFIG_MCI_OBS_TXRX | \
  99                                          ATH_MCI_CONFIG_MCI_OBS_BT)
 100 #define ATH_MCI_CONFIG_MCI_OBS_GPIO     0x0000002F
 101
 102 enum mci_message_header {               /* length of payload */
 103         MCI_LNA_CTRL     = 0x10,        /* len = 0 */
 104         MCI_CONT_NACK    = 0x20,        /* len = 0 */
 105         MCI_CONT_INFO    = 0x30,        /* len = 4 */
 106         MCI_CONT_RST     = 0x40,        /* len = 0 */
 107         MCI_SCHD_INFO    = 0x50,        /* len = 16 */
 108         MCI_CPU_INT      = 0x60,        /* len = 4 */
 109         MCI_SYS_WAKING   = 0x70,        /* len = 0 */
 110         MCI_GPM          = 0x80,        /* len = 16 */
 111         MCI_LNA_INFO     = 0x90,        /* len = 1 */
 112         MCI_LNA_STATE    = 0x94,
 113         MCI_LNA_TAKE     = 0x98,
 114         MCI_LNA_TRANS    = 0x9c,
 115         MCI_SYS_SLEEPING = 0xa0,        /* len = 0 */
 116         MCI_REQ_WAKE     = 0xc0,        /* len = 0 */
 117         MCI_DEBUG_16     = 0xfe,        /* len = 2 */
 118         MCI_REMOTE_RESET = 0xff         /* len = 16 */
 119 };
 120
 121 enum ath_mci_gpm_coex_profile_type {
 122         MCI_GPM_COEX_PROFILE_UNKNOWN,
 123         MCI_GPM_COEX_PROFILE_RFCOMM,
 124         MCI_GPM_COEX_PROFILE_A2DP,
 125         MCI_GPM_COEX_PROFILE_HID,
 126         MCI_GPM_COEX_PROFILE_BNEP,
 127         MCI_GPM_COEX_PROFILE_VOICE,
 128         MCI_GPM_COEX_PROFILE_MAX
 129 };
 130
 131 /* MCI GPM/Coex opcode/type definitions */
 132 enum {
 133         MCI_GPM_COEX_W_GPM_PAYLOAD      = 1,
 134         MCI_GPM_COEX_B_GPM_TYPE         = 4,
 135         MCI_GPM_COEX_B_GPM_OPCODE       = 5,
 136         /* MCI_GPM_WLAN_CAL_REQ, MCI_GPM_WLAN_CAL_DONE */
 137         MCI_GPM_WLAN_CAL_W_SEQUENCE     = 2,
 138
 139         /* MCI_GPM_COEX_VERSION_QUERY */
 140         /* MCI_GPM_COEX_VERSION_RESPONSE */
 141         MCI_GPM_COEX_B_MAJOR_VERSION    = 6,
 142         MCI_GPM_COEX_B_MINOR_VERSION    = 7,
 143         /* MCI_GPM_COEX_STATUS_QUERY */
 144         MCI_GPM_COEX_B_BT_BITMAP        = 6,
 145         MCI_GPM_COEX_B_WLAN_BITMAP      = 7,
 146         /* MCI_GPM_COEX_HALT_BT_GPM */
 147         MCI_GPM_COEX_B_HALT_STATE       = 6,
 148         /* MCI_GPM_COEX_WLAN_CHANNELS */
 149         MCI_GPM_COEX_B_CHANNEL_MAP      = 6,
 150         /* MCI_GPM_COEX_BT_PROFILE_INFO */
 151         MCI_GPM_COEX_B_PROFILE_TYPE     = 6,
 152         MCI_GPM_COEX_B_PROFILE_LINKID   = 7,
 153         MCI_GPM_COEX_B_PROFILE_STATE    = 8,
 154         MCI_GPM_COEX_B_PROFILE_ROLE     = 9,
 155         MCI_GPM_COEX_B_PROFILE_RATE     = 10,
 156         MCI_GPM_COEX_B_PROFILE_VOTYPE   = 11,
 157         MCI_GPM_COEX_H_PROFILE_T        = 12,
 158         MCI_GPM_COEX_B_PROFILE_W        = 14,
 159         MCI_GPM_COEX_B_PROFILE_A        = 15,
 160         /* MCI_GPM_COEX_BT_STATUS_UPDATE */
 161         MCI_GPM_COEX_B_STATUS_TYPE      = 6,
 162         MCI_GPM_COEX_B_STATUS_LINKID    = 7,
 163         MCI_GPM_COEX_B_STATUS_STATE     = 8,
 164         /* MCI_GPM_COEX_BT_UPDATE_FLAGS */
 165         MCI_GPM_COEX_W_BT_FLAGS         = 6,
 166         MCI_GPM_COEX_B_BT_FLAGS_OP      = 10
 167 };
 168
 169 enum mci_gpm_subtype {
 170         MCI_GPM_BT_CAL_REQ      = 0,
 171         MCI_GPM_BT_CAL_GRANT    = 1,
 172         MCI_GPM_BT_CAL_DONE     = 2,
 173         MCI_GPM_WLAN_CAL_REQ    = 3,
 174         MCI_GPM_WLAN_CAL_GRANT  = 4,
 175         MCI_GPM_WLAN_CAL_DONE   = 5,
 176         MCI_GPM_COEX_AGENT      = 0x0c,
 177         MCI_GPM_RSVD_PATTERN    = 0xfe,
 178         MCI_GPM_RSVD_PATTERN32  = 0xfefefefe,
 179         MCI_GPM_BT_DEBUG        = 0xff
 180 };
 181
 182 enum mci_bt_state {
 183         MCI_BT_SLEEP,
 184         MCI_BT_AWAKE,
 185         MCI_BT_CAL_START,
 186         MCI_BT_CAL
 187 };
 188
 189 /* Type of state query */
 190 enum mci_state_type {
 191         MCI_STATE_ENABLE,
 192         MCI_STATE_INIT_GPM_OFFSET,
 193         MCI_STATE_NEXT_GPM_OFFSET,
 194         MCI_STATE_LAST_GPM_OFFSET,
 195         MCI_STATE_BT,
 196         MCI_STATE_SET_BT_SLEEP,
 197         MCI_STATE_SET_BT_AWAKE,
 198         MCI_STATE_SET_BT_CAL_START,
 199         MCI_STATE_SET_BT_CAL,
 200         MCI_STATE_LAST_SCHD_MSG_OFFSET,
 201         MCI_STATE_REMOTE_SLEEP,
 202         MCI_STATE_CONT_RSSI_POWER,
 203         MCI_STATE_CONT_PRIORITY,
 204         MCI_STATE_CONT_TXRX,
 205         MCI_STATE_RESET_REQ_WAKE,
 206         MCI_STATE_SEND_WLAN_COEX_VERSION,
 207         MCI_STATE_SET_BT_COEX_VERSION,
 208         MCI_STATE_SEND_WLAN_CHANNELS,
 209         MCI_STATE_SEND_VERSION_QUERY,
 210         MCI_STATE_SEND_STATUS_QUERY,
 211         MCI_STATE_NEED_FLUSH_BT_INFO,
 212         MCI_STATE_SET_CONCUR_TX_PRI,
 213         MCI_STATE_RECOVER_RX,
 214         MCI_STATE_NEED_FTP_STOMP,
 215         MCI_STATE_NEED_TUNING,
 216         MCI_STATE_DEBUG,
 217         MCI_STATE_MAX
 218 };
 219
 220 enum mci_gpm_coex_opcode {
 221         MCI_GPM_COEX_VERSION_QUERY,
 222         MCI_GPM_COEX_VERSION_RESPONSE,
 223         MCI_GPM_COEX_STATUS_QUERY,
 224         MCI_GPM_COEX_HALT_BT_GPM,
 225         MCI_GPM_COEX_WLAN_CHANNELS,
 226         MCI_GPM_COEX_BT_PROFILE_INFO,
 227         MCI_GPM_COEX_BT_STATUS_UPDATE,
 228         MCI_GPM_COEX_BT_UPDATE_FLAGS
 229 };
 230
 231 #define MCI_GPM_NOMORE  0
 232 #define MCI_GPM_MORE    1
 233 #define MCI_GPM_INVALID 0xffffffff
 234
 235 #define MCI_GPM_RECYCLE(_p_gpm) do {                      \
 236         *(((u32 *)_p_gpm) + MCI_GPM_COEX_W_GPM_PAYLOAD) = \
 237                                 MCI_GPM_RSVD_PATTERN32;   \
 238 } while (0)
 239
 240 #define MCI_GPM_TYPE(_p_gpm)    \
 241         (*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) & 0xff)
 242
 243 #define MCI_GPM_OPCODE(_p_gpm)  \
 244         (*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) & 0xff)
 245
 246 #define MCI_GPM_SET_CAL_TYPE(_p_gpm, _cal_type) do {                       \
 247         *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_cal_type) & 0xff;\
 248 } while (0)
 249
 250 #define MCI_GPM_SET_TYPE_OPCODE(_p_gpm, _type, _opcode) do {               \
 251         *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_type) & 0xff;    \
 252         *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) = (_opcode) & 0xff;\
 253 } while (0)
 254
 255 #define MCI_GPM_IS_CAL_TYPE(_type) ((_type) <= MCI_GPM_WLAN_CAL_DONE)
 256
 257 /*
 258  * Functions that are available to the MCI driver core.
 259  */
 260 bool ar9003_mci_send_message(struct ath_hw *ah, u8 header, u32 flag,
 261                              u32 *payload, u8 len, bool wait_done,
 262                              bool check_bt);
 263 u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data);
 264 void ar9003_mci_setup(struct ath_hw *ah, u32 gpm_addr, void *gpm_buf,
 265                       u16 len, u32 sched_addr);
 266 void ar9003_mci_cleanup(struct ath_hw *ah);
 267 void ar9003_mci_get_interrupt(struct ath_hw *ah, u32 *raw_intr,
 268                               u32 *rx_msg_intr);
 269
 270 /*
 271  * These functions are used by ath9k_hw.
 272  */
 273
 274 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
 275
 276 void ar9003_mci_stop_bt(struct ath_hw *ah, bool save_fullsleep);
 277 void ar9003_mci_init_cal_req(struct ath_hw *ah, bool *is_reusable);
 278 void ar9003_mci_init_cal_done(struct ath_hw *ah);
 279 void ar9003_mci_set_full_sleep(struct ath_hw *ah);
 280 void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool wait_done);
 281 void ar9003_mci_check_bt(struct ath_hw *ah);
 282 bool ar9003_mci_start_reset(struct ath_hw *ah, struct ath9k_channel *chan);
 283 int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan,
 284                          struct ath9k_hw_cal_data *caldata);
 285 void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
 286                       bool is_full_sleep);
 287 void ar9003_mci_get_isr(struct ath_hw *ah, enum ath9k_int *masked);
 288
 289 #else
 290
 291 static inline void ar9003_mci_stop_bt(struct ath_hw *ah, bool save_fullsleep)
 292 {
 293 }
 294 static inline void ar9003_mci_init_cal_req(struct ath_hw *ah, bool *is_reusable)
 295 {
 296 }
 297 static inline void ar9003_mci_init_cal_done(struct ath_hw *ah)
 298 {
 299 }
 300 static inline void ar9003_mci_set_full_sleep(struct ath_hw *ah)
 301 {
 302 }
 303 static inline void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool wait_done)
 304 {
 305 }
 306 static inline void ar9003_mci_check_bt(struct ath_hw *ah)
 307 {
 308 }
 309 static inline bool ar9003_mci_start_reset(struct ath_hw *ah, struct ath9k_channel *chan)
 310 {
 311         return false;
 312 }
 313 static inline int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan,
 314                                        struct ath9k_hw_cal_data *caldata)
 315 {
 316         return 0;
 317 }
 318 static inline void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
 319                                     bool is_full_sleep)
 320 {
 321 }
 322 static inline void ar9003_mci_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
 323 {
 324 }
 325 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
 326
 327 #endif