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[PATCH] fbdev: fill in the access_align field.
[linux-2.6/btrfs-unstable.git] / drivers / video / nvidia / nvidia.c
blobb2e6b240786917d9c1cae810a76729d3ff2c0686
1 /*
2 * linux/drivers/video/nvidia/nvidia.c - nVidia fb driver
3 *
4 * Copyright 2004 Antonino Daplas <adaplas@pol.net>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 *
10 */
11
12 #include <linux/config.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/errno.h>
16 #include <linux/string.h>
17 #include <linux/mm.h>
18 #include <linux/tty.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/fb.h>
22 #include <linux/init.h>
23 #include <linux/pci.h>
24 #ifdef CONFIG_MTRR
25 #include <asm/mtrr.h>
26 #endif
27 #ifdef CONFIG_PPC_OF
28 #include <asm/prom.h>
29 #include <asm/pci-bridge.h>
30 #endif
31 #ifdef CONFIG_PMAC_BACKLIGHT
32 #include <asm/backlight.h>
33 #endif
34
35 #include "nv_local.h"
36 #include "nv_type.h"
37 #include "nv_proto.h"
38 #include "nv_dma.h"
39
40 #ifndef CONFIG_PCI /* sanity check */
41 #error This driver requires PCI support.
42 #endif
43
44 #undef CONFIG_FB_NVIDIA_DEBUG
45 #ifdef CONFIG_FB_NVIDIA_DEBUG
46 #define NVTRACE printk
47 #else
48 #define NVTRACE if (0) printk
49 #endif
50
51 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
52 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
53
54 #ifdef CONFIG_FB_NVIDIA_DEBUG
55 #define assert(expr) \
56 if (!(expr)) { \
57 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
58 #expr,__FILE__,__FUNCTION__,__LINE__); \
59 BUG(); \
60 }
61 #else
62 #define assert(expr)
63 #endif
64
65 #define PFX "nvidiafb: "
66
67 /* HW cursor parameters */
68 #define MAX_CURS 32
69
70 static struct pci_device_id nvidiafb_pci_tbl[] = {
71 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
72 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
73 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
74 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
75 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
76 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
77 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT_UNKNOWN,
78 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
79 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
80 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
81 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
82 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
83 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
84 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
85 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
86 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
87 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
88 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
89 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
90 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
91 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
92 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
93 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
94 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
95 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
96 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
97 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
98 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
99 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
100 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
101 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
102 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
103 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
104 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
105 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
106 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
107 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
108 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
109 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
110 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
111 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
112 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
113 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_SE,
114 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
115 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
117 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
119 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
121 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
123 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
125 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
127 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
129 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
131 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
133 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO_M16,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
135 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_8X,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
137 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440SE_8X,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
139 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420_8X,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
141 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
143 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
145 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL,
146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
147 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_MAC,
148 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
149 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS,
150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
151 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL,
152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
153 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
155 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
157 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
159 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
161 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
163 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
165 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
167 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
169 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
171 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
173 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
175 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
177 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
179 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
181 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200_GO,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
183 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_980_XGL,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
185 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_780_XGL,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
187 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700_GOGL,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
189 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800_ULTRA,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
191 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
193 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
195 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
197 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600_ULTRA,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
199 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
201 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
203 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
205 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
207 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
209 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
211 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_ULTRA,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
213 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_1,
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
215 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
217 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
219 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
221 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250_32,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
223 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
225 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
227 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
229 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
231 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
233 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900_ULTRA,
234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
235 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900,
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
237 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
239 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950_ULTRA,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
241 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000,
242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
243 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700_ULTRA,
244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
245 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700,
246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
247 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE,
248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
249 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE,
250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
251 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_1,
252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
253 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2,
254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
255 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000,
256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
257 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100,
258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
259 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5500,
260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
261 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5100,
262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
263 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_700,
264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
265 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900ZT,
266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
267 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_ULTRA,
268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
269 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800,
270 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
271 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_LE,
272 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
273 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_GT,
274 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
275 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_4000,
276 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
277 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6600_GT,
278 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
279 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6600,
280 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
281 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6610_XL,
282 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
283 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_540,
284 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
285 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6200,
286 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
287 {PCI_VENDOR_ID_NVIDIA, 0x0252,
288 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
289 {PCI_VENDOR_ID_NVIDIA, 0x0313,
290 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
291 {PCI_VENDOR_ID_NVIDIA, 0x0316,
292 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
293 {PCI_VENDOR_ID_NVIDIA, 0x0317,
294 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
295 {PCI_VENDOR_ID_NVIDIA, 0x031D,
296 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
297 {PCI_VENDOR_ID_NVIDIA, 0x031E,
298 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
299 {PCI_VENDOR_ID_NVIDIA, 0x031F,
300 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
301 {PCI_VENDOR_ID_NVIDIA, 0x0329,
302 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
303 {PCI_VENDOR_ID_NVIDIA, 0x032F,
304 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
305 {PCI_VENDOR_ID_NVIDIA, 0x0345,
306 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
307 {PCI_VENDOR_ID_NVIDIA, 0x0349,
308 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
309 {PCI_VENDOR_ID_NVIDIA, 0x034B,
310 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
311 {PCI_VENDOR_ID_NVIDIA, 0x034F,
312 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
313 {PCI_VENDOR_ID_NVIDIA, 0x00c0,
314 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
315 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_6800A,
316 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
317 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_6800A_LE,
318 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
319 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_GO_6800,
320 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
321 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_GO_6800_ULTRA,
322 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
323 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_QUADRO_FX_GO1400,
324 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
325 {PCI_VENDOR_ID_NVIDIA, 0x00cd,
326 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
327 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_QUADRO_FX_1400,
328 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
329 {PCI_VENDOR_ID_NVIDIA, 0x0142,
330 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
331 {PCI_VENDOR_ID_NVIDIA, 0x0143,
332 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
333 {PCI_VENDOR_ID_NVIDIA, 0x0144,
334 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
335 {PCI_VENDOR_ID_NVIDIA, 0x0145,
336 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
337 {PCI_VENDOR_ID_NVIDIA, 0x0146,
338 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
339 {PCI_VENDOR_ID_NVIDIA, 0x0147,
340 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
341 {PCI_VENDOR_ID_NVIDIA, 0x0148,
342 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
343 {PCI_VENDOR_ID_NVIDIA, 0x0149,
344 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
345 {PCI_VENDOR_ID_NVIDIA, 0x014b,
346 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
347 {PCI_VENDOR_ID_NVIDIA, 0x14c,
348 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
349 {PCI_VENDOR_ID_NVIDIA, 0x014d,
350 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
351 {PCI_VENDOR_ID_NVIDIA, 0x0160,
352 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
353 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6200_TURBOCACHE,
354 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
355 {PCI_VENDOR_ID_NVIDIA, 0x0162,
356 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
357 {PCI_VENDOR_ID_NVIDIA, 0x0163,
358 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
359 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200,
360 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
361 {PCI_VENDOR_ID_NVIDIA, 0x0165,
362 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
363 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250,
364 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
365 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200_1,
366 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
367 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250_1,
368 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
369 {PCI_VENDOR_ID_NVIDIA, 0x0169,
370 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
371 {PCI_VENDOR_ID_NVIDIA, 0x016b,
372 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
373 {PCI_VENDOR_ID_NVIDIA, 0x016c,
374 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
375 {PCI_VENDOR_ID_NVIDIA, 0x016d,
376 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
377 {PCI_VENDOR_ID_NVIDIA, 0x016e,
378 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
379 {PCI_VENDOR_ID_NVIDIA, 0x0210,
380 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
381 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B,
382 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
383 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_LE,
384 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
385 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_GT,
386 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
387 {PCI_VENDOR_ID_NVIDIA, 0x021d,
388 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
389 {PCI_VENDOR_ID_NVIDIA, 0x021e,
390 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
391 {PCI_VENDOR_ID_NVIDIA, 0x0220,
392 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
393 {PCI_VENDOR_ID_NVIDIA, 0x0221,
394 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
395 {PCI_VENDOR_ID_NVIDIA, 0x0222,
396 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
397 {PCI_VENDOR_ID_NVIDIA, 0x0228,
398 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
399 {0,} /* terminate list */
400 };
401
402 MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl);
403
404 /* command line data, set in nvidiafb_setup() */
405 static int flatpanel __devinitdata = -1; /* Autodetect later */
406 static int forceCRTC __devinitdata = -1;
407 static int hwcur __devinitdata = 0;
408 static int noaccel __devinitdata = 0;
409 static int noscale __devinitdata = 0;
410 static int paneltweak __devinitdata = 0;
411 static int vram __devinitdata = 0;
412 #ifdef CONFIG_MTRR
413 static int nomtrr __devinitdata = 0;
414 #endif
415
416 static char *mode_option __devinitdata = NULL;
417
418 static struct fb_fix_screeninfo __devinitdata nvidiafb_fix = {
419 .type = FB_TYPE_PACKED_PIXELS,
420 .xpanstep = 8,
421 .ypanstep = 1,
422 };
423
424 static struct fb_var_screeninfo __devinitdata nvidiafb_default_var = {
425 .xres = 640,
426 .yres = 480,
427 .xres_virtual = 640,
428 .yres_virtual = 480,
429 .bits_per_pixel = 8,
430 .red = {0, 8, 0},
431 .green = {0, 8, 0},
432 .blue = {0, 8, 0},
433 .transp = {0, 0, 0},
434 .activate = FB_ACTIVATE_NOW,
435 .height = -1,
436 .width = -1,
437 .pixclock = 39721,
438 .left_margin = 40,
439 .right_margin = 24,
440 .upper_margin = 32,
441 .lower_margin = 11,
442 .hsync_len = 96,
443 .vsync_len = 2,
444 .vmode = FB_VMODE_NONINTERLACED
445 };
446
447 /*
448 * Backlight control
449 */
450 #ifdef CONFIG_PMAC_BACKLIGHT
451
452 static int nvidia_backlight_levels[] = {
453 0x158,
454 0x192,
455 0x1c6,
456 0x200,
457 0x234,
458 0x268,
459 0x2a2,
460 0x2d6,
461 0x310,
462 0x344,
463 0x378,
464 0x3b2,
465 0x3e6,
466 0x41a,
467 0x454,
468 0x534,
469 };
470
471 /* ------------------------------------------------------------------------- *
472 *
473 * Backlight operations
474 *
475 * ------------------------------------------------------------------------- */
476
477 static int nvidia_set_backlight_enable(int on, int level, void *data)
478 {
479 struct nvidia_par *par = (struct nvidia_par *)data;
480 u32 tmp_pcrt, tmp_pmc, fpcontrol;
481
482 tmp_pmc = NV_RD32(par->PMC, 0x10F0) & 0x0000FFFF;
483 tmp_pcrt = NV_RD32(par->PCRTC0, 0x081C) & 0xFFFFFFFC;
484 fpcontrol = NV_RD32(par->PRAMDAC, 0x0848) & 0xCFFFFFCC;
485
486 if (on && (level > BACKLIGHT_OFF)) {
487 tmp_pcrt |= 0x1;
488 tmp_pmc |= (1 << 31); // backlight bit
489 tmp_pmc |= nvidia_backlight_levels[level - 1] << 16;
490 }
491
492 if (on)
493 fpcontrol |= par->fpSyncs;
494 else
495 fpcontrol |= 0x20000022;
496
497 NV_WR32(par->PCRTC0, 0x081C, tmp_pcrt);
498 NV_WR32(par->PMC, 0x10F0, tmp_pmc);
499 NV_WR32(par->PRAMDAC, 0x848, fpcontrol);
500
501 return 0;
502 }
503
504 static int nvidia_set_backlight_level(int level, void *data)
505 {
506 return nvidia_set_backlight_enable(1, level, data);
507 }
508
509 static struct backlight_controller nvidia_backlight_controller = {
510 nvidia_set_backlight_enable,
511 nvidia_set_backlight_level
512 };
513
514 #endif /* CONFIG_PMAC_BACKLIGHT */
515
516 static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8,
517 u16 bg, u16 fg, u32 w, u32 h)
518 {
519 u32 *data = (u32 *) data8;
520 int i, j, k = 0;
521 u32 b, tmp;
522
523 w = (w + 1) & ~1;
524
525 for (i = 0; i < h; i++) {
526 b = *data++;
527 reverse_order(&b);
528
529 for (j = 0; j < w / 2; j++) {
530 tmp = 0;
531 #if defined (__BIG_ENDIAN)
532 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
533 b <<= 1;
534 tmp |= (b & (1 << 31)) ? fg : bg;
535 b <<= 1;
536 #else
537 tmp = (b & 1) ? fg : bg;
538 b >>= 1;
539 tmp |= (b & 1) ? fg << 16 : bg << 16;
540 b >>= 1;
541 #endif
542 NV_WR32(&par->CURSOR[k++], 0, tmp);
543 }
544 k += (MAX_CURS - w) / 2;
545 }
546 }
547
548 static void nvidia_write_clut(struct nvidia_par *par,
549 u8 regnum, u8 red, u8 green, u8 blue)
550 {
551 NVWriteDacMask(par, 0xff);
552 NVWriteDacWriteAddr(par, regnum);
553 NVWriteDacData(par, red);
554 NVWriteDacData(par, green);
555 NVWriteDacData(par, blue);
556 }
557
558 static void nvidia_read_clut(struct nvidia_par *par,
559 u8 regnum, u8 * red, u8 * green, u8 * blue)
560 {
561 NVWriteDacMask(par, 0xff);
562 NVWriteDacReadAddr(par, regnum);
563 *red = NVReadDacData(par);
564 *green = NVReadDacData(par);
565 *blue = NVReadDacData(par);
566 }
567
568 static int nvidia_panel_tweak(struct nvidia_par *par,
569 struct _riva_hw_state *state)
570 {
571 int tweak = 0;
572
573 if (par->paneltweak) {
574 tweak = par->paneltweak;
575 } else {
576 /* begin flat panel hacks */
577 /* This is unfortunate, but some chips need this register
578 tweaked or else you get artifacts where adjacent pixels are
579 swapped. There are no hard rules for what to set here so all
580 we can do is experiment and apply hacks. */
581
582 if(((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) {
583 /* At least one NV34 laptop needs this workaround. */
584 tweak = -1;
585 }
586
587 if((par->Chipset & 0xfff0) == 0x0310) {
588 tweak = 1;
589 }
590 /* end flat panel hacks */
591 }
592
593 return tweak;
594 }
595
596 static void nvidia_save_vga(struct nvidia_par *par,
597 struct _riva_hw_state *state)
598 {
599 int i;
600
601 NVTRACE_ENTER();
602 NVLockUnlock(par, 0);
603
604 NVUnloadStateExt(par, state);
605
606 state->misc_output = NVReadMiscOut(par);
607
608 for (i = 0; i < NUM_CRT_REGS; i++)
609 state->crtc[i] = NVReadCrtc(par, i);
610
611 for (i = 0; i < NUM_ATC_REGS; i++)
612 state->attr[i] = NVReadAttr(par, i);
613
614 for (i = 0; i < NUM_GRC_REGS; i++)
615 state->gra[i] = NVReadGr(par, i);
616
617 for (i = 0; i < NUM_SEQ_REGS; i++)
618 state->seq[i] = NVReadSeq(par, i);
619 NVTRACE_LEAVE();
620 }
621
622 static void nvidia_write_regs(struct nvidia_par *par)
623 {
624 struct _riva_hw_state *state = &par->ModeReg;
625 int i;
626
627 NVTRACE_ENTER();
628 NVWriteCrtc(par, 0x11, 0x00);
629
630 NVLockUnlock(par, 0);
631
632 NVLoadStateExt(par, state);
633
634 NVWriteMiscOut(par, state->misc_output);
635
636 for (i = 0; i < NUM_CRT_REGS; i++) {
637 switch (i) {
638 case 0x19:
639 case 0x20 ... 0x40:
640 break;
641 default:
642 NVWriteCrtc(par, i, state->crtc[i]);
643 }
644 }
645
646 for (i = 0; i < NUM_ATC_REGS; i++)
647 NVWriteAttr(par, i, state->attr[i]);
648
649 for (i = 0; i < NUM_GRC_REGS; i++)
650 NVWriteGr(par, i, state->gra[i]);
651
652 for (i = 0; i < NUM_SEQ_REGS; i++)
653 NVWriteSeq(par, i, state->seq[i]);
654 NVTRACE_LEAVE();
655 }
656
657 static int nvidia_calc_regs(struct fb_info *info)
658 {
659 struct nvidia_par *par = info->par;
660 struct _riva_hw_state *state = &par->ModeReg;
661 int i, depth = fb_get_color_depth(&info->var);
662 int h_display = info->var.xres / 8 - 1;
663 int h_start = (info->var.xres + info->var.right_margin) / 8 - 1;
664 int h_end = (info->var.xres + info->var.right_margin +
665 info->var.hsync_len) / 8 - 1;
666 int h_total = (info->var.xres + info->var.right_margin +
667 info->var.hsync_len + info->var.left_margin) / 8 - 5;
668 int h_blank_s = h_display;
669 int h_blank_e = h_total + 4;
670 int v_display = info->var.yres - 1;
671 int v_start = info->var.yres + info->var.lower_margin - 1;
672 int v_end = (info->var.yres + info->var.lower_margin +
673 info->var.vsync_len) - 1;
674 int v_total = (info->var.yres + info->var.lower_margin +
675 info->var.vsync_len + info->var.upper_margin) - 2;
676 int v_blank_s = v_display;
677 int v_blank_e = v_total + 1;
678
679 /*
680 * Set all CRTC values.
681 */
682
683 if (info->var.vmode & FB_VMODE_INTERLACED)
684 v_total |= 1;
685
686 if (par->FlatPanel == 1) {
687 v_start = v_total - 3;
688 v_end = v_total - 2;
689 v_blank_s = v_start;
690 h_start = h_total - 5;
691 h_end = h_total - 2;
692 h_blank_e = h_total + 4;
693 }
694
695 state->crtc[0x0] = Set8Bits(h_total);
696 state->crtc[0x1] = Set8Bits(h_display);
697 state->crtc[0x2] = Set8Bits(h_blank_s);
698 state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0)
699 | SetBit(7);
700 state->crtc[0x4] = Set8Bits(h_start);
701 state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7)
702 | SetBitField(h_end, 4: 0, 4:0);
703 state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0);
704 state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0)
705 | SetBitField(v_display, 8: 8, 1:1)
706 | SetBitField(v_start, 8: 8, 2:2)
707 | SetBitField(v_blank_s, 8: 8, 3:3)
708 | SetBit(4)
709 | SetBitField(v_total, 9: 9, 5:5)
710 | SetBitField(v_display, 9: 9, 6:6)
711 | SetBitField(v_start, 9: 9, 7:7);
712 state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5)
713 | SetBit(6)
714 | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00);
715 state->crtc[0x10] = Set8Bits(v_start);
716 state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5);
717 state->crtc[0x12] = Set8Bits(v_display);
718 state->crtc[0x13] = ((info->var.xres_virtual / 8) *
719 (info->var.bits_per_pixel / 8));
720 state->crtc[0x15] = Set8Bits(v_blank_s);
721 state->crtc[0x16] = Set8Bits(v_blank_e);
722
723 state->attr[0x10] = 0x01;
724
725 if (par->Television)
726 state->attr[0x11] = 0x00;
727
728 state->screen = SetBitField(h_blank_e, 6: 6, 4:4)
729 | SetBitField(v_blank_s, 10: 10, 3:3)
730 | SetBitField(v_start, 10: 10, 2:2)
731 | SetBitField(v_display, 10: 10, 1:1)
732 | SetBitField(v_total, 10: 10, 0:0);
733
734 state->horiz = SetBitField(h_total, 8: 8, 0:0)
735 | SetBitField(h_display, 8: 8, 1:1)
736 | SetBitField(h_blank_s, 8: 8, 2:2)
737 | SetBitField(h_start, 8: 8, 3:3);
738
739 state->extra = SetBitField(v_total, 11: 11, 0:0)
740 | SetBitField(v_display, 11: 11, 2:2)
741 | SetBitField(v_start, 11: 11, 4:4)
742 | SetBitField(v_blank_s, 11: 11, 6:6);
743
744 if (info->var.vmode & FB_VMODE_INTERLACED) {
745 h_total = (h_total >> 1) & ~1;
746 state->interlace = Set8Bits(h_total);
747 state->horiz |= SetBitField(h_total, 8: 8, 4:4);
748 } else {
749 state->interlace = 0xff; /* interlace off */
750 }
751
752 /*
753 * Calculate the extended registers.
754 */
755
756 if (depth < 24)
757 i = depth;
758 else
759 i = 32;
760
761 if (par->Architecture >= NV_ARCH_10)
762 par->CURSOR = (volatile u32 __iomem *)(info->screen_base +
763 par->CursorStart);
764
765 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
766 state->misc_output &= ~0x40;
767 else
768 state->misc_output |= 0x40;
769 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
770 state->misc_output &= ~0x80;
771 else
772 state->misc_output |= 0x80;
773
774 NVCalcStateExt(par, state, i, info->var.xres_virtual,
775 info->var.xres, info->var.yres_virtual,
776 1000000000 / info->var.pixclock, info->var.vmode);
777
778 state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff;
779 if (par->FlatPanel == 1) {
780 state->pixel |= (1 << 7);
781
782 if (!par->fpScaler || (par->fpWidth <= info->var.xres)
783 || (par->fpHeight <= info->var.yres)) {
784 state->scale |= (1 << 8);
785 }
786
787 if (!par->crtcSync_read) {
788 state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828);
789 par->crtcSync_read = 1;
790 }
791
792 par->PanelTweak = nvidia_panel_tweak(par, state);
793 }
794
795 state->vpll = state->pll;
796 state->vpll2 = state->pll;
797 state->vpllB = state->pllB;
798 state->vpll2B = state->pllB;
799
800 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
801 state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5);
802
803 if (par->CRTCnumber) {
804 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000;
805 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000;
806 state->crtcOwner = 3;
807 state->pllsel |= 0x20000800;
808 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508);
809 if (par->twoStagePLL)
810 state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578);
811 } else if (par->twoHeads) {
812 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000;
813 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000;
814 state->crtcOwner = 0;
815 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
816 if (par->twoStagePLL)
817 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
818 }
819
820 state->cursorConfig = 0x00000100;
821
822 if (info->var.vmode & FB_VMODE_DOUBLE)
823 state->cursorConfig |= (1 << 4);
824
825 if (par->alphaCursor) {
826 if ((par->Chipset & 0x0ff0) != 0x0110)
827 state->cursorConfig |= 0x04011000;
828 else
829 state->cursorConfig |= 0x14011000;
830 state->general |= (1 << 29);
831 } else
832 state->cursorConfig |= 0x02000000;
833
834 if (par->twoHeads) {
835 if ((par->Chipset & 0x0ff0) == 0x0110) {
836 state->dither = NV_RD32(par->PRAMDAC, 0x0528) &
837 ~0x00010000;
838 if (par->FPDither)
839 state->dither |= 0x00010000;
840 } else {
841 state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1;
842 if (par->FPDither)
843 state->dither |= 1;
844 }
845 }
846
847 state->timingH = 0;
848 state->timingV = 0;
849 state->displayV = info->var.xres;
850
851 return 0;
852 }
853
854 static void nvidia_init_vga(struct fb_info *info)
855 {
856 struct nvidia_par *par = info->par;
857 struct _riva_hw_state *state = &par->ModeReg;
858 int i;
859
860 for (i = 0; i < 0x10; i++)
861 state->attr[i] = i;
862 state->attr[0x10] = 0x41;
863 state->attr[0x11] = 0x01;
864 state->attr[0x12] = 0x0f;
865 state->attr[0x13] = 0x00;
866 state->attr[0x14] = 0x00;
867
868 memset(state->crtc, 0x00, NUM_CRT_REGS);
869 state->crtc[0x0a] = 0x20;
870 state->crtc[0x17] = 0xe3;
871 state->crtc[0x18] = 0xff;
872 state->crtc[0x28] = 0x40;
873
874 memset(state->gra, 0x00, NUM_GRC_REGS);
875 state->gra[0x05] = 0x40;
876 state->gra[0x06] = 0x05;
877 state->gra[0x07] = 0x0f;
878 state->gra[0x08] = 0xff;
879
880 state->seq[0x00] = 0x03;
881 state->seq[0x01] = 0x01;
882 state->seq[0x02] = 0x0f;
883 state->seq[0x03] = 0x00;
884 state->seq[0x04] = 0x0e;
885
886 state->misc_output = 0xeb;
887 }
888
889 static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
890 {
891 struct nvidia_par *par = info->par;
892 u8 data[MAX_CURS * MAX_CURS / 8];
893 int i, set = cursor->set;
894 u16 fg, bg;
895
896 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
897 return -ENXIO;
898
899 NVShowHideCursor(par, 0);
900
901 if (par->cursor_reset) {
902 set = FB_CUR_SETALL;
903 par->cursor_reset = 0;
904 }
905
906 if (set & FB_CUR_SETSIZE)
907 memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2);
908
909 if (set & FB_CUR_SETPOS) {
910 u32 xx, yy, temp;
911
912 yy = cursor->image.dy - info->var.yoffset;
913 xx = cursor->image.dx - info->var.xoffset;
914 temp = xx & 0xFFFF;
915 temp |= yy << 16;
916
917 NV_WR32(par->PRAMDAC, 0x0000300, temp);
918 }
919
920 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
921 u32 bg_idx = cursor->image.bg_color;
922 u32 fg_idx = cursor->image.fg_color;
923 u32 s_pitch = (cursor->image.width + 7) >> 3;
924 u32 d_pitch = MAX_CURS / 8;
925 u8 *dat = (u8 *) cursor->image.data;
926 u8 *msk = (u8 *) cursor->mask;
927 u8 *src;
928
929 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
930
931 if (src) {
932 switch (cursor->rop) {
933 case ROP_XOR:
934 for (i = 0; i < s_pitch * cursor->image.height; i++)
935 src[i] = dat[i] ^ msk[i];
936 break;
937 case ROP_COPY:
938 default:
939 for (i = 0; i < s_pitch * cursor->image.height; i++)
940 src[i] = dat[i] & msk[i];
941 break;
942 }
943
944 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
945 cursor->image.height);
946
947 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
948 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
949 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15;
950
951 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
952 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
953 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
954
955 NVLockUnlock(par, 0);
956
957 nvidiafb_load_cursor_image(par, data, bg, fg,
958 cursor->image.width,
959 cursor->image.height);
960 kfree(src);
961 }
962 }
963
964 if (cursor->enable)
965 NVShowHideCursor(par, 1);
966
967 return 0;
968 }
969
970 static int nvidiafb_set_par(struct fb_info *info)
971 {
972 struct nvidia_par *par = info->par;
973
974 NVTRACE_ENTER();
975
976 NVLockUnlock(par, 1);
977 if (!par->FlatPanel || (info->var.bits_per_pixel != 24) ||
978 !par->twoHeads)
979 par->FPDither = 0;
980
981 nvidia_init_vga(info);
982 nvidia_calc_regs(info);
983 nvidia_write_regs(par);
984
985 NVLockUnlock(par, 0);
986 if (par->twoHeads) {
987 VGA_WR08(par->PCIO, 0x03D4, 0x44);
988 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner);
989 NVLockUnlock(par, 0);
990 }
991
992 NVWriteCrtc(par, 0x11, 0x00);
993 info->fix.line_length = (info->var.xres_virtual *
994 info->var.bits_per_pixel) >> 3;
995 info->fix.visual = (info->var.bits_per_pixel == 8) ?
996 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
997
998 if (info->var.accel_flags) {
999 info->fbops->fb_imageblit = nvidiafb_imageblit;
1000 info->fbops->fb_fillrect = nvidiafb_fillrect;
1001 info->fbops->fb_copyarea = nvidiafb_copyarea;
1002 info->fbops->fb_sync = nvidiafb_sync;
1003 info->pixmap.scan_align = 4;
1004 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1005 NVResetGraphics(info);
1006 } else {
1007 info->fbops->fb_imageblit = cfb_imageblit;
1008 info->fbops->fb_fillrect = cfb_fillrect;
1009 info->fbops->fb_copyarea = cfb_copyarea;
1010 info->fbops->fb_sync = NULL;
1011 info->pixmap.scan_align = 1;
1012 info->flags |= FBINFO_HWACCEL_DISABLED;
1013 }
1014
1015 par->cursor_reset = 1;
1016
1017 NVWriteCrtc(par, 0x11, 0xff);
1018
1019 NVTRACE_LEAVE();
1020 return 0;
1021 }
1022
1023 static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1024 unsigned blue, unsigned transp,
1025 struct fb_info *info)
1026 {
1027 struct nvidia_par *par = info->par;
1028 int i;
1029
1030 NVTRACE_ENTER();
1031 if (regno >= (1 << info->var.green.length))
1032 return -EINVAL;
1033
1034 if (info->var.grayscale) {
1035 /* gray = 0.30*R + 0.59*G + 0.11*B */
1036 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
1037 }
1038
1039 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1040 ((u32 *) info->pseudo_palette)[regno] =
1041 (regno << info->var.red.offset) |
1042 (regno << info->var.green.offset) |
1043 (regno << info->var.blue.offset);
1044 }
1045
1046 switch (info->var.bits_per_pixel) {
1047 case 8:
1048 /* "transparent" stuff is completely ignored. */
1049 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
1050 break;
1051 case 16:
1052 if (info->var.green.length == 5) {
1053 for (i = 0; i < 8; i++) {
1054 nvidia_write_clut(par, regno * 8 + i, red >> 8,
1055 green >> 8, blue >> 8);
1056 }
1057 } else {
1058 u8 r, g, b;
1059
1060 if (regno < 32) {
1061 for (i = 0; i < 8; i++) {
1062 nvidia_write_clut(par, regno * 8 + i,
1063 red >> 8, green >> 8,
1064 blue >> 8);
1065 }
1066 }
1067
1068 nvidia_read_clut(par, regno * 4, &r, &g, &b);
1069
1070 for (i = 0; i < 4; i++)
1071 nvidia_write_clut(par, regno * 4 + i, r,
1072 green >> 8, b);
1073 }
1074 break;
1075 case 32:
1076 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
1077 break;
1078 default:
1079 /* do nothing */
1080 break;
1081 }
1082
1083 NVTRACE_LEAVE();
1084 return 0;
1085 }
1086
1087 static int nvidiafb_check_var(struct fb_var_screeninfo *var,
1088 struct fb_info *info)
1089 {
1090 struct nvidia_par *par = info->par;
1091 int memlen, vramlen, mode_valid = 0;
1092 int pitch, err = 0;
1093
1094 NVTRACE_ENTER();
1095
1096 var->transp.offset = 0;
1097 var->transp.length = 0;
1098
1099 var->xres &= ~7;
1100
1101 if (var->bits_per_pixel <= 8)
1102 var->bits_per_pixel = 8;
1103 else if (var->bits_per_pixel <= 16)
1104 var->bits_per_pixel = 16;
1105 else
1106 var->bits_per_pixel = 32;
1107
1108 switch (var->bits_per_pixel) {
1109 case 8:
1110 var->red.offset = 0;
1111 var->red.length = 8;
1112 var->green.offset = 0;
1113 var->green.length = 8;
1114 var->blue.offset = 0;
1115 var->blue.length = 8;
1116 var->transp.offset = 0;
1117 var->transp.length = 0;
1118 break;
1119 case 16:
1120 var->green.length = (var->green.length < 6) ? 5 : 6;
1121 var->red.length = 5;
1122 var->blue.length = 5;
1123 var->transp.length = 6 - var->green.length;
1124 var->blue.offset = 0;
1125 var->green.offset = 5;
1126 var->red.offset = 5 + var->green.length;
1127 var->transp.offset = (5 + var->red.offset) & 15;
1128 break;
1129 case 32: /* RGBA 8888 */
1130 var->red.offset = 16;
1131 var->red.length = 8;
1132 var->green.offset = 8;
1133 var->green.length = 8;
1134 var->blue.offset = 0;
1135 var->blue.length = 8;
1136 var->transp.length = 8;
1137 var->transp.offset = 24;
1138 break;
1139 }
1140
1141 var->red.msb_right = 0;
1142 var->green.msb_right = 0;
1143 var->blue.msb_right = 0;
1144 var->transp.msb_right = 0;
1145
1146 if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
1147 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1148 mode_valid = 1;
1149
1150 /* calculate modeline if supported by monitor */
1151 if (!mode_valid && info->monspecs.gtf) {
1152 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1153 mode_valid = 1;
1154 }
1155
1156 if (!mode_valid) {
1157 struct fb_videomode *mode;
1158
1159 mode = fb_find_best_mode(var, &info->modelist);
1160 if (mode) {
1161 fb_videomode_to_var(var, mode);
1162 mode_valid = 1;
1163 }
1164 }
1165
1166 if (!mode_valid && info->monspecs.modedb_len)
1167 return -EINVAL;
1168
1169 if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres ||
1170 par->fpHeight < var->yres))
1171 return -EINVAL;
1172
1173 if (var->yres_virtual < var->yres)
1174 var->yres_virtual = var->yres;
1175
1176 if (var->xres_virtual < var->xres)
1177 var->xres_virtual = var->xres;
1178
1179 var->xres_virtual = (var->xres_virtual + 63) & ~63;
1180
1181 vramlen = info->screen_size;
1182 pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8;
1183 memlen = pitch * var->yres_virtual;
1184
1185 if (memlen > vramlen) {
1186 var->yres_virtual = vramlen / pitch;
1187
1188 if (var->yres_virtual < var->yres) {
1189 var->yres_virtual = var->yres;
1190 var->xres_virtual = vramlen / var->yres_virtual;
1191 var->xres_virtual /= var->bits_per_pixel / 8;
1192 var->xres_virtual &= ~63;
1193 pitch = (var->xres_virtual *
1194 var->bits_per_pixel + 7) / 8;
1195 memlen = pitch * var->yres;
1196
1197 if (var->xres_virtual < var->xres) {
1198 printk("nvidiafb: required video memory, "
1199 "%d bytes, for %dx%d-%d (virtual) "
1200 "is out of range\n",
1201 memlen, var->xres_virtual,
1202 var->yres_virtual, var->bits_per_pixel);
1203 err = -ENOMEM;
1204 }
1205 }
1206 }
1207
1208 if (var->accel_flags) {
1209 if (var->yres_virtual > 0x7fff)
1210 var->yres_virtual = 0x7fff;
1211 if (var->xres_virtual > 0x7fff)
1212 var->xres_virtual = 0x7fff;
1213 }
1214
1215 var->xres_virtual &= ~63;
1216
1217 NVTRACE_LEAVE();
1218
1219 return err;
1220 }
1221
1222 static int nvidiafb_pan_display(struct fb_var_screeninfo *var,
1223 struct fb_info *info)
1224 {
1225 struct nvidia_par *par = info->par;
1226 u32 total;
1227
1228 total = info->var.yoffset * info->fix.line_length + info->var.xoffset;
1229
1230 NVSetStartAddress(par, total);
1231
1232 return 0;
1233 }
1234
1235 static int nvidiafb_blank(int blank, struct fb_info *info)
1236 {
1237 struct nvidia_par *par = info->par;
1238 unsigned char tmp, vesa;
1239
1240 tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */
1241 vesa = NVReadCrtc(par, 0x1a) & ~0xc0; /* sync on/off */
1242
1243 NVTRACE_ENTER();
1244
1245 if (blank)
1246 tmp |= 0x20;
1247
1248 switch (blank) {
1249 case FB_BLANK_UNBLANK:
1250 case FB_BLANK_NORMAL:
1251 break;
1252 case FB_BLANK_VSYNC_SUSPEND:
1253 vesa |= 0x80;
1254 break;
1255 case FB_BLANK_HSYNC_SUSPEND:
1256 vesa |= 0x40;
1257 break;
1258 case FB_BLANK_POWERDOWN:
1259 vesa |= 0xc0;
1260 break;
1261 }
1262
1263 NVWriteSeq(par, 0x01, tmp);
1264 NVWriteCrtc(par, 0x1a, vesa);
1265
1266 #ifdef CONFIG_PMAC_BACKLIGHT
1267 if (par->FlatPanel && _machine == _MACH_Pmac) {
1268 set_backlight_enable(!blank);
1269 }
1270 #endif
1271
1272 NVTRACE_LEAVE();
1273
1274 return 0;
1275 }
1276
1277 static struct fb_ops nvidia_fb_ops = {
1278 .owner = THIS_MODULE,
1279 .fb_check_var = nvidiafb_check_var,
1280 .fb_set_par = nvidiafb_set_par,
1281 .fb_setcolreg = nvidiafb_setcolreg,
1282 .fb_pan_display = nvidiafb_pan_display,
1283 .fb_blank = nvidiafb_blank,
1284 .fb_fillrect = nvidiafb_fillrect,
1285 .fb_copyarea = nvidiafb_copyarea,
1286 .fb_imageblit = nvidiafb_imageblit,
1287 .fb_cursor = nvidiafb_cursor,
1288 .fb_sync = nvidiafb_sync,
1289 };
1290
1291 static int __devinit nvidia_set_fbinfo(struct fb_info *info)
1292 {
1293 struct fb_monspecs *specs = &info->monspecs;
1294 struct fb_videomode modedb;
1295 struct nvidia_par *par = info->par;
1296 int lpitch;
1297
1298 NVTRACE_ENTER();
1299 info->flags = FBINFO_DEFAULT
1300 | FBINFO_HWACCEL_IMAGEBLIT
1301 | FBINFO_HWACCEL_FILLRECT
1302 | FBINFO_HWACCEL_COPYAREA
1303 | FBINFO_HWACCEL_YPAN;
1304
1305 fb_videomode_to_modelist(info->monspecs.modedb,
1306 info->monspecs.modedb_len, &info->modelist);
1307 fb_var_to_videomode(&modedb, &nvidiafb_default_var);
1308
1309 if (specs->modedb != NULL) {
1310 /* get preferred timing */
1311 if (specs->misc & FB_MISC_1ST_DETAIL) {
1312 int i;
1313
1314 for (i = 0; i < specs->modedb_len; i++) {
1315 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1316 modedb = specs->modedb[i];
1317 break;
1318 }
1319 }
1320 } else {
1321 /* otherwise, get first mode in database */
1322 modedb = specs->modedb[0];
1323 }
1324
1325 fb_videomode_to_var(&nvidiafb_default_var, &modedb);
1326 nvidiafb_default_var.bits_per_pixel = 8;
1327 }
1328
1329 if (mode_option)
1330 fb_find_mode(&nvidiafb_default_var, info, mode_option,
1331 specs->modedb, specs->modedb_len, &modedb, 8);
1332
1333 info->var = nvidiafb_default_var;
1334 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1335 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1336 info->pseudo_palette = par->pseudo_palette;
1337 fb_alloc_cmap(&info->cmap, 256, 0);
1338 fb_destroy_modedb(info->monspecs.modedb);
1339 info->monspecs.modedb = NULL;
1340
1341 /* maximize virtual vertical length */
1342 lpitch = info->var.xres_virtual *
1343 ((info->var.bits_per_pixel + 7) >> 3);
1344 info->var.yres_virtual = info->screen_size / lpitch;
1345
1346 info->pixmap.scan_align = 4;
1347 info->pixmap.buf_align = 4;
1348 info->pixmap.access_align = 32;
1349 info->pixmap.size = 8 * 1024;
1350 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1351
1352 if (!hwcur)
1353 info->fbops->fb_cursor = soft_cursor;
1354 info->var.accel_flags = (!noaccel);
1355
1356 switch (par->Architecture) {
1357 case NV_ARCH_04:
1358 info->fix.accel = FB_ACCEL_NV4;
1359 break;
1360 case NV_ARCH_10:
1361 info->fix.accel = FB_ACCEL_NV_10;
1362 break;
1363 case NV_ARCH_20:
1364 info->fix.accel = FB_ACCEL_NV_20;
1365 break;
1366 case NV_ARCH_30:
1367 info->fix.accel = FB_ACCEL_NV_30;
1368 break;
1369 case NV_ARCH_40:
1370 info->fix.accel = FB_ACCEL_NV_40;
1371 break;
1372 }
1373
1374 NVTRACE_LEAVE();
1375
1376 return nvidiafb_check_var(&info->var, info);
1377 }
1378
1379 static u32 __devinit nvidia_get_arch(struct pci_dev *pd)
1380 {
1381 u32 arch = 0;
1382
1383 switch (pd->device & 0x0ff0) {
1384 case 0x0100: /* GeForce 256 */
1385 case 0x0110: /* GeForce2 MX */
1386 case 0x0150: /* GeForce2 */
1387 case 0x0170: /* GeForce4 MX */
1388 case 0x0180: /* GeForce4 MX (8x AGP) */
1389 case 0x01A0: /* nForce */
1390 case 0x01F0: /* nForce2 */
1391 arch = NV_ARCH_10;
1392 break;
1393 case 0x0200: /* GeForce3 */
1394 case 0x0250: /* GeForce4 Ti */
1395 case 0x0280: /* GeForce4 Ti (8x AGP) */
1396 arch = NV_ARCH_20;
1397 break;
1398 case 0x0300: /* GeForceFX 5800 */
1399 case 0x0310: /* GeForceFX 5600 */
1400 case 0x0320: /* GeForceFX 5200 */
1401 case 0x0330: /* GeForceFX 5900 */
1402 case 0x0340: /* GeForceFX 5700 */
1403 arch = NV_ARCH_30;
1404 break;
1405 case 0x0040:
1406 case 0x00C0:
1407 case 0x0120:
1408 case 0x0130:
1409 case 0x0140:
1410 case 0x0160:
1411 case 0x01D0:
1412 case 0x0090:
1413 case 0x0210:
1414 case 0x0220:
1415 case 0x0230:
1416 arch = NV_ARCH_40;
1417 break;
1418 case 0x0020: /* TNT, TNT2 */
1419 arch = NV_ARCH_04;
1420 break;
1421 default: /* unknown architecture */
1422 break;
1423 }
1424
1425 return arch;
1426 }
1427
1428 static int __devinit nvidiafb_probe(struct pci_dev *pd,
1429 const struct pci_device_id *ent)
1430 {
1431 struct nvidia_par *par;
1432 struct fb_info *info;
1433 unsigned short cmd;
1434
1435
1436 NVTRACE_ENTER();
1437 assert(pd != NULL);
1438
1439 info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev);
1440
1441 if (!info)
1442 goto err_out;
1443
1444 par = (struct nvidia_par *)info->par;
1445 par->pci_dev = pd;
1446
1447 info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL);
1448
1449 if (info->pixmap.addr == NULL)
1450 goto err_out_kfree;
1451
1452 memset(info->pixmap.addr, 0, 8 * 1024);
1453
1454 if (pci_enable_device(pd)) {
1455 printk(KERN_ERR PFX "cannot enable PCI device\n");
1456 goto err_out_enable;
1457 }
1458
1459 if (pci_request_regions(pd, "nvidiafb")) {
1460 printk(KERN_ERR PFX "cannot request PCI regions\n");
1461 goto err_out_request;
1462 }
1463
1464 par->Architecture = nvidia_get_arch(pd);
1465
1466 par->Chipset = (pd->vendor << 16) | pd->device;
1467 printk(KERN_INFO PFX "nVidia device/chipset %X\n", par->Chipset);
1468
1469 #ifdef CONFIG_PCI_NAMES
1470 printk(KERN_INFO PFX "%s\n", pd->pretty_name);
1471 #endif
1472
1473 if (par->Architecture == 0) {
1474 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1475 goto err_out_free_base0;
1476 }
1477
1478 sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1479
1480 par->FlatPanel = flatpanel;
1481
1482 if (flatpanel == 1)
1483 printk(KERN_INFO PFX "flatpanel support enabled\n");
1484
1485 par->CRTCnumber = forceCRTC;
1486 par->FpScale = (!noscale);
1487 par->paneltweak = paneltweak;
1488
1489 /* enable IO and mem if not already done */
1490 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1491 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1492 pci_write_config_word(pd, PCI_COMMAND, cmd);
1493
1494 nvidiafb_fix.mmio_start = pci_resource_start(pd, 0);
1495 nvidiafb_fix.smem_start = pci_resource_start(pd, 1);
1496 nvidiafb_fix.mmio_len = pci_resource_len(pd, 0);
1497
1498 par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len);
1499
1500 if (!par->REGS) {
1501 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1502 goto err_out_free_base0;
1503 }
1504
1505 NVCommonSetup(info);
1506
1507 par->FbAddress = nvidiafb_fix.smem_start;
1508 par->FbMapSize = par->RamAmountKBytes * 1024;
1509 if (vram && vram * 1024 * 1024 < par->FbMapSize)
1510 par->FbMapSize = vram * 1024 * 1024;
1511
1512 /* Limit amount of vram to 64 MB */
1513 if (par->FbMapSize > 64 * 1024 * 1024)
1514 par->FbMapSize = 64 * 1024 * 1024;
1515
1516 par->FbUsableSize = par->FbMapSize - (128 * 1024);
1517 par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 :
1518 16 * 1024;
1519 par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize;
1520 info->screen_base = ioremap(nvidiafb_fix.smem_start, par->FbMapSize);
1521 info->screen_size = par->FbUsableSize;
1522 nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024;
1523
1524 if (!info->screen_base) {
1525 printk(KERN_ERR PFX "cannot ioremap FB base\n");
1526 goto err_out_free_base1;
1527 }
1528
1529 par->FbStart = info->screen_base;
1530
1531 #ifdef CONFIG_MTRR
1532 if (!nomtrr) {
1533 par->mtrr.vram = mtrr_add(nvidiafb_fix.smem_start,
1534 par->RamAmountKBytes * 1024,
1535 MTRR_TYPE_WRCOMB, 1);
1536 if (par->mtrr.vram < 0) {
1537 printk(KERN_ERR PFX "unable to setup MTRR\n");
1538 } else {
1539 par->mtrr.vram_valid = 1;
1540 /* let there be speed */
1541 printk(KERN_INFO PFX "MTRR set to ON\n");
1542 }
1543 }
1544 #endif /* CONFIG_MTRR */
1545
1546 info->fbops = &nvidia_fb_ops;
1547 info->fix = nvidiafb_fix;
1548
1549 if (nvidia_set_fbinfo(info) < 0) {
1550 printk(KERN_ERR PFX "error setting initial video mode\n");
1551 goto err_out_iounmap_fb;
1552 }
1553
1554 nvidia_save_vga(par, &par->SavedReg);
1555
1556 if (register_framebuffer(info) < 0) {
1557 printk(KERN_ERR PFX "error registering nVidia framebuffer\n");
1558 goto err_out_iounmap_fb;
1559 }
1560
1561 pci_set_drvdata(pd, info);
1562
1563 printk(KERN_INFO PFX
1564 "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n",
1565 info->fix.id,
1566 par->FbMapSize / (1024 * 1024), info->fix.smem_start);
1567 #ifdef CONFIG_PMAC_BACKLIGHT
1568 if (par->FlatPanel && _machine == _MACH_Pmac)
1569 register_backlight_controller(&nvidia_backlight_controller,
1570 par, "mnca");
1571 #endif
1572 NVTRACE_LEAVE();
1573 return 0;
1574
1575 err_out_iounmap_fb:
1576 iounmap(info->screen_base);
1577 err_out_free_base1:
1578 fb_destroy_modedb(info->monspecs.modedb);
1579 nvidia_delete_i2c_busses(par);
1580 iounmap(par->REGS);
1581 err_out_free_base0:
1582 pci_release_regions(pd);
1583 err_out_request:
1584 pci_disable_device(pd);
1585 err_out_enable:
1586 kfree(info->pixmap.addr);
1587 err_out_kfree:
1588 framebuffer_release(info);
1589 err_out:
1590 return -ENODEV;
1591 }
1592
1593 static void __exit nvidiafb_remove(struct pci_dev *pd)
1594 {
1595 struct fb_info *info = pci_get_drvdata(pd);
1596 struct nvidia_par *par = info->par;
1597
1598 NVTRACE_ENTER();
1599 if (!info)
1600 return;
1601
1602 unregister_framebuffer(info);
1603 #ifdef CONFIG_MTRR
1604 if (par->mtrr.vram_valid)
1605 mtrr_del(par->mtrr.vram, info->fix.smem_start,
1606 info->fix.smem_len);
1607 #endif /* CONFIG_MTRR */
1608
1609 iounmap(info->screen_base);
1610 fb_destroy_modedb(info->monspecs.modedb);
1611 nvidia_delete_i2c_busses(par);
1612 iounmap(par->REGS);
1613 pci_release_regions(pd);
1614 pci_disable_device(pd);
1615 kfree(info->pixmap.addr);
1616 framebuffer_release(info);
1617 pci_set_drvdata(pd, NULL);
1618 NVTRACE_LEAVE();
1619 }
1620
1621 /* ------------------------------------------------------------------------- *
1622 *
1623 * initialization
1624 *
1625 * ------------------------------------------------------------------------- */
1626
1627 #ifndef MODULE
1628 static int __devinit nvidiafb_setup(char *options)
1629 {
1630 char *this_opt;
1631
1632 NVTRACE_ENTER();
1633 if (!options || !*options)
1634 return 0;
1635
1636 while ((this_opt = strsep(&options, ",")) != NULL) {
1637 if (!strncmp(this_opt, "forceCRTC", 9)) {
1638 char *p;
1639
1640 p = this_opt + 9;
1641 if (!*p || !*(++p))
1642 continue;
1643 forceCRTC = *p - '0';
1644 if (forceCRTC < 0 || forceCRTC > 1)
1645 forceCRTC = -1;
1646 } else if (!strncmp(this_opt, "flatpanel", 9)) {
1647 flatpanel = 1;
1648 } else if (!strncmp(this_opt, "hwcur", 5)) {
1649 hwcur = 1;
1650 } else if (!strncmp(this_opt, "noaccel", 6)) {
1651 noaccel = 1;
1652 } else if (!strncmp(this_opt, "noscale", 7)) {
1653 noscale = 1;
1654 } else if (!strncmp(this_opt, "paneltweak:", 11)) {
1655 paneltweak = simple_strtoul(this_opt+11, NULL, 0);
1656 } else if (!strncmp(this_opt, "vram:", 5)) {
1657 vram = simple_strtoul(this_opt+5, NULL, 0);
1658 #ifdef CONFIG_MTRR
1659 } else if (!strncmp(this_opt, "nomtrr", 6)) {
1660 nomtrr = 1;
1661 #endif
1662 } else
1663 mode_option = this_opt;
1664 }
1665 NVTRACE_LEAVE();
1666 return 0;
1667 }
1668 #endif /* !MODULE */
1669
1670 static struct pci_driver nvidiafb_driver = {
1671 .name = "nvidiafb",
1672 .id_table = nvidiafb_pci_tbl,
1673 .probe = nvidiafb_probe,
1674 .remove = __exit_p(nvidiafb_remove),
1675 };
1676
1677 /* ------------------------------------------------------------------------- *
1678 *
1679 * modularization
1680 *
1681 * ------------------------------------------------------------------------- */
1682
1683 static int __devinit nvidiafb_init(void)
1684 {
1685 #ifndef MODULE
1686 char *option = NULL;
1687
1688 if (fb_get_options("nvidiafb", &option))
1689 return -ENODEV;
1690 nvidiafb_setup(option);
1691 #endif
1692 return pci_register_driver(&nvidiafb_driver);
1693 }
1694
1695 module_init(nvidiafb_init);
1696
1697 #ifdef MODULE
1698 static void __exit nvidiafb_exit(void)
1699 {
1700 pci_unregister_driver(&nvidiafb_driver);
1701 }
1702
1703 module_exit(nvidiafb_exit);
1704
1705 module_param(flatpanel, int, 0);
1706 MODULE_PARM_DESC(flatpanel,
1707 "Enables experimental flat panel support for some chipsets. "
1708 "(0 or 1=enabled) (default=0)");
1709 module_param(hwcur, int, 0);
1710 MODULE_PARM_DESC(hwcur,
1711 "Enables hardware cursor implementation. (0 or 1=enabled) "
1712 "(default=0)");
1713 module_param(noaccel, int, 0);
1714 MODULE_PARM_DESC(noaccel,
1715 "Disables hardware acceleration. (0 or 1=disable) "
1716 "(default=0)");
1717 module_param(noscale, int, 0);
1718 MODULE_PARM_DESC(noscale,
1719 "Disables screen scaleing. (0 or 1=disable) "
1720 "(default=0, do scaling)");
1721 module_param(paneltweak, int, 0);
1722 MODULE_PARM_DESC(paneltweak,
1723 "Tweak display settings for flatpanels. "
1724 "(default=0, no tweaks)");
1725 module_param(forceCRTC, int, 0);
1726 MODULE_PARM_DESC(forceCRTC,
1727 "Forces usage of a particular CRTC in case autodetection "
1728 "fails. (0 or 1) (default=autodetect)");
1729 module_param(vram, int, 0);
1730 MODULE_PARM_DESC(vram,
1731 "amount of framebuffer memory to remap in MiB"
1732 "(default=0 - remap entire memory)");
1733 #ifdef CONFIG_MTRR
1734 module_param(nomtrr, bool, 0);
1735 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) "
1736 "(default=0)");
1737 #endif
1738
1739 MODULE_AUTHOR("Antonino Daplas");
1740 MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset");
1741 MODULE_LICENSE("GPL");
1742 #endif /* MODULE */
1743
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