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r8169: split rtl8169_tso_csum
[linux-2.6/btrfs-unstable.git] / drivers / net / ethernet / realtek / r8169.c
blob6b7e21a8da57989d1e8f4f902939790a4e8865d4
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
29 #include <linux/prefetch.h>
30
31 #include <asm/io.h>
32 #include <asm/irq.h>
33
34 #define RTL8169_VERSION "2.3LK-NAPI"
35 #define MODULENAME "r8169"
36 #define PFX MODULENAME ": "
37
38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
53
54 #ifdef RTL8169_DEBUG
55 #define assert(expr) \
56 if (!(expr)) { \
57 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
58 #expr,__FILE__,__func__,__LINE__); \
59 }
60 #define dprintk(fmt, args...) \
61 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
62 #else
63 #define assert(expr) do {} while (0)
64 #define dprintk(fmt, args...) do {} while (0)
65 #endif /* RTL8169_DEBUG */
66
67 #define R8169_MSG_DEFAULT \
68 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
69
70 #define TX_SLOTS_AVAIL(tp) \
71 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
72
73 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
74 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
75 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
76
77 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
78 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
79 static const int multicast_filter_limit = 32;
80
81 #define MAX_READ_REQUEST_SHIFT 12
82 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
83 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
84
85 #define R8169_REGS_SIZE 256
86 #define R8169_NAPI_WEIGHT 64
87 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
88 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
89 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
90 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
91
92 #define RTL8169_TX_TIMEOUT (6*HZ)
93 #define RTL8169_PHY_TIMEOUT (10*HZ)
94
95 /* write/read MMIO register */
96 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
97 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
98 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
99 #define RTL_R8(reg) readb (ioaddr + (reg))
100 #define RTL_R16(reg) readw (ioaddr + (reg))
101 #define RTL_R32(reg) readl (ioaddr + (reg))
102
103 enum mac_version {
104 RTL_GIGA_MAC_VER_01 = 0,
105 RTL_GIGA_MAC_VER_02,
106 RTL_GIGA_MAC_VER_03,
107 RTL_GIGA_MAC_VER_04,
108 RTL_GIGA_MAC_VER_05,
109 RTL_GIGA_MAC_VER_06,
110 RTL_GIGA_MAC_VER_07,
111 RTL_GIGA_MAC_VER_08,
112 RTL_GIGA_MAC_VER_09,
113 RTL_GIGA_MAC_VER_10,
114 RTL_GIGA_MAC_VER_11,
115 RTL_GIGA_MAC_VER_12,
116 RTL_GIGA_MAC_VER_13,
117 RTL_GIGA_MAC_VER_14,
118 RTL_GIGA_MAC_VER_15,
119 RTL_GIGA_MAC_VER_16,
120 RTL_GIGA_MAC_VER_17,
121 RTL_GIGA_MAC_VER_18,
122 RTL_GIGA_MAC_VER_19,
123 RTL_GIGA_MAC_VER_20,
124 RTL_GIGA_MAC_VER_21,
125 RTL_GIGA_MAC_VER_22,
126 RTL_GIGA_MAC_VER_23,
127 RTL_GIGA_MAC_VER_24,
128 RTL_GIGA_MAC_VER_25,
129 RTL_GIGA_MAC_VER_26,
130 RTL_GIGA_MAC_VER_27,
131 RTL_GIGA_MAC_VER_28,
132 RTL_GIGA_MAC_VER_29,
133 RTL_GIGA_MAC_VER_30,
134 RTL_GIGA_MAC_VER_31,
135 RTL_GIGA_MAC_VER_32,
136 RTL_GIGA_MAC_VER_33,
137 RTL_GIGA_MAC_VER_34,
138 RTL_GIGA_MAC_VER_35,
139 RTL_GIGA_MAC_VER_36,
140 RTL_GIGA_MAC_VER_37,
141 RTL_GIGA_MAC_VER_38,
142 RTL_GIGA_MAC_VER_39,
143 RTL_GIGA_MAC_VER_40,
144 RTL_GIGA_MAC_VER_41,
145 RTL_GIGA_MAC_VER_42,
146 RTL_GIGA_MAC_VER_43,
147 RTL_GIGA_MAC_VER_44,
148 RTL_GIGA_MAC_NONE = 0xff,
149 };
150
151 enum rtl_tx_desc_version {
152 RTL_TD_0 = 0,
153 RTL_TD_1 = 1,
154 };
155
156 #define JUMBO_1K ETH_DATA_LEN
157 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
158 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
159 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
160 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
161
162 #define _R(NAME,TD,FW,SZ,B) { \
163 .name = NAME, \
164 .txd_version = TD, \
165 .fw_name = FW, \
166 .jumbo_max = SZ, \
167 .jumbo_tx_csum = B \
168 }
169
170 static const struct {
171 const char *name;
172 enum rtl_tx_desc_version txd_version;
173 const char *fw_name;
174 u16 jumbo_max;
175 bool jumbo_tx_csum;
176 } rtl_chip_infos[] = {
177 /* PCI devices. */
178 [RTL_GIGA_MAC_VER_01] =
179 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
180 [RTL_GIGA_MAC_VER_02] =
181 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
182 [RTL_GIGA_MAC_VER_03] =
183 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
184 [RTL_GIGA_MAC_VER_04] =
185 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
186 [RTL_GIGA_MAC_VER_05] =
187 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
188 [RTL_GIGA_MAC_VER_06] =
189 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
190 /* PCI-E devices. */
191 [RTL_GIGA_MAC_VER_07] =
192 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
193 [RTL_GIGA_MAC_VER_08] =
194 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
195 [RTL_GIGA_MAC_VER_09] =
196 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
197 [RTL_GIGA_MAC_VER_10] =
198 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
199 [RTL_GIGA_MAC_VER_11] =
200 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
201 [RTL_GIGA_MAC_VER_12] =
202 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
203 [RTL_GIGA_MAC_VER_13] =
204 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
205 [RTL_GIGA_MAC_VER_14] =
206 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
207 [RTL_GIGA_MAC_VER_15] =
208 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
209 [RTL_GIGA_MAC_VER_16] =
210 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
211 [RTL_GIGA_MAC_VER_17] =
212 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
213 [RTL_GIGA_MAC_VER_18] =
214 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
215 [RTL_GIGA_MAC_VER_19] =
216 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
217 [RTL_GIGA_MAC_VER_20] =
218 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
219 [RTL_GIGA_MAC_VER_21] =
220 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
221 [RTL_GIGA_MAC_VER_22] =
222 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
223 [RTL_GIGA_MAC_VER_23] =
224 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
225 [RTL_GIGA_MAC_VER_24] =
226 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
227 [RTL_GIGA_MAC_VER_25] =
228 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
229 JUMBO_9K, false),
230 [RTL_GIGA_MAC_VER_26] =
231 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
232 JUMBO_9K, false),
233 [RTL_GIGA_MAC_VER_27] =
234 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
235 [RTL_GIGA_MAC_VER_28] =
236 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
237 [RTL_GIGA_MAC_VER_29] =
238 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
239 JUMBO_1K, true),
240 [RTL_GIGA_MAC_VER_30] =
241 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
242 JUMBO_1K, true),
243 [RTL_GIGA_MAC_VER_31] =
244 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
245 [RTL_GIGA_MAC_VER_32] =
246 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
247 JUMBO_9K, false),
248 [RTL_GIGA_MAC_VER_33] =
249 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
250 JUMBO_9K, false),
251 [RTL_GIGA_MAC_VER_34] =
252 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
253 JUMBO_9K, false),
254 [RTL_GIGA_MAC_VER_35] =
255 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
256 JUMBO_9K, false),
257 [RTL_GIGA_MAC_VER_36] =
258 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
259 JUMBO_9K, false),
260 [RTL_GIGA_MAC_VER_37] =
261 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
262 JUMBO_1K, true),
263 [RTL_GIGA_MAC_VER_38] =
264 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
265 JUMBO_9K, false),
266 [RTL_GIGA_MAC_VER_39] =
267 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
268 JUMBO_1K, true),
269 [RTL_GIGA_MAC_VER_40] =
270 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
271 JUMBO_9K, false),
272 [RTL_GIGA_MAC_VER_41] =
273 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
274 [RTL_GIGA_MAC_VER_42] =
275 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
276 JUMBO_9K, false),
277 [RTL_GIGA_MAC_VER_43] =
278 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
279 JUMBO_1K, true),
280 [RTL_GIGA_MAC_VER_44] =
281 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
282 JUMBO_9K, false),
283 };
284 #undef _R
285
286 enum cfg_version {
287 RTL_CFG_0 = 0x00,
288 RTL_CFG_1,
289 RTL_CFG_2
290 };
291
292 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
293 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
294 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
295 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
296 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
297 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
298 { PCI_VENDOR_ID_DLINK, 0x4300,
299 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
300 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
301 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
302 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
303 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
304 { PCI_VENDOR_ID_LINKSYS, 0x1032,
305 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
306 { 0x0001, 0x8168,
307 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
308 {0,},
309 };
310
311 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
312
313 static int rx_buf_sz = 16383;
314 static int use_dac;
315 static struct {
316 u32 msg_enable;
317 } debug = { -1 };
318
319 enum rtl_registers {
320 MAC0 = 0, /* Ethernet hardware address. */
321 MAC4 = 4,
322 MAR0 = 8, /* Multicast filter. */
323 CounterAddrLow = 0x10,
324 CounterAddrHigh = 0x14,
325 TxDescStartAddrLow = 0x20,
326 TxDescStartAddrHigh = 0x24,
327 TxHDescStartAddrLow = 0x28,
328 TxHDescStartAddrHigh = 0x2c,
329 FLASH = 0x30,
330 ERSR = 0x36,
331 ChipCmd = 0x37,
332 TxPoll = 0x38,
333 IntrMask = 0x3c,
334 IntrStatus = 0x3e,
335
336 TxConfig = 0x40,
337 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
338 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
339
340 RxConfig = 0x44,
341 #define RX128_INT_EN (1 << 15) /* 8111c and later */
342 #define RX_MULTI_EN (1 << 14) /* 8111c only */
343 #define RXCFG_FIFO_SHIFT 13
344 /* No threshold before first PCI xfer */
345 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
346 #define RX_EARLY_OFF (1 << 11)
347 #define RXCFG_DMA_SHIFT 8
348 /* Unlimited maximum PCI burst. */
349 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
350
351 RxMissed = 0x4c,
352 Cfg9346 = 0x50,
353 Config0 = 0x51,
354 Config1 = 0x52,
355 Config2 = 0x53,
356 #define PME_SIGNAL (1 << 5) /* 8168c and later */
357
358 Config3 = 0x54,
359 Config4 = 0x55,
360 Config5 = 0x56,
361 MultiIntr = 0x5c,
362 PHYAR = 0x60,
363 PHYstatus = 0x6c,
364 RxMaxSize = 0xda,
365 CPlusCmd = 0xe0,
366 IntrMitigate = 0xe2,
367 RxDescAddrLow = 0xe4,
368 RxDescAddrHigh = 0xe8,
369 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
370
371 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
372
373 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
374
375 #define TxPacketMax (8064 >> 7)
376 #define EarlySize 0x27
377
378 FuncEvent = 0xf0,
379 FuncEventMask = 0xf4,
380 FuncPresetState = 0xf8,
381 FuncForceEvent = 0xfc,
382 };
383
384 enum rtl8110_registers {
385 TBICSR = 0x64,
386 TBI_ANAR = 0x68,
387 TBI_LPAR = 0x6a,
388 };
389
390 enum rtl8168_8101_registers {
391 CSIDR = 0x64,
392 CSIAR = 0x68,
393 #define CSIAR_FLAG 0x80000000
394 #define CSIAR_WRITE_CMD 0x80000000
395 #define CSIAR_BYTE_ENABLE 0x0f
396 #define CSIAR_BYTE_ENABLE_SHIFT 12
397 #define CSIAR_ADDR_MASK 0x0fff
398 #define CSIAR_FUNC_CARD 0x00000000
399 #define CSIAR_FUNC_SDIO 0x00010000
400 #define CSIAR_FUNC_NIC 0x00020000
401 #define CSIAR_FUNC_NIC2 0x00010000
402 PMCH = 0x6f,
403 EPHYAR = 0x80,
404 #define EPHYAR_FLAG 0x80000000
405 #define EPHYAR_WRITE_CMD 0x80000000
406 #define EPHYAR_REG_MASK 0x1f
407 #define EPHYAR_REG_SHIFT 16
408 #define EPHYAR_DATA_MASK 0xffff
409 DLLPR = 0xd0,
410 #define PFM_EN (1 << 6)
411 DBG_REG = 0xd1,
412 #define FIX_NAK_1 (1 << 4)
413 #define FIX_NAK_2 (1 << 3)
414 TWSI = 0xd2,
415 MCU = 0xd3,
416 #define NOW_IS_OOB (1 << 7)
417 #define TX_EMPTY (1 << 5)
418 #define RX_EMPTY (1 << 4)
419 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
420 #define EN_NDP (1 << 3)
421 #define EN_OOB_RESET (1 << 2)
422 #define LINK_LIST_RDY (1 << 1)
423 EFUSEAR = 0xdc,
424 #define EFUSEAR_FLAG 0x80000000
425 #define EFUSEAR_WRITE_CMD 0x80000000
426 #define EFUSEAR_READ_CMD 0x00000000
427 #define EFUSEAR_REG_MASK 0x03ff
428 #define EFUSEAR_REG_SHIFT 8
429 #define EFUSEAR_DATA_MASK 0xff
430 };
431
432 enum rtl8168_registers {
433 LED_FREQ = 0x1a,
434 EEE_LED = 0x1b,
435 ERIDR = 0x70,
436 ERIAR = 0x74,
437 #define ERIAR_FLAG 0x80000000
438 #define ERIAR_WRITE_CMD 0x80000000
439 #define ERIAR_READ_CMD 0x00000000
440 #define ERIAR_ADDR_BYTE_ALIGN 4
441 #define ERIAR_TYPE_SHIFT 16
442 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
443 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
444 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
445 #define ERIAR_MASK_SHIFT 12
446 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
447 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
448 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
449 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
450 EPHY_RXER_NUM = 0x7c,
451 OCPDR = 0xb0, /* OCP GPHY access */
452 #define OCPDR_WRITE_CMD 0x80000000
453 #define OCPDR_READ_CMD 0x00000000
454 #define OCPDR_REG_MASK 0x7f
455 #define OCPDR_GPHY_REG_SHIFT 16
456 #define OCPDR_DATA_MASK 0xffff
457 OCPAR = 0xb4,
458 #define OCPAR_FLAG 0x80000000
459 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
460 #define OCPAR_GPHY_READ_CMD 0x0000f060
461 GPHY_OCP = 0xb8,
462 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
463 MISC = 0xf0, /* 8168e only. */
464 #define TXPLA_RST (1 << 29)
465 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
466 #define PWM_EN (1 << 22)
467 #define RXDV_GATED_EN (1 << 19)
468 #define EARLY_TALLY_EN (1 << 16)
469 };
470
471 enum rtl_register_content {
472 /* InterruptStatusBits */
473 SYSErr = 0x8000,
474 PCSTimeout = 0x4000,
475 SWInt = 0x0100,
476 TxDescUnavail = 0x0080,
477 RxFIFOOver = 0x0040,
478 LinkChg = 0x0020,
479 RxOverflow = 0x0010,
480 TxErr = 0x0008,
481 TxOK = 0x0004,
482 RxErr = 0x0002,
483 RxOK = 0x0001,
484
485 /* RxStatusDesc */
486 RxBOVF = (1 << 24),
487 RxFOVF = (1 << 23),
488 RxRWT = (1 << 22),
489 RxRES = (1 << 21),
490 RxRUNT = (1 << 20),
491 RxCRC = (1 << 19),
492
493 /* ChipCmdBits */
494 StopReq = 0x80,
495 CmdReset = 0x10,
496 CmdRxEnb = 0x08,
497 CmdTxEnb = 0x04,
498 RxBufEmpty = 0x01,
499
500 /* TXPoll register p.5 */
501 HPQ = 0x80, /* Poll cmd on the high prio queue */
502 NPQ = 0x40, /* Poll cmd on the low prio queue */
503 FSWInt = 0x01, /* Forced software interrupt */
504
505 /* Cfg9346Bits */
506 Cfg9346_Lock = 0x00,
507 Cfg9346_Unlock = 0xc0,
508
509 /* rx_mode_bits */
510 AcceptErr = 0x20,
511 AcceptRunt = 0x10,
512 AcceptBroadcast = 0x08,
513 AcceptMulticast = 0x04,
514 AcceptMyPhys = 0x02,
515 AcceptAllPhys = 0x01,
516 #define RX_CONFIG_ACCEPT_MASK 0x3f
517
518 /* TxConfigBits */
519 TxInterFrameGapShift = 24,
520 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
521
522 /* Config1 register p.24 */
523 LEDS1 = (1 << 7),
524 LEDS0 = (1 << 6),
525 Speed_down = (1 << 4),
526 MEMMAP = (1 << 3),
527 IOMAP = (1 << 2),
528 VPD = (1 << 1),
529 PMEnable = (1 << 0), /* Power Management Enable */
530
531 /* Config2 register p. 25 */
532 ClkReqEn = (1 << 7), /* Clock Request Enable */
533 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
534 PCI_Clock_66MHz = 0x01,
535 PCI_Clock_33MHz = 0x00,
536
537 /* Config3 register p.25 */
538 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
539 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
540 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
541 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
542
543 /* Config4 register */
544 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
545
546 /* Config5 register p.27 */
547 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
548 MWF = (1 << 5), /* Accept Multicast wakeup frame */
549 UWF = (1 << 4), /* Accept Unicast wakeup frame */
550 Spi_en = (1 << 3),
551 LanWake = (1 << 1), /* LanWake enable/disable */
552 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
553 ASPM_en = (1 << 0), /* ASPM enable */
554
555 /* TBICSR p.28 */
556 TBIReset = 0x80000000,
557 TBILoopback = 0x40000000,
558 TBINwEnable = 0x20000000,
559 TBINwRestart = 0x10000000,
560 TBILinkOk = 0x02000000,
561 TBINwComplete = 0x01000000,
562
563 /* CPlusCmd p.31 */
564 EnableBist = (1 << 15), // 8168 8101
565 Mac_dbgo_oe = (1 << 14), // 8168 8101
566 Normal_mode = (1 << 13), // unused
567 Force_half_dup = (1 << 12), // 8168 8101
568 Force_rxflow_en = (1 << 11), // 8168 8101
569 Force_txflow_en = (1 << 10), // 8168 8101
570 Cxpl_dbg_sel = (1 << 9), // 8168 8101
571 ASF = (1 << 8), // 8168 8101
572 PktCntrDisable = (1 << 7), // 8168 8101
573 Mac_dbgo_sel = 0x001c, // 8168
574 RxVlan = (1 << 6),
575 RxChkSum = (1 << 5),
576 PCIDAC = (1 << 4),
577 PCIMulRW = (1 << 3),
578 INTT_0 = 0x0000, // 8168
579 INTT_1 = 0x0001, // 8168
580 INTT_2 = 0x0002, // 8168
581 INTT_3 = 0x0003, // 8168
582
583 /* rtl8169_PHYstatus */
584 TBI_Enable = 0x80,
585 TxFlowCtrl = 0x40,
586 RxFlowCtrl = 0x20,
587 _1000bpsF = 0x10,
588 _100bps = 0x08,
589 _10bps = 0x04,
590 LinkStatus = 0x02,
591 FullDup = 0x01,
592
593 /* _TBICSRBit */
594 TBILinkOK = 0x02000000,
595
596 /* DumpCounterCommand */
597 CounterDump = 0x8,
598 };
599
600 enum rtl_desc_bit {
601 /* First doubleword. */
602 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
603 RingEnd = (1 << 30), /* End of descriptor ring */
604 FirstFrag = (1 << 29), /* First segment of a packet */
605 LastFrag = (1 << 28), /* Final segment of a packet */
606 };
607
608 /* Generic case. */
609 enum rtl_tx_desc_bit {
610 /* First doubleword. */
611 TD_LSO = (1 << 27), /* Large Send Offload */
612 #define TD_MSS_MAX 0x07ffu /* MSS value */
613
614 /* Second doubleword. */
615 TxVlanTag = (1 << 17), /* Add VLAN tag */
616 };
617
618 /* 8169, 8168b and 810x except 8102e. */
619 enum rtl_tx_desc_bit_0 {
620 /* First doubleword. */
621 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
622 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
623 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
624 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
625 };
626
627 /* 8102e, 8168c and beyond. */
628 enum rtl_tx_desc_bit_1 {
629 /* Second doubleword. */
630 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
631 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
632 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
633 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
634 };
635
636 enum rtl_rx_desc_bit {
637 /* Rx private */
638 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
639 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
640
641 #define RxProtoUDP (PID1)
642 #define RxProtoTCP (PID0)
643 #define RxProtoIP (PID1 | PID0)
644 #define RxProtoMask RxProtoIP
645
646 IPFail = (1 << 16), /* IP checksum failed */
647 UDPFail = (1 << 15), /* UDP/IP checksum failed */
648 TCPFail = (1 << 14), /* TCP/IP checksum failed */
649 RxVlanTag = (1 << 16), /* VLAN tag available */
650 };
651
652 #define RsvdMask 0x3fffc000
653
654 struct TxDesc {
655 __le32 opts1;
656 __le32 opts2;
657 __le64 addr;
658 };
659
660 struct RxDesc {
661 __le32 opts1;
662 __le32 opts2;
663 __le64 addr;
664 };
665
666 struct ring_info {
667 struct sk_buff *skb;
668 u32 len;
669 u8 __pad[sizeof(void *) - sizeof(u32)];
670 };
671
672 enum features {
673 RTL_FEATURE_WOL = (1 << 0),
674 RTL_FEATURE_MSI = (1 << 1),
675 RTL_FEATURE_GMII = (1 << 2),
676 };
677
678 struct rtl8169_counters {
679 __le64 tx_packets;
680 __le64 rx_packets;
681 __le64 tx_errors;
682 __le32 rx_errors;
683 __le16 rx_missed;
684 __le16 align_errors;
685 __le32 tx_one_collision;
686 __le32 tx_multi_collision;
687 __le64 rx_unicast;
688 __le64 rx_broadcast;
689 __le32 rx_multicast;
690 __le16 tx_aborted;
691 __le16 tx_underun;
692 };
693
694 enum rtl_flag {
695 RTL_FLAG_TASK_ENABLED,
696 RTL_FLAG_TASK_SLOW_PENDING,
697 RTL_FLAG_TASK_RESET_PENDING,
698 RTL_FLAG_TASK_PHY_PENDING,
699 RTL_FLAG_MAX
700 };
701
702 struct rtl8169_stats {
703 u64 packets;
704 u64 bytes;
705 struct u64_stats_sync syncp;
706 };
707
708 struct rtl8169_private {
709 void __iomem *mmio_addr; /* memory map physical address */
710 struct pci_dev *pci_dev;
711 struct net_device *dev;
712 struct napi_struct napi;
713 u32 msg_enable;
714 u16 txd_version;
715 u16 mac_version;
716 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
717 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
718 u32 dirty_tx;
719 struct rtl8169_stats rx_stats;
720 struct rtl8169_stats tx_stats;
721 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
722 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
723 dma_addr_t TxPhyAddr;
724 dma_addr_t RxPhyAddr;
725 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
726 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
727 struct timer_list timer;
728 u16 cp_cmd;
729
730 u16 event_slow;
731
732 struct mdio_ops {
733 void (*write)(struct rtl8169_private *, int, int);
734 int (*read)(struct rtl8169_private *, int);
735 } mdio_ops;
736
737 struct pll_power_ops {
738 void (*down)(struct rtl8169_private *);
739 void (*up)(struct rtl8169_private *);
740 } pll_power_ops;
741
742 struct jumbo_ops {
743 void (*enable)(struct rtl8169_private *);
744 void (*disable)(struct rtl8169_private *);
745 } jumbo_ops;
746
747 struct csi_ops {
748 void (*write)(struct rtl8169_private *, int, int);
749 u32 (*read)(struct rtl8169_private *, int);
750 } csi_ops;
751
752 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
753 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
754 void (*phy_reset_enable)(struct rtl8169_private *tp);
755 void (*hw_start)(struct net_device *);
756 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
757 unsigned int (*link_ok)(void __iomem *);
758 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
759 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
760
761 struct {
762 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
763 struct mutex mutex;
764 struct work_struct work;
765 } wk;
766
767 unsigned features;
768
769 struct mii_if_info mii;
770 struct rtl8169_counters counters;
771 u32 saved_wolopts;
772 u32 opts1_mask;
773
774 struct rtl_fw {
775 const struct firmware *fw;
776
777 #define RTL_VER_SIZE 32
778
779 char version[RTL_VER_SIZE];
780
781 struct rtl_fw_phy_action {
782 __le32 *code;
783 size_t size;
784 } phy_action;
785 } *rtl_fw;
786 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
787
788 u32 ocp_base;
789 };
790
791 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
792 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
793 module_param(use_dac, int, 0);
794 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
795 module_param_named(debug, debug.msg_enable, int, 0);
796 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
797 MODULE_LICENSE("GPL");
798 MODULE_VERSION(RTL8169_VERSION);
799 MODULE_FIRMWARE(FIRMWARE_8168D_1);
800 MODULE_FIRMWARE(FIRMWARE_8168D_2);
801 MODULE_FIRMWARE(FIRMWARE_8168E_1);
802 MODULE_FIRMWARE(FIRMWARE_8168E_2);
803 MODULE_FIRMWARE(FIRMWARE_8168E_3);
804 MODULE_FIRMWARE(FIRMWARE_8105E_1);
805 MODULE_FIRMWARE(FIRMWARE_8168F_1);
806 MODULE_FIRMWARE(FIRMWARE_8168F_2);
807 MODULE_FIRMWARE(FIRMWARE_8402_1);
808 MODULE_FIRMWARE(FIRMWARE_8411_1);
809 MODULE_FIRMWARE(FIRMWARE_8411_2);
810 MODULE_FIRMWARE(FIRMWARE_8106E_1);
811 MODULE_FIRMWARE(FIRMWARE_8106E_2);
812 MODULE_FIRMWARE(FIRMWARE_8168G_2);
813 MODULE_FIRMWARE(FIRMWARE_8168G_3);
814
815 static void rtl_lock_work(struct rtl8169_private *tp)
816 {
817 mutex_lock(&tp->wk.mutex);
818 }
819
820 static void rtl_unlock_work(struct rtl8169_private *tp)
821 {
822 mutex_unlock(&tp->wk.mutex);
823 }
824
825 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
826 {
827 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
828 PCI_EXP_DEVCTL_READRQ, force);
829 }
830
831 struct rtl_cond {
832 bool (*check)(struct rtl8169_private *);
833 const char *msg;
834 };
835
836 static void rtl_udelay(unsigned int d)
837 {
838 udelay(d);
839 }
840
841 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
842 void (*delay)(unsigned int), unsigned int d, int n,
843 bool high)
844 {
845 int i;
846
847 for (i = 0; i < n; i++) {
848 delay(d);
849 if (c->check(tp) == high)
850 return true;
851 }
852 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
853 c->msg, !high, n, d);
854 return false;
855 }
856
857 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
858 const struct rtl_cond *c,
859 unsigned int d, int n)
860 {
861 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
862 }
863
864 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
865 const struct rtl_cond *c,
866 unsigned int d, int n)
867 {
868 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
869 }
870
871 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
872 const struct rtl_cond *c,
873 unsigned int d, int n)
874 {
875 return rtl_loop_wait(tp, c, msleep, d, n, true);
876 }
877
878 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
879 const struct rtl_cond *c,
880 unsigned int d, int n)
881 {
882 return rtl_loop_wait(tp, c, msleep, d, n, false);
883 }
884
885 #define DECLARE_RTL_COND(name) \
886 static bool name ## _check(struct rtl8169_private *); \
887 \
888 static const struct rtl_cond name = { \
889 .check = name ## _check, \
890 .msg = #name \
891 }; \
892 \
893 static bool name ## _check(struct rtl8169_private *tp)
894
895 DECLARE_RTL_COND(rtl_ocpar_cond)
896 {
897 void __iomem *ioaddr = tp->mmio_addr;
898
899 return RTL_R32(OCPAR) & OCPAR_FLAG;
900 }
901
902 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
903 {
904 void __iomem *ioaddr = tp->mmio_addr;
905
906 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
907
908 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
909 RTL_R32(OCPDR) : ~0;
910 }
911
912 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
913 {
914 void __iomem *ioaddr = tp->mmio_addr;
915
916 RTL_W32(OCPDR, data);
917 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
918
919 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
920 }
921
922 DECLARE_RTL_COND(rtl_eriar_cond)
923 {
924 void __iomem *ioaddr = tp->mmio_addr;
925
926 return RTL_R32(ERIAR) & ERIAR_FLAG;
927 }
928
929 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
930 {
931 void __iomem *ioaddr = tp->mmio_addr;
932
933 RTL_W8(ERIDR, cmd);
934 RTL_W32(ERIAR, 0x800010e8);
935 msleep(2);
936
937 if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
938 return;
939
940 ocp_write(tp, 0x1, 0x30, 0x00000001);
941 }
942
943 #define OOB_CMD_RESET 0x00
944 #define OOB_CMD_DRIVER_START 0x05
945 #define OOB_CMD_DRIVER_STOP 0x06
946
947 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
948 {
949 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
950 }
951
952 DECLARE_RTL_COND(rtl_ocp_read_cond)
953 {
954 u16 reg;
955
956 reg = rtl8168_get_ocp_reg(tp);
957
958 return ocp_read(tp, 0x0f, reg) & 0x00000800;
959 }
960
961 static void rtl8168_driver_start(struct rtl8169_private *tp)
962 {
963 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
964
965 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
966 }
967
968 static void rtl8168_driver_stop(struct rtl8169_private *tp)
969 {
970 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
971
972 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
973 }
974
975 static int r8168dp_check_dash(struct rtl8169_private *tp)
976 {
977 u16 reg = rtl8168_get_ocp_reg(tp);
978
979 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
980 }
981
982 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
983 {
984 if (reg & 0xffff0001) {
985 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
986 return true;
987 }
988 return false;
989 }
990
991 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
992 {
993 void __iomem *ioaddr = tp->mmio_addr;
994
995 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
996 }
997
998 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
999 {
1000 void __iomem *ioaddr = tp->mmio_addr;
1001
1002 if (rtl_ocp_reg_failure(tp, reg))
1003 return;
1004
1005 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1006
1007 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1008 }
1009
1010 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1011 {
1012 void __iomem *ioaddr = tp->mmio_addr;
1013
1014 if (rtl_ocp_reg_failure(tp, reg))
1015 return 0;
1016
1017 RTL_W32(GPHY_OCP, reg << 15);
1018
1019 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1020 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1021 }
1022
1023 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1024 {
1025 void __iomem *ioaddr = tp->mmio_addr;
1026
1027 if (rtl_ocp_reg_failure(tp, reg))
1028 return;
1029
1030 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1031 }
1032
1033 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1034 {
1035 void __iomem *ioaddr = tp->mmio_addr;
1036
1037 if (rtl_ocp_reg_failure(tp, reg))
1038 return 0;
1039
1040 RTL_W32(OCPDR, reg << 15);
1041
1042 return RTL_R32(OCPDR);
1043 }
1044
1045 #define OCP_STD_PHY_BASE 0xa400
1046
1047 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1048 {
1049 if (reg == 0x1f) {
1050 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1051 return;
1052 }
1053
1054 if (tp->ocp_base != OCP_STD_PHY_BASE)
1055 reg -= 0x10;
1056
1057 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1058 }
1059
1060 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1061 {
1062 if (tp->ocp_base != OCP_STD_PHY_BASE)
1063 reg -= 0x10;
1064
1065 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1066 }
1067
1068 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1069 {
1070 if (reg == 0x1f) {
1071 tp->ocp_base = value << 4;
1072 return;
1073 }
1074
1075 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1076 }
1077
1078 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1079 {
1080 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1081 }
1082
1083 DECLARE_RTL_COND(rtl_phyar_cond)
1084 {
1085 void __iomem *ioaddr = tp->mmio_addr;
1086
1087 return RTL_R32(PHYAR) & 0x80000000;
1088 }
1089
1090 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1091 {
1092 void __iomem *ioaddr = tp->mmio_addr;
1093
1094 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1095
1096 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1097 /*
1098 * According to hardware specs a 20us delay is required after write
1099 * complete indication, but before sending next command.
1100 */
1101 udelay(20);
1102 }
1103
1104 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1105 {
1106 void __iomem *ioaddr = tp->mmio_addr;
1107 int value;
1108
1109 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1110
1111 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1112 RTL_R32(PHYAR) & 0xffff : ~0;
1113
1114 /*
1115 * According to hardware specs a 20us delay is required after read
1116 * complete indication, but before sending next command.
1117 */
1118 udelay(20);
1119
1120 return value;
1121 }
1122
1123 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1124 {
1125 void __iomem *ioaddr = tp->mmio_addr;
1126
1127 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1128 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1129 RTL_W32(EPHY_RXER_NUM, 0);
1130
1131 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1132 }
1133
1134 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1135 {
1136 r8168dp_1_mdio_access(tp, reg,
1137 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1138 }
1139
1140 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1141 {
1142 void __iomem *ioaddr = tp->mmio_addr;
1143
1144 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1145
1146 mdelay(1);
1147 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1148 RTL_W32(EPHY_RXER_NUM, 0);
1149
1150 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1151 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1152 }
1153
1154 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1155
1156 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1157 {
1158 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1159 }
1160
1161 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1162 {
1163 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1164 }
1165
1166 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1167 {
1168 void __iomem *ioaddr = tp->mmio_addr;
1169
1170 r8168dp_2_mdio_start(ioaddr);
1171
1172 r8169_mdio_write(tp, reg, value);
1173
1174 r8168dp_2_mdio_stop(ioaddr);
1175 }
1176
1177 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1178 {
1179 void __iomem *ioaddr = tp->mmio_addr;
1180 int value;
1181
1182 r8168dp_2_mdio_start(ioaddr);
1183
1184 value = r8169_mdio_read(tp, reg);
1185
1186 r8168dp_2_mdio_stop(ioaddr);
1187
1188 return value;
1189 }
1190
1191 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1192 {
1193 tp->mdio_ops.write(tp, location, val);
1194 }
1195
1196 static int rtl_readphy(struct rtl8169_private *tp, int location)
1197 {
1198 return tp->mdio_ops.read(tp, location);
1199 }
1200
1201 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1202 {
1203 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1204 }
1205
1206 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1207 {
1208 int val;
1209
1210 val = rtl_readphy(tp, reg_addr);
1211 rtl_writephy(tp, reg_addr, (val | p) & ~m);
1212 }
1213
1214 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1215 int val)
1216 {
1217 struct rtl8169_private *tp = netdev_priv(dev);
1218
1219 rtl_writephy(tp, location, val);
1220 }
1221
1222 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1223 {
1224 struct rtl8169_private *tp = netdev_priv(dev);
1225
1226 return rtl_readphy(tp, location);
1227 }
1228
1229 DECLARE_RTL_COND(rtl_ephyar_cond)
1230 {
1231 void __iomem *ioaddr = tp->mmio_addr;
1232
1233 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1234 }
1235
1236 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1237 {
1238 void __iomem *ioaddr = tp->mmio_addr;
1239
1240 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1241 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1242
1243 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1244
1245 udelay(10);
1246 }
1247
1248 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1249 {
1250 void __iomem *ioaddr = tp->mmio_addr;
1251
1252 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1253
1254 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1255 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1256 }
1257
1258 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1259 u32 val, int type)
1260 {
1261 void __iomem *ioaddr = tp->mmio_addr;
1262
1263 BUG_ON((addr & 3) || (mask == 0));
1264 RTL_W32(ERIDR, val);
1265 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1266
1267 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1268 }
1269
1270 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1271 {
1272 void __iomem *ioaddr = tp->mmio_addr;
1273
1274 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1275
1276 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1277 RTL_R32(ERIDR) : ~0;
1278 }
1279
1280 static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1281 u32 m, int type)
1282 {
1283 u32 val;
1284
1285 val = rtl_eri_read(tp, addr, type);
1286 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1287 }
1288
1289 struct exgmac_reg {
1290 u16 addr;
1291 u16 mask;
1292 u32 val;
1293 };
1294
1295 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1296 const struct exgmac_reg *r, int len)
1297 {
1298 while (len-- > 0) {
1299 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1300 r++;
1301 }
1302 }
1303
1304 DECLARE_RTL_COND(rtl_efusear_cond)
1305 {
1306 void __iomem *ioaddr = tp->mmio_addr;
1307
1308 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1309 }
1310
1311 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1312 {
1313 void __iomem *ioaddr = tp->mmio_addr;
1314
1315 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1316
1317 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1318 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1319 }
1320
1321 static u16 rtl_get_events(struct rtl8169_private *tp)
1322 {
1323 void __iomem *ioaddr = tp->mmio_addr;
1324
1325 return RTL_R16(IntrStatus);
1326 }
1327
1328 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1329 {
1330 void __iomem *ioaddr = tp->mmio_addr;
1331
1332 RTL_W16(IntrStatus, bits);
1333 mmiowb();
1334 }
1335
1336 static void rtl_irq_disable(struct rtl8169_private *tp)
1337 {
1338 void __iomem *ioaddr = tp->mmio_addr;
1339
1340 RTL_W16(IntrMask, 0);
1341 mmiowb();
1342 }
1343
1344 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1345 {
1346 void __iomem *ioaddr = tp->mmio_addr;
1347
1348 RTL_W16(IntrMask, bits);
1349 }
1350
1351 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1352 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1353 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1354
1355 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1356 {
1357 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1358 }
1359
1360 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1361 {
1362 void __iomem *ioaddr = tp->mmio_addr;
1363
1364 rtl_irq_disable(tp);
1365 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1366 RTL_R8(ChipCmd);
1367 }
1368
1369 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1370 {
1371 void __iomem *ioaddr = tp->mmio_addr;
1372
1373 return RTL_R32(TBICSR) & TBIReset;
1374 }
1375
1376 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1377 {
1378 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1379 }
1380
1381 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1382 {
1383 return RTL_R32(TBICSR) & TBILinkOk;
1384 }
1385
1386 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1387 {
1388 return RTL_R8(PHYstatus) & LinkStatus;
1389 }
1390
1391 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1392 {
1393 void __iomem *ioaddr = tp->mmio_addr;
1394
1395 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1396 }
1397
1398 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1399 {
1400 unsigned int val;
1401
1402 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1403 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1404 }
1405
1406 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1407 {
1408 void __iomem *ioaddr = tp->mmio_addr;
1409 struct net_device *dev = tp->dev;
1410
1411 if (!netif_running(dev))
1412 return;
1413
1414 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1415 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1416 if (RTL_R8(PHYstatus) & _1000bpsF) {
1417 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1418 ERIAR_EXGMAC);
1419 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1420 ERIAR_EXGMAC);
1421 } else if (RTL_R8(PHYstatus) & _100bps) {
1422 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1423 ERIAR_EXGMAC);
1424 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1425 ERIAR_EXGMAC);
1426 } else {
1427 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1428 ERIAR_EXGMAC);
1429 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1430 ERIAR_EXGMAC);
1431 }
1432 /* Reset packet filter */
1433 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1434 ERIAR_EXGMAC);
1435 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1436 ERIAR_EXGMAC);
1437 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1438 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1439 if (RTL_R8(PHYstatus) & _1000bpsF) {
1440 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1441 ERIAR_EXGMAC);
1442 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1443 ERIAR_EXGMAC);
1444 } else {
1445 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1446 ERIAR_EXGMAC);
1447 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1448 ERIAR_EXGMAC);
1449 }
1450 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1451 if (RTL_R8(PHYstatus) & _10bps) {
1452 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1453 ERIAR_EXGMAC);
1454 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1455 ERIAR_EXGMAC);
1456 } else {
1457 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1458 ERIAR_EXGMAC);
1459 }
1460 }
1461 }
1462
1463 static void __rtl8169_check_link_status(struct net_device *dev,
1464 struct rtl8169_private *tp,
1465 void __iomem *ioaddr, bool pm)
1466 {
1467 if (tp->link_ok(ioaddr)) {
1468 rtl_link_chg_patch(tp);
1469 /* This is to cancel a scheduled suspend if there's one. */
1470 if (pm)
1471 pm_request_resume(&tp->pci_dev->dev);
1472 netif_carrier_on(dev);
1473 if (net_ratelimit())
1474 netif_info(tp, ifup, dev, "link up\n");
1475 } else {
1476 netif_carrier_off(dev);
1477 netif_info(tp, ifdown, dev, "link down\n");
1478 if (pm)
1479 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1480 }
1481 }
1482
1483 static void rtl8169_check_link_status(struct net_device *dev,
1484 struct rtl8169_private *tp,
1485 void __iomem *ioaddr)
1486 {
1487 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1488 }
1489
1490 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1491
1492 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1493 {
1494 void __iomem *ioaddr = tp->mmio_addr;
1495 u8 options;
1496 u32 wolopts = 0;
1497
1498 options = RTL_R8(Config1);
1499 if (!(options & PMEnable))
1500 return 0;
1501
1502 options = RTL_R8(Config3);
1503 if (options & LinkUp)
1504 wolopts |= WAKE_PHY;
1505 if (options & MagicPacket)
1506 wolopts |= WAKE_MAGIC;
1507
1508 options = RTL_R8(Config5);
1509 if (options & UWF)
1510 wolopts |= WAKE_UCAST;
1511 if (options & BWF)
1512 wolopts |= WAKE_BCAST;
1513 if (options & MWF)
1514 wolopts |= WAKE_MCAST;
1515
1516 return wolopts;
1517 }
1518
1519 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1520 {
1521 struct rtl8169_private *tp = netdev_priv(dev);
1522
1523 rtl_lock_work(tp);
1524
1525 wol->supported = WAKE_ANY;
1526 wol->wolopts = __rtl8169_get_wol(tp);
1527
1528 rtl_unlock_work(tp);
1529 }
1530
1531 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1532 {
1533 void __iomem *ioaddr = tp->mmio_addr;
1534 unsigned int i;
1535 static const struct {
1536 u32 opt;
1537 u16 reg;
1538 u8 mask;
1539 } cfg[] = {
1540 { WAKE_PHY, Config3, LinkUp },
1541 { WAKE_MAGIC, Config3, MagicPacket },
1542 { WAKE_UCAST, Config5, UWF },
1543 { WAKE_BCAST, Config5, BWF },
1544 { WAKE_MCAST, Config5, MWF },
1545 { WAKE_ANY, Config5, LanWake }
1546 };
1547 u8 options;
1548
1549 RTL_W8(Cfg9346, Cfg9346_Unlock);
1550
1551 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1552 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1553 if (wolopts & cfg[i].opt)
1554 options |= cfg[i].mask;
1555 RTL_W8(cfg[i].reg, options);
1556 }
1557
1558 switch (tp->mac_version) {
1559 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1560 options = RTL_R8(Config1) & ~PMEnable;
1561 if (wolopts)
1562 options |= PMEnable;
1563 RTL_W8(Config1, options);
1564 break;
1565 default:
1566 options = RTL_R8(Config2) & ~PME_SIGNAL;
1567 if (wolopts)
1568 options |= PME_SIGNAL;
1569 RTL_W8(Config2, options);
1570 break;
1571 }
1572
1573 RTL_W8(Cfg9346, Cfg9346_Lock);
1574 }
1575
1576 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1577 {
1578 struct rtl8169_private *tp = netdev_priv(dev);
1579
1580 rtl_lock_work(tp);
1581
1582 if (wol->wolopts)
1583 tp->features |= RTL_FEATURE_WOL;
1584 else
1585 tp->features &= ~RTL_FEATURE_WOL;
1586 __rtl8169_set_wol(tp, wol->wolopts);
1587
1588 rtl_unlock_work(tp);
1589
1590 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1591
1592 return 0;
1593 }
1594
1595 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1596 {
1597 return rtl_chip_infos[tp->mac_version].fw_name;
1598 }
1599
1600 static void rtl8169_get_drvinfo(struct net_device *dev,
1601 struct ethtool_drvinfo *info)
1602 {
1603 struct rtl8169_private *tp = netdev_priv(dev);
1604 struct rtl_fw *rtl_fw = tp->rtl_fw;
1605
1606 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1607 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1608 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1609 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1610 if (!IS_ERR_OR_NULL(rtl_fw))
1611 strlcpy(info->fw_version, rtl_fw->version,
1612 sizeof(info->fw_version));
1613 }
1614
1615 static int rtl8169_get_regs_len(struct net_device *dev)
1616 {
1617 return R8169_REGS_SIZE;
1618 }
1619
1620 static int rtl8169_set_speed_tbi(struct net_device *dev,
1621 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1622 {
1623 struct rtl8169_private *tp = netdev_priv(dev);
1624 void __iomem *ioaddr = tp->mmio_addr;
1625 int ret = 0;
1626 u32 reg;
1627
1628 reg = RTL_R32(TBICSR);
1629 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1630 (duplex == DUPLEX_FULL)) {
1631 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1632 } else if (autoneg == AUTONEG_ENABLE)
1633 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1634 else {
1635 netif_warn(tp, link, dev,
1636 "incorrect speed setting refused in TBI mode\n");
1637 ret = -EOPNOTSUPP;
1638 }
1639
1640 return ret;
1641 }
1642
1643 static int rtl8169_set_speed_xmii(struct net_device *dev,
1644 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1645 {
1646 struct rtl8169_private *tp = netdev_priv(dev);
1647 int giga_ctrl, bmcr;
1648 int rc = -EINVAL;
1649
1650 rtl_writephy(tp, 0x1f, 0x0000);
1651
1652 if (autoneg == AUTONEG_ENABLE) {
1653 int auto_nego;
1654
1655 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1656 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1657 ADVERTISE_100HALF | ADVERTISE_100FULL);
1658
1659 if (adv & ADVERTISED_10baseT_Half)
1660 auto_nego |= ADVERTISE_10HALF;
1661 if (adv & ADVERTISED_10baseT_Full)
1662 auto_nego |= ADVERTISE_10FULL;
1663 if (adv & ADVERTISED_100baseT_Half)
1664 auto_nego |= ADVERTISE_100HALF;
1665 if (adv & ADVERTISED_100baseT_Full)
1666 auto_nego |= ADVERTISE_100FULL;
1667
1668 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1669
1670 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1671 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1672
1673 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1674 if (tp->mii.supports_gmii) {
1675 if (adv & ADVERTISED_1000baseT_Half)
1676 giga_ctrl |= ADVERTISE_1000HALF;
1677 if (adv & ADVERTISED_1000baseT_Full)
1678 giga_ctrl |= ADVERTISE_1000FULL;
1679 } else if (adv & (ADVERTISED_1000baseT_Half |
1680 ADVERTISED_1000baseT_Full)) {
1681 netif_info(tp, link, dev,
1682 "PHY does not support 1000Mbps\n");
1683 goto out;
1684 }
1685
1686 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1687
1688 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1689 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1690 } else {
1691 giga_ctrl = 0;
1692
1693 if (speed == SPEED_10)
1694 bmcr = 0;
1695 else if (speed == SPEED_100)
1696 bmcr = BMCR_SPEED100;
1697 else
1698 goto out;
1699
1700 if (duplex == DUPLEX_FULL)
1701 bmcr |= BMCR_FULLDPLX;
1702 }
1703
1704 rtl_writephy(tp, MII_BMCR, bmcr);
1705
1706 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1707 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1708 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1709 rtl_writephy(tp, 0x17, 0x2138);
1710 rtl_writephy(tp, 0x0e, 0x0260);
1711 } else {
1712 rtl_writephy(tp, 0x17, 0x2108);
1713 rtl_writephy(tp, 0x0e, 0x0000);
1714 }
1715 }
1716
1717 rc = 0;
1718 out:
1719 return rc;
1720 }
1721
1722 static int rtl8169_set_speed(struct net_device *dev,
1723 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1724 {
1725 struct rtl8169_private *tp = netdev_priv(dev);
1726 int ret;
1727
1728 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1729 if (ret < 0)
1730 goto out;
1731
1732 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1733 (advertising & ADVERTISED_1000baseT_Full)) {
1734 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1735 }
1736 out:
1737 return ret;
1738 }
1739
1740 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1741 {
1742 struct rtl8169_private *tp = netdev_priv(dev);
1743 int ret;
1744
1745 del_timer_sync(&tp->timer);
1746
1747 rtl_lock_work(tp);
1748 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1749 cmd->duplex, cmd->advertising);
1750 rtl_unlock_work(tp);
1751
1752 return ret;
1753 }
1754
1755 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1756 netdev_features_t features)
1757 {
1758 struct rtl8169_private *tp = netdev_priv(dev);
1759
1760 if (dev->mtu > TD_MSS_MAX)
1761 features &= ~NETIF_F_ALL_TSO;
1762
1763 if (dev->mtu > JUMBO_1K &&
1764 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1765 features &= ~NETIF_F_IP_CSUM;
1766
1767 return features;
1768 }
1769
1770 static void __rtl8169_set_features(struct net_device *dev,
1771 netdev_features_t features)
1772 {
1773 struct rtl8169_private *tp = netdev_priv(dev);
1774 netdev_features_t changed = features ^ dev->features;
1775 void __iomem *ioaddr = tp->mmio_addr;
1776
1777 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM |
1778 NETIF_F_HW_VLAN_CTAG_RX)))
1779 return;
1780
1781 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX)) {
1782 if (features & NETIF_F_RXCSUM)
1783 tp->cp_cmd |= RxChkSum;
1784 else
1785 tp->cp_cmd &= ~RxChkSum;
1786
1787 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
1788 tp->cp_cmd |= RxVlan;
1789 else
1790 tp->cp_cmd &= ~RxVlan;
1791
1792 RTL_W16(CPlusCmd, tp->cp_cmd);
1793 RTL_R16(CPlusCmd);
1794 }
1795 if (changed & NETIF_F_RXALL) {
1796 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1797 if (features & NETIF_F_RXALL)
1798 tmp |= (AcceptErr | AcceptRunt);
1799 RTL_W32(RxConfig, tmp);
1800 }
1801 }
1802
1803 static int rtl8169_set_features(struct net_device *dev,
1804 netdev_features_t features)
1805 {
1806 struct rtl8169_private *tp = netdev_priv(dev);
1807
1808 rtl_lock_work(tp);
1809 __rtl8169_set_features(dev, features);
1810 rtl_unlock_work(tp);
1811
1812 return 0;
1813 }
1814
1815
1816 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1817 {
1818 return (vlan_tx_tag_present(skb)) ?
1819 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1820 }
1821
1822 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1823 {
1824 u32 opts2 = le32_to_cpu(desc->opts2);
1825
1826 if (opts2 & RxVlanTag)
1827 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1828 }
1829
1830 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1831 {
1832 struct rtl8169_private *tp = netdev_priv(dev);
1833 void __iomem *ioaddr = tp->mmio_addr;
1834 u32 status;
1835
1836 cmd->supported =
1837 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1838 cmd->port = PORT_FIBRE;
1839 cmd->transceiver = XCVR_INTERNAL;
1840
1841 status = RTL_R32(TBICSR);
1842 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1843 cmd->autoneg = !!(status & TBINwEnable);
1844
1845 ethtool_cmd_speed_set(cmd, SPEED_1000);
1846 cmd->duplex = DUPLEX_FULL; /* Always set */
1847
1848 return 0;
1849 }
1850
1851 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1852 {
1853 struct rtl8169_private *tp = netdev_priv(dev);
1854
1855 return mii_ethtool_gset(&tp->mii, cmd);
1856 }
1857
1858 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1859 {
1860 struct rtl8169_private *tp = netdev_priv(dev);
1861 int rc;
1862
1863 rtl_lock_work(tp);
1864 rc = tp->get_settings(dev, cmd);
1865 rtl_unlock_work(tp);
1866
1867 return rc;
1868 }
1869
1870 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1871 void *p)
1872 {
1873 struct rtl8169_private *tp = netdev_priv(dev);
1874 u32 __iomem *data = tp->mmio_addr;
1875 u32 *dw = p;
1876 int i;
1877
1878 rtl_lock_work(tp);
1879 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1880 memcpy_fromio(dw++, data++, 4);
1881 rtl_unlock_work(tp);
1882 }
1883
1884 static u32 rtl8169_get_msglevel(struct net_device *dev)
1885 {
1886 struct rtl8169_private *tp = netdev_priv(dev);
1887
1888 return tp->msg_enable;
1889 }
1890
1891 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1892 {
1893 struct rtl8169_private *tp = netdev_priv(dev);
1894
1895 tp->msg_enable = value;
1896 }
1897
1898 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1899 "tx_packets",
1900 "rx_packets",
1901 "tx_errors",
1902 "rx_errors",
1903 "rx_missed",
1904 "align_errors",
1905 "tx_single_collisions",
1906 "tx_multi_collisions",
1907 "unicast",
1908 "broadcast",
1909 "multicast",
1910 "tx_aborted",
1911 "tx_underrun",
1912 };
1913
1914 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1915 {
1916 switch (sset) {
1917 case ETH_SS_STATS:
1918 return ARRAY_SIZE(rtl8169_gstrings);
1919 default:
1920 return -EOPNOTSUPP;
1921 }
1922 }
1923
1924 DECLARE_RTL_COND(rtl_counters_cond)
1925 {
1926 void __iomem *ioaddr = tp->mmio_addr;
1927
1928 return RTL_R32(CounterAddrLow) & CounterDump;
1929 }
1930
1931 static void rtl8169_update_counters(struct net_device *dev)
1932 {
1933 struct rtl8169_private *tp = netdev_priv(dev);
1934 void __iomem *ioaddr = tp->mmio_addr;
1935 struct device *d = &tp->pci_dev->dev;
1936 struct rtl8169_counters *counters;
1937 dma_addr_t paddr;
1938 u32 cmd;
1939
1940 /*
1941 * Some chips are unable to dump tally counters when the receiver
1942 * is disabled.
1943 */
1944 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1945 return;
1946
1947 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1948 if (!counters)
1949 return;
1950
1951 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1952 cmd = (u64)paddr & DMA_BIT_MASK(32);
1953 RTL_W32(CounterAddrLow, cmd);
1954 RTL_W32(CounterAddrLow, cmd | CounterDump);
1955
1956 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1957 memcpy(&tp->counters, counters, sizeof(*counters));
1958
1959 RTL_W32(CounterAddrLow, 0);
1960 RTL_W32(CounterAddrHigh, 0);
1961
1962 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1963 }
1964
1965 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1966 struct ethtool_stats *stats, u64 *data)
1967 {
1968 struct rtl8169_private *tp = netdev_priv(dev);
1969
1970 ASSERT_RTNL();
1971
1972 rtl8169_update_counters(dev);
1973
1974 data[0] = le64_to_cpu(tp->counters.tx_packets);
1975 data[1] = le64_to_cpu(tp->counters.rx_packets);
1976 data[2] = le64_to_cpu(tp->counters.tx_errors);
1977 data[3] = le32_to_cpu(tp->counters.rx_errors);
1978 data[4] = le16_to_cpu(tp->counters.rx_missed);
1979 data[5] = le16_to_cpu(tp->counters.align_errors);
1980 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1981 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1982 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1983 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1984 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1985 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1986 data[12] = le16_to_cpu(tp->counters.tx_underun);
1987 }
1988
1989 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1990 {
1991 switch(stringset) {
1992 case ETH_SS_STATS:
1993 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1994 break;
1995 }
1996 }
1997
1998 static const struct ethtool_ops rtl8169_ethtool_ops = {
1999 .get_drvinfo = rtl8169_get_drvinfo,
2000 .get_regs_len = rtl8169_get_regs_len,
2001 .get_link = ethtool_op_get_link,
2002 .get_settings = rtl8169_get_settings,
2003 .set_settings = rtl8169_set_settings,
2004 .get_msglevel = rtl8169_get_msglevel,
2005 .set_msglevel = rtl8169_set_msglevel,
2006 .get_regs = rtl8169_get_regs,
2007 .get_wol = rtl8169_get_wol,
2008 .set_wol = rtl8169_set_wol,
2009 .get_strings = rtl8169_get_strings,
2010 .get_sset_count = rtl8169_get_sset_count,
2011 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2012 .get_ts_info = ethtool_op_get_ts_info,
2013 };
2014
2015 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2016 struct net_device *dev, u8 default_version)
2017 {
2018 void __iomem *ioaddr = tp->mmio_addr;
2019 /*
2020 * The driver currently handles the 8168Bf and the 8168Be identically
2021 * but they can be identified more specifically through the test below
2022 * if needed:
2023 *
2024 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2025 *
2026 * Same thing for the 8101Eb and the 8101Ec:
2027 *
2028 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2029 */
2030 static const struct rtl_mac_info {
2031 u32 mask;
2032 u32 val;
2033 int mac_version;
2034 } mac_info[] = {
2035 /* 8168G family. */
2036 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
2037 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
2038 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2039 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2040
2041 /* 8168F family. */
2042 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
2043 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2044 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2045
2046 /* 8168E family. */
2047 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
2048 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2049 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2050 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2051
2052 /* 8168D family. */
2053 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2054 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
2055 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
2056
2057 /* 8168DP family. */
2058 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2059 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
2060 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
2061
2062 /* 8168C family. */
2063 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
2064 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
2065 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
2066 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
2067 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2068 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
2069 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
2070 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
2071 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
2072
2073 /* 8168B family. */
2074 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2075 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2076 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2077 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2078
2079 /* 8101 family. */
2080 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2081 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
2082 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
2083 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
2084 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2085 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2086 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2087 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2088 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2089 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2090 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2091 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2092 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
2093 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2094 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
2095 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2096 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2097 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
2098 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2099 /* FIXME: where did these entries come from ? -- FR */
2100 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2101 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2102
2103 /* 8110 family. */
2104 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2105 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2106 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2107 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2108 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2109 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2110
2111 /* Catch-all */
2112 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
2113 };
2114 const struct rtl_mac_info *p = mac_info;
2115 u32 reg;
2116
2117 reg = RTL_R32(TxConfig);
2118 while ((reg & p->mask) != p->val)
2119 p++;
2120 tp->mac_version = p->mac_version;
2121
2122 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2123 netif_notice(tp, probe, dev,
2124 "unknown MAC, using family default\n");
2125 tp->mac_version = default_version;
2126 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2127 tp->mac_version = tp->mii.supports_gmii ?
2128 RTL_GIGA_MAC_VER_42 :
2129 RTL_GIGA_MAC_VER_43;
2130 }
2131 }
2132
2133 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2134 {
2135 dprintk("mac_version = 0x%02x\n", tp->mac_version);
2136 }
2137
2138 struct phy_reg {
2139 u16 reg;
2140 u16 val;
2141 };
2142
2143 static void rtl_writephy_batch(struct rtl8169_private *tp,
2144 const struct phy_reg *regs, int len)
2145 {
2146 while (len-- > 0) {
2147 rtl_writephy(tp, regs->reg, regs->val);
2148 regs++;
2149 }
2150 }
2151
2152 #define PHY_READ 0x00000000
2153 #define PHY_DATA_OR 0x10000000
2154 #define PHY_DATA_AND 0x20000000
2155 #define PHY_BJMPN 0x30000000
2156 #define PHY_MDIO_CHG 0x40000000
2157 #define PHY_CLEAR_READCOUNT 0x70000000
2158 #define PHY_WRITE 0x80000000
2159 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2160 #define PHY_COMP_EQ_SKIPN 0xa0000000
2161 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2162 #define PHY_WRITE_PREVIOUS 0xc0000000
2163 #define PHY_SKIPN 0xd0000000
2164 #define PHY_DELAY_MS 0xe0000000
2165
2166 struct fw_info {
2167 u32 magic;
2168 char version[RTL_VER_SIZE];
2169 __le32 fw_start;
2170 __le32 fw_len;
2171 u8 chksum;
2172 } __packed;
2173
2174 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2175
2176 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2177 {
2178 const struct firmware *fw = rtl_fw->fw;
2179 struct fw_info *fw_info = (struct fw_info *)fw->data;
2180 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2181 char *version = rtl_fw->version;
2182 bool rc = false;
2183
2184 if (fw->size < FW_OPCODE_SIZE)
2185 goto out;
2186
2187 if (!fw_info->magic) {
2188 size_t i, size, start;
2189 u8 checksum = 0;
2190
2191 if (fw->size < sizeof(*fw_info))
2192 goto out;
2193
2194 for (i = 0; i < fw->size; i++)
2195 checksum += fw->data[i];
2196 if (checksum != 0)
2197 goto out;
2198
2199 start = le32_to_cpu(fw_info->fw_start);
2200 if (start > fw->size)
2201 goto out;
2202
2203 size = le32_to_cpu(fw_info->fw_len);
2204 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2205 goto out;
2206
2207 memcpy(version, fw_info->version, RTL_VER_SIZE);
2208
2209 pa->code = (__le32 *)(fw->data + start);
2210 pa->size = size;
2211 } else {
2212 if (fw->size % FW_OPCODE_SIZE)
2213 goto out;
2214
2215 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2216
2217 pa->code = (__le32 *)fw->data;
2218 pa->size = fw->size / FW_OPCODE_SIZE;
2219 }
2220 version[RTL_VER_SIZE - 1] = 0;
2221
2222 rc = true;
2223 out:
2224 return rc;
2225 }
2226
2227 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2228 struct rtl_fw_phy_action *pa)
2229 {
2230 bool rc = false;
2231 size_t index;
2232
2233 for (index = 0; index < pa->size; index++) {
2234 u32 action = le32_to_cpu(pa->code[index]);
2235 u32 regno = (action & 0x0fff0000) >> 16;
2236
2237 switch(action & 0xf0000000) {
2238 case PHY_READ:
2239 case PHY_DATA_OR:
2240 case PHY_DATA_AND:
2241 case PHY_MDIO_CHG:
2242 case PHY_CLEAR_READCOUNT:
2243 case PHY_WRITE:
2244 case PHY_WRITE_PREVIOUS:
2245 case PHY_DELAY_MS:
2246 break;
2247
2248 case PHY_BJMPN:
2249 if (regno > index) {
2250 netif_err(tp, ifup, tp->dev,
2251 "Out of range of firmware\n");
2252 goto out;
2253 }
2254 break;
2255 case PHY_READCOUNT_EQ_SKIP:
2256 if (index + 2 >= pa->size) {
2257 netif_err(tp, ifup, tp->dev,
2258 "Out of range of firmware\n");
2259 goto out;
2260 }
2261 break;
2262 case PHY_COMP_EQ_SKIPN:
2263 case PHY_COMP_NEQ_SKIPN:
2264 case PHY_SKIPN:
2265 if (index + 1 + regno >= pa->size) {
2266 netif_err(tp, ifup, tp->dev,
2267 "Out of range of firmware\n");
2268 goto out;
2269 }
2270 break;
2271
2272 default:
2273 netif_err(tp, ifup, tp->dev,
2274 "Invalid action 0x%08x\n", action);
2275 goto out;
2276 }
2277 }
2278 rc = true;
2279 out:
2280 return rc;
2281 }
2282
2283 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2284 {
2285 struct net_device *dev = tp->dev;
2286 int rc = -EINVAL;
2287
2288 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2289 netif_err(tp, ifup, dev, "invalid firwmare\n");
2290 goto out;
2291 }
2292
2293 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2294 rc = 0;
2295 out:
2296 return rc;
2297 }
2298
2299 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2300 {
2301 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2302 struct mdio_ops org, *ops = &tp->mdio_ops;
2303 u32 predata, count;
2304 size_t index;
2305
2306 predata = count = 0;
2307 org.write = ops->write;
2308 org.read = ops->read;
2309
2310 for (index = 0; index < pa->size; ) {
2311 u32 action = le32_to_cpu(pa->code[index]);
2312 u32 data = action & 0x0000ffff;
2313 u32 regno = (action & 0x0fff0000) >> 16;
2314
2315 if (!action)
2316 break;
2317
2318 switch(action & 0xf0000000) {
2319 case PHY_READ:
2320 predata = rtl_readphy(tp, regno);
2321 count++;
2322 index++;
2323 break;
2324 case PHY_DATA_OR:
2325 predata |= data;
2326 index++;
2327 break;
2328 case PHY_DATA_AND:
2329 predata &= data;
2330 index++;
2331 break;
2332 case PHY_BJMPN:
2333 index -= regno;
2334 break;
2335 case PHY_MDIO_CHG:
2336 if (data == 0) {
2337 ops->write = org.write;
2338 ops->read = org.read;
2339 } else if (data == 1) {
2340 ops->write = mac_mcu_write;
2341 ops->read = mac_mcu_read;
2342 }
2343
2344 index++;
2345 break;
2346 case PHY_CLEAR_READCOUNT:
2347 count = 0;
2348 index++;
2349 break;
2350 case PHY_WRITE:
2351 rtl_writephy(tp, regno, data);
2352 index++;
2353 break;
2354 case PHY_READCOUNT_EQ_SKIP:
2355 index += (count == data) ? 2 : 1;
2356 break;
2357 case PHY_COMP_EQ_SKIPN:
2358 if (predata == data)
2359 index += regno;
2360 index++;
2361 break;
2362 case PHY_COMP_NEQ_SKIPN:
2363 if (predata != data)
2364 index += regno;
2365 index++;
2366 break;
2367 case PHY_WRITE_PREVIOUS:
2368 rtl_writephy(tp, regno, predata);
2369 index++;
2370 break;
2371 case PHY_SKIPN:
2372 index += regno + 1;
2373 break;
2374 case PHY_DELAY_MS:
2375 mdelay(data);
2376 index++;
2377 break;
2378
2379 default:
2380 BUG();
2381 }
2382 }
2383
2384 ops->write = org.write;
2385 ops->read = org.read;
2386 }
2387
2388 static void rtl_release_firmware(struct rtl8169_private *tp)
2389 {
2390 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2391 release_firmware(tp->rtl_fw->fw);
2392 kfree(tp->rtl_fw);
2393 }
2394 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2395 }
2396
2397 static void rtl_apply_firmware(struct rtl8169_private *tp)
2398 {
2399 struct rtl_fw *rtl_fw = tp->rtl_fw;
2400
2401 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2402 if (!IS_ERR_OR_NULL(rtl_fw))
2403 rtl_phy_write_fw(tp, rtl_fw);
2404 }
2405
2406 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2407 {
2408 if (rtl_readphy(tp, reg) != val)
2409 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2410 else
2411 rtl_apply_firmware(tp);
2412 }
2413
2414 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2415 {
2416 static const struct phy_reg phy_reg_init[] = {
2417 { 0x1f, 0x0001 },
2418 { 0x06, 0x006e },
2419 { 0x08, 0x0708 },
2420 { 0x15, 0x4000 },
2421 { 0x18, 0x65c7 },
2422
2423 { 0x1f, 0x0001 },
2424 { 0x03, 0x00a1 },
2425 { 0x02, 0x0008 },
2426 { 0x01, 0x0120 },
2427 { 0x00, 0x1000 },
2428 { 0x04, 0x0800 },
2429 { 0x04, 0x0000 },
2430
2431 { 0x03, 0xff41 },
2432 { 0x02, 0xdf60 },
2433 { 0x01, 0x0140 },
2434 { 0x00, 0x0077 },
2435 { 0x04, 0x7800 },
2436 { 0x04, 0x7000 },
2437
2438 { 0x03, 0x802f },
2439 { 0x02, 0x4f02 },
2440 { 0x01, 0x0409 },
2441 { 0x00, 0xf0f9 },
2442 { 0x04, 0x9800 },
2443 { 0x04, 0x9000 },
2444
2445 { 0x03, 0xdf01 },
2446 { 0x02, 0xdf20 },
2447 { 0x01, 0xff95 },
2448 { 0x00, 0xba00 },
2449 { 0x04, 0xa800 },
2450 { 0x04, 0xa000 },
2451
2452 { 0x03, 0xff41 },
2453 { 0x02, 0xdf20 },
2454 { 0x01, 0x0140 },
2455 { 0x00, 0x00bb },
2456 { 0x04, 0xb800 },
2457 { 0x04, 0xb000 },
2458
2459 { 0x03, 0xdf41 },
2460 { 0x02, 0xdc60 },
2461 { 0x01, 0x6340 },
2462 { 0x00, 0x007d },
2463 { 0x04, 0xd800 },
2464 { 0x04, 0xd000 },
2465
2466 { 0x03, 0xdf01 },
2467 { 0x02, 0xdf20 },
2468 { 0x01, 0x100a },
2469 { 0x00, 0xa0ff },
2470 { 0x04, 0xf800 },
2471 { 0x04, 0xf000 },
2472
2473 { 0x1f, 0x0000 },
2474 { 0x0b, 0x0000 },
2475 { 0x00, 0x9200 }
2476 };
2477
2478 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2479 }
2480
2481 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2482 {
2483 static const struct phy_reg phy_reg_init[] = {
2484 { 0x1f, 0x0002 },
2485 { 0x01, 0x90d0 },
2486 { 0x1f, 0x0000 }
2487 };
2488
2489 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2490 }
2491
2492 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2493 {
2494 struct pci_dev *pdev = tp->pci_dev;
2495
2496 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2497 (pdev->subsystem_device != 0xe000))
2498 return;
2499
2500 rtl_writephy(tp, 0x1f, 0x0001);
2501 rtl_writephy(tp, 0x10, 0xf01b);
2502 rtl_writephy(tp, 0x1f, 0x0000);
2503 }
2504
2505 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2506 {
2507 static const struct phy_reg phy_reg_init[] = {
2508 { 0x1f, 0x0001 },
2509 { 0x04, 0x0000 },
2510 { 0x03, 0x00a1 },
2511 { 0x02, 0x0008 },
2512 { 0x01, 0x0120 },
2513 { 0x00, 0x1000 },
2514 { 0x04, 0x0800 },
2515 { 0x04, 0x9000 },
2516 { 0x03, 0x802f },
2517 { 0x02, 0x4f02 },
2518 { 0x01, 0x0409 },
2519 { 0x00, 0xf099 },
2520 { 0x04, 0x9800 },
2521 { 0x04, 0xa000 },
2522 { 0x03, 0xdf01 },
2523 { 0x02, 0xdf20 },
2524 { 0x01, 0xff95 },
2525 { 0x00, 0xba00 },
2526 { 0x04, 0xa800 },
2527 { 0x04, 0xf000 },
2528 { 0x03, 0xdf01 },
2529 { 0x02, 0xdf20 },
2530 { 0x01, 0x101a },
2531 { 0x00, 0xa0ff },
2532 { 0x04, 0xf800 },
2533 { 0x04, 0x0000 },
2534 { 0x1f, 0x0000 },
2535
2536 { 0x1f, 0x0001 },
2537 { 0x10, 0xf41b },
2538 { 0x14, 0xfb54 },
2539 { 0x18, 0xf5c7 },
2540 { 0x1f, 0x0000 },
2541
2542 { 0x1f, 0x0001 },
2543 { 0x17, 0x0cc0 },
2544 { 0x1f, 0x0000 }
2545 };
2546
2547 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2548
2549 rtl8169scd_hw_phy_config_quirk(tp);
2550 }
2551
2552 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2553 {
2554 static const struct phy_reg phy_reg_init[] = {
2555 { 0x1f, 0x0001 },
2556 { 0x04, 0x0000 },
2557 { 0x03, 0x00a1 },
2558 { 0x02, 0x0008 },
2559 { 0x01, 0x0120 },
2560 { 0x00, 0x1000 },
2561 { 0x04, 0x0800 },
2562 { 0x04, 0x9000 },
2563 { 0x03, 0x802f },
2564 { 0x02, 0x4f02 },
2565 { 0x01, 0x0409 },
2566 { 0x00, 0xf099 },
2567 { 0x04, 0x9800 },
2568 { 0x04, 0xa000 },
2569 { 0x03, 0xdf01 },
2570 { 0x02, 0xdf20 },
2571 { 0x01, 0xff95 },
2572 { 0x00, 0xba00 },
2573 { 0x04, 0xa800 },
2574 { 0x04, 0xf000 },
2575 { 0x03, 0xdf01 },
2576 { 0x02, 0xdf20 },
2577 { 0x01, 0x101a },
2578 { 0x00, 0xa0ff },
2579 { 0x04, 0xf800 },
2580 { 0x04, 0x0000 },
2581 { 0x1f, 0x0000 },
2582
2583 { 0x1f, 0x0001 },
2584 { 0x0b, 0x8480 },
2585 { 0x1f, 0x0000 },
2586
2587 { 0x1f, 0x0001 },
2588 { 0x18, 0x67c7 },
2589 { 0x04, 0x2000 },
2590 { 0x03, 0x002f },
2591 { 0x02, 0x4360 },
2592 { 0x01, 0x0109 },
2593 { 0x00, 0x3022 },
2594 { 0x04, 0x2800 },
2595 { 0x1f, 0x0000 },
2596
2597 { 0x1f, 0x0001 },
2598 { 0x17, 0x0cc0 },
2599 { 0x1f, 0x0000 }
2600 };
2601
2602 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2603 }
2604
2605 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2606 {
2607 static const struct phy_reg phy_reg_init[] = {
2608 { 0x10, 0xf41b },
2609 { 0x1f, 0x0000 }
2610 };
2611
2612 rtl_writephy(tp, 0x1f, 0x0001);
2613 rtl_patchphy(tp, 0x16, 1 << 0);
2614
2615 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2616 }
2617
2618 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2619 {
2620 static const struct phy_reg phy_reg_init[] = {
2621 { 0x1f, 0x0001 },
2622 { 0x10, 0xf41b },
2623 { 0x1f, 0x0000 }
2624 };
2625
2626 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2627 }
2628
2629 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2630 {
2631 static const struct phy_reg phy_reg_init[] = {
2632 { 0x1f, 0x0000 },
2633 { 0x1d, 0x0f00 },
2634 { 0x1f, 0x0002 },
2635 { 0x0c, 0x1ec8 },
2636 { 0x1f, 0x0000 }
2637 };
2638
2639 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2640 }
2641
2642 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2643 {
2644 static const struct phy_reg phy_reg_init[] = {
2645 { 0x1f, 0x0001 },
2646 { 0x1d, 0x3d98 },
2647 { 0x1f, 0x0000 }
2648 };
2649
2650 rtl_writephy(tp, 0x1f, 0x0000);
2651 rtl_patchphy(tp, 0x14, 1 << 5);
2652 rtl_patchphy(tp, 0x0d, 1 << 5);
2653
2654 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2655 }
2656
2657 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2658 {
2659 static const struct phy_reg phy_reg_init[] = {
2660 { 0x1f, 0x0001 },
2661 { 0x12, 0x2300 },
2662 { 0x1f, 0x0002 },
2663 { 0x00, 0x88d4 },
2664 { 0x01, 0x82b1 },
2665 { 0x03, 0x7002 },
2666 { 0x08, 0x9e30 },
2667 { 0x09, 0x01f0 },
2668 { 0x0a, 0x5500 },
2669 { 0x0c, 0x00c8 },
2670 { 0x1f, 0x0003 },
2671 { 0x12, 0xc096 },
2672 { 0x16, 0x000a },
2673 { 0x1f, 0x0000 },
2674 { 0x1f, 0x0000 },
2675 { 0x09, 0x2000 },
2676 { 0x09, 0x0000 }
2677 };
2678
2679 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2680
2681 rtl_patchphy(tp, 0x14, 1 << 5);
2682 rtl_patchphy(tp, 0x0d, 1 << 5);
2683 rtl_writephy(tp, 0x1f, 0x0000);
2684 }
2685
2686 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2687 {
2688 static const struct phy_reg phy_reg_init[] = {
2689 { 0x1f, 0x0001 },
2690 { 0x12, 0x2300 },
2691 { 0x03, 0x802f },
2692 { 0x02, 0x4f02 },
2693 { 0x01, 0x0409 },
2694 { 0x00, 0xf099 },
2695 { 0x04, 0x9800 },
2696 { 0x04, 0x9000 },
2697 { 0x1d, 0x3d98 },
2698 { 0x1f, 0x0002 },
2699 { 0x0c, 0x7eb8 },
2700 { 0x06, 0x0761 },
2701 { 0x1f, 0x0003 },
2702 { 0x16, 0x0f0a },
2703 { 0x1f, 0x0000 }
2704 };
2705
2706 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2707
2708 rtl_patchphy(tp, 0x16, 1 << 0);
2709 rtl_patchphy(tp, 0x14, 1 << 5);
2710 rtl_patchphy(tp, 0x0d, 1 << 5);
2711 rtl_writephy(tp, 0x1f, 0x0000);
2712 }
2713
2714 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2715 {
2716 static const struct phy_reg phy_reg_init[] = {
2717 { 0x1f, 0x0001 },
2718 { 0x12, 0x2300 },
2719 { 0x1d, 0x3d98 },
2720 { 0x1f, 0x0002 },
2721 { 0x0c, 0x7eb8 },
2722 { 0x06, 0x5461 },
2723 { 0x1f, 0x0003 },
2724 { 0x16, 0x0f0a },
2725 { 0x1f, 0x0000 }
2726 };
2727
2728 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2729
2730 rtl_patchphy(tp, 0x16, 1 << 0);
2731 rtl_patchphy(tp, 0x14, 1 << 5);
2732 rtl_patchphy(tp, 0x0d, 1 << 5);
2733 rtl_writephy(tp, 0x1f, 0x0000);
2734 }
2735
2736 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2737 {
2738 rtl8168c_3_hw_phy_config(tp);
2739 }
2740
2741 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2742 {
2743 static const struct phy_reg phy_reg_init_0[] = {
2744 /* Channel Estimation */
2745 { 0x1f, 0x0001 },
2746 { 0x06, 0x4064 },
2747 { 0x07, 0x2863 },
2748 { 0x08, 0x059c },
2749 { 0x09, 0x26b4 },
2750 { 0x0a, 0x6a19 },
2751 { 0x0b, 0xdcc8 },
2752 { 0x10, 0xf06d },
2753 { 0x14, 0x7f68 },
2754 { 0x18, 0x7fd9 },
2755 { 0x1c, 0xf0ff },
2756 { 0x1d, 0x3d9c },
2757 { 0x1f, 0x0003 },
2758 { 0x12, 0xf49f },
2759 { 0x13, 0x070b },
2760 { 0x1a, 0x05ad },
2761 { 0x14, 0x94c0 },
2762
2763 /*
2764 * Tx Error Issue
2765 * Enhance line driver power
2766 */
2767 { 0x1f, 0x0002 },
2768 { 0x06, 0x5561 },
2769 { 0x1f, 0x0005 },
2770 { 0x05, 0x8332 },
2771 { 0x06, 0x5561 },
2772
2773 /*
2774 * Can not link to 1Gbps with bad cable
2775 * Decrease SNR threshold form 21.07dB to 19.04dB
2776 */
2777 { 0x1f, 0x0001 },
2778 { 0x17, 0x0cc0 },
2779
2780 { 0x1f, 0x0000 },
2781 { 0x0d, 0xf880 }
2782 };
2783
2784 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2785
2786 /*
2787 * Rx Error Issue
2788 * Fine Tune Switching regulator parameter
2789 */
2790 rtl_writephy(tp, 0x1f, 0x0002);
2791 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2792 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2793
2794 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2795 static const struct phy_reg phy_reg_init[] = {
2796 { 0x1f, 0x0002 },
2797 { 0x05, 0x669a },
2798 { 0x1f, 0x0005 },
2799 { 0x05, 0x8330 },
2800 { 0x06, 0x669a },
2801 { 0x1f, 0x0002 }
2802 };
2803 int val;
2804
2805 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2806
2807 val = rtl_readphy(tp, 0x0d);
2808
2809 if ((val & 0x00ff) != 0x006c) {
2810 static const u32 set[] = {
2811 0x0065, 0x0066, 0x0067, 0x0068,
2812 0x0069, 0x006a, 0x006b, 0x006c
2813 };
2814 int i;
2815
2816 rtl_writephy(tp, 0x1f, 0x0002);
2817
2818 val &= 0xff00;
2819 for (i = 0; i < ARRAY_SIZE(set); i++)
2820 rtl_writephy(tp, 0x0d, val | set[i]);
2821 }
2822 } else {
2823 static const struct phy_reg phy_reg_init[] = {
2824 { 0x1f, 0x0002 },
2825 { 0x05, 0x6662 },
2826 { 0x1f, 0x0005 },
2827 { 0x05, 0x8330 },
2828 { 0x06, 0x6662 }
2829 };
2830
2831 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2832 }
2833
2834 /* RSET couple improve */
2835 rtl_writephy(tp, 0x1f, 0x0002);
2836 rtl_patchphy(tp, 0x0d, 0x0300);
2837 rtl_patchphy(tp, 0x0f, 0x0010);
2838
2839 /* Fine tune PLL performance */
2840 rtl_writephy(tp, 0x1f, 0x0002);
2841 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2842 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2843
2844 rtl_writephy(tp, 0x1f, 0x0005);
2845 rtl_writephy(tp, 0x05, 0x001b);
2846
2847 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2848
2849 rtl_writephy(tp, 0x1f, 0x0000);
2850 }
2851
2852 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2853 {
2854 static const struct phy_reg phy_reg_init_0[] = {
2855 /* Channel Estimation */
2856 { 0x1f, 0x0001 },
2857 { 0x06, 0x4064 },
2858 { 0x07, 0x2863 },
2859 { 0x08, 0x059c },
2860 { 0x09, 0x26b4 },
2861 { 0x0a, 0x6a19 },
2862 { 0x0b, 0xdcc8 },
2863 { 0x10, 0xf06d },
2864 { 0x14, 0x7f68 },
2865 { 0x18, 0x7fd9 },
2866 { 0x1c, 0xf0ff },
2867 { 0x1d, 0x3d9c },
2868 { 0x1f, 0x0003 },
2869 { 0x12, 0xf49f },
2870 { 0x13, 0x070b },
2871 { 0x1a, 0x05ad },
2872 { 0x14, 0x94c0 },
2873
2874 /*
2875 * Tx Error Issue
2876 * Enhance line driver power
2877 */
2878 { 0x1f, 0x0002 },
2879 { 0x06, 0x5561 },
2880 { 0x1f, 0x0005 },
2881 { 0x05, 0x8332 },
2882 { 0x06, 0x5561 },
2883
2884 /*
2885 * Can not link to 1Gbps with bad cable
2886 * Decrease SNR threshold form 21.07dB to 19.04dB
2887 */
2888 { 0x1f, 0x0001 },
2889 { 0x17, 0x0cc0 },
2890
2891 { 0x1f, 0x0000 },
2892 { 0x0d, 0xf880 }
2893 };
2894
2895 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2896
2897 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2898 static const struct phy_reg phy_reg_init[] = {
2899 { 0x1f, 0x0002 },
2900 { 0x05, 0x669a },
2901 { 0x1f, 0x0005 },
2902 { 0x05, 0x8330 },
2903 { 0x06, 0x669a },
2904
2905 { 0x1f, 0x0002 }
2906 };
2907 int val;
2908
2909 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2910
2911 val = rtl_readphy(tp, 0x0d);
2912 if ((val & 0x00ff) != 0x006c) {
2913 static const u32 set[] = {
2914 0x0065, 0x0066, 0x0067, 0x0068,
2915 0x0069, 0x006a, 0x006b, 0x006c
2916 };
2917 int i;
2918
2919 rtl_writephy(tp, 0x1f, 0x0002);
2920
2921 val &= 0xff00;
2922 for (i = 0; i < ARRAY_SIZE(set); i++)
2923 rtl_writephy(tp, 0x0d, val | set[i]);
2924 }
2925 } else {
2926 static const struct phy_reg phy_reg_init[] = {
2927 { 0x1f, 0x0002 },
2928 { 0x05, 0x2642 },
2929 { 0x1f, 0x0005 },
2930 { 0x05, 0x8330 },
2931 { 0x06, 0x2642 }
2932 };
2933
2934 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2935 }
2936
2937 /* Fine tune PLL performance */
2938 rtl_writephy(tp, 0x1f, 0x0002);
2939 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2940 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2941
2942 /* Switching regulator Slew rate */
2943 rtl_writephy(tp, 0x1f, 0x0002);
2944 rtl_patchphy(tp, 0x0f, 0x0017);
2945
2946 rtl_writephy(tp, 0x1f, 0x0005);
2947 rtl_writephy(tp, 0x05, 0x001b);
2948
2949 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2950
2951 rtl_writephy(tp, 0x1f, 0x0000);
2952 }
2953
2954 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2955 {
2956 static const struct phy_reg phy_reg_init[] = {
2957 { 0x1f, 0x0002 },
2958 { 0x10, 0x0008 },
2959 { 0x0d, 0x006c },
2960
2961 { 0x1f, 0x0000 },
2962 { 0x0d, 0xf880 },
2963
2964 { 0x1f, 0x0001 },
2965 { 0x17, 0x0cc0 },
2966
2967 { 0x1f, 0x0001 },
2968 { 0x0b, 0xa4d8 },
2969 { 0x09, 0x281c },
2970 { 0x07, 0x2883 },
2971 { 0x0a, 0x6b35 },
2972 { 0x1d, 0x3da4 },
2973 { 0x1c, 0xeffd },
2974 { 0x14, 0x7f52 },
2975 { 0x18, 0x7fc6 },
2976 { 0x08, 0x0601 },
2977 { 0x06, 0x4063 },
2978 { 0x10, 0xf074 },
2979 { 0x1f, 0x0003 },
2980 { 0x13, 0x0789 },
2981 { 0x12, 0xf4bd },
2982 { 0x1a, 0x04fd },
2983 { 0x14, 0x84b0 },
2984 { 0x1f, 0x0000 },
2985 { 0x00, 0x9200 },
2986
2987 { 0x1f, 0x0005 },
2988 { 0x01, 0x0340 },
2989 { 0x1f, 0x0001 },
2990 { 0x04, 0x4000 },
2991 { 0x03, 0x1d21 },
2992 { 0x02, 0x0c32 },
2993 { 0x01, 0x0200 },
2994 { 0x00, 0x5554 },
2995 { 0x04, 0x4800 },
2996 { 0x04, 0x4000 },
2997 { 0x04, 0xf000 },
2998 { 0x03, 0xdf01 },
2999 { 0x02, 0xdf20 },
3000 { 0x01, 0x101a },
3001 { 0x00, 0xa0ff },
3002 { 0x04, 0xf800 },
3003 { 0x04, 0xf000 },
3004 { 0x1f, 0x0000 },
3005
3006 { 0x1f, 0x0007 },
3007 { 0x1e, 0x0023 },
3008 { 0x16, 0x0000 },
3009 { 0x1f, 0x0000 }
3010 };
3011
3012 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3013 }
3014
3015 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3016 {
3017 static const struct phy_reg phy_reg_init[] = {
3018 { 0x1f, 0x0001 },
3019 { 0x17, 0x0cc0 },
3020
3021 { 0x1f, 0x0007 },
3022 { 0x1e, 0x002d },
3023 { 0x18, 0x0040 },
3024 { 0x1f, 0x0000 }
3025 };
3026
3027 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3028 rtl_patchphy(tp, 0x0d, 1 << 5);
3029 }
3030
3031 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3032 {
3033 static const struct phy_reg phy_reg_init[] = {
3034 /* Enable Delay cap */
3035 { 0x1f, 0x0005 },
3036 { 0x05, 0x8b80 },
3037 { 0x06, 0xc896 },
3038 { 0x1f, 0x0000 },
3039
3040 /* Channel estimation fine tune */
3041 { 0x1f, 0x0001 },
3042 { 0x0b, 0x6c20 },
3043 { 0x07, 0x2872 },
3044 { 0x1c, 0xefff },
3045 { 0x1f, 0x0003 },
3046 { 0x14, 0x6420 },
3047 { 0x1f, 0x0000 },
3048
3049 /* Update PFM & 10M TX idle timer */
3050 { 0x1f, 0x0007 },
3051 { 0x1e, 0x002f },
3052 { 0x15, 0x1919 },
3053 { 0x1f, 0x0000 },
3054
3055 { 0x1f, 0x0007 },
3056 { 0x1e, 0x00ac },
3057 { 0x18, 0x0006 },
3058 { 0x1f, 0x0000 }
3059 };
3060
3061 rtl_apply_firmware(tp);
3062
3063 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3064
3065 /* DCO enable for 10M IDLE Power */
3066 rtl_writephy(tp, 0x1f, 0x0007);
3067 rtl_writephy(tp, 0x1e, 0x0023);
3068 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3069 rtl_writephy(tp, 0x1f, 0x0000);
3070
3071 /* For impedance matching */
3072 rtl_writephy(tp, 0x1f, 0x0002);
3073 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
3074 rtl_writephy(tp, 0x1f, 0x0000);
3075
3076 /* PHY auto speed down */
3077 rtl_writephy(tp, 0x1f, 0x0007);
3078 rtl_writephy(tp, 0x1e, 0x002d);
3079 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3080 rtl_writephy(tp, 0x1f, 0x0000);
3081 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3082
3083 rtl_writephy(tp, 0x1f, 0x0005);
3084 rtl_writephy(tp, 0x05, 0x8b86);
3085 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3086 rtl_writephy(tp, 0x1f, 0x0000);
3087
3088 rtl_writephy(tp, 0x1f, 0x0005);
3089 rtl_writephy(tp, 0x05, 0x8b85);
3090 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3091 rtl_writephy(tp, 0x1f, 0x0007);
3092 rtl_writephy(tp, 0x1e, 0x0020);
3093 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3094 rtl_writephy(tp, 0x1f, 0x0006);
3095 rtl_writephy(tp, 0x00, 0x5a00);
3096 rtl_writephy(tp, 0x1f, 0x0000);
3097 rtl_writephy(tp, 0x0d, 0x0007);
3098 rtl_writephy(tp, 0x0e, 0x003c);
3099 rtl_writephy(tp, 0x0d, 0x4007);
3100 rtl_writephy(tp, 0x0e, 0x0000);
3101 rtl_writephy(tp, 0x0d, 0x0000);
3102 }
3103
3104 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3105 {
3106 const u16 w[] = {
3107 addr[0] | (addr[1] << 8),
3108 addr[2] | (addr[3] << 8),
3109 addr[4] | (addr[5] << 8)
3110 };
3111 const struct exgmac_reg e[] = {
3112 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3113 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3114 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3115 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3116 };
3117
3118 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3119 }
3120
3121 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3122 {
3123 static const struct phy_reg phy_reg_init[] = {
3124 /* Enable Delay cap */
3125 { 0x1f, 0x0004 },
3126 { 0x1f, 0x0007 },
3127 { 0x1e, 0x00ac },
3128 { 0x18, 0x0006 },
3129 { 0x1f, 0x0002 },
3130 { 0x1f, 0x0000 },
3131 { 0x1f, 0x0000 },
3132
3133 /* Channel estimation fine tune */
3134 { 0x1f, 0x0003 },
3135 { 0x09, 0xa20f },
3136 { 0x1f, 0x0000 },
3137 { 0x1f, 0x0000 },
3138
3139 /* Green Setting */
3140 { 0x1f, 0x0005 },
3141 { 0x05, 0x8b5b },
3142 { 0x06, 0x9222 },
3143 { 0x05, 0x8b6d },
3144 { 0x06, 0x8000 },
3145 { 0x05, 0x8b76 },
3146 { 0x06, 0x8000 },
3147 { 0x1f, 0x0000 }
3148 };
3149
3150 rtl_apply_firmware(tp);
3151
3152 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3153
3154 /* For 4-corner performance improve */
3155 rtl_writephy(tp, 0x1f, 0x0005);
3156 rtl_writephy(tp, 0x05, 0x8b80);
3157 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3158 rtl_writephy(tp, 0x1f, 0x0000);
3159
3160 /* PHY auto speed down */
3161 rtl_writephy(tp, 0x1f, 0x0004);
3162 rtl_writephy(tp, 0x1f, 0x0007);
3163 rtl_writephy(tp, 0x1e, 0x002d);
3164 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3165 rtl_writephy(tp, 0x1f, 0x0002);
3166 rtl_writephy(tp, 0x1f, 0x0000);
3167 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3168
3169 /* improve 10M EEE waveform */
3170 rtl_writephy(tp, 0x1f, 0x0005);
3171 rtl_writephy(tp, 0x05, 0x8b86);
3172 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3173 rtl_writephy(tp, 0x1f, 0x0000);
3174
3175 /* Improve 2-pair detection performance */
3176 rtl_writephy(tp, 0x1f, 0x0005);
3177 rtl_writephy(tp, 0x05, 0x8b85);
3178 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3179 rtl_writephy(tp, 0x1f, 0x0000);
3180
3181 /* EEE setting */
3182 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3183 rtl_writephy(tp, 0x1f, 0x0005);
3184 rtl_writephy(tp, 0x05, 0x8b85);
3185 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3186 rtl_writephy(tp, 0x1f, 0x0004);
3187 rtl_writephy(tp, 0x1f, 0x0007);
3188 rtl_writephy(tp, 0x1e, 0x0020);
3189 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3190 rtl_writephy(tp, 0x1f, 0x0002);
3191 rtl_writephy(tp, 0x1f, 0x0000);
3192 rtl_writephy(tp, 0x0d, 0x0007);
3193 rtl_writephy(tp, 0x0e, 0x003c);
3194 rtl_writephy(tp, 0x0d, 0x4007);
3195 rtl_writephy(tp, 0x0e, 0x0000);
3196 rtl_writephy(tp, 0x0d, 0x0000);
3197
3198 /* Green feature */
3199 rtl_writephy(tp, 0x1f, 0x0003);
3200 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3201 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3202 rtl_writephy(tp, 0x1f, 0x0000);
3203
3204 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3205 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3206 }
3207
3208 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3209 {
3210 /* For 4-corner performance improve */
3211 rtl_writephy(tp, 0x1f, 0x0005);
3212 rtl_writephy(tp, 0x05, 0x8b80);
3213 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3214 rtl_writephy(tp, 0x1f, 0x0000);
3215
3216 /* PHY auto speed down */
3217 rtl_writephy(tp, 0x1f, 0x0007);
3218 rtl_writephy(tp, 0x1e, 0x002d);
3219 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3220 rtl_writephy(tp, 0x1f, 0x0000);
3221 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3222
3223 /* Improve 10M EEE waveform */
3224 rtl_writephy(tp, 0x1f, 0x0005);
3225 rtl_writephy(tp, 0x05, 0x8b86);
3226 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3227 rtl_writephy(tp, 0x1f, 0x0000);
3228 }
3229
3230 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3231 {
3232 static const struct phy_reg phy_reg_init[] = {
3233 /* Channel estimation fine tune */
3234 { 0x1f, 0x0003 },
3235 { 0x09, 0xa20f },
3236 { 0x1f, 0x0000 },
3237
3238 /* Modify green table for giga & fnet */
3239 { 0x1f, 0x0005 },
3240 { 0x05, 0x8b55 },
3241 { 0x06, 0x0000 },
3242 { 0x05, 0x8b5e },
3243 { 0x06, 0x0000 },
3244 { 0x05, 0x8b67 },
3245 { 0x06, 0x0000 },
3246 { 0x05, 0x8b70 },
3247 { 0x06, 0x0000 },
3248 { 0x1f, 0x0000 },
3249 { 0x1f, 0x0007 },
3250 { 0x1e, 0x0078 },
3251 { 0x17, 0x0000 },
3252 { 0x19, 0x00fb },
3253 { 0x1f, 0x0000 },
3254
3255 /* Modify green table for 10M */
3256 { 0x1f, 0x0005 },
3257 { 0x05, 0x8b79 },
3258 { 0x06, 0xaa00 },
3259 { 0x1f, 0x0000 },
3260
3261 /* Disable hiimpedance detection (RTCT) */
3262 { 0x1f, 0x0003 },
3263 { 0x01, 0x328a },
3264 { 0x1f, 0x0000 }
3265 };
3266
3267 rtl_apply_firmware(tp);
3268
3269 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3270
3271 rtl8168f_hw_phy_config(tp);
3272
3273 /* Improve 2-pair detection performance */
3274 rtl_writephy(tp, 0x1f, 0x0005);
3275 rtl_writephy(tp, 0x05, 0x8b85);
3276 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3277 rtl_writephy(tp, 0x1f, 0x0000);
3278 }
3279
3280 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3281 {
3282 rtl_apply_firmware(tp);
3283
3284 rtl8168f_hw_phy_config(tp);
3285 }
3286
3287 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3288 {
3289 static const struct phy_reg phy_reg_init[] = {
3290 /* Channel estimation fine tune */
3291 { 0x1f, 0x0003 },
3292 { 0x09, 0xa20f },
3293 { 0x1f, 0x0000 },
3294
3295 /* Modify green table for giga & fnet */
3296 { 0x1f, 0x0005 },
3297 { 0x05, 0x8b55 },
3298 { 0x06, 0x0000 },
3299 { 0x05, 0x8b5e },
3300 { 0x06, 0x0000 },
3301 { 0x05, 0x8b67 },
3302 { 0x06, 0x0000 },
3303 { 0x05, 0x8b70 },
3304 { 0x06, 0x0000 },
3305 { 0x1f, 0x0000 },
3306 { 0x1f, 0x0007 },
3307 { 0x1e, 0x0078 },
3308 { 0x17, 0x0000 },
3309 { 0x19, 0x00aa },
3310 { 0x1f, 0x0000 },
3311
3312 /* Modify green table for 10M */
3313 { 0x1f, 0x0005 },
3314 { 0x05, 0x8b79 },
3315 { 0x06, 0xaa00 },
3316 { 0x1f, 0x0000 },
3317
3318 /* Disable hiimpedance detection (RTCT) */
3319 { 0x1f, 0x0003 },
3320 { 0x01, 0x328a },
3321 { 0x1f, 0x0000 }
3322 };
3323
3324
3325 rtl_apply_firmware(tp);
3326
3327 rtl8168f_hw_phy_config(tp);
3328
3329 /* Improve 2-pair detection performance */
3330 rtl_writephy(tp, 0x1f, 0x0005);
3331 rtl_writephy(tp, 0x05, 0x8b85);
3332 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3333 rtl_writephy(tp, 0x1f, 0x0000);
3334
3335 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3336
3337 /* Modify green table for giga */
3338 rtl_writephy(tp, 0x1f, 0x0005);
3339 rtl_writephy(tp, 0x05, 0x8b54);
3340 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3341 rtl_writephy(tp, 0x05, 0x8b5d);
3342 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3343 rtl_writephy(tp, 0x05, 0x8a7c);
3344 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3345 rtl_writephy(tp, 0x05, 0x8a7f);
3346 rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3347 rtl_writephy(tp, 0x05, 0x8a82);
3348 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3349 rtl_writephy(tp, 0x05, 0x8a85);
3350 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3351 rtl_writephy(tp, 0x05, 0x8a88);
3352 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3353 rtl_writephy(tp, 0x1f, 0x0000);
3354
3355 /* uc same-seed solution */
3356 rtl_writephy(tp, 0x1f, 0x0005);
3357 rtl_writephy(tp, 0x05, 0x8b85);
3358 rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3359 rtl_writephy(tp, 0x1f, 0x0000);
3360
3361 /* eee setting */
3362 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3363 rtl_writephy(tp, 0x1f, 0x0005);
3364 rtl_writephy(tp, 0x05, 0x8b85);
3365 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3366 rtl_writephy(tp, 0x1f, 0x0004);
3367 rtl_writephy(tp, 0x1f, 0x0007);
3368 rtl_writephy(tp, 0x1e, 0x0020);
3369 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3370 rtl_writephy(tp, 0x1f, 0x0000);
3371 rtl_writephy(tp, 0x0d, 0x0007);
3372 rtl_writephy(tp, 0x0e, 0x003c);
3373 rtl_writephy(tp, 0x0d, 0x4007);
3374 rtl_writephy(tp, 0x0e, 0x0000);
3375 rtl_writephy(tp, 0x0d, 0x0000);
3376
3377 /* Green feature */
3378 rtl_writephy(tp, 0x1f, 0x0003);
3379 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3380 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3381 rtl_writephy(tp, 0x1f, 0x0000);
3382 }
3383
3384 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3385 {
3386 rtl_apply_firmware(tp);
3387
3388 rtl_writephy(tp, 0x1f, 0x0a46);
3389 if (rtl_readphy(tp, 0x10) & 0x0100) {
3390 rtl_writephy(tp, 0x1f, 0x0bcc);
3391 rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
3392 } else {
3393 rtl_writephy(tp, 0x1f, 0x0bcc);
3394 rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
3395 }
3396
3397 rtl_writephy(tp, 0x1f, 0x0a46);
3398 if (rtl_readphy(tp, 0x13) & 0x0100) {
3399 rtl_writephy(tp, 0x1f, 0x0c41);
3400 rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
3401 } else {
3402 rtl_writephy(tp, 0x1f, 0x0c41);
3403 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0002);
3404 }
3405
3406 /* Enable PHY auto speed down */
3407 rtl_writephy(tp, 0x1f, 0x0a44);
3408 rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
3409
3410 rtl_writephy(tp, 0x1f, 0x0bcc);
3411 rtl_w1w0_phy(tp, 0x14, 0x0100, 0x0000);
3412 rtl_writephy(tp, 0x1f, 0x0a44);
3413 rtl_w1w0_phy(tp, 0x11, 0x00c0, 0x0000);
3414 rtl_writephy(tp, 0x1f, 0x0a43);
3415 rtl_writephy(tp, 0x13, 0x8084);
3416 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x6000);
3417 rtl_w1w0_phy(tp, 0x10, 0x1003, 0x0000);
3418
3419 /* EEE auto-fallback function */
3420 rtl_writephy(tp, 0x1f, 0x0a4b);
3421 rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
3422
3423 /* Enable UC LPF tune function */
3424 rtl_writephy(tp, 0x1f, 0x0a43);
3425 rtl_writephy(tp, 0x13, 0x8012);
3426 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3427
3428 rtl_writephy(tp, 0x1f, 0x0c42);
3429 rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);
3430
3431 /* Improve SWR Efficiency */
3432 rtl_writephy(tp, 0x1f, 0x0bcd);
3433 rtl_writephy(tp, 0x14, 0x5065);
3434 rtl_writephy(tp, 0x14, 0xd065);
3435 rtl_writephy(tp, 0x1f, 0x0bc8);
3436 rtl_writephy(tp, 0x11, 0x5655);
3437 rtl_writephy(tp, 0x1f, 0x0bcd);
3438 rtl_writephy(tp, 0x14, 0x1065);
3439 rtl_writephy(tp, 0x14, 0x9065);
3440 rtl_writephy(tp, 0x14, 0x1065);
3441
3442 /* Check ALDPS bit, disable it if enabled */
3443 rtl_writephy(tp, 0x1f, 0x0a43);
3444 if (rtl_readphy(tp, 0x10) & 0x0004)
3445 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004);
3446
3447 rtl_writephy(tp, 0x1f, 0x0000);
3448 }
3449
3450 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3451 {
3452 rtl_apply_firmware(tp);
3453 }
3454
3455 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3456 {
3457 static const struct phy_reg phy_reg_init[] = {
3458 { 0x1f, 0x0003 },
3459 { 0x08, 0x441d },
3460 { 0x01, 0x9100 },
3461 { 0x1f, 0x0000 }
3462 };
3463
3464 rtl_writephy(tp, 0x1f, 0x0000);
3465 rtl_patchphy(tp, 0x11, 1 << 12);
3466 rtl_patchphy(tp, 0x19, 1 << 13);
3467 rtl_patchphy(tp, 0x10, 1 << 15);
3468
3469 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3470 }
3471
3472 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3473 {
3474 static const struct phy_reg phy_reg_init[] = {
3475 { 0x1f, 0x0005 },
3476 { 0x1a, 0x0000 },
3477 { 0x1f, 0x0000 },
3478
3479 { 0x1f, 0x0004 },
3480 { 0x1c, 0x0000 },
3481 { 0x1f, 0x0000 },
3482
3483 { 0x1f, 0x0001 },
3484 { 0x15, 0x7701 },
3485 { 0x1f, 0x0000 }
3486 };
3487
3488 /* Disable ALDPS before ram code */
3489 rtl_writephy(tp, 0x1f, 0x0000);
3490 rtl_writephy(tp, 0x18, 0x0310);
3491 msleep(100);
3492
3493 rtl_apply_firmware(tp);
3494
3495 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3496 }
3497
3498 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3499 {
3500 /* Disable ALDPS before setting firmware */
3501 rtl_writephy(tp, 0x1f, 0x0000);
3502 rtl_writephy(tp, 0x18, 0x0310);
3503 msleep(20);
3504
3505 rtl_apply_firmware(tp);
3506
3507 /* EEE setting */
3508 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3509 rtl_writephy(tp, 0x1f, 0x0004);
3510 rtl_writephy(tp, 0x10, 0x401f);
3511 rtl_writephy(tp, 0x19, 0x7030);
3512 rtl_writephy(tp, 0x1f, 0x0000);
3513 }
3514
3515 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3516 {
3517 static const struct phy_reg phy_reg_init[] = {
3518 { 0x1f, 0x0004 },
3519 { 0x10, 0xc07f },
3520 { 0x19, 0x7030 },
3521 { 0x1f, 0x0000 }
3522 };
3523
3524 /* Disable ALDPS before ram code */
3525 rtl_writephy(tp, 0x1f, 0x0000);
3526 rtl_writephy(tp, 0x18, 0x0310);
3527 msleep(100);
3528
3529 rtl_apply_firmware(tp);
3530
3531 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3532 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3533
3534 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3535 }
3536
3537 static void rtl_hw_phy_config(struct net_device *dev)
3538 {
3539 struct rtl8169_private *tp = netdev_priv(dev);
3540
3541 rtl8169_print_mac_version(tp);
3542
3543 switch (tp->mac_version) {
3544 case RTL_GIGA_MAC_VER_01:
3545 break;
3546 case RTL_GIGA_MAC_VER_02:
3547 case RTL_GIGA_MAC_VER_03:
3548 rtl8169s_hw_phy_config(tp);
3549 break;
3550 case RTL_GIGA_MAC_VER_04:
3551 rtl8169sb_hw_phy_config(tp);
3552 break;
3553 case RTL_GIGA_MAC_VER_05:
3554 rtl8169scd_hw_phy_config(tp);
3555 break;
3556 case RTL_GIGA_MAC_VER_06:
3557 rtl8169sce_hw_phy_config(tp);
3558 break;
3559 case RTL_GIGA_MAC_VER_07:
3560 case RTL_GIGA_MAC_VER_08:
3561 case RTL_GIGA_MAC_VER_09:
3562 rtl8102e_hw_phy_config(tp);
3563 break;
3564 case RTL_GIGA_MAC_VER_11:
3565 rtl8168bb_hw_phy_config(tp);
3566 break;
3567 case RTL_GIGA_MAC_VER_12:
3568 rtl8168bef_hw_phy_config(tp);
3569 break;
3570 case RTL_GIGA_MAC_VER_17:
3571 rtl8168bef_hw_phy_config(tp);
3572 break;
3573 case RTL_GIGA_MAC_VER_18:
3574 rtl8168cp_1_hw_phy_config(tp);
3575 break;
3576 case RTL_GIGA_MAC_VER_19:
3577 rtl8168c_1_hw_phy_config(tp);
3578 break;
3579 case RTL_GIGA_MAC_VER_20:
3580 rtl8168c_2_hw_phy_config(tp);
3581 break;
3582 case RTL_GIGA_MAC_VER_21:
3583 rtl8168c_3_hw_phy_config(tp);
3584 break;
3585 case RTL_GIGA_MAC_VER_22:
3586 rtl8168c_4_hw_phy_config(tp);
3587 break;
3588 case RTL_GIGA_MAC_VER_23:
3589 case RTL_GIGA_MAC_VER_24:
3590 rtl8168cp_2_hw_phy_config(tp);
3591 break;
3592 case RTL_GIGA_MAC_VER_25:
3593 rtl8168d_1_hw_phy_config(tp);
3594 break;
3595 case RTL_GIGA_MAC_VER_26:
3596 rtl8168d_2_hw_phy_config(tp);
3597 break;
3598 case RTL_GIGA_MAC_VER_27:
3599 rtl8168d_3_hw_phy_config(tp);
3600 break;
3601 case RTL_GIGA_MAC_VER_28:
3602 rtl8168d_4_hw_phy_config(tp);
3603 break;
3604 case RTL_GIGA_MAC_VER_29:
3605 case RTL_GIGA_MAC_VER_30:
3606 rtl8105e_hw_phy_config(tp);
3607 break;
3608 case RTL_GIGA_MAC_VER_31:
3609 /* None. */
3610 break;
3611 case RTL_GIGA_MAC_VER_32:
3612 case RTL_GIGA_MAC_VER_33:
3613 rtl8168e_1_hw_phy_config(tp);
3614 break;
3615 case RTL_GIGA_MAC_VER_34:
3616 rtl8168e_2_hw_phy_config(tp);
3617 break;
3618 case RTL_GIGA_MAC_VER_35:
3619 rtl8168f_1_hw_phy_config(tp);
3620 break;
3621 case RTL_GIGA_MAC_VER_36:
3622 rtl8168f_2_hw_phy_config(tp);
3623 break;
3624
3625 case RTL_GIGA_MAC_VER_37:
3626 rtl8402_hw_phy_config(tp);
3627 break;
3628
3629 case RTL_GIGA_MAC_VER_38:
3630 rtl8411_hw_phy_config(tp);
3631 break;
3632
3633 case RTL_GIGA_MAC_VER_39:
3634 rtl8106e_hw_phy_config(tp);
3635 break;
3636
3637 case RTL_GIGA_MAC_VER_40:
3638 rtl8168g_1_hw_phy_config(tp);
3639 break;
3640 case RTL_GIGA_MAC_VER_42:
3641 case RTL_GIGA_MAC_VER_43:
3642 case RTL_GIGA_MAC_VER_44:
3643 rtl8168g_2_hw_phy_config(tp);
3644 break;
3645
3646 case RTL_GIGA_MAC_VER_41:
3647 default:
3648 break;
3649 }
3650 }
3651
3652 static void rtl_phy_work(struct rtl8169_private *tp)
3653 {
3654 struct timer_list *timer = &tp->timer;
3655 void __iomem *ioaddr = tp->mmio_addr;
3656 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3657
3658 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3659
3660 if (tp->phy_reset_pending(tp)) {
3661 /*
3662 * A busy loop could burn quite a few cycles on nowadays CPU.
3663 * Let's delay the execution of the timer for a few ticks.
3664 */
3665 timeout = HZ/10;
3666 goto out_mod_timer;
3667 }
3668
3669 if (tp->link_ok(ioaddr))
3670 return;
3671
3672 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
3673
3674 tp->phy_reset_enable(tp);
3675
3676 out_mod_timer:
3677 mod_timer(timer, jiffies + timeout);
3678 }
3679
3680 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3681 {
3682 if (!test_and_set_bit(flag, tp->wk.flags))
3683 schedule_work(&tp->wk.work);
3684 }
3685
3686 static void rtl8169_phy_timer(unsigned long __opaque)
3687 {
3688 struct net_device *dev = (struct net_device *)__opaque;
3689 struct rtl8169_private *tp = netdev_priv(dev);
3690
3691 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3692 }
3693
3694 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3695 void __iomem *ioaddr)
3696 {
3697 iounmap(ioaddr);
3698 pci_release_regions(pdev);
3699 pci_clear_mwi(pdev);
3700 pci_disable_device(pdev);
3701 free_netdev(dev);
3702 }
3703
3704 DECLARE_RTL_COND(rtl_phy_reset_cond)
3705 {
3706 return tp->phy_reset_pending(tp);
3707 }
3708
3709 static void rtl8169_phy_reset(struct net_device *dev,
3710 struct rtl8169_private *tp)
3711 {
3712 tp->phy_reset_enable(tp);
3713 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
3714 }
3715
3716 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3717 {
3718 void __iomem *ioaddr = tp->mmio_addr;
3719
3720 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3721 (RTL_R8(PHYstatus) & TBI_Enable);
3722 }
3723
3724 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3725 {
3726 void __iomem *ioaddr = tp->mmio_addr;
3727
3728 rtl_hw_phy_config(dev);
3729
3730 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3731 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3732 RTL_W8(0x82, 0x01);
3733 }
3734
3735 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3736
3737 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3738 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3739
3740 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3741 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3742 RTL_W8(0x82, 0x01);
3743 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3744 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3745 }
3746
3747 rtl8169_phy_reset(dev, tp);
3748
3749 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3750 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3751 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3752 (tp->mii.supports_gmii ?
3753 ADVERTISED_1000baseT_Half |
3754 ADVERTISED_1000baseT_Full : 0));
3755
3756 if (rtl_tbi_enabled(tp))
3757 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3758 }
3759
3760 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3761 {
3762 void __iomem *ioaddr = tp->mmio_addr;
3763
3764 rtl_lock_work(tp);
3765
3766 RTL_W8(Cfg9346, Cfg9346_Unlock);
3767
3768 RTL_W32(MAC4, addr[4] | addr[5] << 8);
3769 RTL_R32(MAC4);
3770
3771 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3772 RTL_R32(MAC0);
3773
3774 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3775 rtl_rar_exgmac_set(tp, addr);
3776
3777 RTL_W8(Cfg9346, Cfg9346_Lock);
3778
3779 rtl_unlock_work(tp);
3780 }
3781
3782 static int rtl_set_mac_address(struct net_device *dev, void *p)
3783 {
3784 struct rtl8169_private *tp = netdev_priv(dev);
3785 struct sockaddr *addr = p;
3786
3787 if (!is_valid_ether_addr(addr->sa_data))
3788 return -EADDRNOTAVAIL;
3789
3790 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3791
3792 rtl_rar_set(tp, dev->dev_addr);
3793
3794 return 0;
3795 }
3796
3797 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3798 {
3799 struct rtl8169_private *tp = netdev_priv(dev);
3800 struct mii_ioctl_data *data = if_mii(ifr);
3801
3802 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3803 }
3804
3805 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3806 struct mii_ioctl_data *data, int cmd)
3807 {
3808 switch (cmd) {
3809 case SIOCGMIIPHY:
3810 data->phy_id = 32; /* Internal PHY */
3811 return 0;
3812
3813 case SIOCGMIIREG:
3814 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3815 return 0;
3816
3817 case SIOCSMIIREG:
3818 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3819 return 0;
3820 }
3821 return -EOPNOTSUPP;
3822 }
3823
3824 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3825 {
3826 return -EOPNOTSUPP;
3827 }
3828
3829 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3830 {
3831 if (tp->features & RTL_FEATURE_MSI) {
3832 pci_disable_msi(pdev);
3833 tp->features &= ~RTL_FEATURE_MSI;
3834 }
3835 }
3836
3837 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
3838 {
3839 struct mdio_ops *ops = &tp->mdio_ops;
3840
3841 switch (tp->mac_version) {
3842 case RTL_GIGA_MAC_VER_27:
3843 ops->write = r8168dp_1_mdio_write;
3844 ops->read = r8168dp_1_mdio_read;
3845 break;
3846 case RTL_GIGA_MAC_VER_28:
3847 case RTL_GIGA_MAC_VER_31:
3848 ops->write = r8168dp_2_mdio_write;
3849 ops->read = r8168dp_2_mdio_read;
3850 break;
3851 case RTL_GIGA_MAC_VER_40:
3852 case RTL_GIGA_MAC_VER_41:
3853 case RTL_GIGA_MAC_VER_42:
3854 case RTL_GIGA_MAC_VER_43:
3855 case RTL_GIGA_MAC_VER_44:
3856 ops->write = r8168g_mdio_write;
3857 ops->read = r8168g_mdio_read;
3858 break;
3859 default:
3860 ops->write = r8169_mdio_write;
3861 ops->read = r8169_mdio_read;
3862 break;
3863 }
3864 }
3865
3866 static void rtl_speed_down(struct rtl8169_private *tp)
3867 {
3868 u32 adv;
3869 int lpa;
3870
3871 rtl_writephy(tp, 0x1f, 0x0000);
3872 lpa = rtl_readphy(tp, MII_LPA);
3873
3874 if (lpa & (LPA_10HALF | LPA_10FULL))
3875 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
3876 else if (lpa & (LPA_100HALF | LPA_100FULL))
3877 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3878 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3879 else
3880 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3881 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3882 (tp->mii.supports_gmii ?
3883 ADVERTISED_1000baseT_Half |
3884 ADVERTISED_1000baseT_Full : 0);
3885
3886 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3887 adv);
3888 }
3889
3890 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3891 {
3892 void __iomem *ioaddr = tp->mmio_addr;
3893
3894 switch (tp->mac_version) {
3895 case RTL_GIGA_MAC_VER_25:
3896 case RTL_GIGA_MAC_VER_26:
3897 case RTL_GIGA_MAC_VER_29:
3898 case RTL_GIGA_MAC_VER_30:
3899 case RTL_GIGA_MAC_VER_32:
3900 case RTL_GIGA_MAC_VER_33:
3901 case RTL_GIGA_MAC_VER_34:
3902 case RTL_GIGA_MAC_VER_37:
3903 case RTL_GIGA_MAC_VER_38:
3904 case RTL_GIGA_MAC_VER_39:
3905 case RTL_GIGA_MAC_VER_40:
3906 case RTL_GIGA_MAC_VER_41:
3907 case RTL_GIGA_MAC_VER_42:
3908 case RTL_GIGA_MAC_VER_43:
3909 case RTL_GIGA_MAC_VER_44:
3910 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3911 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3912 break;
3913 default:
3914 break;
3915 }
3916 }
3917
3918 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3919 {
3920 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3921 return false;
3922
3923 rtl_speed_down(tp);
3924 rtl_wol_suspend_quirk(tp);
3925
3926 return true;
3927 }
3928
3929 static void r810x_phy_power_down(struct rtl8169_private *tp)
3930 {
3931 rtl_writephy(tp, 0x1f, 0x0000);
3932 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3933 }
3934
3935 static void r810x_phy_power_up(struct rtl8169_private *tp)
3936 {
3937 rtl_writephy(tp, 0x1f, 0x0000);
3938 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3939 }
3940
3941 static void r810x_pll_power_down(struct rtl8169_private *tp)
3942 {
3943 void __iomem *ioaddr = tp->mmio_addr;
3944
3945 if (rtl_wol_pll_power_down(tp))
3946 return;
3947
3948 r810x_phy_power_down(tp);
3949
3950 switch (tp->mac_version) {
3951 case RTL_GIGA_MAC_VER_07:
3952 case RTL_GIGA_MAC_VER_08:
3953 case RTL_GIGA_MAC_VER_09:
3954 case RTL_GIGA_MAC_VER_10:
3955 case RTL_GIGA_MAC_VER_13:
3956 case RTL_GIGA_MAC_VER_16:
3957 break;
3958 default:
3959 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3960 break;
3961 }
3962 }
3963
3964 static void r810x_pll_power_up(struct rtl8169_private *tp)
3965 {
3966 void __iomem *ioaddr = tp->mmio_addr;
3967
3968 r810x_phy_power_up(tp);
3969
3970 switch (tp->mac_version) {
3971 case RTL_GIGA_MAC_VER_07:
3972 case RTL_GIGA_MAC_VER_08:
3973 case RTL_GIGA_MAC_VER_09:
3974 case RTL_GIGA_MAC_VER_10:
3975 case RTL_GIGA_MAC_VER_13:
3976 case RTL_GIGA_MAC_VER_16:
3977 break;
3978 default:
3979 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3980 break;
3981 }
3982 }
3983
3984 static void r8168_phy_power_up(struct rtl8169_private *tp)
3985 {
3986 rtl_writephy(tp, 0x1f, 0x0000);
3987 switch (tp->mac_version) {
3988 case RTL_GIGA_MAC_VER_11:
3989 case RTL_GIGA_MAC_VER_12:
3990 case RTL_GIGA_MAC_VER_17:
3991 case RTL_GIGA_MAC_VER_18:
3992 case RTL_GIGA_MAC_VER_19:
3993 case RTL_GIGA_MAC_VER_20:
3994 case RTL_GIGA_MAC_VER_21:
3995 case RTL_GIGA_MAC_VER_22:
3996 case RTL_GIGA_MAC_VER_23:
3997 case RTL_GIGA_MAC_VER_24:
3998 case RTL_GIGA_MAC_VER_25:
3999 case RTL_GIGA_MAC_VER_26:
4000 case RTL_GIGA_MAC_VER_27:
4001 case RTL_GIGA_MAC_VER_28:
4002 case RTL_GIGA_MAC_VER_31:
4003 rtl_writephy(tp, 0x0e, 0x0000);
4004 break;
4005 default:
4006 break;
4007 }
4008 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4009 }
4010
4011 static void r8168_phy_power_down(struct rtl8169_private *tp)
4012 {
4013 rtl_writephy(tp, 0x1f, 0x0000);
4014 switch (tp->mac_version) {
4015 case RTL_GIGA_MAC_VER_32:
4016 case RTL_GIGA_MAC_VER_33:
4017 case RTL_GIGA_MAC_VER_40:
4018 case RTL_GIGA_MAC_VER_41:
4019 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4020 break;
4021
4022 case RTL_GIGA_MAC_VER_11:
4023 case RTL_GIGA_MAC_VER_12:
4024 case RTL_GIGA_MAC_VER_17:
4025 case RTL_GIGA_MAC_VER_18:
4026 case RTL_GIGA_MAC_VER_19:
4027 case RTL_GIGA_MAC_VER_20:
4028 case RTL_GIGA_MAC_VER_21:
4029 case RTL_GIGA_MAC_VER_22:
4030 case RTL_GIGA_MAC_VER_23:
4031 case RTL_GIGA_MAC_VER_24:
4032 case RTL_GIGA_MAC_VER_25:
4033 case RTL_GIGA_MAC_VER_26:
4034 case RTL_GIGA_MAC_VER_27:
4035 case RTL_GIGA_MAC_VER_28:
4036 case RTL_GIGA_MAC_VER_31:
4037 rtl_writephy(tp, 0x0e, 0x0200);
4038 default:
4039 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4040 break;
4041 }
4042 }
4043
4044 static void r8168_pll_power_down(struct rtl8169_private *tp)
4045 {
4046 void __iomem *ioaddr = tp->mmio_addr;
4047
4048 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4049 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4050 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4051 r8168dp_check_dash(tp)) {
4052 return;
4053 }
4054
4055 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4056 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4057 (RTL_R16(CPlusCmd) & ASF)) {
4058 return;
4059 }
4060
4061 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4062 tp->mac_version == RTL_GIGA_MAC_VER_33)
4063 rtl_ephy_write(tp, 0x19, 0xff64);
4064
4065 if (rtl_wol_pll_power_down(tp))
4066 return;
4067
4068 r8168_phy_power_down(tp);
4069
4070 switch (tp->mac_version) {
4071 case RTL_GIGA_MAC_VER_25:
4072 case RTL_GIGA_MAC_VER_26:
4073 case RTL_GIGA_MAC_VER_27:
4074 case RTL_GIGA_MAC_VER_28:
4075 case RTL_GIGA_MAC_VER_31:
4076 case RTL_GIGA_MAC_VER_32:
4077 case RTL_GIGA_MAC_VER_33:
4078 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4079 break;
4080 case RTL_GIGA_MAC_VER_40:
4081 case RTL_GIGA_MAC_VER_41:
4082 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4083 0xfc000000, ERIAR_EXGMAC);
4084 break;
4085 }
4086 }
4087
4088 static void r8168_pll_power_up(struct rtl8169_private *tp)
4089 {
4090 void __iomem *ioaddr = tp->mmio_addr;
4091
4092 switch (tp->mac_version) {
4093 case RTL_GIGA_MAC_VER_25:
4094 case RTL_GIGA_MAC_VER_26:
4095 case RTL_GIGA_MAC_VER_27:
4096 case RTL_GIGA_MAC_VER_28:
4097 case RTL_GIGA_MAC_VER_31:
4098 case RTL_GIGA_MAC_VER_32:
4099 case RTL_GIGA_MAC_VER_33:
4100 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4101 break;
4102 case RTL_GIGA_MAC_VER_40:
4103 case RTL_GIGA_MAC_VER_41:
4104 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4105 0x00000000, ERIAR_EXGMAC);
4106 break;
4107 }
4108
4109 r8168_phy_power_up(tp);
4110 }
4111
4112 static void rtl_generic_op(struct rtl8169_private *tp,
4113 void (*op)(struct rtl8169_private *))
4114 {
4115 if (op)
4116 op(tp);
4117 }
4118
4119 static void rtl_pll_power_down(struct rtl8169_private *tp)
4120 {
4121 rtl_generic_op(tp, tp->pll_power_ops.down);
4122 }
4123
4124 static void rtl_pll_power_up(struct rtl8169_private *tp)
4125 {
4126 rtl_generic_op(tp, tp->pll_power_ops.up);
4127 }
4128
4129 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4130 {
4131 struct pll_power_ops *ops = &tp->pll_power_ops;
4132
4133 switch (tp->mac_version) {
4134 case RTL_GIGA_MAC_VER_07:
4135 case RTL_GIGA_MAC_VER_08:
4136 case RTL_GIGA_MAC_VER_09:
4137 case RTL_GIGA_MAC_VER_10:
4138 case RTL_GIGA_MAC_VER_16:
4139 case RTL_GIGA_MAC_VER_29:
4140 case RTL_GIGA_MAC_VER_30:
4141 case RTL_GIGA_MAC_VER_37:
4142 case RTL_GIGA_MAC_VER_39:
4143 case RTL_GIGA_MAC_VER_43:
4144 ops->down = r810x_pll_power_down;
4145 ops->up = r810x_pll_power_up;
4146 break;
4147
4148 case RTL_GIGA_MAC_VER_11:
4149 case RTL_GIGA_MAC_VER_12:
4150 case RTL_GIGA_MAC_VER_17:
4151 case RTL_GIGA_MAC_VER_18:
4152 case RTL_GIGA_MAC_VER_19:
4153 case RTL_GIGA_MAC_VER_20:
4154 case RTL_GIGA_MAC_VER_21:
4155 case RTL_GIGA_MAC_VER_22:
4156 case RTL_GIGA_MAC_VER_23:
4157 case RTL_GIGA_MAC_VER_24:
4158 case RTL_GIGA_MAC_VER_25:
4159 case RTL_GIGA_MAC_VER_26:
4160 case RTL_GIGA_MAC_VER_27:
4161 case RTL_GIGA_MAC_VER_28:
4162 case RTL_GIGA_MAC_VER_31:
4163 case RTL_GIGA_MAC_VER_32:
4164 case RTL_GIGA_MAC_VER_33:
4165 case RTL_GIGA_MAC_VER_34:
4166 case RTL_GIGA_MAC_VER_35:
4167 case RTL_GIGA_MAC_VER_36:
4168 case RTL_GIGA_MAC_VER_38:
4169 case RTL_GIGA_MAC_VER_40:
4170 case RTL_GIGA_MAC_VER_41:
4171 case RTL_GIGA_MAC_VER_42:
4172 case RTL_GIGA_MAC_VER_44:
4173 ops->down = r8168_pll_power_down;
4174 ops->up = r8168_pll_power_up;
4175 break;
4176
4177 default:
4178 ops->down = NULL;
4179 ops->up = NULL;
4180 break;
4181 }
4182 }
4183
4184 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4185 {
4186 void __iomem *ioaddr = tp->mmio_addr;
4187
4188 switch (tp->mac_version) {
4189 case RTL_GIGA_MAC_VER_01:
4190 case RTL_GIGA_MAC_VER_02:
4191 case RTL_GIGA_MAC_VER_03:
4192 case RTL_GIGA_MAC_VER_04:
4193 case RTL_GIGA_MAC_VER_05:
4194 case RTL_GIGA_MAC_VER_06:
4195 case RTL_GIGA_MAC_VER_10:
4196 case RTL_GIGA_MAC_VER_11:
4197 case RTL_GIGA_MAC_VER_12:
4198 case RTL_GIGA_MAC_VER_13:
4199 case RTL_GIGA_MAC_VER_14:
4200 case RTL_GIGA_MAC_VER_15:
4201 case RTL_GIGA_MAC_VER_16:
4202 case RTL_GIGA_MAC_VER_17:
4203 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4204 break;
4205 case RTL_GIGA_MAC_VER_18:
4206 case RTL_GIGA_MAC_VER_19:
4207 case RTL_GIGA_MAC_VER_20:
4208 case RTL_GIGA_MAC_VER_21:
4209 case RTL_GIGA_MAC_VER_22:
4210 case RTL_GIGA_MAC_VER_23:
4211 case RTL_GIGA_MAC_VER_24:
4212 case RTL_GIGA_MAC_VER_34:
4213 case RTL_GIGA_MAC_VER_35:
4214 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4215 break;
4216 case RTL_GIGA_MAC_VER_40:
4217 case RTL_GIGA_MAC_VER_41:
4218 case RTL_GIGA_MAC_VER_42:
4219 case RTL_GIGA_MAC_VER_43:
4220 case RTL_GIGA_MAC_VER_44:
4221 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4222 break;
4223 default:
4224 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4225 break;
4226 }
4227 }
4228
4229 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4230 {
4231 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4232 }
4233
4234 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4235 {
4236 void __iomem *ioaddr = tp->mmio_addr;
4237
4238 RTL_W8(Cfg9346, Cfg9346_Unlock);
4239 rtl_generic_op(tp, tp->jumbo_ops.enable);
4240 RTL_W8(Cfg9346, Cfg9346_Lock);
4241 }
4242
4243 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4244 {
4245 void __iomem *ioaddr = tp->mmio_addr;
4246
4247 RTL_W8(Cfg9346, Cfg9346_Unlock);
4248 rtl_generic_op(tp, tp->jumbo_ops.disable);
4249 RTL_W8(Cfg9346, Cfg9346_Lock);
4250 }
4251
4252 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4253 {
4254 void __iomem *ioaddr = tp->mmio_addr;
4255
4256 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4257 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4258 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4259 }
4260
4261 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4262 {
4263 void __iomem *ioaddr = tp->mmio_addr;
4264
4265 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4266 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4267 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4268 }
4269
4270 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4271 {
4272 void __iomem *ioaddr = tp->mmio_addr;
4273
4274 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4275 }
4276
4277 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4278 {
4279 void __iomem *ioaddr = tp->mmio_addr;
4280
4281 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4282 }
4283
4284 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4285 {
4286 void __iomem *ioaddr = tp->mmio_addr;
4287
4288 RTL_W8(MaxTxPacketSize, 0x3f);
4289 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4290 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4291 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4292 }
4293
4294 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4295 {
4296 void __iomem *ioaddr = tp->mmio_addr;
4297
4298 RTL_W8(MaxTxPacketSize, 0x0c);
4299 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4300 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4301 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4302 }
4303
4304 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4305 {
4306 rtl_tx_performance_tweak(tp->pci_dev,
4307 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4308 }
4309
4310 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4311 {
4312 rtl_tx_performance_tweak(tp->pci_dev,
4313 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4314 }
4315
4316 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4317 {
4318 void __iomem *ioaddr = tp->mmio_addr;
4319
4320 r8168b_0_hw_jumbo_enable(tp);
4321
4322 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4323 }
4324
4325 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4326 {
4327 void __iomem *ioaddr = tp->mmio_addr;
4328
4329 r8168b_0_hw_jumbo_disable(tp);
4330
4331 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4332 }
4333
4334 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4335 {
4336 struct jumbo_ops *ops = &tp->jumbo_ops;
4337
4338 switch (tp->mac_version) {
4339 case RTL_GIGA_MAC_VER_11:
4340 ops->disable = r8168b_0_hw_jumbo_disable;
4341 ops->enable = r8168b_0_hw_jumbo_enable;
4342 break;
4343 case RTL_GIGA_MAC_VER_12:
4344 case RTL_GIGA_MAC_VER_17:
4345 ops->disable = r8168b_1_hw_jumbo_disable;
4346 ops->enable = r8168b_1_hw_jumbo_enable;
4347 break;
4348 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4349 case RTL_GIGA_MAC_VER_19:
4350 case RTL_GIGA_MAC_VER_20:
4351 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4352 case RTL_GIGA_MAC_VER_22:
4353 case RTL_GIGA_MAC_VER_23:
4354 case RTL_GIGA_MAC_VER_24:
4355 case RTL_GIGA_MAC_VER_25:
4356 case RTL_GIGA_MAC_VER_26:
4357 ops->disable = r8168c_hw_jumbo_disable;
4358 ops->enable = r8168c_hw_jumbo_enable;
4359 break;
4360 case RTL_GIGA_MAC_VER_27:
4361 case RTL_GIGA_MAC_VER_28:
4362 ops->disable = r8168dp_hw_jumbo_disable;
4363 ops->enable = r8168dp_hw_jumbo_enable;
4364 break;
4365 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4366 case RTL_GIGA_MAC_VER_32:
4367 case RTL_GIGA_MAC_VER_33:
4368 case RTL_GIGA_MAC_VER_34:
4369 ops->disable = r8168e_hw_jumbo_disable;
4370 ops->enable = r8168e_hw_jumbo_enable;
4371 break;
4372
4373 /*
4374 * No action needed for jumbo frames with 8169.
4375 * No jumbo for 810x at all.
4376 */
4377 case RTL_GIGA_MAC_VER_40:
4378 case RTL_GIGA_MAC_VER_41:
4379 case RTL_GIGA_MAC_VER_42:
4380 case RTL_GIGA_MAC_VER_43:
4381 case RTL_GIGA_MAC_VER_44:
4382 default:
4383 ops->disable = NULL;
4384 ops->enable = NULL;
4385 break;
4386 }
4387 }
4388
4389 DECLARE_RTL_COND(rtl_chipcmd_cond)
4390 {
4391 void __iomem *ioaddr = tp->mmio_addr;
4392
4393 return RTL_R8(ChipCmd) & CmdReset;
4394 }
4395
4396 static void rtl_hw_reset(struct rtl8169_private *tp)
4397 {
4398 void __iomem *ioaddr = tp->mmio_addr;
4399
4400 RTL_W8(ChipCmd, CmdReset);
4401
4402 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4403 }
4404
4405 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4406 {
4407 struct rtl_fw *rtl_fw;
4408 const char *name;
4409 int rc = -ENOMEM;
4410
4411 name = rtl_lookup_firmware_name(tp);
4412 if (!name)
4413 goto out_no_firmware;
4414
4415 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4416 if (!rtl_fw)
4417 goto err_warn;
4418
4419 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4420 if (rc < 0)
4421 goto err_free;
4422
4423 rc = rtl_check_firmware(tp, rtl_fw);
4424 if (rc < 0)
4425 goto err_release_firmware;
4426
4427 tp->rtl_fw = rtl_fw;
4428 out:
4429 return;
4430
4431 err_release_firmware:
4432 release_firmware(rtl_fw->fw);
4433 err_free:
4434 kfree(rtl_fw);
4435 err_warn:
4436 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4437 name, rc);
4438 out_no_firmware:
4439 tp->rtl_fw = NULL;
4440 goto out;
4441 }
4442
4443 static void rtl_request_firmware(struct rtl8169_private *tp)
4444 {
4445 if (IS_ERR(tp->rtl_fw))
4446 rtl_request_uncached_firmware(tp);
4447 }
4448
4449 static void rtl_rx_close(struct rtl8169_private *tp)
4450 {
4451 void __iomem *ioaddr = tp->mmio_addr;
4452
4453 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4454 }
4455
4456 DECLARE_RTL_COND(rtl_npq_cond)
4457 {
4458 void __iomem *ioaddr = tp->mmio_addr;
4459
4460 return RTL_R8(TxPoll) & NPQ;
4461 }
4462
4463 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4464 {
4465 void __iomem *ioaddr = tp->mmio_addr;
4466
4467 return RTL_R32(TxConfig) & TXCFG_EMPTY;
4468 }
4469
4470 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4471 {
4472 void __iomem *ioaddr = tp->mmio_addr;
4473
4474 /* Disable interrupts */
4475 rtl8169_irq_mask_and_ack(tp);
4476
4477 rtl_rx_close(tp);
4478
4479 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4480 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4481 tp->mac_version == RTL_GIGA_MAC_VER_31) {
4482 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4483 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4484 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4485 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
4486 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
4487 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4488 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
4489 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
4490 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
4491 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
4492 tp->mac_version == RTL_GIGA_MAC_VER_38) {
4493 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4494 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4495 } else {
4496 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4497 udelay(100);
4498 }
4499
4500 rtl_hw_reset(tp);
4501 }
4502
4503 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4504 {
4505 void __iomem *ioaddr = tp->mmio_addr;
4506
4507 /* Set DMA burst size and Interframe Gap Time */
4508 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4509 (InterFrameGap << TxInterFrameGapShift));
4510 }
4511
4512 static void rtl_hw_start(struct net_device *dev)
4513 {
4514 struct rtl8169_private *tp = netdev_priv(dev);
4515
4516 tp->hw_start(dev);
4517
4518 rtl_irq_enable_all(tp);
4519 }
4520
4521 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4522 void __iomem *ioaddr)
4523 {
4524 /*
4525 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4526 * register to be written before TxDescAddrLow to work.
4527 * Switching from MMIO to I/O access fixes the issue as well.
4528 */
4529 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4530 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4531 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4532 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4533 }
4534
4535 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4536 {
4537 u16 cmd;
4538
4539 cmd = RTL_R16(CPlusCmd);
4540 RTL_W16(CPlusCmd, cmd);
4541 return cmd;
4542 }
4543
4544 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4545 {
4546 /* Low hurts. Let's disable the filtering. */
4547 RTL_W16(RxMaxSize, rx_buf_sz + 1);
4548 }
4549
4550 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4551 {
4552 static const struct rtl_cfg2_info {
4553 u32 mac_version;
4554 u32 clk;
4555 u32 val;
4556 } cfg2_info [] = {
4557 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4558 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4559 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4560 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4561 };
4562 const struct rtl_cfg2_info *p = cfg2_info;
4563 unsigned int i;
4564 u32 clk;
4565
4566 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4567 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4568 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4569 RTL_W32(0x7c, p->val);
4570 break;
4571 }
4572 }
4573 }
4574
4575 static void rtl_set_rx_mode(struct net_device *dev)
4576 {
4577 struct rtl8169_private *tp = netdev_priv(dev);
4578 void __iomem *ioaddr = tp->mmio_addr;
4579 u32 mc_filter[2]; /* Multicast hash filter */
4580 int rx_mode;
4581 u32 tmp = 0;
4582
4583 if (dev->flags & IFF_PROMISC) {
4584 /* Unconditionally log net taps. */
4585 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4586 rx_mode =
4587 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4588 AcceptAllPhys;
4589 mc_filter[1] = mc_filter[0] = 0xffffffff;
4590 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4591 (dev->flags & IFF_ALLMULTI)) {
4592 /* Too many to filter perfectly -- accept all multicasts. */
4593 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4594 mc_filter[1] = mc_filter[0] = 0xffffffff;
4595 } else {
4596 struct netdev_hw_addr *ha;
4597
4598 rx_mode = AcceptBroadcast | AcceptMyPhys;
4599 mc_filter[1] = mc_filter[0] = 0;
4600 netdev_for_each_mc_addr(ha, dev) {
4601 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4602 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4603 rx_mode |= AcceptMulticast;
4604 }
4605 }
4606
4607 if (dev->features & NETIF_F_RXALL)
4608 rx_mode |= (AcceptErr | AcceptRunt);
4609
4610 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4611
4612 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4613 u32 data = mc_filter[0];
4614
4615 mc_filter[0] = swab32(mc_filter[1]);
4616 mc_filter[1] = swab32(data);
4617 }
4618
4619 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4620 mc_filter[1] = mc_filter[0] = 0xffffffff;
4621
4622 RTL_W32(MAR0 + 4, mc_filter[1]);
4623 RTL_W32(MAR0 + 0, mc_filter[0]);
4624
4625 RTL_W32(RxConfig, tmp);
4626 }
4627
4628 static void rtl_hw_start_8169(struct net_device *dev)
4629 {
4630 struct rtl8169_private *tp = netdev_priv(dev);
4631 void __iomem *ioaddr = tp->mmio_addr;
4632 struct pci_dev *pdev = tp->pci_dev;
4633
4634 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4635 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4636 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4637 }
4638
4639 RTL_W8(Cfg9346, Cfg9346_Unlock);
4640 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4641 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4642 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4643 tp->mac_version == RTL_GIGA_MAC_VER_04)
4644 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4645
4646 rtl_init_rxcfg(tp);
4647
4648 RTL_W8(EarlyTxThres, NoEarlyTx);
4649
4650 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4651
4652 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4653 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4654 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4655 tp->mac_version == RTL_GIGA_MAC_VER_04)
4656 rtl_set_rx_tx_config_registers(tp);
4657
4658 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4659
4660 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4661 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4662 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4663 "Bit-3 and bit-14 MUST be 1\n");
4664 tp->cp_cmd |= (1 << 14);
4665 }
4666
4667 RTL_W16(CPlusCmd, tp->cp_cmd);
4668
4669 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4670
4671 /*
4672 * Undocumented corner. Supposedly:
4673 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4674 */
4675 RTL_W16(IntrMitigate, 0x0000);
4676
4677 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4678
4679 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4680 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4681 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4682 tp->mac_version != RTL_GIGA_MAC_VER_04) {
4683 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4684 rtl_set_rx_tx_config_registers(tp);
4685 }
4686
4687 RTL_W8(Cfg9346, Cfg9346_Lock);
4688
4689 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4690 RTL_R8(IntrMask);
4691
4692 RTL_W32(RxMissed, 0);
4693
4694 rtl_set_rx_mode(dev);
4695
4696 /* no early-rx interrupts */
4697 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4698 }
4699
4700 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4701 {
4702 if (tp->csi_ops.write)
4703 tp->csi_ops.write(tp, addr, value);
4704 }
4705
4706 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4707 {
4708 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
4709 }
4710
4711 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
4712 {
4713 u32 csi;
4714
4715 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4716 rtl_csi_write(tp, 0x070c, csi | bits);
4717 }
4718
4719 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4720 {
4721 rtl_csi_access_enable(tp, 0x17000000);
4722 }
4723
4724 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
4725 {
4726 rtl_csi_access_enable(tp, 0x27000000);
4727 }
4728
4729 DECLARE_RTL_COND(rtl_csiar_cond)
4730 {
4731 void __iomem *ioaddr = tp->mmio_addr;
4732
4733 return RTL_R32(CSIAR) & CSIAR_FLAG;
4734 }
4735
4736 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
4737 {
4738 void __iomem *ioaddr = tp->mmio_addr;
4739
4740 RTL_W32(CSIDR, value);
4741 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4742 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4743
4744 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4745 }
4746
4747 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
4748 {
4749 void __iomem *ioaddr = tp->mmio_addr;
4750
4751 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4752 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4753
4754 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4755 RTL_R32(CSIDR) : ~0;
4756 }
4757
4758 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
4759 {
4760 void __iomem *ioaddr = tp->mmio_addr;
4761
4762 RTL_W32(CSIDR, value);
4763 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4764 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4765 CSIAR_FUNC_NIC);
4766
4767 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4768 }
4769
4770 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
4771 {
4772 void __iomem *ioaddr = tp->mmio_addr;
4773
4774 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4775 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4776
4777 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4778 RTL_R32(CSIDR) : ~0;
4779 }
4780
4781 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
4782 {
4783 void __iomem *ioaddr = tp->mmio_addr;
4784
4785 RTL_W32(CSIDR, value);
4786 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4787 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4788 CSIAR_FUNC_NIC2);
4789
4790 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4791 }
4792
4793 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
4794 {
4795 void __iomem *ioaddr = tp->mmio_addr;
4796
4797 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
4798 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4799
4800 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4801 RTL_R32(CSIDR) : ~0;
4802 }
4803
4804 static void rtl_init_csi_ops(struct rtl8169_private *tp)
4805 {
4806 struct csi_ops *ops = &tp->csi_ops;
4807
4808 switch (tp->mac_version) {
4809 case RTL_GIGA_MAC_VER_01:
4810 case RTL_GIGA_MAC_VER_02:
4811 case RTL_GIGA_MAC_VER_03:
4812 case RTL_GIGA_MAC_VER_04:
4813 case RTL_GIGA_MAC_VER_05:
4814 case RTL_GIGA_MAC_VER_06:
4815 case RTL_GIGA_MAC_VER_10:
4816 case RTL_GIGA_MAC_VER_11:
4817 case RTL_GIGA_MAC_VER_12:
4818 case RTL_GIGA_MAC_VER_13:
4819 case RTL_GIGA_MAC_VER_14:
4820 case RTL_GIGA_MAC_VER_15:
4821 case RTL_GIGA_MAC_VER_16:
4822 case RTL_GIGA_MAC_VER_17:
4823 ops->write = NULL;
4824 ops->read = NULL;
4825 break;
4826
4827 case RTL_GIGA_MAC_VER_37:
4828 case RTL_GIGA_MAC_VER_38:
4829 ops->write = r8402_csi_write;
4830 ops->read = r8402_csi_read;
4831 break;
4832
4833 case RTL_GIGA_MAC_VER_44:
4834 ops->write = r8411_csi_write;
4835 ops->read = r8411_csi_read;
4836 break;
4837
4838 default:
4839 ops->write = r8169_csi_write;
4840 ops->read = r8169_csi_read;
4841 break;
4842 }
4843 }
4844
4845 struct ephy_info {
4846 unsigned int offset;
4847 u16 mask;
4848 u16 bits;
4849 };
4850
4851 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4852 int len)
4853 {
4854 u16 w;
4855
4856 while (len-- > 0) {
4857 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4858 rtl_ephy_write(tp, e->offset, w);
4859 e++;
4860 }
4861 }
4862
4863 static void rtl_disable_clock_request(struct pci_dev *pdev)
4864 {
4865 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
4866 PCI_EXP_LNKCTL_CLKREQ_EN);
4867 }
4868
4869 static void rtl_enable_clock_request(struct pci_dev *pdev)
4870 {
4871 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
4872 PCI_EXP_LNKCTL_CLKREQ_EN);
4873 }
4874
4875 #define R8168_CPCMD_QUIRK_MASK (\
4876 EnableBist | \
4877 Mac_dbgo_oe | \
4878 Force_half_dup | \
4879 Force_rxflow_en | \
4880 Force_txflow_en | \
4881 Cxpl_dbg_sel | \
4882 ASF | \
4883 PktCntrDisable | \
4884 Mac_dbgo_sel)
4885
4886 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4887 {
4888 void __iomem *ioaddr = tp->mmio_addr;
4889 struct pci_dev *pdev = tp->pci_dev;
4890
4891 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4892
4893 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4894
4895 if (tp->dev->mtu <= ETH_DATA_LEN) {
4896 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
4897 PCI_EXP_DEVCTL_NOSNOOP_EN);
4898 }
4899 }
4900
4901 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4902 {
4903 void __iomem *ioaddr = tp->mmio_addr;
4904
4905 rtl_hw_start_8168bb(tp);
4906
4907 RTL_W8(MaxTxPacketSize, TxPacketMax);
4908
4909 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4910 }
4911
4912 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4913 {
4914 void __iomem *ioaddr = tp->mmio_addr;
4915 struct pci_dev *pdev = tp->pci_dev;
4916
4917 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4918
4919 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4920
4921 if (tp->dev->mtu <= ETH_DATA_LEN)
4922 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4923
4924 rtl_disable_clock_request(pdev);
4925
4926 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4927 }
4928
4929 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4930 {
4931 static const struct ephy_info e_info_8168cp[] = {
4932 { 0x01, 0, 0x0001 },
4933 { 0x02, 0x0800, 0x1000 },
4934 { 0x03, 0, 0x0042 },
4935 { 0x06, 0x0080, 0x0000 },
4936 { 0x07, 0, 0x2000 }
4937 };
4938
4939 rtl_csi_access_enable_2(tp);
4940
4941 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4942
4943 __rtl_hw_start_8168cp(tp);
4944 }
4945
4946 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4947 {
4948 void __iomem *ioaddr = tp->mmio_addr;
4949 struct pci_dev *pdev = tp->pci_dev;
4950
4951 rtl_csi_access_enable_2(tp);
4952
4953 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4954
4955 if (tp->dev->mtu <= ETH_DATA_LEN)
4956 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4957
4958 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4959 }
4960
4961 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4962 {
4963 void __iomem *ioaddr = tp->mmio_addr;
4964 struct pci_dev *pdev = tp->pci_dev;
4965
4966 rtl_csi_access_enable_2(tp);
4967
4968 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4969
4970 /* Magic. */
4971 RTL_W8(DBG_REG, 0x20);
4972
4973 RTL_W8(MaxTxPacketSize, TxPacketMax);
4974
4975 if (tp->dev->mtu <= ETH_DATA_LEN)
4976 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4977
4978 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4979 }
4980
4981 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4982 {
4983 void __iomem *ioaddr = tp->mmio_addr;
4984 static const struct ephy_info e_info_8168c_1[] = {
4985 { 0x02, 0x0800, 0x1000 },
4986 { 0x03, 0, 0x0002 },
4987 { 0x06, 0x0080, 0x0000 }
4988 };
4989
4990 rtl_csi_access_enable_2(tp);
4991
4992 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4993
4994 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4995
4996 __rtl_hw_start_8168cp(tp);
4997 }
4998
4999 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5000 {
5001 static const struct ephy_info e_info_8168c_2[] = {
5002 { 0x01, 0, 0x0001 },
5003 { 0x03, 0x0400, 0x0220 }
5004 };
5005
5006 rtl_csi_access_enable_2(tp);
5007
5008 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5009
5010 __rtl_hw_start_8168cp(tp);
5011 }
5012
5013 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5014 {
5015 rtl_hw_start_8168c_2(tp);
5016 }
5017
5018 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5019 {
5020 rtl_csi_access_enable_2(tp);
5021
5022 __rtl_hw_start_8168cp(tp);
5023 }
5024
5025 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5026 {
5027 void __iomem *ioaddr = tp->mmio_addr;
5028 struct pci_dev *pdev = tp->pci_dev;
5029
5030 rtl_csi_access_enable_2(tp);
5031
5032 rtl_disable_clock_request(pdev);
5033
5034 RTL_W8(MaxTxPacketSize, TxPacketMax);
5035
5036 if (tp->dev->mtu <= ETH_DATA_LEN)
5037 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5038
5039 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5040 }
5041
5042 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5043 {
5044 void __iomem *ioaddr = tp->mmio_addr;
5045 struct pci_dev *pdev = tp->pci_dev;
5046
5047 rtl_csi_access_enable_1(tp);
5048
5049 if (tp->dev->mtu <= ETH_DATA_LEN)
5050 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5051
5052 RTL_W8(MaxTxPacketSize, TxPacketMax);
5053
5054 rtl_disable_clock_request(pdev);
5055 }
5056
5057 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5058 {
5059 void __iomem *ioaddr = tp->mmio_addr;
5060 struct pci_dev *pdev = tp->pci_dev;
5061 static const struct ephy_info e_info_8168d_4[] = {
5062 { 0x0b, ~0, 0x48 },
5063 { 0x19, 0x20, 0x50 },
5064 { 0x0c, ~0, 0x20 }
5065 };
5066 int i;
5067
5068 rtl_csi_access_enable_1(tp);
5069
5070 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5071
5072 RTL_W8(MaxTxPacketSize, TxPacketMax);
5073
5074 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5075 const struct ephy_info *e = e_info_8168d_4 + i;
5076 u16 w;
5077
5078 w = rtl_ephy_read(tp, e->offset);
5079 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
5080 }
5081
5082 rtl_enable_clock_request(pdev);
5083 }
5084
5085 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5086 {
5087 void __iomem *ioaddr = tp->mmio_addr;
5088 struct pci_dev *pdev = tp->pci_dev;
5089 static const struct ephy_info e_info_8168e_1[] = {
5090 { 0x00, 0x0200, 0x0100 },
5091 { 0x00, 0x0000, 0x0004 },
5092 { 0x06, 0x0002, 0x0001 },
5093 { 0x06, 0x0000, 0x0030 },
5094 { 0x07, 0x0000, 0x2000 },
5095 { 0x00, 0x0000, 0x0020 },
5096 { 0x03, 0x5800, 0x2000 },
5097 { 0x03, 0x0000, 0x0001 },
5098 { 0x01, 0x0800, 0x1000 },
5099 { 0x07, 0x0000, 0x4000 },
5100 { 0x1e, 0x0000, 0x2000 },
5101 { 0x19, 0xffff, 0xfe6c },
5102 { 0x0a, 0x0000, 0x0040 }
5103 };
5104
5105 rtl_csi_access_enable_2(tp);
5106
5107 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5108
5109 if (tp->dev->mtu <= ETH_DATA_LEN)
5110 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5111
5112 RTL_W8(MaxTxPacketSize, TxPacketMax);
5113
5114 rtl_disable_clock_request(pdev);
5115
5116 /* Reset tx FIFO pointer */
5117 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5118 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5119
5120 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5121 }
5122
5123 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5124 {
5125 void __iomem *ioaddr = tp->mmio_addr;
5126 struct pci_dev *pdev = tp->pci_dev;
5127 static const struct ephy_info e_info_8168e_2[] = {
5128 { 0x09, 0x0000, 0x0080 },
5129 { 0x19, 0x0000, 0x0224 }
5130 };
5131
5132 rtl_csi_access_enable_1(tp);
5133
5134 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5135
5136 if (tp->dev->mtu <= ETH_DATA_LEN)
5137 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5138
5139 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5140 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5141 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5142 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5143 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5144 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5145 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5146 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5147
5148 RTL_W8(MaxTxPacketSize, EarlySize);
5149
5150 rtl_disable_clock_request(pdev);
5151
5152 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5153 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5154
5155 /* Adjust EEE LED frequency */
5156 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5157
5158 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5159 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5160 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5161 }
5162
5163 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5164 {
5165 void __iomem *ioaddr = tp->mmio_addr;
5166 struct pci_dev *pdev = tp->pci_dev;
5167
5168 rtl_csi_access_enable_2(tp);
5169
5170 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5171
5172 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5173 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5174 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5175 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5176 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5177 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5178 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5179 rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5180 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5181 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5182
5183 RTL_W8(MaxTxPacketSize, EarlySize);
5184
5185 rtl_disable_clock_request(pdev);
5186
5187 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5188 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5189 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5190 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5191 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5192 }
5193
5194 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5195 {
5196 void __iomem *ioaddr = tp->mmio_addr;
5197 static const struct ephy_info e_info_8168f_1[] = {
5198 { 0x06, 0x00c0, 0x0020 },
5199 { 0x08, 0x0001, 0x0002 },
5200 { 0x09, 0x0000, 0x0080 },
5201 { 0x19, 0x0000, 0x0224 }
5202 };
5203
5204 rtl_hw_start_8168f(tp);
5205
5206 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5207
5208 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5209
5210 /* Adjust EEE LED frequency */
5211 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5212 }
5213
5214 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5215 {
5216 static const struct ephy_info e_info_8168f_1[] = {
5217 { 0x06, 0x00c0, 0x0020 },
5218 { 0x0f, 0xffff, 0x5200 },
5219 { 0x1e, 0x0000, 0x4000 },
5220 { 0x19, 0x0000, 0x0224 }
5221 };
5222
5223 rtl_hw_start_8168f(tp);
5224
5225 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5226
5227 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5228 }
5229
5230 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5231 {
5232 void __iomem *ioaddr = tp->mmio_addr;
5233 struct pci_dev *pdev = tp->pci_dev;
5234
5235 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5236
5237 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5238 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5239 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5240 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5241
5242 rtl_csi_access_enable_1(tp);
5243
5244 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5245
5246 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5247 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5248 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5249
5250 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5251 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5252 RTL_W8(MaxTxPacketSize, EarlySize);
5253
5254 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5255 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5256
5257 /* Adjust EEE LED frequency */
5258 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5259
5260 rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5261 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5262 }
5263
5264 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5265 {
5266 void __iomem *ioaddr = tp->mmio_addr;
5267 static const struct ephy_info e_info_8168g_2[] = {
5268 { 0x00, 0x0000, 0x0008 },
5269 { 0x0c, 0x3df0, 0x0200 },
5270 { 0x19, 0xffff, 0xfc00 },
5271 { 0x1e, 0xffff, 0x20eb }
5272 };
5273
5274 rtl_hw_start_8168g_1(tp);
5275
5276 /* disable aspm and clock request before access ephy */
5277 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5278 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5279 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5280 }
5281
5282 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5283 {
5284 void __iomem *ioaddr = tp->mmio_addr;
5285 static const struct ephy_info e_info_8411_2[] = {
5286 { 0x00, 0x0000, 0x0008 },
5287 { 0x0c, 0x3df0, 0x0200 },
5288 { 0x0f, 0xffff, 0x5200 },
5289 { 0x19, 0x0020, 0x0000 },
5290 { 0x1e, 0x0000, 0x2000 }
5291 };
5292
5293 rtl_hw_start_8168g_1(tp);
5294
5295 /* disable aspm and clock request before access ephy */
5296 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5297 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5298 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5299 }
5300
5301 static void rtl_hw_start_8168(struct net_device *dev)
5302 {
5303 struct rtl8169_private *tp = netdev_priv(dev);
5304 void __iomem *ioaddr = tp->mmio_addr;
5305
5306 RTL_W8(Cfg9346, Cfg9346_Unlock);
5307
5308 RTL_W8(MaxTxPacketSize, TxPacketMax);
5309
5310 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5311
5312 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
5313
5314 RTL_W16(CPlusCmd, tp->cp_cmd);
5315
5316 RTL_W16(IntrMitigate, 0x5151);
5317
5318 /* Work around for RxFIFO overflow. */
5319 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5320 tp->event_slow |= RxFIFOOver | PCSTimeout;
5321 tp->event_slow &= ~RxOverflow;
5322 }
5323
5324 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5325
5326 rtl_set_rx_tx_config_registers(tp);
5327
5328 RTL_R8(IntrMask);
5329
5330 switch (tp->mac_version) {
5331 case RTL_GIGA_MAC_VER_11:
5332 rtl_hw_start_8168bb(tp);
5333 break;
5334
5335 case RTL_GIGA_MAC_VER_12:
5336 case RTL_GIGA_MAC_VER_17:
5337 rtl_hw_start_8168bef(tp);
5338 break;
5339
5340 case RTL_GIGA_MAC_VER_18:
5341 rtl_hw_start_8168cp_1(tp);
5342 break;
5343
5344 case RTL_GIGA_MAC_VER_19:
5345 rtl_hw_start_8168c_1(tp);
5346 break;
5347
5348 case RTL_GIGA_MAC_VER_20:
5349 rtl_hw_start_8168c_2(tp);
5350 break;
5351
5352 case RTL_GIGA_MAC_VER_21:
5353 rtl_hw_start_8168c_3(tp);
5354 break;
5355
5356 case RTL_GIGA_MAC_VER_22:
5357 rtl_hw_start_8168c_4(tp);
5358 break;
5359
5360 case RTL_GIGA_MAC_VER_23:
5361 rtl_hw_start_8168cp_2(tp);
5362 break;
5363
5364 case RTL_GIGA_MAC_VER_24:
5365 rtl_hw_start_8168cp_3(tp);
5366 break;
5367
5368 case RTL_GIGA_MAC_VER_25:
5369 case RTL_GIGA_MAC_VER_26:
5370 case RTL_GIGA_MAC_VER_27:
5371 rtl_hw_start_8168d(tp);
5372 break;
5373
5374 case RTL_GIGA_MAC_VER_28:
5375 rtl_hw_start_8168d_4(tp);
5376 break;
5377
5378 case RTL_GIGA_MAC_VER_31:
5379 rtl_hw_start_8168dp(tp);
5380 break;
5381
5382 case RTL_GIGA_MAC_VER_32:
5383 case RTL_GIGA_MAC_VER_33:
5384 rtl_hw_start_8168e_1(tp);
5385 break;
5386 case RTL_GIGA_MAC_VER_34:
5387 rtl_hw_start_8168e_2(tp);
5388 break;
5389
5390 case RTL_GIGA_MAC_VER_35:
5391 case RTL_GIGA_MAC_VER_36:
5392 rtl_hw_start_8168f_1(tp);
5393 break;
5394
5395 case RTL_GIGA_MAC_VER_38:
5396 rtl_hw_start_8411(tp);
5397 break;
5398
5399 case RTL_GIGA_MAC_VER_40:
5400 case RTL_GIGA_MAC_VER_41:
5401 rtl_hw_start_8168g_1(tp);
5402 break;
5403 case RTL_GIGA_MAC_VER_42:
5404 rtl_hw_start_8168g_2(tp);
5405 break;
5406
5407 case RTL_GIGA_MAC_VER_44:
5408 rtl_hw_start_8411_2(tp);
5409 break;
5410
5411 default:
5412 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5413 dev->name, tp->mac_version);
5414 break;
5415 }
5416
5417 RTL_W8(Cfg9346, Cfg9346_Lock);
5418
5419 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5420
5421 rtl_set_rx_mode(dev);
5422
5423 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
5424 }
5425
5426 #define R810X_CPCMD_QUIRK_MASK (\
5427 EnableBist | \
5428 Mac_dbgo_oe | \
5429 Force_half_dup | \
5430 Force_rxflow_en | \
5431 Force_txflow_en | \
5432 Cxpl_dbg_sel | \
5433 ASF | \
5434 PktCntrDisable | \
5435 Mac_dbgo_sel)
5436
5437 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5438 {
5439 void __iomem *ioaddr = tp->mmio_addr;
5440 struct pci_dev *pdev = tp->pci_dev;
5441 static const struct ephy_info e_info_8102e_1[] = {
5442 { 0x01, 0, 0x6e65 },
5443 { 0x02, 0, 0x091f },
5444 { 0x03, 0, 0xc2f9 },
5445 { 0x06, 0, 0xafb5 },
5446 { 0x07, 0, 0x0e00 },
5447 { 0x19, 0, 0xec80 },
5448 { 0x01, 0, 0x2e65 },
5449 { 0x01, 0, 0x6e65 }
5450 };
5451 u8 cfg1;
5452
5453 rtl_csi_access_enable_2(tp);
5454
5455 RTL_W8(DBG_REG, FIX_NAK_1);
5456
5457 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5458
5459 RTL_W8(Config1,
5460 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5461 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5462
5463 cfg1 = RTL_R8(Config1);
5464 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5465 RTL_W8(Config1, cfg1 & ~LEDS0);
5466
5467 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5468 }
5469
5470 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5471 {
5472 void __iomem *ioaddr = tp->mmio_addr;
5473 struct pci_dev *pdev = tp->pci_dev;
5474
5475 rtl_csi_access_enable_2(tp);
5476
5477 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5478
5479 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5480 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5481 }
5482
5483 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5484 {
5485 rtl_hw_start_8102e_2(tp);
5486
5487 rtl_ephy_write(tp, 0x03, 0xc2f9);
5488 }
5489
5490 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5491 {
5492 void __iomem *ioaddr = tp->mmio_addr;
5493 static const struct ephy_info e_info_8105e_1[] = {
5494 { 0x07, 0, 0x4000 },
5495 { 0x19, 0, 0x0200 },
5496 { 0x19, 0, 0x0020 },
5497 { 0x1e, 0, 0x2000 },
5498 { 0x03, 0, 0x0001 },
5499 { 0x19, 0, 0x0100 },
5500 { 0x19, 0, 0x0004 },
5501 { 0x0a, 0, 0x0020 }
5502 };
5503
5504 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5505 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5506
5507 /* Disable Early Tally Counter */
5508 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5509
5510 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5511 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5512
5513 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5514 }
5515
5516 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5517 {
5518 rtl_hw_start_8105e_1(tp);
5519 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5520 }
5521
5522 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5523 {
5524 void __iomem *ioaddr = tp->mmio_addr;
5525 static const struct ephy_info e_info_8402[] = {
5526 { 0x19, 0xffff, 0xff64 },
5527 { 0x1e, 0, 0x4000 }
5528 };
5529
5530 rtl_csi_access_enable_2(tp);
5531
5532 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5533 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5534
5535 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5536 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5537
5538 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5539
5540 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5541
5542 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5543 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5544 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5545 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5546 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5547 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5548 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5549 }
5550
5551 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5552 {
5553 void __iomem *ioaddr = tp->mmio_addr;
5554
5555 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5556 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5557
5558 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5559 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5560 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5561 }
5562
5563 static void rtl_hw_start_8101(struct net_device *dev)
5564 {
5565 struct rtl8169_private *tp = netdev_priv(dev);
5566 void __iomem *ioaddr = tp->mmio_addr;
5567 struct pci_dev *pdev = tp->pci_dev;
5568
5569 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5570 tp->event_slow &= ~RxFIFOOver;
5571
5572 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5573 tp->mac_version == RTL_GIGA_MAC_VER_16)
5574 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
5575 PCI_EXP_DEVCTL_NOSNOOP_EN);
5576
5577 RTL_W8(Cfg9346, Cfg9346_Unlock);
5578
5579 RTL_W8(MaxTxPacketSize, TxPacketMax);
5580
5581 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5582
5583 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5584 RTL_W16(CPlusCmd, tp->cp_cmd);
5585
5586 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5587
5588 rtl_set_rx_tx_config_registers(tp);
5589
5590 switch (tp->mac_version) {
5591 case RTL_GIGA_MAC_VER_07:
5592 rtl_hw_start_8102e_1(tp);
5593 break;
5594
5595 case RTL_GIGA_MAC_VER_08:
5596 rtl_hw_start_8102e_3(tp);
5597 break;
5598
5599 case RTL_GIGA_MAC_VER_09:
5600 rtl_hw_start_8102e_2(tp);
5601 break;
5602
5603 case RTL_GIGA_MAC_VER_29:
5604 rtl_hw_start_8105e_1(tp);
5605 break;
5606 case RTL_GIGA_MAC_VER_30:
5607 rtl_hw_start_8105e_2(tp);
5608 break;
5609
5610 case RTL_GIGA_MAC_VER_37:
5611 rtl_hw_start_8402(tp);
5612 break;
5613
5614 case RTL_GIGA_MAC_VER_39:
5615 rtl_hw_start_8106(tp);
5616 break;
5617 case RTL_GIGA_MAC_VER_43:
5618 rtl_hw_start_8168g_2(tp);
5619 break;
5620 }
5621
5622 RTL_W8(Cfg9346, Cfg9346_Lock);
5623
5624 RTL_W16(IntrMitigate, 0x0000);
5625
5626 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5627
5628 rtl_set_rx_mode(dev);
5629
5630 RTL_R8(IntrMask);
5631
5632 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5633 }
5634
5635 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5636 {
5637 struct rtl8169_private *tp = netdev_priv(dev);
5638
5639 if (new_mtu < ETH_ZLEN ||
5640 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
5641 return -EINVAL;
5642
5643 if (new_mtu > ETH_DATA_LEN)
5644 rtl_hw_jumbo_enable(tp);
5645 else
5646 rtl_hw_jumbo_disable(tp);
5647
5648 dev->mtu = new_mtu;
5649 netdev_update_features(dev);
5650
5651 return 0;
5652 }
5653
5654 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5655 {
5656 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5657 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5658 }
5659
5660 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5661 void **data_buff, struct RxDesc *desc)
5662 {
5663 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
5664 DMA_FROM_DEVICE);
5665
5666 kfree(*data_buff);
5667 *data_buff = NULL;
5668 rtl8169_make_unusable_by_asic(desc);
5669 }
5670
5671 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5672 {
5673 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5674
5675 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5676 }
5677
5678 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5679 u32 rx_buf_sz)
5680 {
5681 desc->addr = cpu_to_le64(mapping);
5682 wmb();
5683 rtl8169_mark_to_asic(desc, rx_buf_sz);
5684 }
5685
5686 static inline void *rtl8169_align(void *data)
5687 {
5688 return (void *)ALIGN((long)data, 16);
5689 }
5690
5691 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5692 struct RxDesc *desc)
5693 {
5694 void *data;
5695 dma_addr_t mapping;
5696 struct device *d = &tp->pci_dev->dev;
5697 struct net_device *dev = tp->dev;
5698 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
5699
5700 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5701 if (!data)
5702 return NULL;
5703
5704 if (rtl8169_align(data) != data) {
5705 kfree(data);
5706 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5707 if (!data)
5708 return NULL;
5709 }
5710
5711 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5712 DMA_FROM_DEVICE);
5713 if (unlikely(dma_mapping_error(d, mapping))) {
5714 if (net_ratelimit())
5715 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5716 goto err_out;
5717 }
5718
5719 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5720 return data;
5721
5722 err_out:
5723 kfree(data);
5724 return NULL;
5725 }
5726
5727 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5728 {
5729 unsigned int i;
5730
5731 for (i = 0; i < NUM_RX_DESC; i++) {
5732 if (tp->Rx_databuff[i]) {
5733 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5734 tp->RxDescArray + i);
5735 }
5736 }
5737 }
5738
5739 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5740 {
5741 desc->opts1 |= cpu_to_le32(RingEnd);
5742 }
5743
5744 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5745 {
5746 unsigned int i;
5747
5748 for (i = 0; i < NUM_RX_DESC; i++) {
5749 void *data;
5750
5751 if (tp->Rx_databuff[i])
5752 continue;
5753
5754 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5755 if (!data) {
5756 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5757 goto err_out;
5758 }
5759 tp->Rx_databuff[i] = data;
5760 }
5761
5762 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5763 return 0;
5764
5765 err_out:
5766 rtl8169_rx_clear(tp);
5767 return -ENOMEM;
5768 }
5769
5770 static int rtl8169_init_ring(struct net_device *dev)
5771 {
5772 struct rtl8169_private *tp = netdev_priv(dev);
5773
5774 rtl8169_init_ring_indexes(tp);
5775
5776 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5777 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5778
5779 return rtl8169_rx_fill(tp);
5780 }
5781
5782 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5783 struct TxDesc *desc)
5784 {
5785 unsigned int len = tx_skb->len;
5786
5787 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5788
5789 desc->opts1 = 0x00;
5790 desc->opts2 = 0x00;
5791 desc->addr = 0x00;
5792 tx_skb->len = 0;
5793 }
5794
5795 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5796 unsigned int n)
5797 {
5798 unsigned int i;
5799
5800 for (i = 0; i < n; i++) {
5801 unsigned int entry = (start + i) % NUM_TX_DESC;
5802 struct ring_info *tx_skb = tp->tx_skb + entry;
5803 unsigned int len = tx_skb->len;
5804
5805 if (len) {
5806 struct sk_buff *skb = tx_skb->skb;
5807
5808 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5809 tp->TxDescArray + entry);
5810 if (skb) {
5811 tp->dev->stats.tx_dropped++;
5812 dev_kfree_skb_any(skb);
5813 tx_skb->skb = NULL;
5814 }
5815 }
5816 }
5817 }
5818
5819 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5820 {
5821 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5822 tp->cur_tx = tp->dirty_tx = 0;
5823 }
5824
5825 static void rtl_reset_work(struct rtl8169_private *tp)
5826 {
5827 struct net_device *dev = tp->dev;
5828 int i;
5829
5830 napi_disable(&tp->napi);
5831 netif_stop_queue(dev);
5832 synchronize_sched();
5833
5834 rtl8169_hw_reset(tp);
5835
5836 for (i = 0; i < NUM_RX_DESC; i++)
5837 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5838
5839 rtl8169_tx_clear(tp);
5840 rtl8169_init_ring_indexes(tp);
5841
5842 napi_enable(&tp->napi);
5843 rtl_hw_start(dev);
5844 netif_wake_queue(dev);
5845 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5846 }
5847
5848 static void rtl8169_tx_timeout(struct net_device *dev)
5849 {
5850 struct rtl8169_private *tp = netdev_priv(dev);
5851
5852 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5853 }
5854
5855 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5856 u32 *opts)
5857 {
5858 struct skb_shared_info *info = skb_shinfo(skb);
5859 unsigned int cur_frag, entry;
5860 struct TxDesc * uninitialized_var(txd);
5861 struct device *d = &tp->pci_dev->dev;
5862
5863 entry = tp->cur_tx;
5864 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5865 const skb_frag_t *frag = info->frags + cur_frag;
5866 dma_addr_t mapping;
5867 u32 status, len;
5868 void *addr;
5869
5870 entry = (entry + 1) % NUM_TX_DESC;
5871
5872 txd = tp->TxDescArray + entry;
5873 len = skb_frag_size(frag);
5874 addr = skb_frag_address(frag);
5875 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5876 if (unlikely(dma_mapping_error(d, mapping))) {
5877 if (net_ratelimit())
5878 netif_err(tp, drv, tp->dev,
5879 "Failed to map TX fragments DMA!\n");
5880 goto err_out;
5881 }
5882
5883 /* Anti gcc 2.95.3 bugware (sic) */
5884 status = opts[0] | len |
5885 (RingEnd * !((entry + 1) % NUM_TX_DESC));
5886
5887 txd->opts1 = cpu_to_le32(status);
5888 txd->opts2 = cpu_to_le32(opts[1]);
5889 txd->addr = cpu_to_le64(mapping);
5890
5891 tp->tx_skb[entry].len = len;
5892 }
5893
5894 if (cur_frag) {
5895 tp->tx_skb[entry].skb = skb;
5896 txd->opts1 |= cpu_to_le32(LastFrag);
5897 }
5898
5899 return cur_frag;
5900
5901 err_out:
5902 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5903 return -EIO;
5904 }
5905
5906 static bool rtl_skb_pad(struct sk_buff *skb)
5907 {
5908 if (skb_padto(skb, ETH_ZLEN))
5909 return false;
5910 skb_put(skb, ETH_ZLEN - skb->len);
5911 return true;
5912 }
5913
5914 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5915 {
5916 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5917 }
5918
5919 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
5920 struct sk_buff *skb, u32 *opts)
5921 {
5922 u32 mss = skb_shinfo(skb)->gso_size;
5923
5924 if (mss) {
5925 opts[0] |= TD_LSO;
5926 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5927 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5928 const struct iphdr *ip = ip_hdr(skb);
5929
5930 if (ip->protocol == IPPROTO_TCP)
5931 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5932 else if (ip->protocol == IPPROTO_UDP)
5933 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5934 else
5935 WARN_ON_ONCE(1);
5936 }
5937
5938 return true;
5939 }
5940
5941 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5942 struct sk_buff *skb, u32 *opts)
5943 {
5944 u32 mss = skb_shinfo(skb)->gso_size;
5945
5946 if (mss) {
5947 opts[0] |= TD_LSO;
5948 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5949 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5950 const struct iphdr *ip = ip_hdr(skb);
5951
5952 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5953 return skb_checksum_help(skb) == 0 && rtl_skb_pad(skb);
5954
5955 if (ip->protocol == IPPROTO_TCP)
5956 opts[1] |= TD1_IP_CS | TD1_TCP_CS;
5957 else if (ip->protocol == IPPROTO_UDP)
5958 opts[1] |= TD1_IP_CS | TD1_UDP_CS;
5959 else
5960 WARN_ON_ONCE(1);
5961 } else {
5962 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5963 return rtl_skb_pad(skb);
5964 }
5965
5966 return true;
5967 }
5968
5969 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5970 struct net_device *dev)
5971 {
5972 struct rtl8169_private *tp = netdev_priv(dev);
5973 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5974 struct TxDesc *txd = tp->TxDescArray + entry;
5975 void __iomem *ioaddr = tp->mmio_addr;
5976 struct device *d = &tp->pci_dev->dev;
5977 dma_addr_t mapping;
5978 u32 status, len;
5979 u32 opts[2];
5980 int frags;
5981
5982 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5983 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5984 goto err_stop_0;
5985 }
5986
5987 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5988 goto err_stop_0;
5989
5990 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
5991 opts[0] = DescOwn;
5992
5993 if (!tp->tso_csum(tp, skb, opts))
5994 goto err_update_stats;
5995
5996 len = skb_headlen(skb);
5997 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5998 if (unlikely(dma_mapping_error(d, mapping))) {
5999 if (net_ratelimit())
6000 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6001 goto err_dma_0;
6002 }
6003
6004 tp->tx_skb[entry].len = len;
6005 txd->addr = cpu_to_le64(mapping);
6006
6007 frags = rtl8169_xmit_frags(tp, skb, opts);
6008 if (frags < 0)
6009 goto err_dma_1;
6010 else if (frags)
6011 opts[0] |= FirstFrag;
6012 else {
6013 opts[0] |= FirstFrag | LastFrag;
6014 tp->tx_skb[entry].skb = skb;
6015 }
6016
6017 txd->opts2 = cpu_to_le32(opts[1]);
6018
6019 skb_tx_timestamp(skb);
6020
6021 wmb();
6022
6023 /* Anti gcc 2.95.3 bugware (sic) */
6024 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
6025 txd->opts1 = cpu_to_le32(status);
6026
6027 tp->cur_tx += frags + 1;
6028
6029 wmb();
6030
6031 RTL_W8(TxPoll, NPQ);
6032
6033 mmiowb();
6034
6035 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6036 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6037 * not miss a ring update when it notices a stopped queue.
6038 */
6039 smp_wmb();
6040 netif_stop_queue(dev);
6041 /* Sync with rtl_tx:
6042 * - publish queue status and cur_tx ring index (write barrier)
6043 * - refresh dirty_tx ring index (read barrier).
6044 * May the current thread have a pessimistic view of the ring
6045 * status and forget to wake up queue, a racing rtl_tx thread
6046 * can't.
6047 */
6048 smp_mb();
6049 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
6050 netif_wake_queue(dev);
6051 }
6052
6053 return NETDEV_TX_OK;
6054
6055 err_dma_1:
6056 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6057 err_dma_0:
6058 dev_kfree_skb_any(skb);
6059 err_update_stats:
6060 dev->stats.tx_dropped++;
6061 return NETDEV_TX_OK;
6062
6063 err_stop_0:
6064 netif_stop_queue(dev);
6065 dev->stats.tx_dropped++;
6066 return NETDEV_TX_BUSY;
6067 }
6068
6069 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6070 {
6071 struct rtl8169_private *tp = netdev_priv(dev);
6072 struct pci_dev *pdev = tp->pci_dev;
6073 u16 pci_status, pci_cmd;
6074
6075 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6076 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6077
6078 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6079 pci_cmd, pci_status);
6080
6081 /*
6082 * The recovery sequence below admits a very elaborated explanation:
6083 * - it seems to work;
6084 * - I did not see what else could be done;
6085 * - it makes iop3xx happy.
6086 *
6087 * Feel free to adjust to your needs.
6088 */
6089 if (pdev->broken_parity_status)
6090 pci_cmd &= ~PCI_COMMAND_PARITY;
6091 else
6092 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6093
6094 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6095
6096 pci_write_config_word(pdev, PCI_STATUS,
6097 pci_status & (PCI_STATUS_DETECTED_PARITY |
6098 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6099 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6100
6101 /* The infamous DAC f*ckup only happens at boot time */
6102 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6103 void __iomem *ioaddr = tp->mmio_addr;
6104
6105 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6106 tp->cp_cmd &= ~PCIDAC;
6107 RTL_W16(CPlusCmd, tp->cp_cmd);
6108 dev->features &= ~NETIF_F_HIGHDMA;
6109 }
6110
6111 rtl8169_hw_reset(tp);
6112
6113 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6114 }
6115
6116 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6117 {
6118 unsigned int dirty_tx, tx_left;
6119
6120 dirty_tx = tp->dirty_tx;
6121 smp_rmb();
6122 tx_left = tp->cur_tx - dirty_tx;
6123
6124 while (tx_left > 0) {
6125 unsigned int entry = dirty_tx % NUM_TX_DESC;
6126 struct ring_info *tx_skb = tp->tx_skb + entry;
6127 u32 status;
6128
6129 rmb();
6130 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6131 if (status & DescOwn)
6132 break;
6133
6134 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6135 tp->TxDescArray + entry);
6136 if (status & LastFrag) {
6137 u64_stats_update_begin(&tp->tx_stats.syncp);
6138 tp->tx_stats.packets++;
6139 tp->tx_stats.bytes += tx_skb->skb->len;
6140 u64_stats_update_end(&tp->tx_stats.syncp);
6141 dev_kfree_skb_any(tx_skb->skb);
6142 tx_skb->skb = NULL;
6143 }
6144 dirty_tx++;
6145 tx_left--;
6146 }
6147
6148 if (tp->dirty_tx != dirty_tx) {
6149 tp->dirty_tx = dirty_tx;
6150 /* Sync with rtl8169_start_xmit:
6151 * - publish dirty_tx ring index (write barrier)
6152 * - refresh cur_tx ring index and queue status (read barrier)
6153 * May the current thread miss the stopped queue condition,
6154 * a racing xmit thread can only have a right view of the
6155 * ring status.
6156 */
6157 smp_mb();
6158 if (netif_queue_stopped(dev) &&
6159 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6160 netif_wake_queue(dev);
6161 }
6162 /*
6163 * 8168 hack: TxPoll requests are lost when the Tx packets are
6164 * too close. Let's kick an extra TxPoll request when a burst
6165 * of start_xmit activity is detected (if it is not detected,
6166 * it is slow enough). -- FR
6167 */
6168 if (tp->cur_tx != dirty_tx) {
6169 void __iomem *ioaddr = tp->mmio_addr;
6170
6171 RTL_W8(TxPoll, NPQ);
6172 }
6173 }
6174 }
6175
6176 static inline int rtl8169_fragmented_frame(u32 status)
6177 {
6178 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6179 }
6180
6181 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6182 {
6183 u32 status = opts1 & RxProtoMask;
6184
6185 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6186 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6187 skb->ip_summed = CHECKSUM_UNNECESSARY;
6188 else
6189 skb_checksum_none_assert(skb);
6190 }
6191
6192 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6193 struct rtl8169_private *tp,
6194 int pkt_size,
6195 dma_addr_t addr)
6196 {
6197 struct sk_buff *skb;
6198 struct device *d = &tp->pci_dev->dev;
6199
6200 data = rtl8169_align(data);
6201 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6202 prefetch(data);
6203 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
6204 if (skb)
6205 memcpy(skb->data, data, pkt_size);
6206 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6207
6208 return skb;
6209 }
6210
6211 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6212 {
6213 unsigned int cur_rx, rx_left;
6214 unsigned int count;
6215
6216 cur_rx = tp->cur_rx;
6217
6218 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6219 unsigned int entry = cur_rx % NUM_RX_DESC;
6220 struct RxDesc *desc = tp->RxDescArray + entry;
6221 u32 status;
6222
6223 rmb();
6224 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
6225
6226 if (status & DescOwn)
6227 break;
6228 if (unlikely(status & RxRES)) {
6229 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6230 status);
6231 dev->stats.rx_errors++;
6232 if (status & (RxRWT | RxRUNT))
6233 dev->stats.rx_length_errors++;
6234 if (status & RxCRC)
6235 dev->stats.rx_crc_errors++;
6236 if (status & RxFOVF) {
6237 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6238 dev->stats.rx_fifo_errors++;
6239 }
6240 if ((status & (RxRUNT | RxCRC)) &&
6241 !(status & (RxRWT | RxFOVF)) &&
6242 (dev->features & NETIF_F_RXALL))
6243 goto process_pkt;
6244 } else {
6245 struct sk_buff *skb;
6246 dma_addr_t addr;
6247 int pkt_size;
6248
6249 process_pkt:
6250 addr = le64_to_cpu(desc->addr);
6251 if (likely(!(dev->features & NETIF_F_RXFCS)))
6252 pkt_size = (status & 0x00003fff) - 4;
6253 else
6254 pkt_size = status & 0x00003fff;
6255
6256 /*
6257 * The driver does not support incoming fragmented
6258 * frames. They are seen as a symptom of over-mtu
6259 * sized frames.
6260 */
6261 if (unlikely(rtl8169_fragmented_frame(status))) {
6262 dev->stats.rx_dropped++;
6263 dev->stats.rx_length_errors++;
6264 goto release_descriptor;
6265 }
6266
6267 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6268 tp, pkt_size, addr);
6269 if (!skb) {
6270 dev->stats.rx_dropped++;
6271 goto release_descriptor;
6272 }
6273
6274 rtl8169_rx_csum(skb, status);
6275 skb_put(skb, pkt_size);
6276 skb->protocol = eth_type_trans(skb, dev);
6277
6278 rtl8169_rx_vlan_tag(desc, skb);
6279
6280 napi_gro_receive(&tp->napi, skb);
6281
6282 u64_stats_update_begin(&tp->rx_stats.syncp);
6283 tp->rx_stats.packets++;
6284 tp->rx_stats.bytes += pkt_size;
6285 u64_stats_update_end(&tp->rx_stats.syncp);
6286 }
6287 release_descriptor:
6288 desc->opts2 = 0;
6289 wmb();
6290 rtl8169_mark_to_asic(desc, rx_buf_sz);
6291 }
6292
6293 count = cur_rx - tp->cur_rx;
6294 tp->cur_rx = cur_rx;
6295
6296 return count;
6297 }
6298
6299 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6300 {
6301 struct net_device *dev = dev_instance;
6302 struct rtl8169_private *tp = netdev_priv(dev);
6303 int handled = 0;
6304 u16 status;
6305
6306 status = rtl_get_events(tp);
6307 if (status && status != 0xffff) {
6308 status &= RTL_EVENT_NAPI | tp->event_slow;
6309 if (status) {
6310 handled = 1;
6311
6312 rtl_irq_disable(tp);
6313 napi_schedule(&tp->napi);
6314 }
6315 }
6316 return IRQ_RETVAL(handled);
6317 }
6318
6319 /*
6320 * Workqueue context.
6321 */
6322 static void rtl_slow_event_work(struct rtl8169_private *tp)
6323 {
6324 struct net_device *dev = tp->dev;
6325 u16 status;
6326
6327 status = rtl_get_events(tp) & tp->event_slow;
6328 rtl_ack_events(tp, status);
6329
6330 if (unlikely(status & RxFIFOOver)) {
6331 switch (tp->mac_version) {
6332 /* Work around for rx fifo overflow */
6333 case RTL_GIGA_MAC_VER_11:
6334 netif_stop_queue(dev);
6335 /* XXX - Hack alert. See rtl_task(). */
6336 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6337 default:
6338 break;
6339 }
6340 }
6341
6342 if (unlikely(status & SYSErr))
6343 rtl8169_pcierr_interrupt(dev);
6344
6345 if (status & LinkChg)
6346 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
6347
6348 rtl_irq_enable_all(tp);
6349 }
6350
6351 static void rtl_task(struct work_struct *work)
6352 {
6353 static const struct {
6354 int bitnr;
6355 void (*action)(struct rtl8169_private *);
6356 } rtl_work[] = {
6357 /* XXX - keep rtl_slow_event_work() as first element. */
6358 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6359 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6360 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
6361 };
6362 struct rtl8169_private *tp =
6363 container_of(work, struct rtl8169_private, wk.work);
6364 struct net_device *dev = tp->dev;
6365 int i;
6366
6367 rtl_lock_work(tp);
6368
6369 if (!netif_running(dev) ||
6370 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6371 goto out_unlock;
6372
6373 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6374 bool pending;
6375
6376 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6377 if (pending)
6378 rtl_work[i].action(tp);
6379 }
6380
6381 out_unlock:
6382 rtl_unlock_work(tp);
6383 }
6384
6385 static int rtl8169_poll(struct napi_struct *napi, int budget)
6386 {
6387 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6388 struct net_device *dev = tp->dev;
6389 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6390 int work_done= 0;
6391 u16 status;
6392
6393 status = rtl_get_events(tp);
6394 rtl_ack_events(tp, status & ~tp->event_slow);
6395
6396 if (status & RTL_EVENT_NAPI_RX)
6397 work_done = rtl_rx(dev, tp, (u32) budget);
6398
6399 if (status & RTL_EVENT_NAPI_TX)
6400 rtl_tx(dev, tp);
6401
6402 if (status & tp->event_slow) {
6403 enable_mask &= ~tp->event_slow;
6404
6405 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6406 }
6407
6408 if (work_done < budget) {
6409 napi_complete(napi);
6410
6411 rtl_irq_enable(tp, enable_mask);
6412 mmiowb();
6413 }
6414
6415 return work_done;
6416 }
6417
6418 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6419 {
6420 struct rtl8169_private *tp = netdev_priv(dev);
6421
6422 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6423 return;
6424
6425 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6426 RTL_W32(RxMissed, 0);
6427 }
6428
6429 static void rtl8169_down(struct net_device *dev)
6430 {
6431 struct rtl8169_private *tp = netdev_priv(dev);
6432 void __iomem *ioaddr = tp->mmio_addr;
6433
6434 del_timer_sync(&tp->timer);
6435
6436 napi_disable(&tp->napi);
6437 netif_stop_queue(dev);
6438
6439 rtl8169_hw_reset(tp);
6440 /*
6441 * At this point device interrupts can not be enabled in any function,
6442 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6443 * and napi is disabled (rtl8169_poll).
6444 */
6445 rtl8169_rx_missed(dev, ioaddr);
6446
6447 /* Give a racing hard_start_xmit a few cycles to complete. */
6448 synchronize_sched();
6449
6450 rtl8169_tx_clear(tp);
6451
6452 rtl8169_rx_clear(tp);
6453
6454 rtl_pll_power_down(tp);
6455 }
6456
6457 static int rtl8169_close(struct net_device *dev)
6458 {
6459 struct rtl8169_private *tp = netdev_priv(dev);
6460 struct pci_dev *pdev = tp->pci_dev;
6461
6462 pm_runtime_get_sync(&pdev->dev);
6463
6464 /* Update counters before going down */
6465 rtl8169_update_counters(dev);
6466
6467 rtl_lock_work(tp);
6468 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6469
6470 rtl8169_down(dev);
6471 rtl_unlock_work(tp);
6472
6473 cancel_work_sync(&tp->wk.work);
6474
6475 free_irq(pdev->irq, dev);
6476
6477 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6478 tp->RxPhyAddr);
6479 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6480 tp->TxPhyAddr);
6481 tp->TxDescArray = NULL;
6482 tp->RxDescArray = NULL;
6483
6484 pm_runtime_put_sync(&pdev->dev);
6485
6486 return 0;
6487 }
6488
6489 #ifdef CONFIG_NET_POLL_CONTROLLER
6490 static void rtl8169_netpoll(struct net_device *dev)
6491 {
6492 struct rtl8169_private *tp = netdev_priv(dev);
6493
6494 rtl8169_interrupt(tp->pci_dev->irq, dev);
6495 }
6496 #endif
6497
6498 static int rtl_open(struct net_device *dev)
6499 {
6500 struct rtl8169_private *tp = netdev_priv(dev);
6501 void __iomem *ioaddr = tp->mmio_addr;
6502 struct pci_dev *pdev = tp->pci_dev;
6503 int retval = -ENOMEM;
6504
6505 pm_runtime_get_sync(&pdev->dev);
6506
6507 /*
6508 * Rx and Tx descriptors needs 256 bytes alignment.
6509 * dma_alloc_coherent provides more.
6510 */
6511 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6512 &tp->TxPhyAddr, GFP_KERNEL);
6513 if (!tp->TxDescArray)
6514 goto err_pm_runtime_put;
6515
6516 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6517 &tp->RxPhyAddr, GFP_KERNEL);
6518 if (!tp->RxDescArray)
6519 goto err_free_tx_0;
6520
6521 retval = rtl8169_init_ring(dev);
6522 if (retval < 0)
6523 goto err_free_rx_1;
6524
6525 INIT_WORK(&tp->wk.work, rtl_task);
6526
6527 smp_mb();
6528
6529 rtl_request_firmware(tp);
6530
6531 retval = request_irq(pdev->irq, rtl8169_interrupt,
6532 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6533 dev->name, dev);
6534 if (retval < 0)
6535 goto err_release_fw_2;
6536
6537 rtl_lock_work(tp);
6538
6539 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6540
6541 napi_enable(&tp->napi);
6542
6543 rtl8169_init_phy(dev, tp);
6544
6545 __rtl8169_set_features(dev, dev->features);
6546
6547 rtl_pll_power_up(tp);
6548
6549 rtl_hw_start(dev);
6550
6551 netif_start_queue(dev);
6552
6553 rtl_unlock_work(tp);
6554
6555 tp->saved_wolopts = 0;
6556 pm_runtime_put_noidle(&pdev->dev);
6557
6558 rtl8169_check_link_status(dev, tp, ioaddr);
6559 out:
6560 return retval;
6561
6562 err_release_fw_2:
6563 rtl_release_firmware(tp);
6564 rtl8169_rx_clear(tp);
6565 err_free_rx_1:
6566 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6567 tp->RxPhyAddr);
6568 tp->RxDescArray = NULL;
6569 err_free_tx_0:
6570 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6571 tp->TxPhyAddr);
6572 tp->TxDescArray = NULL;
6573 err_pm_runtime_put:
6574 pm_runtime_put_noidle(&pdev->dev);
6575 goto out;
6576 }
6577
6578 static struct rtnl_link_stats64 *
6579 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6580 {
6581 struct rtl8169_private *tp = netdev_priv(dev);
6582 void __iomem *ioaddr = tp->mmio_addr;
6583 unsigned int start;
6584
6585 if (netif_running(dev))
6586 rtl8169_rx_missed(dev, ioaddr);
6587
6588 do {
6589 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6590 stats->rx_packets = tp->rx_stats.packets;
6591 stats->rx_bytes = tp->rx_stats.bytes;
6592 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6593
6594
6595 do {
6596 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6597 stats->tx_packets = tp->tx_stats.packets;
6598 stats->tx_bytes = tp->tx_stats.bytes;
6599 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6600
6601 stats->rx_dropped = dev->stats.rx_dropped;
6602 stats->tx_dropped = dev->stats.tx_dropped;
6603 stats->rx_length_errors = dev->stats.rx_length_errors;
6604 stats->rx_errors = dev->stats.rx_errors;
6605 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6606 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6607 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6608
6609 return stats;
6610 }
6611
6612 static void rtl8169_net_suspend(struct net_device *dev)
6613 {
6614 struct rtl8169_private *tp = netdev_priv(dev);
6615
6616 if (!netif_running(dev))
6617 return;
6618
6619 netif_device_detach(dev);
6620 netif_stop_queue(dev);
6621
6622 rtl_lock_work(tp);
6623 napi_disable(&tp->napi);
6624 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6625 rtl_unlock_work(tp);
6626
6627 rtl_pll_power_down(tp);
6628 }
6629
6630 #ifdef CONFIG_PM
6631
6632 static int rtl8169_suspend(struct device *device)
6633 {
6634 struct pci_dev *pdev = to_pci_dev(device);
6635 struct net_device *dev = pci_get_drvdata(pdev);
6636
6637 rtl8169_net_suspend(dev);
6638
6639 return 0;
6640 }
6641
6642 static void __rtl8169_resume(struct net_device *dev)
6643 {
6644 struct rtl8169_private *tp = netdev_priv(dev);
6645
6646 netif_device_attach(dev);
6647
6648 rtl_pll_power_up(tp);
6649
6650 rtl_lock_work(tp);
6651 napi_enable(&tp->napi);
6652 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6653 rtl_unlock_work(tp);
6654
6655 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6656 }
6657
6658 static int rtl8169_resume(struct device *device)
6659 {
6660 struct pci_dev *pdev = to_pci_dev(device);
6661 struct net_device *dev = pci_get_drvdata(pdev);
6662 struct rtl8169_private *tp = netdev_priv(dev);
6663
6664 rtl8169_init_phy(dev, tp);
6665
6666 if (netif_running(dev))
6667 __rtl8169_resume(dev);
6668
6669 return 0;
6670 }
6671
6672 static int rtl8169_runtime_suspend(struct device *device)
6673 {
6674 struct pci_dev *pdev = to_pci_dev(device);
6675 struct net_device *dev = pci_get_drvdata(pdev);
6676 struct rtl8169_private *tp = netdev_priv(dev);
6677
6678 if (!tp->TxDescArray)
6679 return 0;
6680
6681 rtl_lock_work(tp);
6682 tp->saved_wolopts = __rtl8169_get_wol(tp);
6683 __rtl8169_set_wol(tp, WAKE_ANY);
6684 rtl_unlock_work(tp);
6685
6686 rtl8169_net_suspend(dev);
6687
6688 return 0;
6689 }
6690
6691 static int rtl8169_runtime_resume(struct device *device)
6692 {
6693 struct pci_dev *pdev = to_pci_dev(device);
6694 struct net_device *dev = pci_get_drvdata(pdev);
6695 struct rtl8169_private *tp = netdev_priv(dev);
6696
6697 if (!tp->TxDescArray)
6698 return 0;
6699
6700 rtl_lock_work(tp);
6701 __rtl8169_set_wol(tp, tp->saved_wolopts);
6702 tp->saved_wolopts = 0;
6703 rtl_unlock_work(tp);
6704
6705 rtl8169_init_phy(dev, tp);
6706
6707 __rtl8169_resume(dev);
6708
6709 return 0;
6710 }
6711
6712 static int rtl8169_runtime_idle(struct device *device)
6713 {
6714 struct pci_dev *pdev = to_pci_dev(device);
6715 struct net_device *dev = pci_get_drvdata(pdev);
6716 struct rtl8169_private *tp = netdev_priv(dev);
6717
6718 return tp->TxDescArray ? -EBUSY : 0;
6719 }
6720
6721 static const struct dev_pm_ops rtl8169_pm_ops = {
6722 .suspend = rtl8169_suspend,
6723 .resume = rtl8169_resume,
6724 .freeze = rtl8169_suspend,
6725 .thaw = rtl8169_resume,
6726 .poweroff = rtl8169_suspend,
6727 .restore = rtl8169_resume,
6728 .runtime_suspend = rtl8169_runtime_suspend,
6729 .runtime_resume = rtl8169_runtime_resume,
6730 .runtime_idle = rtl8169_runtime_idle,
6731 };
6732
6733 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6734
6735 #else /* !CONFIG_PM */
6736
6737 #define RTL8169_PM_OPS NULL
6738
6739 #endif /* !CONFIG_PM */
6740
6741 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6742 {
6743 void __iomem *ioaddr = tp->mmio_addr;
6744
6745 /* WoL fails with 8168b when the receiver is disabled. */
6746 switch (tp->mac_version) {
6747 case RTL_GIGA_MAC_VER_11:
6748 case RTL_GIGA_MAC_VER_12:
6749 case RTL_GIGA_MAC_VER_17:
6750 pci_clear_master(tp->pci_dev);
6751
6752 RTL_W8(ChipCmd, CmdRxEnb);
6753 /* PCI commit */
6754 RTL_R8(ChipCmd);
6755 break;
6756 default:
6757 break;
6758 }
6759 }
6760
6761 static void rtl_shutdown(struct pci_dev *pdev)
6762 {
6763 struct net_device *dev = pci_get_drvdata(pdev);
6764 struct rtl8169_private *tp = netdev_priv(dev);
6765 struct device *d = &pdev->dev;
6766
6767 pm_runtime_get_sync(d);
6768
6769 rtl8169_net_suspend(dev);
6770
6771 /* Restore original MAC address */
6772 rtl_rar_set(tp, dev->perm_addr);
6773
6774 rtl8169_hw_reset(tp);
6775
6776 if (system_state == SYSTEM_POWER_OFF) {
6777 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6778 rtl_wol_suspend_quirk(tp);
6779 rtl_wol_shutdown_quirk(tp);
6780 }
6781
6782 pci_wake_from_d3(pdev, true);
6783 pci_set_power_state(pdev, PCI_D3hot);
6784 }
6785
6786 pm_runtime_put_noidle(d);
6787 }
6788
6789 static void rtl_remove_one(struct pci_dev *pdev)
6790 {
6791 struct net_device *dev = pci_get_drvdata(pdev);
6792 struct rtl8169_private *tp = netdev_priv(dev);
6793
6794 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6795 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6796 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6797 rtl8168_driver_stop(tp);
6798 }
6799
6800 netif_napi_del(&tp->napi);
6801
6802 unregister_netdev(dev);
6803
6804 rtl_release_firmware(tp);
6805
6806 if (pci_dev_run_wake(pdev))
6807 pm_runtime_get_noresume(&pdev->dev);
6808
6809 /* restore original MAC address */
6810 rtl_rar_set(tp, dev->perm_addr);
6811
6812 rtl_disable_msi(pdev, tp);
6813 rtl8169_release_board(pdev, dev, tp->mmio_addr);
6814 }
6815
6816 static const struct net_device_ops rtl_netdev_ops = {
6817 .ndo_open = rtl_open,
6818 .ndo_stop = rtl8169_close,
6819 .ndo_get_stats64 = rtl8169_get_stats64,
6820 .ndo_start_xmit = rtl8169_start_xmit,
6821 .ndo_tx_timeout = rtl8169_tx_timeout,
6822 .ndo_validate_addr = eth_validate_addr,
6823 .ndo_change_mtu = rtl8169_change_mtu,
6824 .ndo_fix_features = rtl8169_fix_features,
6825 .ndo_set_features = rtl8169_set_features,
6826 .ndo_set_mac_address = rtl_set_mac_address,
6827 .ndo_do_ioctl = rtl8169_ioctl,
6828 .ndo_set_rx_mode = rtl_set_rx_mode,
6829 #ifdef CONFIG_NET_POLL_CONTROLLER
6830 .ndo_poll_controller = rtl8169_netpoll,
6831 #endif
6832
6833 };
6834
6835 static const struct rtl_cfg_info {
6836 void (*hw_start)(struct net_device *);
6837 unsigned int region;
6838 unsigned int align;
6839 u16 event_slow;
6840 unsigned features;
6841 u8 default_ver;
6842 } rtl_cfg_infos [] = {
6843 [RTL_CFG_0] = {
6844 .hw_start = rtl_hw_start_8169,
6845 .region = 1,
6846 .align = 0,
6847 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6848 .features = RTL_FEATURE_GMII,
6849 .default_ver = RTL_GIGA_MAC_VER_01,
6850 },
6851 [RTL_CFG_1] = {
6852 .hw_start = rtl_hw_start_8168,
6853 .region = 2,
6854 .align = 8,
6855 .event_slow = SYSErr | LinkChg | RxOverflow,
6856 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6857 .default_ver = RTL_GIGA_MAC_VER_11,
6858 },
6859 [RTL_CFG_2] = {
6860 .hw_start = rtl_hw_start_8101,
6861 .region = 2,
6862 .align = 8,
6863 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6864 PCSTimeout,
6865 .features = RTL_FEATURE_MSI,
6866 .default_ver = RTL_GIGA_MAC_VER_13,
6867 }
6868 };
6869
6870 /* Cfg9346_Unlock assumed. */
6871 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6872 const struct rtl_cfg_info *cfg)
6873 {
6874 void __iomem *ioaddr = tp->mmio_addr;
6875 unsigned msi = 0;
6876 u8 cfg2;
6877
6878 cfg2 = RTL_R8(Config2) & ~MSIEnable;
6879 if (cfg->features & RTL_FEATURE_MSI) {
6880 if (pci_enable_msi(tp->pci_dev)) {
6881 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6882 } else {
6883 cfg2 |= MSIEnable;
6884 msi = RTL_FEATURE_MSI;
6885 }
6886 }
6887 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6888 RTL_W8(Config2, cfg2);
6889 return msi;
6890 }
6891
6892 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6893 {
6894 void __iomem *ioaddr = tp->mmio_addr;
6895
6896 return RTL_R8(MCU) & LINK_LIST_RDY;
6897 }
6898
6899 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6900 {
6901 void __iomem *ioaddr = tp->mmio_addr;
6902
6903 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6904 }
6905
6906 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6907 {
6908 void __iomem *ioaddr = tp->mmio_addr;
6909 u32 data;
6910
6911 tp->ocp_base = OCP_STD_PHY_BASE;
6912
6913 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
6914
6915 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6916 return;
6917
6918 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6919 return;
6920
6921 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6922 msleep(1);
6923 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6924
6925 data = r8168_mac_ocp_read(tp, 0xe8de);
6926 data &= ~(1 << 14);
6927 r8168_mac_ocp_write(tp, 0xe8de, data);
6928
6929 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6930 return;
6931
6932 data = r8168_mac_ocp_read(tp, 0xe8de);
6933 data |= (1 << 15);
6934 r8168_mac_ocp_write(tp, 0xe8de, data);
6935
6936 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6937 return;
6938 }
6939
6940 static void rtl_hw_initialize(struct rtl8169_private *tp)
6941 {
6942 switch (tp->mac_version) {
6943 case RTL_GIGA_MAC_VER_40:
6944 case RTL_GIGA_MAC_VER_41:
6945 case RTL_GIGA_MAC_VER_42:
6946 case RTL_GIGA_MAC_VER_43:
6947 case RTL_GIGA_MAC_VER_44:
6948 rtl_hw_init_8168g(tp);
6949 break;
6950
6951 default:
6952 break;
6953 }
6954 }
6955
6956 static int
6957 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6958 {
6959 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6960 const unsigned int region = cfg->region;
6961 struct rtl8169_private *tp;
6962 struct mii_if_info *mii;
6963 struct net_device *dev;
6964 void __iomem *ioaddr;
6965 int chipset, i;
6966 int rc;
6967
6968 if (netif_msg_drv(&debug)) {
6969 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6970 MODULENAME, RTL8169_VERSION);
6971 }
6972
6973 dev = alloc_etherdev(sizeof (*tp));
6974 if (!dev) {
6975 rc = -ENOMEM;
6976 goto out;
6977 }
6978
6979 SET_NETDEV_DEV(dev, &pdev->dev);
6980 dev->netdev_ops = &rtl_netdev_ops;
6981 tp = netdev_priv(dev);
6982 tp->dev = dev;
6983 tp->pci_dev = pdev;
6984 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6985
6986 mii = &tp->mii;
6987 mii->dev = dev;
6988 mii->mdio_read = rtl_mdio_read;
6989 mii->mdio_write = rtl_mdio_write;
6990 mii->phy_id_mask = 0x1f;
6991 mii->reg_num_mask = 0x1f;
6992 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6993
6994 /* disable ASPM completely as that cause random device stop working
6995 * problems as well as full system hangs for some PCIe devices users */
6996 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6997 PCIE_LINK_STATE_CLKPM);
6998
6999 /* enable device (incl. PCI PM wakeup and hotplug setup) */
7000 rc = pci_enable_device(pdev);
7001 if (rc < 0) {
7002 netif_err(tp, probe, dev, "enable failure\n");
7003 goto err_out_free_dev_1;
7004 }
7005
7006 if (pci_set_mwi(pdev) < 0)
7007 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
7008
7009 /* make sure PCI base addr 1 is MMIO */
7010 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
7011 netif_err(tp, probe, dev,
7012 "region #%d not an MMIO resource, aborting\n",
7013 region);
7014 rc = -ENODEV;
7015 goto err_out_mwi_2;
7016 }
7017
7018 /* check for weird/broken PCI region reporting */
7019 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7020 netif_err(tp, probe, dev,
7021 "Invalid PCI region size(s), aborting\n");
7022 rc = -ENODEV;
7023 goto err_out_mwi_2;
7024 }
7025
7026 rc = pci_request_regions(pdev, MODULENAME);
7027 if (rc < 0) {
7028 netif_err(tp, probe, dev, "could not request regions\n");
7029 goto err_out_mwi_2;
7030 }
7031
7032 tp->cp_cmd = RxChkSum;
7033
7034 if ((sizeof(dma_addr_t) > 4) &&
7035 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
7036 tp->cp_cmd |= PCIDAC;
7037 dev->features |= NETIF_F_HIGHDMA;
7038 } else {
7039 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7040 if (rc < 0) {
7041 netif_err(tp, probe, dev, "DMA configuration failed\n");
7042 goto err_out_free_res_3;
7043 }
7044 }
7045
7046 /* ioremap MMIO region */
7047 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
7048 if (!ioaddr) {
7049 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
7050 rc = -EIO;
7051 goto err_out_free_res_3;
7052 }
7053 tp->mmio_addr = ioaddr;
7054
7055 if (!pci_is_pcie(pdev))
7056 netif_info(tp, probe, dev, "not PCI Express\n");
7057
7058 /* Identify chip attached to board */
7059 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
7060
7061 rtl_init_rxcfg(tp);
7062
7063 rtl_irq_disable(tp);
7064
7065 rtl_hw_initialize(tp);
7066
7067 rtl_hw_reset(tp);
7068
7069 rtl_ack_events(tp, 0xffff);
7070
7071 pci_set_master(pdev);
7072
7073 /*
7074 * Pretend we are using VLANs; This bypasses a nasty bug where
7075 * Interrupts stop flowing on high load on 8110SCd controllers.
7076 */
7077 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7078 tp->cp_cmd |= RxVlan;
7079
7080 rtl_init_mdio_ops(tp);
7081 rtl_init_pll_power_ops(tp);
7082 rtl_init_jumbo_ops(tp);
7083 rtl_init_csi_ops(tp);
7084
7085 rtl8169_print_mac_version(tp);
7086
7087 chipset = tp->mac_version;
7088 tp->txd_version = rtl_chip_infos[chipset].txd_version;
7089
7090 RTL_W8(Cfg9346, Cfg9346_Unlock);
7091 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
7092 RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
7093 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
7094 tp->features |= RTL_FEATURE_WOL;
7095 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
7096 tp->features |= RTL_FEATURE_WOL;
7097 tp->features |= rtl_try_msi(tp, cfg);
7098 RTL_W8(Cfg9346, Cfg9346_Lock);
7099
7100 if (rtl_tbi_enabled(tp)) {
7101 tp->set_speed = rtl8169_set_speed_tbi;
7102 tp->get_settings = rtl8169_gset_tbi;
7103 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
7104 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
7105 tp->link_ok = rtl8169_tbi_link_ok;
7106 tp->do_ioctl = rtl_tbi_ioctl;
7107 } else {
7108 tp->set_speed = rtl8169_set_speed_xmii;
7109 tp->get_settings = rtl8169_gset_xmii;
7110 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
7111 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
7112 tp->link_ok = rtl8169_xmii_link_ok;
7113 tp->do_ioctl = rtl_xmii_ioctl;
7114 }
7115
7116 mutex_init(&tp->wk.mutex);
7117 u64_stats_init(&tp->rx_stats.syncp);
7118 u64_stats_init(&tp->tx_stats.syncp);
7119
7120 /* Get MAC address */
7121 for (i = 0; i < ETH_ALEN; i++)
7122 dev->dev_addr[i] = RTL_R8(MAC0 + i);
7123
7124 dev->ethtool_ops = &rtl8169_ethtool_ops;
7125 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
7126
7127 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
7128
7129 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7130 * properly for all devices */
7131 dev->features |= NETIF_F_RXCSUM |
7132 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7133
7134 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7135 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7136 NETIF_F_HW_VLAN_CTAG_RX;
7137 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7138 NETIF_F_HIGHDMA;
7139
7140 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7141 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
7142 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7143
7144 if (tp->txd_version == RTL_TD_0)
7145 tp->tso_csum = rtl8169_tso_csum_v1;
7146 else if (tp->txd_version == RTL_TD_1)
7147 tp->tso_csum = rtl8169_tso_csum_v2;
7148 else
7149 WARN_ON_ONCE(1);
7150
7151 dev->hw_features |= NETIF_F_RXALL;
7152 dev->hw_features |= NETIF_F_RXFCS;
7153
7154 tp->hw_start = cfg->hw_start;
7155 tp->event_slow = cfg->event_slow;
7156
7157 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
7158 ~(RxBOVF | RxFOVF) : ~0;
7159
7160 init_timer(&tp->timer);
7161 tp->timer.data = (unsigned long) dev;
7162 tp->timer.function = rtl8169_phy_timer;
7163
7164 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7165
7166 rc = register_netdev(dev);
7167 if (rc < 0)
7168 goto err_out_msi_4;
7169
7170 pci_set_drvdata(pdev, dev);
7171
7172 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
7173 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
7174 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
7175 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7176 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7177 "tx checksumming: %s]\n",
7178 rtl_chip_infos[chipset].jumbo_max,
7179 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
7180 }
7181
7182 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7183 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7184 tp->mac_version == RTL_GIGA_MAC_VER_31) {
7185 rtl8168_driver_start(tp);
7186 }
7187
7188 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
7189
7190 if (pci_dev_run_wake(pdev))
7191 pm_runtime_put_noidle(&pdev->dev);
7192
7193 netif_carrier_off(dev);
7194
7195 out:
7196 return rc;
7197
7198 err_out_msi_4:
7199 netif_napi_del(&tp->napi);
7200 rtl_disable_msi(pdev, tp);
7201 iounmap(ioaddr);
7202 err_out_free_res_3:
7203 pci_release_regions(pdev);
7204 err_out_mwi_2:
7205 pci_clear_mwi(pdev);
7206 pci_disable_device(pdev);
7207 err_out_free_dev_1:
7208 free_netdev(dev);
7209 goto out;
7210 }
7211
7212 static struct pci_driver rtl8169_pci_driver = {
7213 .name = MODULENAME,
7214 .id_table = rtl8169_pci_tbl,
7215 .probe = rtl_init_one,
7216 .remove = rtl_remove_one,
7217 .shutdown = rtl_shutdown,
7218 .driver.pm = RTL8169_PM_OPS,
7219 };
7220
7221 module_pci_driver(rtl8169_pci_driver);
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