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[media] s5p-fimc: Redefine platform data structure for fimc-is
[linux-2.6/btrfs-unstable.git] / drivers / media / platform / s5p-fimc / fimc-reg.c
blob50b97c75b956d7f47f6195812cc043499f4b12b0
1 /*
2 * Register interface file for Samsung Camera Interface (FIMC) driver
3 *
4 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
5 * Sylwester Nawrocki, <s.nawrocki@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/io.h>
13 #include <linux/delay.h>
14 #include <media/s5p_fimc.h>
15
16 #include "fimc-reg.h"
17 #include "fimc-core.h"
18
19
20 void fimc_hw_reset(struct fimc_dev *dev)
21 {
22 u32 cfg;
23
24 cfg = readl(dev->regs + FIMC_REG_CISRCFMT);
25 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT;
26 writel(cfg, dev->regs + FIMC_REG_CISRCFMT);
27
28 /* Software reset. */
29 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
30 cfg |= (FIMC_REG_CIGCTRL_SWRST | FIMC_REG_CIGCTRL_IRQ_LEVEL);
31 writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
32 udelay(10);
33
34 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
35 cfg &= ~FIMC_REG_CIGCTRL_SWRST;
36 writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
37
38 if (dev->variant->out_buf_count > 4)
39 fimc_hw_set_dma_seq(dev, 0xF);
40 }
41
42 static u32 fimc_hw_get_in_flip(struct fimc_ctx *ctx)
43 {
44 u32 flip = FIMC_REG_MSCTRL_FLIP_NORMAL;
45
46 if (ctx->hflip)
47 flip = FIMC_REG_MSCTRL_FLIP_Y_MIRROR;
48 if (ctx->vflip)
49 flip = FIMC_REG_MSCTRL_FLIP_X_MIRROR;
50
51 if (ctx->rotation <= 90)
52 return flip;
53
54 return (flip ^ FIMC_REG_MSCTRL_FLIP_180) & FIMC_REG_MSCTRL_FLIP_180;
55 }
56
57 static u32 fimc_hw_get_target_flip(struct fimc_ctx *ctx)
58 {
59 u32 flip = FIMC_REG_CITRGFMT_FLIP_NORMAL;
60
61 if (ctx->hflip)
62 flip |= FIMC_REG_CITRGFMT_FLIP_Y_MIRROR;
63 if (ctx->vflip)
64 flip |= FIMC_REG_CITRGFMT_FLIP_X_MIRROR;
65
66 if (ctx->rotation <= 90)
67 return flip;
68
69 return (flip ^ FIMC_REG_CITRGFMT_FLIP_180) & FIMC_REG_CITRGFMT_FLIP_180;
70 }
71
72 void fimc_hw_set_rotation(struct fimc_ctx *ctx)
73 {
74 u32 cfg, flip;
75 struct fimc_dev *dev = ctx->fimc_dev;
76
77 cfg = readl(dev->regs + FIMC_REG_CITRGFMT);
78 cfg &= ~(FIMC_REG_CITRGFMT_INROT90 | FIMC_REG_CITRGFMT_OUTROT90 |
79 FIMC_REG_CITRGFMT_FLIP_180);
80
81 /*
82 * The input and output rotator cannot work simultaneously.
83 * Use the output rotator in output DMA mode or the input rotator
84 * in direct fifo output mode.
85 */
86 if (ctx->rotation == 90 || ctx->rotation == 270) {
87 if (ctx->out_path == FIMC_IO_LCDFIFO)
88 cfg |= FIMC_REG_CITRGFMT_INROT90;
89 else
90 cfg |= FIMC_REG_CITRGFMT_OUTROT90;
91 }
92
93 if (ctx->out_path == FIMC_IO_DMA) {
94 cfg |= fimc_hw_get_target_flip(ctx);
95 writel(cfg, dev->regs + FIMC_REG_CITRGFMT);
96 } else {
97 /* LCD FIFO path */
98 flip = readl(dev->regs + FIMC_REG_MSCTRL);
99 flip &= ~FIMC_REG_MSCTRL_FLIP_MASK;
100 flip |= fimc_hw_get_in_flip(ctx);
101 writel(flip, dev->regs + FIMC_REG_MSCTRL);
102 }
103 }
104
105 void fimc_hw_set_target_format(struct fimc_ctx *ctx)
106 {
107 u32 cfg;
108 struct fimc_dev *dev = ctx->fimc_dev;
109 struct fimc_frame *frame = &ctx->d_frame;
110
111 dbg("w= %d, h= %d color: %d", frame->width,
112 frame->height, frame->fmt->color);
113
114 cfg = readl(dev->regs + FIMC_REG_CITRGFMT);
115 cfg &= ~(FIMC_REG_CITRGFMT_FMT_MASK | FIMC_REG_CITRGFMT_HSIZE_MASK |
116 FIMC_REG_CITRGFMT_VSIZE_MASK);
117
118 switch (frame->fmt->color) {
119 case FIMC_FMT_RGB444...FIMC_FMT_RGB888:
120 cfg |= FIMC_REG_CITRGFMT_RGB;
121 break;
122 case FIMC_FMT_YCBCR420:
123 cfg |= FIMC_REG_CITRGFMT_YCBCR420;
124 break;
125 case FIMC_FMT_YCBYCR422...FIMC_FMT_CRYCBY422:
126 if (frame->fmt->colplanes == 1)
127 cfg |= FIMC_REG_CITRGFMT_YCBCR422_1P;
128 else
129 cfg |= FIMC_REG_CITRGFMT_YCBCR422;
130 break;
131 default:
132 break;
133 }
134
135 if (ctx->rotation == 90 || ctx->rotation == 270)
136 cfg |= (frame->height << 16) | frame->width;
137 else
138 cfg |= (frame->width << 16) | frame->height;
139
140 writel(cfg, dev->regs + FIMC_REG_CITRGFMT);
141
142 cfg = readl(dev->regs + FIMC_REG_CITAREA);
143 cfg &= ~FIMC_REG_CITAREA_MASK;
144 cfg |= (frame->width * frame->height);
145 writel(cfg, dev->regs + FIMC_REG_CITAREA);
146 }
147
148 static void fimc_hw_set_out_dma_size(struct fimc_ctx *ctx)
149 {
150 struct fimc_dev *dev = ctx->fimc_dev;
151 struct fimc_frame *frame = &ctx->d_frame;
152 u32 cfg;
153
154 cfg = (frame->f_height << 16) | frame->f_width;
155 writel(cfg, dev->regs + FIMC_REG_ORGOSIZE);
156
157 /* Select color space conversion equation (HD/SD size).*/
158 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
159 if (frame->f_width >= 1280) /* HD */
160 cfg |= FIMC_REG_CIGCTRL_CSC_ITU601_709;
161 else /* SD */
162 cfg &= ~FIMC_REG_CIGCTRL_CSC_ITU601_709;
163 writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
164
165 }
166
167 void fimc_hw_set_out_dma(struct fimc_ctx *ctx)
168 {
169 struct fimc_dev *dev = ctx->fimc_dev;
170 struct fimc_frame *frame = &ctx->d_frame;
171 struct fimc_dma_offset *offset = &frame->dma_offset;
172 struct fimc_fmt *fmt = frame->fmt;
173 u32 cfg;
174
175 /* Set the input dma offsets. */
176 cfg = (offset->y_v << 16) | offset->y_h;
177 writel(cfg, dev->regs + FIMC_REG_CIOYOFF);
178
179 cfg = (offset->cb_v << 16) | offset->cb_h;
180 writel(cfg, dev->regs + FIMC_REG_CIOCBOFF);
181
182 cfg = (offset->cr_v << 16) | offset->cr_h;
183 writel(cfg, dev->regs + FIMC_REG_CIOCROFF);
184
185 fimc_hw_set_out_dma_size(ctx);
186
187 /* Configure chroma components order. */
188 cfg = readl(dev->regs + FIMC_REG_CIOCTRL);
189
190 cfg &= ~(FIMC_REG_CIOCTRL_ORDER2P_MASK |
191 FIMC_REG_CIOCTRL_ORDER422_MASK |
192 FIMC_REG_CIOCTRL_YCBCR_PLANE_MASK |
193 FIMC_REG_CIOCTRL_RGB16FMT_MASK);
194
195 if (fmt->colplanes == 1)
196 cfg |= ctx->out_order_1p;
197 else if (fmt->colplanes == 2)
198 cfg |= ctx->out_order_2p | FIMC_REG_CIOCTRL_YCBCR_2PLANE;
199 else if (fmt->colplanes == 3)
200 cfg |= FIMC_REG_CIOCTRL_YCBCR_3PLANE;
201
202 if (fmt->color == FIMC_FMT_RGB565)
203 cfg |= FIMC_REG_CIOCTRL_RGB565;
204 else if (fmt->color == FIMC_FMT_RGB555)
205 cfg |= FIMC_REG_CIOCTRL_ARGB1555;
206 else if (fmt->color == FIMC_FMT_RGB444)
207 cfg |= FIMC_REG_CIOCTRL_ARGB4444;
208
209 writel(cfg, dev->regs + FIMC_REG_CIOCTRL);
210 }
211
212 static void fimc_hw_en_autoload(struct fimc_dev *dev, int enable)
213 {
214 u32 cfg = readl(dev->regs + FIMC_REG_ORGISIZE);
215 if (enable)
216 cfg |= FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN;
217 else
218 cfg &= ~FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN;
219 writel(cfg, dev->regs + FIMC_REG_ORGISIZE);
220 }
221
222 void fimc_hw_en_lastirq(struct fimc_dev *dev, int enable)
223 {
224 u32 cfg = readl(dev->regs + FIMC_REG_CIOCTRL);
225 if (enable)
226 cfg |= FIMC_REG_CIOCTRL_LASTIRQ_ENABLE;
227 else
228 cfg &= ~FIMC_REG_CIOCTRL_LASTIRQ_ENABLE;
229 writel(cfg, dev->regs + FIMC_REG_CIOCTRL);
230 }
231
232 void fimc_hw_set_prescaler(struct fimc_ctx *ctx)
233 {
234 struct fimc_dev *dev = ctx->fimc_dev;
235 struct fimc_scaler *sc = &ctx->scaler;
236 u32 cfg, shfactor;
237
238 shfactor = 10 - (sc->hfactor + sc->vfactor);
239 cfg = shfactor << 28;
240
241 cfg |= (sc->pre_hratio << 16) | sc->pre_vratio;
242 writel(cfg, dev->regs + FIMC_REG_CISCPRERATIO);
243
244 cfg = (sc->pre_dst_width << 16) | sc->pre_dst_height;
245 writel(cfg, dev->regs + FIMC_REG_CISCPREDST);
246 }
247
248 static void fimc_hw_set_scaler(struct fimc_ctx *ctx)
249 {
250 struct fimc_dev *dev = ctx->fimc_dev;
251 struct fimc_scaler *sc = &ctx->scaler;
252 struct fimc_frame *src_frame = &ctx->s_frame;
253 struct fimc_frame *dst_frame = &ctx->d_frame;
254
255 u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);
256
257 cfg &= ~(FIMC_REG_CISCCTRL_CSCR2Y_WIDE | FIMC_REG_CISCCTRL_CSCY2R_WIDE |
258 FIMC_REG_CISCCTRL_SCALEUP_H | FIMC_REG_CISCCTRL_SCALEUP_V |
259 FIMC_REG_CISCCTRL_SCALERBYPASS | FIMC_REG_CISCCTRL_ONE2ONE |
260 FIMC_REG_CISCCTRL_INRGB_FMT_MASK | FIMC_REG_CISCCTRL_OUTRGB_FMT_MASK |
261 FIMC_REG_CISCCTRL_INTERLACE | FIMC_REG_CISCCTRL_RGB_EXT);
262
263 if (!(ctx->flags & FIMC_COLOR_RANGE_NARROW))
264 cfg |= (FIMC_REG_CISCCTRL_CSCR2Y_WIDE |
265 FIMC_REG_CISCCTRL_CSCY2R_WIDE);
266
267 if (!sc->enabled)
268 cfg |= FIMC_REG_CISCCTRL_SCALERBYPASS;
269
270 if (sc->scaleup_h)
271 cfg |= FIMC_REG_CISCCTRL_SCALEUP_H;
272
273 if (sc->scaleup_v)
274 cfg |= FIMC_REG_CISCCTRL_SCALEUP_V;
275
276 if (sc->copy_mode)
277 cfg |= FIMC_REG_CISCCTRL_ONE2ONE;
278
279 if (ctx->in_path == FIMC_IO_DMA) {
280 switch (src_frame->fmt->color) {
281 case FIMC_FMT_RGB565:
282 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB565;
283 break;
284 case FIMC_FMT_RGB666:
285 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB666;
286 break;
287 case FIMC_FMT_RGB888:
288 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB888;
289 break;
290 }
291 }
292
293 if (ctx->out_path == FIMC_IO_DMA) {
294 u32 color = dst_frame->fmt->color;
295
296 if (color >= FIMC_FMT_RGB444 && color <= FIMC_FMT_RGB565)
297 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB565;
298 else if (color == FIMC_FMT_RGB666)
299 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB666;
300 else if (color == FIMC_FMT_RGB888)
301 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888;
302 } else {
303 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888;
304
305 if (ctx->flags & FIMC_SCAN_MODE_INTERLACED)
306 cfg |= FIMC_REG_CISCCTRL_INTERLACE;
307 }
308
309 writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
310 }
311
312 void fimc_hw_set_mainscaler(struct fimc_ctx *ctx)
313 {
314 struct fimc_dev *dev = ctx->fimc_dev;
315 const struct fimc_variant *variant = dev->variant;
316 struct fimc_scaler *sc = &ctx->scaler;
317 u32 cfg;
318
319 dbg("main_hratio= 0x%X main_vratio= 0x%X",
320 sc->main_hratio, sc->main_vratio);
321
322 fimc_hw_set_scaler(ctx);
323
324 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);
325 cfg &= ~(FIMC_REG_CISCCTRL_MHRATIO_MASK |
326 FIMC_REG_CISCCTRL_MVRATIO_MASK);
327
328 if (variant->has_mainscaler_ext) {
329 cfg |= FIMC_REG_CISCCTRL_MHRATIO_EXT(sc->main_hratio);
330 cfg |= FIMC_REG_CISCCTRL_MVRATIO_EXT(sc->main_vratio);
331 writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
332
333 cfg = readl(dev->regs + FIMC_REG_CIEXTEN);
334
335 cfg &= ~(FIMC_REG_CIEXTEN_MVRATIO_EXT_MASK |
336 FIMC_REG_CIEXTEN_MHRATIO_EXT_MASK);
337 cfg |= FIMC_REG_CIEXTEN_MHRATIO_EXT(sc->main_hratio);
338 cfg |= FIMC_REG_CIEXTEN_MVRATIO_EXT(sc->main_vratio);
339 writel(cfg, dev->regs + FIMC_REG_CIEXTEN);
340 } else {
341 cfg |= FIMC_REG_CISCCTRL_MHRATIO(sc->main_hratio);
342 cfg |= FIMC_REG_CISCCTRL_MVRATIO(sc->main_vratio);
343 writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
344 }
345 }
346
347 void fimc_hw_enable_capture(struct fimc_ctx *ctx)
348 {
349 struct fimc_dev *dev = ctx->fimc_dev;
350 u32 cfg;
351
352 cfg = readl(dev->regs + FIMC_REG_CIIMGCPT);
353 cfg |= FIMC_REG_CIIMGCPT_CPT_FREN_ENABLE;
354
355 if (ctx->scaler.enabled)
356 cfg |= FIMC_REG_CIIMGCPT_IMGCPTEN_SC;
357 else
358 cfg &= FIMC_REG_CIIMGCPT_IMGCPTEN_SC;
359
360 cfg |= FIMC_REG_CIIMGCPT_IMGCPTEN;
361 writel(cfg, dev->regs + FIMC_REG_CIIMGCPT);
362 }
363
364 void fimc_hw_disable_capture(struct fimc_dev *dev)
365 {
366 u32 cfg = readl(dev->regs + FIMC_REG_CIIMGCPT);
367 cfg &= ~(FIMC_REG_CIIMGCPT_IMGCPTEN |
368 FIMC_REG_CIIMGCPT_IMGCPTEN_SC);
369 writel(cfg, dev->regs + FIMC_REG_CIIMGCPT);
370 }
371
372 void fimc_hw_set_effect(struct fimc_ctx *ctx)
373 {
374 struct fimc_dev *dev = ctx->fimc_dev;
375 struct fimc_effect *effect = &ctx->effect;
376 u32 cfg = 0;
377
378 if (effect->type != FIMC_REG_CIIMGEFF_FIN_BYPASS) {
379 cfg |= FIMC_REG_CIIMGEFF_IE_SC_AFTER |
380 FIMC_REG_CIIMGEFF_IE_ENABLE;
381 cfg |= effect->type;
382 if (effect->type == FIMC_REG_CIIMGEFF_FIN_ARBITRARY)
383 cfg |= (effect->pat_cb << 13) | effect->pat_cr;
384 }
385
386 writel(cfg, dev->regs + FIMC_REG_CIIMGEFF);
387 }
388
389 void fimc_hw_set_rgb_alpha(struct fimc_ctx *ctx)
390 {
391 struct fimc_dev *dev = ctx->fimc_dev;
392 struct fimc_frame *frame = &ctx->d_frame;
393 u32 cfg;
394
395 if (!(frame->fmt->flags & FMT_HAS_ALPHA))
396 return;
397
398 cfg = readl(dev->regs + FIMC_REG_CIOCTRL);
399 cfg &= ~FIMC_REG_CIOCTRL_ALPHA_OUT_MASK;
400 cfg |= (frame->alpha << 4);
401 writel(cfg, dev->regs + FIMC_REG_CIOCTRL);
402 }
403
404 static void fimc_hw_set_in_dma_size(struct fimc_ctx *ctx)
405 {
406 struct fimc_dev *dev = ctx->fimc_dev;
407 struct fimc_frame *frame = &ctx->s_frame;
408 u32 cfg_o = 0;
409 u32 cfg_r = 0;
410
411 if (FIMC_IO_LCDFIFO == ctx->out_path)
412 cfg_r |= FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN;
413
414 cfg_o |= (frame->f_height << 16) | frame->f_width;
415 cfg_r |= (frame->height << 16) | frame->width;
416
417 writel(cfg_o, dev->regs + FIMC_REG_ORGISIZE);
418 writel(cfg_r, dev->regs + FIMC_REG_CIREAL_ISIZE);
419 }
420
421 void fimc_hw_set_in_dma(struct fimc_ctx *ctx)
422 {
423 struct fimc_dev *dev = ctx->fimc_dev;
424 struct fimc_frame *frame = &ctx->s_frame;
425 struct fimc_dma_offset *offset = &frame->dma_offset;
426 u32 cfg;
427
428 /* Set the pixel offsets. */
429 cfg = (offset->y_v << 16) | offset->y_h;
430 writel(cfg, dev->regs + FIMC_REG_CIIYOFF);
431
432 cfg = (offset->cb_v << 16) | offset->cb_h;
433 writel(cfg, dev->regs + FIMC_REG_CIICBOFF);
434
435 cfg = (offset->cr_v << 16) | offset->cr_h;
436 writel(cfg, dev->regs + FIMC_REG_CIICROFF);
437
438 /* Input original and real size. */
439 fimc_hw_set_in_dma_size(ctx);
440
441 /* Use DMA autoload only in FIFO mode. */
442 fimc_hw_en_autoload(dev, ctx->out_path == FIMC_IO_LCDFIFO);
443
444 /* Set the input DMA to process single frame only. */
445 cfg = readl(dev->regs + FIMC_REG_MSCTRL);
446 cfg &= ~(FIMC_REG_MSCTRL_INFORMAT_MASK
447 | FIMC_REG_MSCTRL_IN_BURST_COUNT_MASK
448 | FIMC_REG_MSCTRL_INPUT_MASK
449 | FIMC_REG_MSCTRL_C_INT_IN_MASK
450 | FIMC_REG_MSCTRL_2P_IN_ORDER_MASK);
451
452 cfg |= (FIMC_REG_MSCTRL_IN_BURST_COUNT(4)
453 | FIMC_REG_MSCTRL_INPUT_MEMORY
454 | FIMC_REG_MSCTRL_FIFO_CTRL_FULL);
455
456 switch (frame->fmt->color) {
457 case FIMC_FMT_RGB565...FIMC_FMT_RGB888:
458 cfg |= FIMC_REG_MSCTRL_INFORMAT_RGB;
459 break;
460 case FIMC_FMT_YCBCR420:
461 cfg |= FIMC_REG_MSCTRL_INFORMAT_YCBCR420;
462
463 if (frame->fmt->colplanes == 2)
464 cfg |= ctx->in_order_2p | FIMC_REG_MSCTRL_C_INT_IN_2PLANE;
465 else
466 cfg |= FIMC_REG_MSCTRL_C_INT_IN_3PLANE;
467
468 break;
469 case FIMC_FMT_YCBYCR422...FIMC_FMT_CRYCBY422:
470 if (frame->fmt->colplanes == 1) {
471 cfg |= ctx->in_order_1p
472 | FIMC_REG_MSCTRL_INFORMAT_YCBCR422_1P;
473 } else {
474 cfg |= FIMC_REG_MSCTRL_INFORMAT_YCBCR422;
475
476 if (frame->fmt->colplanes == 2)
477 cfg |= ctx->in_order_2p
478 | FIMC_REG_MSCTRL_C_INT_IN_2PLANE;
479 else
480 cfg |= FIMC_REG_MSCTRL_C_INT_IN_3PLANE;
481 }
482 break;
483 default:
484 break;
485 }
486
487 writel(cfg, dev->regs + FIMC_REG_MSCTRL);
488
489 /* Input/output DMA linear/tiled mode. */
490 cfg = readl(dev->regs + FIMC_REG_CIDMAPARAM);
491 cfg &= ~FIMC_REG_CIDMAPARAM_TILE_MASK;
492
493 if (tiled_fmt(ctx->s_frame.fmt))
494 cfg |= FIMC_REG_CIDMAPARAM_R_64X32;
495
496 if (tiled_fmt(ctx->d_frame.fmt))
497 cfg |= FIMC_REG_CIDMAPARAM_W_64X32;
498
499 writel(cfg, dev->regs + FIMC_REG_CIDMAPARAM);
500 }
501
502
503 void fimc_hw_set_input_path(struct fimc_ctx *ctx)
504 {
505 struct fimc_dev *dev = ctx->fimc_dev;
506
507 u32 cfg = readl(dev->regs + FIMC_REG_MSCTRL);
508 cfg &= ~FIMC_REG_MSCTRL_INPUT_MASK;
509
510 if (ctx->in_path == FIMC_IO_DMA)
511 cfg |= FIMC_REG_MSCTRL_INPUT_MEMORY;
512 else
513 cfg |= FIMC_REG_MSCTRL_INPUT_EXTCAM;
514
515 writel(cfg, dev->regs + FIMC_REG_MSCTRL);
516 }
517
518 void fimc_hw_set_output_path(struct fimc_ctx *ctx)
519 {
520 struct fimc_dev *dev = ctx->fimc_dev;
521
522 u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);
523 cfg &= ~FIMC_REG_CISCCTRL_LCDPATHEN_FIFO;
524 if (ctx->out_path == FIMC_IO_LCDFIFO)
525 cfg |= FIMC_REG_CISCCTRL_LCDPATHEN_FIFO;
526 writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
527 }
528
529 void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *paddr)
530 {
531 u32 cfg = readl(dev->regs + FIMC_REG_CIREAL_ISIZE);
532 cfg |= FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS;
533 writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE);
534
535 writel(paddr->y, dev->regs + FIMC_REG_CIIYSA(0));
536 writel(paddr->cb, dev->regs + FIMC_REG_CIICBSA(0));
537 writel(paddr->cr, dev->regs + FIMC_REG_CIICRSA(0));
538
539 cfg &= ~FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS;
540 writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE);
541 }
542
543 void fimc_hw_set_output_addr(struct fimc_dev *dev,
544 struct fimc_addr *paddr, int index)
545 {
546 int i = (index == -1) ? 0 : index;
547 do {
548 writel(paddr->y, dev->regs + FIMC_REG_CIOYSA(i));
549 writel(paddr->cb, dev->regs + FIMC_REG_CIOCBSA(i));
550 writel(paddr->cr, dev->regs + FIMC_REG_CIOCRSA(i));
551 dbg("dst_buf[%d]: 0x%X, cb: 0x%X, cr: 0x%X",
552 i, paddr->y, paddr->cb, paddr->cr);
553 } while (index == -1 && ++i < FIMC_MAX_OUT_BUFS);
554 }
555
556 int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
557 struct fimc_source_info *cam)
558 {
559 u32 cfg = readl(fimc->regs + FIMC_REG_CIGCTRL);
560
561 cfg &= ~(FIMC_REG_CIGCTRL_INVPOLPCLK | FIMC_REG_CIGCTRL_INVPOLVSYNC |
562 FIMC_REG_CIGCTRL_INVPOLHREF | FIMC_REG_CIGCTRL_INVPOLHSYNC |
563 FIMC_REG_CIGCTRL_INVPOLFIELD);
564
565 if (cam->flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
566 cfg |= FIMC_REG_CIGCTRL_INVPOLPCLK;
567
568 if (cam->flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
569 cfg |= FIMC_REG_CIGCTRL_INVPOLVSYNC;
570
571 if (cam->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
572 cfg |= FIMC_REG_CIGCTRL_INVPOLHREF;
573
574 if (cam->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
575 cfg |= FIMC_REG_CIGCTRL_INVPOLHSYNC;
576
577 if (cam->flags & V4L2_MBUS_FIELD_EVEN_LOW)
578 cfg |= FIMC_REG_CIGCTRL_INVPOLFIELD;
579
580 writel(cfg, fimc->regs + FIMC_REG_CIGCTRL);
581
582 return 0;
583 }
584
585 struct mbus_pixfmt_desc {
586 u32 pixelcode;
587 u32 cisrcfmt;
588 u16 bus_width;
589 };
590
591 static const struct mbus_pixfmt_desc pix_desc[] = {
592 { V4L2_MBUS_FMT_YUYV8_2X8, FIMC_REG_CISRCFMT_ORDER422_YCBYCR, 8 },
593 { V4L2_MBUS_FMT_YVYU8_2X8, FIMC_REG_CISRCFMT_ORDER422_YCRYCB, 8 },
594 { V4L2_MBUS_FMT_VYUY8_2X8, FIMC_REG_CISRCFMT_ORDER422_CRYCBY, 8 },
595 { V4L2_MBUS_FMT_UYVY8_2X8, FIMC_REG_CISRCFMT_ORDER422_CBYCRY, 8 },
596 };
597
598 int fimc_hw_set_camera_source(struct fimc_dev *fimc,
599 struct fimc_source_info *source)
600 {
601 struct fimc_frame *f = &fimc->vid_cap.ctx->s_frame;
602 u32 bus_width, cfg = 0;
603 int i;
604
605 switch (source->fimc_bus_type) {
606 case FIMC_BUS_TYPE_ITU_601:
607 case FIMC_BUS_TYPE_ITU_656:
608 for (i = 0; i < ARRAY_SIZE(pix_desc); i++) {
609 if (fimc->vid_cap.mf.code == pix_desc[i].pixelcode) {
610 cfg = pix_desc[i].cisrcfmt;
611 bus_width = pix_desc[i].bus_width;
612 break;
613 }
614 }
615
616 if (i == ARRAY_SIZE(pix_desc)) {
617 v4l2_err(&fimc->vid_cap.vfd,
618 "Camera color format not supported: %d\n",
619 fimc->vid_cap.mf.code);
620 return -EINVAL;
621 }
622
623 if (source->fimc_bus_type == FIMC_BUS_TYPE_ITU_601) {
624 if (bus_width == 8)
625 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT;
626 else if (bus_width == 16)
627 cfg |= FIMC_REG_CISRCFMT_ITU601_16BIT;
628 } /* else defaults to ITU-R BT.656 8-bit */
629 break;
630 case FIMC_BUS_TYPE_MIPI_CSI2:
631 if (fimc_fmt_is_user_defined(f->fmt->color))
632 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT;
633 break;
634 }
635
636 cfg |= (f->o_width << 16) | f->o_height;
637 writel(cfg, fimc->regs + FIMC_REG_CISRCFMT);
638 return 0;
639 }
640
641 void fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f)
642 {
643 u32 hoff2, voff2;
644
645 u32 cfg = readl(fimc->regs + FIMC_REG_CIWDOFST);
646
647 cfg &= ~(FIMC_REG_CIWDOFST_HOROFF_MASK | FIMC_REG_CIWDOFST_VEROFF_MASK);
648 cfg |= FIMC_REG_CIWDOFST_OFF_EN |
649 (f->offs_h << 16) | f->offs_v;
650
651 writel(cfg, fimc->regs + FIMC_REG_CIWDOFST);
652
653 /* See CIWDOFSTn register description in the datasheet for details. */
654 hoff2 = f->o_width - f->width - f->offs_h;
655 voff2 = f->o_height - f->height - f->offs_v;
656 cfg = (hoff2 << 16) | voff2;
657 writel(cfg, fimc->regs + FIMC_REG_CIWDOFST2);
658 }
659
660 int fimc_hw_set_camera_type(struct fimc_dev *fimc,
661 struct fimc_source_info *source)
662 {
663 u32 cfg, tmp;
664 struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
665 u32 csis_data_alignment = 32;
666
667 cfg = readl(fimc->regs + FIMC_REG_CIGCTRL);
668
669 /* Select ITU B interface, disable Writeback path and test pattern. */
670 cfg &= ~(FIMC_REG_CIGCTRL_TESTPAT_MASK | FIMC_REG_CIGCTRL_SELCAM_ITU_A |
671 FIMC_REG_CIGCTRL_SELCAM_MIPI | FIMC_REG_CIGCTRL_CAMIF_SELWB |
672 FIMC_REG_CIGCTRL_SELCAM_MIPI_A | FIMC_REG_CIGCTRL_CAM_JPEG);
673
674 switch (source->fimc_bus_type) {
675 case FIMC_BUS_TYPE_MIPI_CSI2:
676 cfg |= FIMC_REG_CIGCTRL_SELCAM_MIPI;
677
678 if (source->mux_id == 0)
679 cfg |= FIMC_REG_CIGCTRL_SELCAM_MIPI_A;
680
681 /* TODO: add remaining supported formats. */
682 switch (vid_cap->mf.code) {
683 case V4L2_MBUS_FMT_VYUY8_2X8:
684 tmp = FIMC_REG_CSIIMGFMT_YCBCR422_8BIT;
685 break;
686 case V4L2_MBUS_FMT_JPEG_1X8:
687 case V4L2_MBUS_FMT_S5C_UYVY_JPEG_1X8:
688 tmp = FIMC_REG_CSIIMGFMT_USER(1);
689 cfg |= FIMC_REG_CIGCTRL_CAM_JPEG;
690 break;
691 default:
692 v4l2_err(&vid_cap->vfd,
693 "Not supported camera pixel format: %#x\n",
694 vid_cap->mf.code);
695 return -EINVAL;
696 }
697 tmp |= (csis_data_alignment == 32) << 8;
698
699 writel(tmp, fimc->regs + FIMC_REG_CSIIMGFMT);
700 break;
701 case FIMC_BUS_TYPE_ITU_601...FIMC_BUS_TYPE_ITU_656:
702 if (source->mux_id == 0) /* ITU-A, ITU-B: 0, 1 */
703 cfg |= FIMC_REG_CIGCTRL_SELCAM_ITU_A;
704 break;
705 case FIMC_BUS_TYPE_LCD_WRITEBACK_A:
706 cfg |= FIMC_REG_CIGCTRL_CAMIF_SELWB;
707 break;
708 default:
709 v4l2_err(&vid_cap->vfd, "Invalid FIMC bus type selected: %d\n",
710 source->fimc_bus_type);
711 return -EINVAL;
712 }
713 writel(cfg, fimc->regs + FIMC_REG_CIGCTRL);
714
715 return 0;
716 }
717
718 void fimc_hw_clear_irq(struct fimc_dev *dev)
719 {
720 u32 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
721 cfg |= FIMC_REG_CIGCTRL_IRQ_CLR;
722 writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
723 }
724
725 void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on)
726 {
727 u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);
728 if (on)
729 cfg |= FIMC_REG_CISCCTRL_SCALERSTART;
730 else
731 cfg &= ~FIMC_REG_CISCCTRL_SCALERSTART;
732 writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
733 }
734
735 void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on)
736 {
737 u32 cfg = readl(dev->regs + FIMC_REG_MSCTRL);
738 if (on)
739 cfg |= FIMC_REG_MSCTRL_ENVID;
740 else
741 cfg &= ~FIMC_REG_MSCTRL_ENVID;
742 writel(cfg, dev->regs + FIMC_REG_MSCTRL);
743 }
744
745 /* Return an index to the buffer actually being written. */
746 s32 fimc_hw_get_frame_index(struct fimc_dev *dev)
747 {
748 s32 reg;
749
750 if (dev->variant->has_cistatus2) {
751 reg = readl(dev->regs + FIMC_REG_CISTATUS2) & 0x3f;
752 return reg - 1;
753 }
754
755 reg = readl(dev->regs + FIMC_REG_CISTATUS);
756
757 return (reg & FIMC_REG_CISTATUS_FRAMECNT_MASK) >>
758 FIMC_REG_CISTATUS_FRAMECNT_SHIFT;
759 }
760
761 /* Return an index to the buffer being written previously. */
762 s32 fimc_hw_get_prev_frame_index(struct fimc_dev *dev)
763 {
764 s32 reg;
765
766 if (!dev->variant->has_cistatus2)
767 return -1;
768
769 reg = readl(dev->regs + FIMC_REG_CISTATUS2);
770 return ((reg >> 7) & 0x3f) - 1;
771 }
772
773 /* Locking: the caller holds fimc->slock */
774 void fimc_activate_capture(struct fimc_ctx *ctx)
775 {
776 fimc_hw_enable_scaler(ctx->fimc_dev, ctx->scaler.enabled);
777 fimc_hw_enable_capture(ctx);
778 }
779
780 void fimc_deactivate_capture(struct fimc_dev *fimc)
781 {
782 fimc_hw_en_lastirq(fimc, true);
783 fimc_hw_disable_capture(fimc);
784 fimc_hw_enable_scaler(fimc, false);
785 fimc_hw_en_lastirq(fimc, false);
786 }
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