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net/mlx4_en: DCB QoS support
[linux-2.6/btrfs-unstable.git] / drivers / net / ethernet / mellanox / mlx4 / mlx4.h
blobcd56f1aea4b505aad5545b515c534dffe6bef1f1
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 */
36
37 #ifndef MLX4_H
38 #define MLX4_H
39
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/timer.h>
43 #include <linux/semaphore.h>
44 #include <linux/workqueue.h>
45
46 #include <linux/mlx4/device.h>
47 #include <linux/mlx4/driver.h>
48 #include <linux/mlx4/doorbell.h>
49 #include <linux/mlx4/cmd.h>
50
51 #define DRV_NAME "mlx4_core"
52 #define PFX DRV_NAME ": "
53 #define DRV_VERSION "1.1"
54 #define DRV_RELDATE "Dec, 2011"
55
56 #define MLX4_NUM_UP 8
57 #define MLX4_NUM_TC 8
58 #define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
59 #define MLX4_RATELIMIT_DEFAULT 0xffff
60
61 struct mlx4_set_port_prio2tc_context {
62 u8 prio2tc[4];
63 };
64
65 struct mlx4_port_scheduler_tc_cfg_be {
66 __be16 pg;
67 __be16 bw_precentage;
68 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
69 __be16 max_bw_value;
70 };
71
72 struct mlx4_set_port_scheduler_context {
73 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
74 };
75
76 enum {
77 MLX4_HCR_BASE = 0x80680,
78 MLX4_HCR_SIZE = 0x0001c,
79 MLX4_CLR_INT_SIZE = 0x00008,
80 MLX4_SLAVE_COMM_BASE = 0x0,
81 MLX4_COMM_PAGESIZE = 0x1000
82 };
83
84 enum {
85 MLX4_MAX_MGM_ENTRY_SIZE = 0x1000,
86 MLX4_MAX_QP_PER_MGM = 4 * (MLX4_MAX_MGM_ENTRY_SIZE / 16 - 2),
87 MLX4_MTT_ENTRY_PER_SEG = 8,
88 };
89
90 enum {
91 MLX4_NUM_PDS = 1 << 15
92 };
93
94 enum {
95 MLX4_CMPT_TYPE_QP = 0,
96 MLX4_CMPT_TYPE_SRQ = 1,
97 MLX4_CMPT_TYPE_CQ = 2,
98 MLX4_CMPT_TYPE_EQ = 3,
99 MLX4_CMPT_NUM_TYPE
100 };
101
102 enum {
103 MLX4_CMPT_SHIFT = 24,
104 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
105 };
106
107 enum mlx4_mr_state {
108 MLX4_MR_DISABLED = 0,
109 MLX4_MR_EN_HW,
110 MLX4_MR_EN_SW
111 };
112
113 #define MLX4_COMM_TIME 10000
114 enum {
115 MLX4_COMM_CMD_RESET,
116 MLX4_COMM_CMD_VHCR0,
117 MLX4_COMM_CMD_VHCR1,
118 MLX4_COMM_CMD_VHCR2,
119 MLX4_COMM_CMD_VHCR_EN,
120 MLX4_COMM_CMD_VHCR_POST,
121 MLX4_COMM_CMD_FLR = 254
122 };
123
124 /*The flag indicates that the slave should delay the RESET cmd*/
125 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
126 /*indicates how many retries will be done if we are in the middle of FLR*/
127 #define NUM_OF_RESET_RETRIES 10
128 #define SLEEP_TIME_IN_RESET (2 * 1000)
129 enum mlx4_resource {
130 RES_QP,
131 RES_CQ,
132 RES_SRQ,
133 RES_XRCD,
134 RES_MPT,
135 RES_MTT,
136 RES_MAC,
137 RES_VLAN,
138 RES_EQ,
139 RES_COUNTER,
140 MLX4_NUM_OF_RESOURCE_TYPE
141 };
142
143 enum mlx4_alloc_mode {
144 RES_OP_RESERVE,
145 RES_OP_RESERVE_AND_MAP,
146 RES_OP_MAP_ICM,
147 };
148
149
150 /*
151 *Virtual HCR structures.
152 * mlx4_vhcr is the sw representation, in machine endianess
153 *
154 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
155 * to FW to go through communication channel.
156 * It is big endian, and has the same structure as the physical HCR
157 * used by command interface
158 */
159 struct mlx4_vhcr {
160 u64 in_param;
161 u64 out_param;
162 u32 in_modifier;
163 u32 errno;
164 u16 op;
165 u16 token;
166 u8 op_modifier;
167 u8 e_bit;
168 };
169
170 struct mlx4_vhcr_cmd {
171 __be64 in_param;
172 __be32 in_modifier;
173 __be64 out_param;
174 __be16 token;
175 u16 reserved;
176 u8 status;
177 u8 flags;
178 __be16 opcode;
179 };
180
181 struct mlx4_cmd_info {
182 u16 opcode;
183 bool has_inbox;
184 bool has_outbox;
185 bool out_is_imm;
186 bool encode_slave_id;
187 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
188 struct mlx4_cmd_mailbox *inbox);
189 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
190 struct mlx4_cmd_mailbox *inbox,
191 struct mlx4_cmd_mailbox *outbox,
192 struct mlx4_cmd_info *cmd);
193 };
194
195 #ifdef CONFIG_MLX4_DEBUG
196 extern int mlx4_debug_level;
197 #else /* CONFIG_MLX4_DEBUG */
198 #define mlx4_debug_level (0)
199 #endif /* CONFIG_MLX4_DEBUG */
200
201 #define mlx4_dbg(mdev, format, arg...) \
202 do { \
203 if (mlx4_debug_level) \
204 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
205 } while (0)
206
207 #define mlx4_err(mdev, format, arg...) \
208 dev_err(&mdev->pdev->dev, format, ##arg)
209 #define mlx4_info(mdev, format, arg...) \
210 dev_info(&mdev->pdev->dev, format, ##arg)
211 #define mlx4_warn(mdev, format, arg...) \
212 dev_warn(&mdev->pdev->dev, format, ##arg)
213
214 extern int mlx4_log_num_mgm_entry_size;
215 extern int log_mtts_per_seg;
216
217 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
218 #define ALL_SLAVES 0xff
219
220 struct mlx4_bitmap {
221 u32 last;
222 u32 top;
223 u32 max;
224 u32 reserved_top;
225 u32 mask;
226 u32 avail;
227 spinlock_t lock;
228 unsigned long *table;
229 };
230
231 struct mlx4_buddy {
232 unsigned long **bits;
233 unsigned int *num_free;
234 int max_order;
235 spinlock_t lock;
236 };
237
238 struct mlx4_icm;
239
240 struct mlx4_icm_table {
241 u64 virt;
242 int num_icm;
243 int num_obj;
244 int obj_size;
245 int lowmem;
246 int coherent;
247 struct mutex mutex;
248 struct mlx4_icm **icm;
249 };
250
251 /*
252 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
253 */
254 struct mlx4_mpt_entry {
255 __be32 flags;
256 __be32 qpn;
257 __be32 key;
258 __be32 pd_flags;
259 __be64 start;
260 __be64 length;
261 __be32 lkey;
262 __be32 win_cnt;
263 u8 reserved1[3];
264 u8 mtt_rep;
265 __be64 mtt_addr;
266 __be32 mtt_sz;
267 __be32 entity_size;
268 __be32 first_byte_offset;
269 } __packed;
270
271 /*
272 * Must be packed because start is 64 bits but only aligned to 32 bits.
273 */
274 struct mlx4_eq_context {
275 __be32 flags;
276 u16 reserved1[3];
277 __be16 page_offset;
278 u8 log_eq_size;
279 u8 reserved2[4];
280 u8 eq_period;
281 u8 reserved3;
282 u8 eq_max_count;
283 u8 reserved4[3];
284 u8 intr;
285 u8 log_page_size;
286 u8 reserved5[2];
287 u8 mtt_base_addr_h;
288 __be32 mtt_base_addr_l;
289 u32 reserved6[2];
290 __be32 consumer_index;
291 __be32 producer_index;
292 u32 reserved7[4];
293 };
294
295 struct mlx4_cq_context {
296 __be32 flags;
297 u16 reserved1[3];
298 __be16 page_offset;
299 __be32 logsize_usrpage;
300 __be16 cq_period;
301 __be16 cq_max_count;
302 u8 reserved2[3];
303 u8 comp_eqn;
304 u8 log_page_size;
305 u8 reserved3[2];
306 u8 mtt_base_addr_h;
307 __be32 mtt_base_addr_l;
308 __be32 last_notified_index;
309 __be32 solicit_producer_index;
310 __be32 consumer_index;
311 __be32 producer_index;
312 u32 reserved4[2];
313 __be64 db_rec_addr;
314 };
315
316 struct mlx4_srq_context {
317 __be32 state_logsize_srqn;
318 u8 logstride;
319 u8 reserved1;
320 __be16 xrcd;
321 __be32 pg_offset_cqn;
322 u32 reserved2;
323 u8 log_page_size;
324 u8 reserved3[2];
325 u8 mtt_base_addr_h;
326 __be32 mtt_base_addr_l;
327 __be32 pd;
328 __be16 limit_watermark;
329 __be16 wqe_cnt;
330 u16 reserved4;
331 __be16 wqe_counter;
332 u32 reserved5;
333 __be64 db_rec_addr;
334 };
335
336 struct mlx4_eqe {
337 u8 reserved1;
338 u8 type;
339 u8 reserved2;
340 u8 subtype;
341 union {
342 u32 raw[6];
343 struct {
344 __be32 cqn;
345 } __packed comp;
346 struct {
347 u16 reserved1;
348 __be16 token;
349 u32 reserved2;
350 u8 reserved3[3];
351 u8 status;
352 __be64 out_param;
353 } __packed cmd;
354 struct {
355 __be32 qpn;
356 } __packed qp;
357 struct {
358 __be32 srqn;
359 } __packed srq;
360 struct {
361 __be32 cqn;
362 u32 reserved1;
363 u8 reserved2[3];
364 u8 syndrome;
365 } __packed cq_err;
366 struct {
367 u32 reserved1[2];
368 __be32 port;
369 } __packed port_change;
370 struct {
371 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
372 u32 reserved;
373 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
374 } __packed comm_channel_arm;
375 struct {
376 u8 port;
377 u8 reserved[3];
378 __be64 mac;
379 } __packed mac_update;
380 struct {
381 u8 port;
382 } __packed sw_event;
383 struct {
384 __be32 slave_id;
385 } __packed flr_event;
386 struct {
387 __be16 current_temperature;
388 __be16 warning_threshold;
389 } __packed warming;
390 } event;
391 u8 slave_id;
392 u8 reserved3[2];
393 u8 owner;
394 } __packed;
395
396 struct mlx4_eq {
397 struct mlx4_dev *dev;
398 void __iomem *doorbell;
399 int eqn;
400 u32 cons_index;
401 u16 irq;
402 u16 have_irq;
403 int nent;
404 struct mlx4_buf_list *page_list;
405 struct mlx4_mtt mtt;
406 };
407
408 struct mlx4_slave_eqe {
409 u8 type;
410 u8 port;
411 u32 param;
412 };
413
414 struct mlx4_slave_event_eq_info {
415 int eqn;
416 u16 token;
417 };
418
419 struct mlx4_profile {
420 int num_qp;
421 int rdmarc_per_qp;
422 int num_srq;
423 int num_cq;
424 int num_mcg;
425 int num_mpt;
426 unsigned num_mtt;
427 };
428
429 struct mlx4_fw {
430 u64 clr_int_base;
431 u64 catas_offset;
432 u64 comm_base;
433 struct mlx4_icm *fw_icm;
434 struct mlx4_icm *aux_icm;
435 u32 catas_size;
436 u16 fw_pages;
437 u8 clr_int_bar;
438 u8 catas_bar;
439 u8 comm_bar;
440 };
441
442 struct mlx4_comm {
443 u32 slave_write;
444 u32 slave_read;
445 };
446
447 enum {
448 MLX4_MCAST_CONFIG = 0,
449 MLX4_MCAST_DISABLE = 1,
450 MLX4_MCAST_ENABLE = 2,
451 };
452
453 #define VLAN_FLTR_SIZE 128
454
455 struct mlx4_vlan_fltr {
456 __be32 entry[VLAN_FLTR_SIZE];
457 };
458
459 struct mlx4_mcast_entry {
460 struct list_head list;
461 u64 addr;
462 };
463
464 struct mlx4_promisc_qp {
465 struct list_head list;
466 u32 qpn;
467 };
468
469 struct mlx4_steer_index {
470 struct list_head list;
471 unsigned int index;
472 struct list_head duplicates;
473 };
474
475 #define MLX4_EVENT_TYPES_NUM 64
476
477 struct mlx4_slave_state {
478 u8 comm_toggle;
479 u8 last_cmd;
480 u8 init_port_mask;
481 bool active;
482 u8 function;
483 dma_addr_t vhcr_dma;
484 u16 mtu[MLX4_MAX_PORTS + 1];
485 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
486 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
487 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
488 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
489 /* event type to eq number lookup */
490 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
491 u16 eq_pi;
492 u16 eq_ci;
493 spinlock_t lock;
494 /*initialized via the kzalloc*/
495 u8 is_slave_going_down;
496 u32 cookie;
497 };
498
499 struct slave_list {
500 struct mutex mutex;
501 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
502 };
503
504 struct mlx4_resource_tracker {
505 spinlock_t lock;
506 /* tree for each resources */
507 struct radix_tree_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
508 /* num_of_slave's lists, one per slave */
509 struct slave_list *slave_list;
510 };
511
512 #define SLAVE_EVENT_EQ_SIZE 128
513 struct mlx4_slave_event_eq {
514 u32 eqn;
515 u32 cons;
516 u32 prod;
517 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
518 };
519
520 struct mlx4_master_qp0_state {
521 int proxy_qp0_active;
522 int qp0_active;
523 int port_active;
524 };
525
526 struct mlx4_mfunc_master_ctx {
527 struct mlx4_slave_state *slave_state;
528 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
529 int init_port_ref[MLX4_MAX_PORTS + 1];
530 u16 max_mtu[MLX4_MAX_PORTS + 1];
531 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
532 struct mlx4_resource_tracker res_tracker;
533 struct workqueue_struct *comm_wq;
534 struct work_struct comm_work;
535 struct work_struct slave_event_work;
536 struct work_struct slave_flr_event_work;
537 spinlock_t slave_state_lock;
538 __be32 comm_arm_bit_vector[4];
539 struct mlx4_eqe cmd_eqe;
540 struct mlx4_slave_event_eq slave_eq;
541 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
542 };
543
544 struct mlx4_mfunc {
545 struct mlx4_comm __iomem *comm;
546 struct mlx4_vhcr_cmd *vhcr;
547 dma_addr_t vhcr_dma;
548
549 struct mlx4_mfunc_master_ctx master;
550 };
551
552 struct mlx4_cmd {
553 struct pci_pool *pool;
554 void __iomem *hcr;
555 struct mutex hcr_mutex;
556 struct semaphore poll_sem;
557 struct semaphore event_sem;
558 struct semaphore slave_sem;
559 int max_cmds;
560 spinlock_t context_lock;
561 int free_head;
562 struct mlx4_cmd_context *context;
563 u16 token_mask;
564 u8 use_events;
565 u8 toggle;
566 u8 comm_toggle;
567 };
568
569 struct mlx4_uar_table {
570 struct mlx4_bitmap bitmap;
571 };
572
573 struct mlx4_mr_table {
574 struct mlx4_bitmap mpt_bitmap;
575 struct mlx4_buddy mtt_buddy;
576 u64 mtt_base;
577 u64 mpt_base;
578 struct mlx4_icm_table mtt_table;
579 struct mlx4_icm_table dmpt_table;
580 };
581
582 struct mlx4_cq_table {
583 struct mlx4_bitmap bitmap;
584 spinlock_t lock;
585 struct radix_tree_root tree;
586 struct mlx4_icm_table table;
587 struct mlx4_icm_table cmpt_table;
588 };
589
590 struct mlx4_eq_table {
591 struct mlx4_bitmap bitmap;
592 char *irq_names;
593 void __iomem *clr_int;
594 void __iomem **uar_map;
595 u32 clr_mask;
596 struct mlx4_eq *eq;
597 struct mlx4_icm_table table;
598 struct mlx4_icm_table cmpt_table;
599 int have_irq;
600 u8 inta_pin;
601 };
602
603 struct mlx4_srq_table {
604 struct mlx4_bitmap bitmap;
605 spinlock_t lock;
606 struct radix_tree_root tree;
607 struct mlx4_icm_table table;
608 struct mlx4_icm_table cmpt_table;
609 };
610
611 struct mlx4_qp_table {
612 struct mlx4_bitmap bitmap;
613 u32 rdmarc_base;
614 int rdmarc_shift;
615 spinlock_t lock;
616 struct mlx4_icm_table qp_table;
617 struct mlx4_icm_table auxc_table;
618 struct mlx4_icm_table altc_table;
619 struct mlx4_icm_table rdmarc_table;
620 struct mlx4_icm_table cmpt_table;
621 };
622
623 struct mlx4_mcg_table {
624 struct mutex mutex;
625 struct mlx4_bitmap bitmap;
626 struct mlx4_icm_table table;
627 };
628
629 struct mlx4_catas_err {
630 u32 __iomem *map;
631 struct timer_list timer;
632 struct list_head list;
633 };
634
635 #define MLX4_MAX_MAC_NUM 128
636 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
637
638 struct mlx4_mac_table {
639 __be64 entries[MLX4_MAX_MAC_NUM];
640 int refs[MLX4_MAX_MAC_NUM];
641 struct mutex mutex;
642 int total;
643 int max;
644 };
645
646 #define MLX4_MAX_VLAN_NUM 128
647 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
648
649 struct mlx4_vlan_table {
650 __be32 entries[MLX4_MAX_VLAN_NUM];
651 int refs[MLX4_MAX_VLAN_NUM];
652 struct mutex mutex;
653 int total;
654 int max;
655 };
656
657 #define SET_PORT_GEN_ALL_VALID 0x7
658 #define SET_PORT_PROMISC_SHIFT 31
659 #define SET_PORT_MC_PROMISC_SHIFT 30
660
661 enum {
662 MCAST_DIRECT_ONLY = 0,
663 MCAST_DIRECT = 1,
664 MCAST_DEFAULT = 2
665 };
666
667
668 struct mlx4_set_port_general_context {
669 u8 reserved[3];
670 u8 flags;
671 u16 reserved2;
672 __be16 mtu;
673 u8 pptx;
674 u8 pfctx;
675 u16 reserved3;
676 u8 pprx;
677 u8 pfcrx;
678 u16 reserved4;
679 };
680
681 struct mlx4_set_port_rqp_calc_context {
682 __be32 base_qpn;
683 u8 rererved;
684 u8 n_mac;
685 u8 n_vlan;
686 u8 n_prio;
687 u8 reserved2[3];
688 u8 mac_miss;
689 u8 intra_no_vlan;
690 u8 no_vlan;
691 u8 intra_vlan_miss;
692 u8 vlan_miss;
693 u8 reserved3[3];
694 u8 no_vlan_prio;
695 __be32 promisc;
696 __be32 mcast;
697 };
698
699 struct mlx4_mac_entry {
700 u64 mac;
701 };
702
703 struct mlx4_port_info {
704 struct mlx4_dev *dev;
705 int port;
706 char dev_name[16];
707 struct device_attribute port_attr;
708 enum mlx4_port_type tmp_type;
709 char dev_mtu_name[16];
710 struct device_attribute port_mtu_attr;
711 struct mlx4_mac_table mac_table;
712 struct radix_tree_root mac_tree;
713 struct mlx4_vlan_table vlan_table;
714 int base_qpn;
715 };
716
717 struct mlx4_sense {
718 struct mlx4_dev *dev;
719 u8 do_sense_port[MLX4_MAX_PORTS + 1];
720 u8 sense_allowed[MLX4_MAX_PORTS + 1];
721 struct delayed_work sense_poll;
722 };
723
724 struct mlx4_msix_ctl {
725 u64 pool_bm;
726 struct mutex pool_lock;
727 };
728
729 struct mlx4_steer {
730 struct list_head promisc_qps[MLX4_NUM_STEERS];
731 struct list_head steer_entries[MLX4_NUM_STEERS];
732 };
733
734 struct mlx4_priv {
735 struct mlx4_dev dev;
736
737 struct list_head dev_list;
738 struct list_head ctx_list;
739 spinlock_t ctx_lock;
740
741 struct list_head pgdir_list;
742 struct mutex pgdir_mutex;
743
744 struct mlx4_fw fw;
745 struct mlx4_cmd cmd;
746 struct mlx4_mfunc mfunc;
747
748 struct mlx4_bitmap pd_bitmap;
749 struct mlx4_bitmap xrcd_bitmap;
750 struct mlx4_uar_table uar_table;
751 struct mlx4_mr_table mr_table;
752 struct mlx4_cq_table cq_table;
753 struct mlx4_eq_table eq_table;
754 struct mlx4_srq_table srq_table;
755 struct mlx4_qp_table qp_table;
756 struct mlx4_mcg_table mcg_table;
757 struct mlx4_bitmap counters_bitmap;
758
759 struct mlx4_catas_err catas_err;
760
761 void __iomem *clr_base;
762
763 struct mlx4_uar driver_uar;
764 void __iomem *kar;
765 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
766 struct mlx4_sense sense;
767 struct mutex port_mutex;
768 struct mlx4_msix_ctl msix_ctl;
769 struct mlx4_steer *steer;
770 struct list_head bf_list;
771 struct mutex bf_mutex;
772 struct io_mapping *bf_mapping;
773 int reserved_mtts;
774 };
775
776 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
777 {
778 return container_of(dev, struct mlx4_priv, dev);
779 }
780
781 #define MLX4_SENSE_RANGE (HZ * 3)
782
783 extern struct workqueue_struct *mlx4_wq;
784
785 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
786 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
787 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
788 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
789 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
790 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
791 u32 reserved_bot, u32 resetrved_top);
792 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
793
794 int mlx4_reset(struct mlx4_dev *dev);
795
796 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
797 void mlx4_free_eq_table(struct mlx4_dev *dev);
798
799 int mlx4_init_pd_table(struct mlx4_dev *dev);
800 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
801 int mlx4_init_uar_table(struct mlx4_dev *dev);
802 int mlx4_init_mr_table(struct mlx4_dev *dev);
803 int mlx4_init_eq_table(struct mlx4_dev *dev);
804 int mlx4_init_cq_table(struct mlx4_dev *dev);
805 int mlx4_init_qp_table(struct mlx4_dev *dev);
806 int mlx4_init_srq_table(struct mlx4_dev *dev);
807 int mlx4_init_mcg_table(struct mlx4_dev *dev);
808
809 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
810 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
811 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
812 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
813 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
814 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
815 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
816 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
817 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
818 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
819 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
820 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
821 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
822 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
823 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
824 int __mlx4_mr_reserve(struct mlx4_dev *dev);
825 void __mlx4_mr_release(struct mlx4_dev *dev, u32 index);
826 int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index);
827 void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index);
828 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
829 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
830
831 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
832 struct mlx4_vhcr *vhcr,
833 struct mlx4_cmd_mailbox *inbox,
834 struct mlx4_cmd_mailbox *outbox,
835 struct mlx4_cmd_info *cmd);
836 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
837 struct mlx4_vhcr *vhcr,
838 struct mlx4_cmd_mailbox *inbox,
839 struct mlx4_cmd_mailbox *outbox,
840 struct mlx4_cmd_info *cmd);
841 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
842 struct mlx4_vhcr *vhcr,
843 struct mlx4_cmd_mailbox *inbox,
844 struct mlx4_cmd_mailbox *outbox,
845 struct mlx4_cmd_info *cmd);
846 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
847 struct mlx4_vhcr *vhcr,
848 struct mlx4_cmd_mailbox *inbox,
849 struct mlx4_cmd_mailbox *outbox,
850 struct mlx4_cmd_info *cmd);
851 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
852 struct mlx4_vhcr *vhcr,
853 struct mlx4_cmd_mailbox *inbox,
854 struct mlx4_cmd_mailbox *outbox,
855 struct mlx4_cmd_info *cmd);
856 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
857 struct mlx4_vhcr *vhcr,
858 struct mlx4_cmd_mailbox *inbox,
859 struct mlx4_cmd_mailbox *outbox,
860 struct mlx4_cmd_info *cmd);
861 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
862 struct mlx4_vhcr *vhcr,
863 struct mlx4_cmd_mailbox *inbox,
864 struct mlx4_cmd_mailbox *outbox,
865 struct mlx4_cmd_info *cmd);
866 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
867 int *base);
868 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
869 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
870 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
871 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
872 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
873 int start_index, int npages, u64 *page_list);
874
875 void mlx4_start_catas_poll(struct mlx4_dev *dev);
876 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
877 void mlx4_catas_init(void);
878 int mlx4_restart_one(struct pci_dev *pdev);
879 int mlx4_register_device(struct mlx4_dev *dev);
880 void mlx4_unregister_device(struct mlx4_dev *dev);
881 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port);
882
883 struct mlx4_dev_cap;
884 struct mlx4_init_hca_param;
885
886 u64 mlx4_make_profile(struct mlx4_dev *dev,
887 struct mlx4_profile *request,
888 struct mlx4_dev_cap *dev_cap,
889 struct mlx4_init_hca_param *init_hca);
890 void mlx4_master_comm_channel(struct work_struct *work);
891 void mlx4_gen_slave_eqe(struct work_struct *work);
892 void mlx4_master_handle_slave_flr(struct work_struct *work);
893
894 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
895 struct mlx4_vhcr *vhcr,
896 struct mlx4_cmd_mailbox *inbox,
897 struct mlx4_cmd_mailbox *outbox,
898 struct mlx4_cmd_info *cmd);
899 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
900 struct mlx4_vhcr *vhcr,
901 struct mlx4_cmd_mailbox *inbox,
902 struct mlx4_cmd_mailbox *outbox,
903 struct mlx4_cmd_info *cmd);
904 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
905 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
906 struct mlx4_cmd_mailbox *outbox,
907 struct mlx4_cmd_info *cmd);
908 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
909 struct mlx4_vhcr *vhcr,
910 struct mlx4_cmd_mailbox *inbox,
911 struct mlx4_cmd_mailbox *outbox,
912 struct mlx4_cmd_info *cmd);
913 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
914 struct mlx4_vhcr *vhcr,
915 struct mlx4_cmd_mailbox *inbox,
916 struct mlx4_cmd_mailbox *outbox,
917 struct mlx4_cmd_info *cmd);
918 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
919 struct mlx4_vhcr *vhcr,
920 struct mlx4_cmd_mailbox *inbox,
921 struct mlx4_cmd_mailbox *outbox,
922 struct mlx4_cmd_info *cmd);
923 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
924 struct mlx4_vhcr *vhcr,
925 struct mlx4_cmd_mailbox *inbox,
926 struct mlx4_cmd_mailbox *outbox,
927 struct mlx4_cmd_info *cmd);
928 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
929 struct mlx4_vhcr *vhcr,
930 struct mlx4_cmd_mailbox *inbox,
931 struct mlx4_cmd_mailbox *outbox,
932 struct mlx4_cmd_info *cmd);
933 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
934 struct mlx4_vhcr *vhcr,
935 struct mlx4_cmd_mailbox *inbox,
936 struct mlx4_cmd_mailbox *outbox,
937 struct mlx4_cmd_info *cmd);
938 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
939 struct mlx4_vhcr *vhcr,
940 struct mlx4_cmd_mailbox *inbox,
941 struct mlx4_cmd_mailbox *outbox,
942 struct mlx4_cmd_info *cmd);
943 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
944 struct mlx4_vhcr *vhcr,
945 struct mlx4_cmd_mailbox *inbox,
946 struct mlx4_cmd_mailbox *outbox,
947 struct mlx4_cmd_info *cmd);
948 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
949 struct mlx4_vhcr *vhcr,
950 struct mlx4_cmd_mailbox *inbox,
951 struct mlx4_cmd_mailbox *outbox,
952 struct mlx4_cmd_info *cmd);
953 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
954 struct mlx4_vhcr *vhcr,
955 struct mlx4_cmd_mailbox *inbox,
956 struct mlx4_cmd_mailbox *outbox,
957 struct mlx4_cmd_info *cmd);
958 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
959 struct mlx4_vhcr *vhcr,
960 struct mlx4_cmd_mailbox *inbox,
961 struct mlx4_cmd_mailbox *outbox,
962 struct mlx4_cmd_info *cmd);
963 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
964 struct mlx4_vhcr *vhcr,
965 struct mlx4_cmd_mailbox *inbox,
966 struct mlx4_cmd_mailbox *outbox,
967 struct mlx4_cmd_info *cmd);
968 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
969 struct mlx4_vhcr *vhcr,
970 struct mlx4_cmd_mailbox *inbox,
971 struct mlx4_cmd_mailbox *outbox,
972 struct mlx4_cmd_info *cmd);
973 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
974 struct mlx4_vhcr *vhcr,
975 struct mlx4_cmd_mailbox *inbox,
976 struct mlx4_cmd_mailbox *outbox,
977 struct mlx4_cmd_info *cmd);
978 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
979 struct mlx4_vhcr *vhcr,
980 struct mlx4_cmd_mailbox *inbox,
981 struct mlx4_cmd_mailbox *outbox,
982 struct mlx4_cmd_info *cmd);
983
984 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
985
986 int mlx4_cmd_init(struct mlx4_dev *dev);
987 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
988 int mlx4_multi_func_init(struct mlx4_dev *dev);
989 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
990 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
991 int mlx4_cmd_use_events(struct mlx4_dev *dev);
992 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
993
994 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
995 unsigned long timeout);
996
997 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
998 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
999
1000 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1001
1002 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1003
1004 void mlx4_handle_catas_err(struct mlx4_dev *dev);
1005
1006 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1007 enum mlx4_port_type *type);
1008 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1009 enum mlx4_port_type *stype,
1010 enum mlx4_port_type *defaults);
1011 void mlx4_start_sense(struct mlx4_dev *dev);
1012 void mlx4_stop_sense(struct mlx4_dev *dev);
1013 void mlx4_sense_init(struct mlx4_dev *dev);
1014 int mlx4_check_port_params(struct mlx4_dev *dev,
1015 enum mlx4_port_type *port_type);
1016 int mlx4_change_port_types(struct mlx4_dev *dev,
1017 enum mlx4_port_type *port_types);
1018
1019 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1020 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1021
1022 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port);
1023 /* resource tracker functions*/
1024 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1025 enum mlx4_resource resource_type,
1026 int resource_id, int *slave);
1027 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1028 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1029
1030 void mlx4_free_resource_tracker(struct mlx4_dev *dev);
1031
1032 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1033 struct mlx4_vhcr *vhcr,
1034 struct mlx4_cmd_mailbox *inbox,
1035 struct mlx4_cmd_mailbox *outbox,
1036 struct mlx4_cmd_info *cmd);
1037 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1038 struct mlx4_vhcr *vhcr,
1039 struct mlx4_cmd_mailbox *inbox,
1040 struct mlx4_cmd_mailbox *outbox,
1041 struct mlx4_cmd_info *cmd);
1042 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1043 struct mlx4_vhcr *vhcr,
1044 struct mlx4_cmd_mailbox *inbox,
1045 struct mlx4_cmd_mailbox *outbox,
1046 struct mlx4_cmd_info *cmd);
1047 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1048 struct mlx4_vhcr *vhcr,
1049 struct mlx4_cmd_mailbox *inbox,
1050 struct mlx4_cmd_mailbox *outbox,
1051 struct mlx4_cmd_info *cmd);
1052 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1053
1054
1055 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1056 struct mlx4_vhcr *vhcr,
1057 struct mlx4_cmd_mailbox *inbox,
1058 struct mlx4_cmd_mailbox *outbox,
1059 struct mlx4_cmd_info *cmd);
1060
1061 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1062 struct mlx4_vhcr *vhcr,
1063 struct mlx4_cmd_mailbox *inbox,
1064 struct mlx4_cmd_mailbox *outbox,
1065 struct mlx4_cmd_info *cmd);
1066 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1067 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1068 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1069 int block_mcast_loopback, enum mlx4_protocol prot,
1070 enum mlx4_steer_type steer);
1071 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1072 struct mlx4_vhcr *vhcr,
1073 struct mlx4_cmd_mailbox *inbox,
1074 struct mlx4_cmd_mailbox *outbox,
1075 struct mlx4_cmd_info *cmd);
1076 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1077 struct mlx4_vhcr *vhcr,
1078 struct mlx4_cmd_mailbox *inbox,
1079 struct mlx4_cmd_mailbox *outbox,
1080 struct mlx4_cmd_info *cmd);
1081 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1082 int port, void *buf);
1083 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1084 struct mlx4_cmd_mailbox *outbox);
1085 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1086 struct mlx4_vhcr *vhcr,
1087 struct mlx4_cmd_mailbox *inbox,
1088 struct mlx4_cmd_mailbox *outbox,
1089 struct mlx4_cmd_info *cmd);
1090 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1091 struct mlx4_vhcr *vhcr,
1092 struct mlx4_cmd_mailbox *inbox,
1093 struct mlx4_cmd_mailbox *outbox,
1094 struct mlx4_cmd_info *cmd);
1095 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1096 struct mlx4_vhcr *vhcr,
1097 struct mlx4_cmd_mailbox *inbox,
1098 struct mlx4_cmd_mailbox *outbox,
1099 struct mlx4_cmd_info *cmd);
1100
1101 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1102 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1103
1104 static inline void set_param_l(u64 *arg, u32 val)
1105 {
1106 *((u32 *)arg) = val;
1107 }
1108
1109 static inline void set_param_h(u64 *arg, u32 val)
1110 {
1111 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1112 }
1113
1114 static inline u32 get_param_l(u64 *arg)
1115 {
1116 return (u32) (*arg & 0xffffffff);
1117 }
1118
1119 static inline u32 get_param_h(u64 *arg)
1120 {
1121 return (u32)(*arg >> 32);
1122 }
1123
1124 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1125 {
1126 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1127 }
1128
1129 #define NOT_MASKED_PD_BITS 17
1130
1131 #endif /* MLX4_H */
(deprecated) Btrfs devel tree