drivers/clocksource/mips-gic-timer.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
   7  */
   8 #include <linux/clk.h>
   9 #include <linux/clockchips.h>
  10 #include <linux/cpu.h>
  11 #include <linux/init.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/irqchip/mips-gic.h>
  14 #include <linux/notifier.h>
  15 #include <linux/of_irq.h>
  16 #include <linux/percpu.h>
  17 #include <linux/smp.h>
  18 #include <linux/time.h>
  19
  20 static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
  21 static int gic_timer_irq;
  22 static unsigned int gic_frequency;
  23
  24 static int gic_next_event(unsigned long delta, struct clock_event_device *evt)
  25 {
  26         u64 cnt;
  27         int res;
  28
  29         cnt = gic_read_count();
  30         cnt += (u64)delta;
  31         gic_write_cpu_compare(cnt, cpumask_first(evt->cpumask));
  32         res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0;
  33         return res;
  34 }
  35
  36 static irqreturn_t gic_compare_interrupt(int irq, void *dev_id)
  37 {
  38         struct clock_event_device *cd = dev_id;
  39
  40         gic_write_compare(gic_read_compare());
  41         cd->event_handler(cd);
  42         return IRQ_HANDLED;
  43 }
  44
  45 struct irqaction gic_compare_irqaction = {
  46         .handler = gic_compare_interrupt,
  47         .percpu_dev_id = &gic_clockevent_device,
  48         .flags = IRQF_PERCPU | IRQF_TIMER,
  49         .name = "timer",
  50 };
  51
  52 static void gic_clockevent_cpu_init(struct clock_event_device *cd)
  53 {
  54         unsigned int cpu = smp_processor_id();
  55
  56         cd->name                = "MIPS GIC";
  57         cd->features            = CLOCK_EVT_FEAT_ONESHOT |
  58                                   CLOCK_EVT_FEAT_C3STOP;
  59
  60         cd->rating              = 350;
  61         cd->irq                 = gic_timer_irq;
  62         cd->cpumask             = cpumask_of(cpu);
  63         cd->set_next_event      = gic_next_event;
  64
  65         clockevents_config_and_register(cd, gic_frequency, 0x300, 0x7fffffff);
  66
  67         enable_percpu_irq(gic_timer_irq, IRQ_TYPE_NONE);
  68 }
  69
  70 static void gic_clockevent_cpu_exit(struct clock_event_device *cd)
  71 {
  72         disable_percpu_irq(gic_timer_irq);
  73 }
  74
  75 static void gic_update_frequency(void *data)
  76 {
  77         unsigned long rate = (unsigned long)data;
  78
  79         clockevents_update_freq(this_cpu_ptr(&gic_clockevent_device), rate);
  80 }
  81
  82 static int gic_cpu_notifier(struct notifier_block *nb, unsigned long action,
  83                                 void *data)
  84 {
  85         switch (action & ~CPU_TASKS_FROZEN) {
  86         case CPU_STARTING:
  87                 gic_clockevent_cpu_init(this_cpu_ptr(&gic_clockevent_device));
  88                 break;
  89         case CPU_DYING:
  90                 gic_clockevent_cpu_exit(this_cpu_ptr(&gic_clockevent_device));
  91                 break;
  92         }
  93
  94         return NOTIFY_OK;
  95 }
  96
  97 static int gic_clk_notifier(struct notifier_block *nb, unsigned long action,
  98                             void *data)
  99 {
 100         struct clk_notifier_data *cnd = data;
 101
 102         if (action == POST_RATE_CHANGE)
 103                 on_each_cpu(gic_update_frequency, (void *)cnd->new_rate, 1);
 104
 105         return NOTIFY_OK;
 106 }
 107
 108
 109 static struct notifier_block gic_cpu_nb = {
 110         .notifier_call = gic_cpu_notifier,
 111 };
 112
 113 static struct notifier_block gic_clk_nb = {
 114         .notifier_call = gic_clk_notifier,
 115 };
 116
 117 static int gic_clockevent_init(void)
 118 {
 119         int ret;
 120
 121         if (!cpu_has_counter || !gic_frequency)
 122                 return -ENXIO;
 123
 124         ret = setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction);
 125         if (ret < 0)
 126                 return ret;
 127
 128         ret = register_cpu_notifier(&gic_cpu_nb);
 129         if (ret < 0)
 130                 pr_warn("GIC: Unable to register CPU notifier\n");
 131
 132         gic_clockevent_cpu_init(this_cpu_ptr(&gic_clockevent_device));
 133
 134         return 0;
 135 }
 136
 137 static cycle_t gic_hpt_read(struct clocksource *cs)
 138 {
 139         return gic_read_count();
 140 }
 141
 142 static struct clocksource gic_clocksource = {
 143         .name           = "GIC",
 144         .read           = gic_hpt_read,
 145         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 146         .archdata       = { .vdso_clock_mode = VDSO_CLOCK_GIC },
 147 };
 148
 149 static void __init __gic_clocksource_init(void)
 150 {
 151         int ret;
 152
 153         /* Set clocksource mask. */
 154         gic_clocksource.mask = CLOCKSOURCE_MASK(gic_get_count_width());
 155
 156         /* Calculate a somewhat reasonable rating value. */
 157         gic_clocksource.rating = 200 + gic_frequency / 10000000;
 158
 159         ret = clocksource_register_hz(&gic_clocksource, gic_frequency);
 160         if (ret < 0)
 161                 pr_warn("GIC: Unable to register clocksource\n");
 162 }
 163
 164 void __init gic_clocksource_init(unsigned int frequency)
 165 {
 166         gic_frequency = frequency;
 167         gic_timer_irq = MIPS_GIC_IRQ_BASE +
 168                 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_COMPARE);
 169
 170         __gic_clocksource_init();
 171         gic_clockevent_init();
 172
 173         /* And finally start the counter */
 174         gic_start_count();
 175 }
 176
 177 static void __init gic_clocksource_of_init(struct device_node *node)
 178 {
 179         struct clk *clk;
 180         int ret;
 181
 182         if (WARN_ON(!gic_present || !node->parent ||
 183                     !of_device_is_compatible(node->parent, "mti,gic")))
 184                 return;
 185
 186         clk = of_clk_get(node, 0);
 187         if (!IS_ERR(clk)) {
 188                 if (clk_prepare_enable(clk) < 0) {
 189                         pr_err("GIC failed to enable clock\n");
 190                         clk_put(clk);
 191                         return;
 192                 }
 193
 194                 gic_frequency = clk_get_rate(clk);
 195         } else if (of_property_read_u32(node, "clock-frequency",
 196                                         &gic_frequency)) {
 197                 pr_err("GIC frequency not specified.\n");
 198                 return;
 199         }
 200         gic_timer_irq = irq_of_parse_and_map(node, 0);
 201         if (!gic_timer_irq) {
 202                 pr_err("GIC timer IRQ not specified.\n");
 203                 return;
 204         }
 205
 206         __gic_clocksource_init();
 207
 208         ret = gic_clockevent_init();
 209         if (!ret && !IS_ERR(clk)) {
 210                 if (clk_notifier_register(clk, &gic_clk_nb) < 0)
 211                         pr_warn("GIC: Unable to register clock notifier\n");
 212         }
 213
 214         /* And finally start the counter */
 215         gic_start_count();
 216 }
 217 CLOCKSOURCE_OF_DECLARE(mips_gic_timer, "mti,gic-timer",
 218                        gic_clocksource_of_init);