| blob | 2d04a5185fe9270ca66b733d89e04d5a315aa0c3 |
1 /*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include "skeleton.dtsi"
17 / {
18 aliases {
19 can0 = &can1;
20 can1 = &can2;
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 gpio4 = &gpio5;
26 gpio5 = &gpio6;
27 gpio6 = &gpio7;
28 i2c0 = &i2c1;
29 i2c1 = &i2c2;
30 i2c2 = &i2c3;
31 mmc0 = &usdhc1;
32 mmc1 = &usdhc2;
33 mmc2 = &usdhc3;
34 mmc3 = &usdhc4;
35 serial0 = &uart1;
36 serial1 = &uart2;
37 serial2 = &uart3;
38 serial3 = &uart4;
39 serial4 = &uart5;
40 spi0 = &ecspi1;
41 spi1 = &ecspi2;
42 spi2 = &ecspi3;
43 spi3 = &ecspi4;
44 usbphy0 = &usbphy1;
45 usbphy1 = &usbphy2;
46 };
48 intc: interrupt-controller@00a01000 {
49 compatible = "arm,cortex-a9-gic";
50 #interrupt-cells = <3>;
51 interrupt-controller;
52 reg = <0x00a01000 0x1000>,
53 <0x00a00100 0x100>;
54 };
56 clocks {
57 #address-cells = <1>;
58 #size-cells = <0>;
60 ckil {
61 compatible = "fsl,imx-ckil", "fixed-clock";
62 clock-frequency = <32768>;
63 };
65 ckih1 {
66 compatible = "fsl,imx-ckih1", "fixed-clock";
67 clock-frequency = <0>;
68 };
70 osc {
71 compatible = "fsl,imx-osc", "fixed-clock";
72 clock-frequency = <24000000>;
73 };
74 };
76 soc {
77 #address-cells = <1>;
78 #size-cells = <1>;
79 compatible = "simple-bus";
80 interrupt-parent = <&intc>;
81 ranges;
83 dma_apbh: dma-apbh@00110000 {
84 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
85 reg = <0x00110000 0x2000>;
86 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
87 <0 13 IRQ_TYPE_LEVEL_HIGH>,
88 <0 13 IRQ_TYPE_LEVEL_HIGH>,
89 <0 13 IRQ_TYPE_LEVEL_HIGH>;
90 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
91 #dma-cells = <1>;
92 dma-channels = <4>;
93 clocks = <&clks 106>;
94 };
96 gpmi: gpmi-nand@00112000 {
97 compatible = "fsl,imx6q-gpmi-nand";
98 #address-cells = <1>;
99 #size-cells = <1>;
100 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
101 reg-names = "gpmi-nand", "bch";
102 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
103 interrupt-names = "bch";
104 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
105 <&clks 150>, <&clks 149>;
106 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
107 "gpmi_bch_apb", "per1_bch";
108 dmas = <&dma_apbh 0>;
109 dma-names = "rx-tx";
110 status = "disabled";
111 };
113 timer@00a00600 {
114 compatible = "arm,cortex-a9-twd-timer";
115 reg = <0x00a00600 0x20>;
116 interrupts = <1 13 0xf01>;
117 clocks = <&clks 15>;
118 };
120 L2: l2-cache@00a02000 {
121 compatible = "arm,pl310-cache";
122 reg = <0x00a02000 0x1000>;
123 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
124 cache-unified;
125 cache-level = <2>;
126 arm,tag-latency = <4 2 3>;
127 arm,data-latency = <4 2 3>;
128 };
130 pcie: pcie@0x01000000 {
131 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
132 reg = <0x01ffc000 0x4000>; /* DBI */
133 #address-cells = <3>;
134 #size-cells = <2>;
135 device_type = "pci";
136 ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
137 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
138 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
139 num-lanes = <1>;
140 interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
141 #interrupt-cells = <1>;
142 interrupt-map-mask = <0 0 0 0x7>;
143 interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
144 <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
145 <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
146 <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
148 clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
149 status = "disabled";
150 };
152 pmu {
153 compatible = "arm,cortex-a9-pmu";
154 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
155 };
157 aips-bus@02000000 { /* AIPS1 */
158 compatible = "fsl,aips-bus", "simple-bus";
159 #address-cells = <1>;
160 #size-cells = <1>;
161 reg = <0x02000000 0x100000>;
162 ranges;
164 spba-bus@02000000 {
165 compatible = "fsl,spba-bus", "simple-bus";
166 #address-cells = <1>;
167 #size-cells = <1>;
168 reg = <0x02000000 0x40000>;
169 ranges;
171 spdif: spdif@02004000 {
172 compatible = "fsl,imx35-spdif";
173 reg = <0x02004000 0x4000>;
174 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
175 dmas = <&sdma 14 18 0>,
176 <&sdma 15 18 0>;
177 dma-names = "rx", "tx";
178 clocks = <&clks 197>, <&clks 3>,
179 <&clks 197>, <&clks 107>,
180 <&clks 0>, <&clks 118>,
181 <&clks 0>, <&clks 139>,
182 <&clks 0>;
183 clock-names = "core", "rxtx0",
184 "rxtx1", "rxtx2",
185 "rxtx3", "rxtx4",
186 "rxtx5", "rxtx6",
187 "rxtx7";
188 status = "disabled";
189 };
191 ecspi1: ecspi@02008000 {
192 #address-cells = <1>;
193 #size-cells = <0>;
194 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
195 reg = <0x02008000 0x4000>;
196 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&clks 112>, <&clks 112>;
198 clock-names = "ipg", "per";
199 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
200 dma-names = "rx", "tx";
201 status = "disabled";
202 };
204 ecspi2: ecspi@0200c000 {
205 #address-cells = <1>;
206 #size-cells = <0>;
207 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
208 reg = <0x0200c000 0x4000>;
209 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&clks 113>, <&clks 113>;
211 clock-names = "ipg", "per";
212 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
213 dma-names = "rx", "tx";
214 status = "disabled";
215 };
217 ecspi3: ecspi@02010000 {
218 #address-cells = <1>;
219 #size-cells = <0>;
220 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
221 reg = <0x02010000 0x4000>;
222 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&clks 114>, <&clks 114>;
224 clock-names = "ipg", "per";
225 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
226 dma-names = "rx", "tx";
227 status = "disabled";
228 };
230 ecspi4: ecspi@02014000 {
231 #address-cells = <1>;
232 #size-cells = <0>;
233 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
234 reg = <0x02014000 0x4000>;
235 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&clks 115>, <&clks 115>;
237 clock-names = "ipg", "per";
238 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
239 dma-names = "rx", "tx";
240 status = "disabled";
241 };
243 uart1: serial@02020000 {
244 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
245 reg = <0x02020000 0x4000>;
246 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&clks 160>, <&clks 161>;
248 clock-names = "ipg", "per";
249 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
250 dma-names = "rx", "tx";
251 status = "disabled";
252 };
254 esai: esai@02024000 {
255 reg = <0x02024000 0x4000>;
256 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
257 };
259 ssi1: ssi@02028000 {
260 compatible = "fsl,imx6q-ssi",
261 "fsl,imx51-ssi",
262 "fsl,imx21-ssi";
263 reg = <0x02028000 0x4000>;
264 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
265 clocks = <&clks 178>;
266 dmas = <&sdma 37 1 0>,
267 <&sdma 38 1 0>;
268 dma-names = "rx", "tx";
269 fsl,fifo-depth = <15>;
270 fsl,ssi-dma-events = <38 37>;
271 status = "disabled";
272 };
274 ssi2: ssi@0202c000 {
275 compatible = "fsl,imx6q-ssi",
276 "fsl,imx51-ssi",
277 "fsl,imx21-ssi";
278 reg = <0x0202c000 0x4000>;
279 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&clks 179>;
281 dmas = <&sdma 41 1 0>,
282 <&sdma 42 1 0>;
283 dma-names = "rx", "tx";
284 fsl,fifo-depth = <15>;
285 fsl,ssi-dma-events = <42 41>;
286 status = "disabled";
287 };
289 ssi3: ssi@02030000 {
290 compatible = "fsl,imx6q-ssi",
291 "fsl,imx51-ssi",
292 "fsl,imx21-ssi";
293 reg = <0x02030000 0x4000>;
294 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&clks 180>;
296 dmas = <&sdma 45 1 0>,
297 <&sdma 46 1 0>;
298 dma-names = "rx", "tx";
299 fsl,fifo-depth = <15>;
300 fsl,ssi-dma-events = <46 45>;
301 status = "disabled";
302 };
304 asrc: asrc@02034000 {
305 reg = <0x02034000 0x4000>;
306 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
307 };
309 spba@0203c000 {
310 reg = <0x0203c000 0x4000>;
311 };
312 };
314 vpu: vpu@02040000 {
315 reg = <0x02040000 0x3c000>;
316 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
317 <0 12 IRQ_TYPE_LEVEL_HIGH>;
318 };
320 aipstz@0207c000 { /* AIPSTZ1 */
321 reg = <0x0207c000 0x4000>;
322 };
324 pwm1: pwm@02080000 {
325 #pwm-cells = <2>;
326 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
327 reg = <0x02080000 0x4000>;
328 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&clks 62>, <&clks 145>;
330 clock-names = "ipg", "per";
331 };
333 pwm2: pwm@02084000 {
334 #pwm-cells = <2>;
335 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
336 reg = <0x02084000 0x4000>;
337 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&clks 62>, <&clks 146>;
339 clock-names = "ipg", "per";
340 };
342 pwm3: pwm@02088000 {
343 #pwm-cells = <2>;
344 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
345 reg = <0x02088000 0x4000>;
346 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&clks 62>, <&clks 147>;
348 clock-names = "ipg", "per";
349 };
351 pwm4: pwm@0208c000 {
352 #pwm-cells = <2>;
353 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
354 reg = <0x0208c000 0x4000>;
355 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&clks 62>, <&clks 148>;
357 clock-names = "ipg", "per";
358 };
360 can1: flexcan@02090000 {
361 compatible = "fsl,imx6q-flexcan";
362 reg = <0x02090000 0x4000>;
363 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&clks 108>, <&clks 109>;
365 clock-names = "ipg", "per";
366 status = "disabled";
367 };
369 can2: flexcan@02094000 {
370 compatible = "fsl,imx6q-flexcan";
371 reg = <0x02094000 0x4000>;
372 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&clks 110>, <&clks 111>;
374 clock-names = "ipg", "per";
375 status = "disabled";
376 };
378 gpt: gpt@02098000 {
379 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
380 reg = <0x02098000 0x4000>;
381 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&clks 119>, <&clks 120>;
383 clock-names = "ipg", "per";
384 };
386 gpio1: gpio@0209c000 {
387 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
388 reg = <0x0209c000 0x4000>;
389 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
390 <0 67 IRQ_TYPE_LEVEL_HIGH>;
391 gpio-controller;
392 #gpio-cells = <2>;
393 interrupt-controller;
394 #interrupt-cells = <2>;
395 };
397 gpio2: gpio@020a0000 {
398 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
399 reg = <0x020a0000 0x4000>;
400 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
401 <0 69 IRQ_TYPE_LEVEL_HIGH>;
402 gpio-controller;
403 #gpio-cells = <2>;
404 interrupt-controller;
405 #interrupt-cells = <2>;
406 };
408 gpio3: gpio@020a4000 {
409 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
410 reg = <0x020a4000 0x4000>;
411 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
412 <0 71 IRQ_TYPE_LEVEL_HIGH>;
413 gpio-controller;
414 #gpio-cells = <2>;
415 interrupt-controller;
416 #interrupt-cells = <2>;
417 };
419 gpio4: gpio@020a8000 {
420 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
421 reg = <0x020a8000 0x4000>;
422 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
423 <0 73 IRQ_TYPE_LEVEL_HIGH>;
424 gpio-controller;
425 #gpio-cells = <2>;
426 interrupt-controller;
427 #interrupt-cells = <2>;
428 };
430 gpio5: gpio@020ac000 {
431 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
432 reg = <0x020ac000 0x4000>;
433 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
434 <0 75 IRQ_TYPE_LEVEL_HIGH>;
435 gpio-controller;
436 #gpio-cells = <2>;
437 interrupt-controller;
438 #interrupt-cells = <2>;
439 };
441 gpio6: gpio@020b0000 {
442 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
443 reg = <0x020b0000 0x4000>;
444 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
445 <0 77 IRQ_TYPE_LEVEL_HIGH>;
446 gpio-controller;
447 #gpio-cells = <2>;
448 interrupt-controller;
449 #interrupt-cells = <2>;
450 };
452 gpio7: gpio@020b4000 {
453 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
454 reg = <0x020b4000 0x4000>;
455 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
456 <0 79 IRQ_TYPE_LEVEL_HIGH>;
457 gpio-controller;
458 #gpio-cells = <2>;
459 interrupt-controller;
460 #interrupt-cells = <2>;
461 };
463 kpp: kpp@020b8000 {
464 reg = <0x020b8000 0x4000>;
465 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
466 };
468 wdog1: wdog@020bc000 {
469 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
470 reg = <0x020bc000 0x4000>;
471 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&clks 0>;
473 };
475 wdog2: wdog@020c0000 {
476 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
477 reg = <0x020c0000 0x4000>;
478 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&clks 0>;
480 status = "disabled";
481 };
483 clks: ccm@020c4000 {
484 compatible = "fsl,imx6q-ccm";
485 reg = <0x020c4000 0x4000>;
486 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
487 <0 88 IRQ_TYPE_LEVEL_HIGH>;
488 #clock-cells = <1>;
489 };
491 anatop: anatop@020c8000 {
492 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
493 reg = <0x020c8000 0x1000>;
494 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
495 <0 54 IRQ_TYPE_LEVEL_HIGH>,
496 <0 127 IRQ_TYPE_LEVEL_HIGH>;
498 regulator-1p1@110 {
499 compatible = "fsl,anatop-regulator";
500 regulator-name = "vdd1p1";
501 regulator-min-microvolt = <800000>;
502 regulator-max-microvolt = <1375000>;
503 regulator-always-on;
504 anatop-reg-offset = <0x110>;
505 anatop-vol-bit-shift = <8>;
506 anatop-vol-bit-width = <5>;
507 anatop-min-bit-val = <4>;
508 anatop-min-voltage = <800000>;
509 anatop-max-voltage = <1375000>;
510 };
512 regulator-3p0@120 {
513 compatible = "fsl,anatop-regulator";
514 regulator-name = "vdd3p0";
515 regulator-min-microvolt = <2800000>;
516 regulator-max-microvolt = <3150000>;
517 regulator-always-on;
518 anatop-reg-offset = <0x120>;
519 anatop-vol-bit-shift = <8>;
520 anatop-vol-bit-width = <5>;
521 anatop-min-bit-val = <0>;
522 anatop-min-voltage = <2625000>;
523 anatop-max-voltage = <3400000>;
524 };
526 regulator-2p5@130 {
527 compatible = "fsl,anatop-regulator";
528 regulator-name = "vdd2p5";
529 regulator-min-microvolt = <2000000>;
530 regulator-max-microvolt = <2750000>;
531 regulator-always-on;
532 anatop-reg-offset = <0x130>;
533 anatop-vol-bit-shift = <8>;
534 anatop-vol-bit-width = <5>;
535 anatop-min-bit-val = <0>;
536 anatop-min-voltage = <2000000>;
537 anatop-max-voltage = <2750000>;
538 };
540 reg_arm: regulator-vddcore@140 {
541 compatible = "fsl,anatop-regulator";
542 regulator-name = "vddarm";
543 regulator-min-microvolt = <725000>;
544 regulator-max-microvolt = <1450000>;
545 regulator-always-on;
546 anatop-reg-offset = <0x140>;
547 anatop-vol-bit-shift = <0>;
548 anatop-vol-bit-width = <5>;
549 anatop-delay-reg-offset = <0x170>;
550 anatop-delay-bit-shift = <24>;
551 anatop-delay-bit-width = <2>;
552 anatop-min-bit-val = <1>;
553 anatop-min-voltage = <725000>;
554 anatop-max-voltage = <1450000>;
555 };
557 reg_pu: regulator-vddpu@140 {
558 compatible = "fsl,anatop-regulator";
559 regulator-name = "vddpu";
560 regulator-min-microvolt = <725000>;
561 regulator-max-microvolt = <1450000>;
562 regulator-always-on;
563 anatop-reg-offset = <0x140>;
564 anatop-vol-bit-shift = <9>;
565 anatop-vol-bit-width = <5>;
566 anatop-delay-reg-offset = <0x170>;
567 anatop-delay-bit-shift = <26>;
568 anatop-delay-bit-width = <2>;
569 anatop-min-bit-val = <1>;
570 anatop-min-voltage = <725000>;
571 anatop-max-voltage = <1450000>;
572 };
574 reg_soc: regulator-vddsoc@140 {
575 compatible = "fsl,anatop-regulator";
576 regulator-name = "vddsoc";
577 regulator-min-microvolt = <725000>;
578 regulator-max-microvolt = <1450000>;
579 regulator-always-on;
580 anatop-reg-offset = <0x140>;
581 anatop-vol-bit-shift = <18>;
582 anatop-vol-bit-width = <5>;
583 anatop-delay-reg-offset = <0x170>;
584 anatop-delay-bit-shift = <28>;
585 anatop-delay-bit-width = <2>;
586 anatop-min-bit-val = <1>;
587 anatop-min-voltage = <725000>;
588 anatop-max-voltage = <1450000>;
589 };
590 };
592 tempmon: tempmon {
593 compatible = "fsl,imx6q-tempmon";
594 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
595 fsl,tempmon = <&anatop>;
596 fsl,tempmon-data = <&ocotp>;
597 clocks = <&clks 172>;
598 };
600 usbphy1: usbphy@020c9000 {
601 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
602 reg = <0x020c9000 0x1000>;
603 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&clks 182>;
605 fsl,anatop = <&anatop>;
606 };
608 usbphy2: usbphy@020ca000 {
609 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
610 reg = <0x020ca000 0x1000>;
611 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&clks 183>;
613 fsl,anatop = <&anatop>;
614 };
616 snvs@020cc000 {
617 compatible = "fsl,sec-v4.0-mon", "simple-bus";
618 #address-cells = <1>;
619 #size-cells = <1>;
620 ranges = <0 0x020cc000 0x4000>;
622 snvs-rtc-lp@34 {
623 compatible = "fsl,sec-v4.0-mon-rtc-lp";
624 reg = <0x34 0x58>;
625 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
626 <0 20 IRQ_TYPE_LEVEL_HIGH>;
627 };
628 };
630 epit1: epit@020d0000 { /* EPIT1 */
631 reg = <0x020d0000 0x4000>;
632 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
633 };
635 epit2: epit@020d4000 { /* EPIT2 */
636 reg = <0x020d4000 0x4000>;
637 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
638 };
640 src: src@020d8000 {
641 compatible = "fsl,imx6q-src", "fsl,imx51-src";
642 reg = <0x020d8000 0x4000>;
643 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
644 <0 96 IRQ_TYPE_LEVEL_HIGH>;
645 #reset-cells = <1>;
646 };
648 gpc: gpc@020dc000 {
649 compatible = "fsl,imx6q-gpc";
650 reg = <0x020dc000 0x4000>;
651 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
652 <0 90 IRQ_TYPE_LEVEL_HIGH>;
653 };
655 gpr: iomuxc-gpr@020e0000 {
656 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
657 reg = <0x020e0000 0x38>;
658 };
660 iomuxc: iomuxc@020e0000 {
661 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
662 reg = <0x020e0000 0x4000>;
663 };
665 ldb: ldb@020e0008 {
666 #address-cells = <1>;
667 #size-cells = <0>;
668 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
669 gpr = <&gpr>;
670 status = "disabled";
672 lvds-channel@0 {
673 #address-cells = <1>;
674 #size-cells = <0>;
675 reg = <0>;
676 status = "disabled";
678 port@0 {
679 reg = <0>;
681 lvds0_mux_0: endpoint {
682 remote-endpoint = <&ipu1_di0_lvds0>;
683 };
684 };
686 port@1 {
687 reg = <1>;
689 lvds0_mux_1: endpoint {
690 remote-endpoint = <&ipu1_di1_lvds0>;
691 };
692 };
693 };
695 lvds-channel@1 {
696 #address-cells = <1>;
697 #size-cells = <0>;
698 reg = <1>;
699 status = "disabled";
701 port@0 {
702 reg = <0>;
704 lvds1_mux_0: endpoint {
705 remote-endpoint = <&ipu1_di0_lvds1>;
706 };
707 };
709 port@1 {
710 reg = <1>;
712 lvds1_mux_1: endpoint {
713 remote-endpoint = <&ipu1_di1_lvds1>;
714 };
715 };
716 };
717 };
719 hdmi: hdmi@0120000 {
720 #address-cells = <1>;
721 #size-cells = <0>;
722 reg = <0x00120000 0x9000>;
723 interrupts = <0 115 0x04>;
724 gpr = <&gpr>;
725 clocks = <&clks 123>, <&clks 124>;
726 clock-names = "iahb", "isfr";
727 status = "disabled";
729 port@0 {
730 reg = <0>;
732 hdmi_mux_0: endpoint {
733 remote-endpoint = <&ipu1_di0_hdmi>;
734 };
735 };
737 port@1 {
738 reg = <1>;
740 hdmi_mux_1: endpoint {
741 remote-endpoint = <&ipu1_di1_hdmi>;
742 };
743 };
744 };
746 dcic1: dcic@020e4000 {
747 reg = <0x020e4000 0x4000>;
748 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
749 };
751 dcic2: dcic@020e8000 {
752 reg = <0x020e8000 0x4000>;
753 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
754 };
756 sdma: sdma@020ec000 {
757 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
758 reg = <0x020ec000 0x4000>;
759 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
760 clocks = <&clks 155>, <&clks 155>;
761 clock-names = "ipg", "ahb";
762 #dma-cells = <3>;
763 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
764 };
765 };
767 aips-bus@02100000 { /* AIPS2 */
768 compatible = "fsl,aips-bus", "simple-bus";
769 #address-cells = <1>;
770 #size-cells = <1>;
771 reg = <0x02100000 0x100000>;
772 ranges;
774 caam@02100000 {
775 reg = <0x02100000 0x40000>;
776 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
777 <0 106 IRQ_TYPE_LEVEL_HIGH>;
778 };
780 aipstz@0217c000 { /* AIPSTZ2 */
781 reg = <0x0217c000 0x4000>;
782 };
784 usbotg: usb@02184000 {
785 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
786 reg = <0x02184000 0x200>;
787 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&clks 162>;
789 fsl,usbphy = <&usbphy1>;
790 fsl,usbmisc = <&usbmisc 0>;
791 status = "disabled";
792 };
794 usbh1: usb@02184200 {
795 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
796 reg = <0x02184200 0x200>;
797 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
798 clocks = <&clks 162>;
799 fsl,usbphy = <&usbphy2>;
800 fsl,usbmisc = <&usbmisc 1>;
801 status = "disabled";
802 };
804 usbh2: usb@02184400 {
805 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
806 reg = <0x02184400 0x200>;
807 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
808 clocks = <&clks 162>;
809 fsl,usbmisc = <&usbmisc 2>;
810 status = "disabled";
811 };
813 usbh3: usb@02184600 {
814 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
815 reg = <0x02184600 0x200>;
816 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
817 clocks = <&clks 162>;
818 fsl,usbmisc = <&usbmisc 3>;
819 status = "disabled";
820 };
822 usbmisc: usbmisc@02184800 {
823 #index-cells = <1>;
824 compatible = "fsl,imx6q-usbmisc";
825 reg = <0x02184800 0x200>;
826 clocks = <&clks 162>;
827 };
829 fec: ethernet@02188000 {
830 compatible = "fsl,imx6q-fec";
831 reg = <0x02188000 0x4000>;
832 interrupts-extended =
833 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
834 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
836 clock-names = "ipg", "ahb", "ptp";
837 status = "disabled";
838 };
840 mlb@0218c000 {
841 reg = <0x0218c000 0x4000>;
842 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
843 <0 117 IRQ_TYPE_LEVEL_HIGH>,
844 <0 126 IRQ_TYPE_LEVEL_HIGH>;
845 };
847 usdhc1: usdhc@02190000 {
848 compatible = "fsl,imx6q-usdhc";
849 reg = <0x02190000 0x4000>;
850 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
851 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
852 clock-names = "ipg", "ahb", "per";
853 bus-width = <4>;
854 status = "disabled";
855 };
857 usdhc2: usdhc@02194000 {
858 compatible = "fsl,imx6q-usdhc";
859 reg = <0x02194000 0x4000>;
860 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
862 clock-names = "ipg", "ahb", "per";
863 bus-width = <4>;
864 status = "disabled";
865 };
867 usdhc3: usdhc@02198000 {
868 compatible = "fsl,imx6q-usdhc";
869 reg = <0x02198000 0x4000>;
870 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
872 clock-names = "ipg", "ahb", "per";
873 bus-width = <4>;
874 status = "disabled";
875 };
877 usdhc4: usdhc@0219c000 {
878 compatible = "fsl,imx6q-usdhc";
879 reg = <0x0219c000 0x4000>;
880 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
881 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
882 clock-names = "ipg", "ahb", "per";
883 bus-width = <4>;
884 status = "disabled";
885 };
887 i2c1: i2c@021a0000 {
888 #address-cells = <1>;
889 #size-cells = <0>;
890 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
891 reg = <0x021a0000 0x4000>;
892 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&clks 125>;
894 status = "disabled";
895 };
897 i2c2: i2c@021a4000 {
898 #address-cells = <1>;
899 #size-cells = <0>;
900 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
901 reg = <0x021a4000 0x4000>;
902 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
903 clocks = <&clks 126>;
904 status = "disabled";
905 };
907 i2c3: i2c@021a8000 {
908 #address-cells = <1>;
909 #size-cells = <0>;
910 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
911 reg = <0x021a8000 0x4000>;
912 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
913 clocks = <&clks 127>;
914 status = "disabled";
915 };
917 romcp@021ac000 {
918 reg = <0x021ac000 0x4000>;
919 };
921 mmdc0: mmdc@021b0000 { /* MMDC0 */
922 compatible = "fsl,imx6q-mmdc";
923 reg = <0x021b0000 0x4000>;
924 };
926 mmdc1: mmdc@021b4000 { /* MMDC1 */
927 reg = <0x021b4000 0x4000>;
928 };
930 weim: weim@021b8000 {
931 compatible = "fsl,imx6q-weim";
932 reg = <0x021b8000 0x4000>;
933 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
934 clocks = <&clks 196>;
935 };
937 ocotp: ocotp@021bc000 {
938 compatible = "fsl,imx6q-ocotp", "syscon";
939 reg = <0x021bc000 0x4000>;
940 };
942 tzasc@021d0000 { /* TZASC1 */
943 reg = <0x021d0000 0x4000>;
944 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
945 };
947 tzasc@021d4000 { /* TZASC2 */
948 reg = <0x021d4000 0x4000>;
949 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
950 };
952 audmux: audmux@021d8000 {
953 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
954 reg = <0x021d8000 0x4000>;
955 status = "disabled";
956 };
958 mipi_csi: mipi@021dc000 {
959 reg = <0x021dc000 0x4000>;
960 };
962 mipi_dsi: mipi@021e0000 {
963 #address-cells = <1>;
964 #size-cells = <0>;
965 reg = <0x021e0000 0x4000>;
966 status = "disabled";
968 port@0 {
969 reg = <0>;
971 mipi_mux_0: endpoint {
972 remote-endpoint = <&ipu1_di0_mipi>;
973 };
974 };
976 port@1 {
977 reg = <1>;
979 mipi_mux_1: endpoint {
980 remote-endpoint = <&ipu1_di1_mipi>;
981 };
982 };
983 };
985 vdoa@021e4000 {
986 reg = <0x021e4000 0x4000>;
987 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
988 };
990 uart2: serial@021e8000 {
991 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
992 reg = <0x021e8000 0x4000>;
993 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
994 clocks = <&clks 160>, <&clks 161>;
995 clock-names = "ipg", "per";
996 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
997 dma-names = "rx", "tx";
998 status = "disabled";
999 };
1001 uart3: serial@021ec000 {
1002 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1003 reg = <0x021ec000 0x4000>;
1004 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1005 clocks = <&clks 160>, <&clks 161>;
1006 clock-names = "ipg", "per";
1007 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1008 dma-names = "rx", "tx";
1009 status = "disabled";
1010 };
1012 uart4: serial@021f0000 {
1013 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1014 reg = <0x021f0000 0x4000>;
1015 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1016 clocks = <&clks 160>, <&clks 161>;
1017 clock-names = "ipg", "per";
1018 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1019 dma-names = "rx", "tx";
1020 status = "disabled";
1021 };
1023 uart5: serial@021f4000 {
1024 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1025 reg = <0x021f4000 0x4000>;
1026 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1027 clocks = <&clks 160>, <&clks 161>;
1028 clock-names = "ipg", "per";
1029 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1030 dma-names = "rx", "tx";
1031 status = "disabled";
1032 };
1033 };
1035 ipu1: ipu@02400000 {
1036 #address-cells = <1>;
1037 #size-cells = <0>;
1038 compatible = "fsl,imx6q-ipu";
1039 reg = <0x02400000 0x400000>;
1040 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1041 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1042 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
1043 clock-names = "bus", "di0", "di1";
1044 resets = <&src 2>;
1046 ipu1_di0: port@2 {
1047 #address-cells = <1>;
1048 #size-cells = <0>;
1049 reg = <2>;
1051 ipu1_di0_disp0: endpoint@0 {
1052 };
1054 ipu1_di0_hdmi: endpoint@1 {
1055 remote-endpoint = <&hdmi_mux_0>;
1056 };
1058 ipu1_di0_mipi: endpoint@2 {
1059 remote-endpoint = <&mipi_mux_0>;
1060 };
1062 ipu1_di0_lvds0: endpoint@3 {
1063 remote-endpoint = <&lvds0_mux_0>;
1064 };
1066 ipu1_di0_lvds1: endpoint@4 {
1067 remote-endpoint = <&lvds1_mux_0>;
1068 };
1069 };
1071 ipu1_di1: port@3 {
1072 #address-cells = <1>;
1073 #size-cells = <0>;
1074 reg = <3>;
1076 ipu1_di0_disp1: endpoint@0 {
1077 };
1079 ipu1_di1_hdmi: endpoint@1 {
1080 remote-endpoint = <&hdmi_mux_1>;
1081 };
1083 ipu1_di1_mipi: endpoint@2 {
1084 remote-endpoint = <&mipi_mux_1>;
1085 };
1087 ipu1_di1_lvds0: endpoint@3 {
1088 remote-endpoint = <&lvds0_mux_1>;
1089 };
1091 ipu1_di1_lvds1: endpoint@4 {
1092 remote-endpoint = <&lvds1_mux_1>;
1093 };
1094 };
1095 };
1096 };
1097 };