1 /* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/types.h>
17 #include <linux/device.h>
19 #include <linux/err.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/smp.h>
24 #include <linux/sysfs.h>
25 #include <linux/stat.h>
26 #include <linux/clk.h>
27 #include <linux/cpu.h>
29 #include <linux/coresight.h>
30 #include <linux/amba/bus.h>
31 #include <linux/seq_file.h>
32 #include <linux/uaccess.h>
33 #include <asm/sections.h>
35 #include "coresight-etm.h"
37 #ifdef CONFIG_CORESIGHT_SOURCE_ETM_DEFAULT_ENABLE
38 static int boot_enable
= 1;
40 static int boot_enable
;
43 boot_enable
, boot_enable
, int, S_IRUGO
46 /* The number of ETM/PTM currently registered */
48 static struct etm_drvdata
*etmdrvdata
[NR_CPUS
];
50 static inline void etm_writel(struct etm_drvdata
*drvdata
,
53 if (drvdata
->use_cp14
) {
54 if (etm_writel_cp14(off
, val
)) {
56 "invalid CP14 access to ETM reg: %#x", off
);
59 writel_relaxed(val
, drvdata
->base
+ off
);
63 static inline unsigned int etm_readl(struct etm_drvdata
*drvdata
, u32 off
)
67 if (drvdata
->use_cp14
) {
68 if (etm_readl_cp14(off
, &val
)) {
70 "invalid CP14 access to ETM reg: %#x", off
);
73 val
= readl_relaxed(drvdata
->base
+ off
);
80 * Memory mapped writes to clear os lock are not supported on some processors
81 * and OS lock must be unlocked before any memory mapped access on such
82 * processors, otherwise memory mapped reads/writes will be invalid.
84 static void etm_os_unlock(void *info
)
86 struct etm_drvdata
*drvdata
= (struct etm_drvdata
*)info
;
87 /* Writing any value to ETMOSLAR unlocks the trace registers */
88 etm_writel(drvdata
, 0x0, ETMOSLAR
);
92 static void etm_set_pwrdwn(struct etm_drvdata
*drvdata
)
96 /* Ensure pending cp14 accesses complete before setting pwrdwn */
99 etmcr
= etm_readl(drvdata
, ETMCR
);
100 etmcr
|= ETMCR_PWD_DWN
;
101 etm_writel(drvdata
, etmcr
, ETMCR
);
104 static void etm_clr_pwrdwn(struct etm_drvdata
*drvdata
)
108 etmcr
= etm_readl(drvdata
, ETMCR
);
109 etmcr
&= ~ETMCR_PWD_DWN
;
110 etm_writel(drvdata
, etmcr
, ETMCR
);
111 /* Ensure pwrup completes before subsequent cp14 accesses */
116 static void etm_set_pwrup(struct etm_drvdata
*drvdata
)
120 etmpdcr
= readl_relaxed(drvdata
->base
+ ETMPDCR
);
121 etmpdcr
|= ETMPDCR_PWD_UP
;
122 writel_relaxed(etmpdcr
, drvdata
->base
+ ETMPDCR
);
123 /* Ensure pwrup completes before subsequent cp14 accesses */
128 static void etm_clr_pwrup(struct etm_drvdata
*drvdata
)
132 /* Ensure pending cp14 accesses complete before clearing pwrup */
135 etmpdcr
= readl_relaxed(drvdata
->base
+ ETMPDCR
);
136 etmpdcr
&= ~ETMPDCR_PWD_UP
;
137 writel_relaxed(etmpdcr
, drvdata
->base
+ ETMPDCR
);
141 * coresight_timeout_etm - loop until a bit has changed to a specific state.
142 * @drvdata: etm's private data structure.
143 * @offset: address of a register, starting from @addr.
144 * @position: the position of the bit of interest.
145 * @value: the value the bit should have.
147 * Basically the same as @coresight_timeout except for the register access
148 * method where we have to account for CP14 configurations.
150 * Return: 0 as soon as the bit has taken the desired state or -EAGAIN if
151 * TIMEOUT_US has elapsed, which ever happens first.
154 static int coresight_timeout_etm(struct etm_drvdata
*drvdata
, u32 offset
,
155 int position
, int value
)
160 for (i
= TIMEOUT_US
; i
> 0; i
--) {
161 val
= etm_readl(drvdata
, offset
);
162 /* Waiting on the bit to go from 0 to 1 */
164 if (val
& BIT(position
))
166 /* Waiting on the bit to go from 1 to 0 */
168 if (!(val
& BIT(position
)))
173 * Delay is arbitrary - the specification doesn't say how long
174 * we are expected to wait. Extra check required to make sure
175 * we don't wait needlessly on the last iteration.
185 static void etm_set_prog(struct etm_drvdata
*drvdata
)
189 etmcr
= etm_readl(drvdata
, ETMCR
);
190 etmcr
|= ETMCR_ETM_PRG
;
191 etm_writel(drvdata
, etmcr
, ETMCR
);
193 * Recommended by spec for cp14 accesses to ensure etmcr write is
194 * complete before polling etmsr
197 if (coresight_timeout_etm(drvdata
, ETMSR
, ETMSR_PROG_BIT
, 1)) {
198 dev_err(drvdata
->dev
,
199 "timeout observed when probing at offset %#x\n", ETMSR
);
203 static void etm_clr_prog(struct etm_drvdata
*drvdata
)
207 etmcr
= etm_readl(drvdata
, ETMCR
);
208 etmcr
&= ~ETMCR_ETM_PRG
;
209 etm_writel(drvdata
, etmcr
, ETMCR
);
211 * Recommended by spec for cp14 accesses to ensure etmcr write is
212 * complete before polling etmsr
215 if (coresight_timeout_etm(drvdata
, ETMSR
, ETMSR_PROG_BIT
, 0)) {
216 dev_err(drvdata
->dev
,
217 "timeout observed when probing at offset %#x\n", ETMSR
);
221 static void etm_set_default(struct etm_drvdata
*drvdata
)
225 drvdata
->trigger_event
= ETM_DEFAULT_EVENT_VAL
;
226 drvdata
->enable_event
= ETM_HARD_WIRE_RES_A
;
228 drvdata
->seq_12_event
= ETM_DEFAULT_EVENT_VAL
;
229 drvdata
->seq_21_event
= ETM_DEFAULT_EVENT_VAL
;
230 drvdata
->seq_23_event
= ETM_DEFAULT_EVENT_VAL
;
231 drvdata
->seq_31_event
= ETM_DEFAULT_EVENT_VAL
;
232 drvdata
->seq_32_event
= ETM_DEFAULT_EVENT_VAL
;
233 drvdata
->seq_13_event
= ETM_DEFAULT_EVENT_VAL
;
234 drvdata
->timestamp_event
= ETM_DEFAULT_EVENT_VAL
;
236 for (i
= 0; i
< drvdata
->nr_cntr
; i
++) {
237 drvdata
->cntr_rld_val
[i
] = 0x0;
238 drvdata
->cntr_event
[i
] = ETM_DEFAULT_EVENT_VAL
;
239 drvdata
->cntr_rld_event
[i
] = ETM_DEFAULT_EVENT_VAL
;
240 drvdata
->cntr_val
[i
] = 0x0;
243 drvdata
->seq_curr_state
= 0x0;
244 drvdata
->ctxid_idx
= 0x0;
245 for (i
= 0; i
< drvdata
->nr_ctxid_cmp
; i
++)
246 drvdata
->ctxid_val
[i
] = 0x0;
247 drvdata
->ctxid_mask
= 0x0;
250 static void etm_enable_hw(void *info
)
254 struct etm_drvdata
*drvdata
= info
;
256 CS_UNLOCK(drvdata
->base
);
259 etm_clr_pwrdwn(drvdata
);
260 /* Apply power to trace registers */
261 etm_set_pwrup(drvdata
);
262 /* Make sure all registers are accessible */
263 etm_os_unlock(drvdata
);
265 etm_set_prog(drvdata
);
267 etmcr
= etm_readl(drvdata
, ETMCR
);
268 etmcr
&= (ETMCR_PWD_DWN
| ETMCR_ETM_PRG
);
269 etmcr
|= drvdata
->port_size
;
270 etm_writel(drvdata
, drvdata
->ctrl
| etmcr
, ETMCR
);
271 etm_writel(drvdata
, drvdata
->trigger_event
, ETMTRIGGER
);
272 etm_writel(drvdata
, drvdata
->startstop_ctrl
, ETMTSSCR
);
273 etm_writel(drvdata
, drvdata
->enable_event
, ETMTEEVR
);
274 etm_writel(drvdata
, drvdata
->enable_ctrl1
, ETMTECR1
);
275 etm_writel(drvdata
, drvdata
->fifofull_level
, ETMFFLR
);
276 for (i
= 0; i
< drvdata
->nr_addr_cmp
; i
++) {
277 etm_writel(drvdata
, drvdata
->addr_val
[i
], ETMACVRn(i
));
278 etm_writel(drvdata
, drvdata
->addr_acctype
[i
], ETMACTRn(i
));
280 for (i
= 0; i
< drvdata
->nr_cntr
; i
++) {
281 etm_writel(drvdata
, drvdata
->cntr_rld_val
[i
], ETMCNTRLDVRn(i
));
282 etm_writel(drvdata
, drvdata
->cntr_event
[i
], ETMCNTENRn(i
));
283 etm_writel(drvdata
, drvdata
->cntr_rld_event
[i
],
285 etm_writel(drvdata
, drvdata
->cntr_val
[i
], ETMCNTVRn(i
));
287 etm_writel(drvdata
, drvdata
->seq_12_event
, ETMSQ12EVR
);
288 etm_writel(drvdata
, drvdata
->seq_21_event
, ETMSQ21EVR
);
289 etm_writel(drvdata
, drvdata
->seq_23_event
, ETMSQ23EVR
);
290 etm_writel(drvdata
, drvdata
->seq_31_event
, ETMSQ31EVR
);
291 etm_writel(drvdata
, drvdata
->seq_32_event
, ETMSQ32EVR
);
292 etm_writel(drvdata
, drvdata
->seq_13_event
, ETMSQ13EVR
);
293 etm_writel(drvdata
, drvdata
->seq_curr_state
, ETMSQR
);
294 for (i
= 0; i
< drvdata
->nr_ext_out
; i
++)
295 etm_writel(drvdata
, ETM_DEFAULT_EVENT_VAL
, ETMEXTOUTEVRn(i
));
296 for (i
= 0; i
< drvdata
->nr_ctxid_cmp
; i
++)
297 etm_writel(drvdata
, drvdata
->ctxid_val
[i
], ETMCIDCVRn(i
));
298 etm_writel(drvdata
, drvdata
->ctxid_mask
, ETMCIDCMR
);
299 etm_writel(drvdata
, drvdata
->sync_freq
, ETMSYNCFR
);
300 /* No external input selected */
301 etm_writel(drvdata
, 0x0, ETMEXTINSELR
);
302 etm_writel(drvdata
, drvdata
->timestamp_event
, ETMTSEVR
);
303 /* No auxiliary control selected */
304 etm_writel(drvdata
, 0x0, ETMAUXCR
);
305 etm_writel(drvdata
, drvdata
->traceid
, ETMTRACEIDR
);
306 /* No VMID comparator value selected */
307 etm_writel(drvdata
, 0x0, ETMVMIDCVR
);
309 /* Ensures trace output is enabled from this ETM */
310 etm_writel(drvdata
, drvdata
->ctrl
| ETMCR_ETM_EN
| etmcr
, ETMCR
);
312 etm_clr_prog(drvdata
);
313 CS_LOCK(drvdata
->base
);
315 dev_dbg(drvdata
->dev
, "cpu: %d enable smp call done\n", drvdata
->cpu
);
318 static int etm_trace_id_simple(struct etm_drvdata
*drvdata
)
320 if (!drvdata
->enable
)
321 return drvdata
->traceid
;
323 return (etm_readl(drvdata
, ETMTRACEIDR
) & ETM_TRACEID_MASK
);
326 static int etm_trace_id(struct coresight_device
*csdev
)
328 struct etm_drvdata
*drvdata
= dev_get_drvdata(csdev
->dev
.parent
);
332 if (!drvdata
->enable
)
333 return drvdata
->traceid
;
335 if (clk_prepare_enable(drvdata
->clk
))
338 spin_lock_irqsave(&drvdata
->spinlock
, flags
);
340 CS_UNLOCK(drvdata
->base
);
341 trace_id
= (etm_readl(drvdata
, ETMTRACEIDR
) & ETM_TRACEID_MASK
);
342 CS_LOCK(drvdata
->base
);
344 spin_unlock_irqrestore(&drvdata
->spinlock
, flags
);
345 clk_disable_unprepare(drvdata
->clk
);
350 static int etm_enable(struct coresight_device
*csdev
)
352 struct etm_drvdata
*drvdata
= dev_get_drvdata(csdev
->dev
.parent
);
355 ret
= clk_prepare_enable(drvdata
->clk
);
359 spin_lock(&drvdata
->spinlock
);
362 * Configure the ETM only if the CPU is online. If it isn't online
363 * hw configuration will take place when 'CPU_STARTING' is received
364 * in @etm_cpu_callback.
366 if (cpu_online(drvdata
->cpu
)) {
367 ret
= smp_call_function_single(drvdata
->cpu
,
368 etm_enable_hw
, drvdata
, 1);
373 drvdata
->enable
= true;
374 drvdata
->sticky_enable
= true;
376 spin_unlock(&drvdata
->spinlock
);
378 dev_info(drvdata
->dev
, "ETM tracing enabled\n");
381 spin_unlock(&drvdata
->spinlock
);
382 clk_disable_unprepare(drvdata
->clk
);
387 static void etm_disable_hw(void *info
)
390 struct etm_drvdata
*drvdata
= info
;
392 CS_UNLOCK(drvdata
->base
);
393 etm_set_prog(drvdata
);
395 /* Program trace enable to low by using always false event */
396 etm_writel(drvdata
, ETM_HARD_WIRE_RES_A
| ETM_EVENT_NOT_A
, ETMTEEVR
);
398 /* Read back sequencer and counters for post trace analysis */
399 drvdata
->seq_curr_state
= (etm_readl(drvdata
, ETMSQR
) & ETM_SQR_MASK
);
401 for (i
= 0; i
< drvdata
->nr_cntr
; i
++)
402 drvdata
->cntr_val
[i
] = etm_readl(drvdata
, ETMCNTVRn(i
));
404 etm_set_pwrdwn(drvdata
);
405 CS_LOCK(drvdata
->base
);
407 dev_dbg(drvdata
->dev
, "cpu: %d disable smp call done\n", drvdata
->cpu
);
410 static void etm_disable(struct coresight_device
*csdev
)
412 struct etm_drvdata
*drvdata
= dev_get_drvdata(csdev
->dev
.parent
);
415 * Taking hotplug lock here protects from clocks getting disabled
416 * with tracing being left on (crash scenario) if user disable occurs
417 * after cpu online mask indicates the cpu is offline but before the
418 * DYING hotplug callback is serviced by the ETM driver.
421 spin_lock(&drvdata
->spinlock
);
424 * Executing etm_disable_hw on the cpu whose ETM is being disabled
425 * ensures that register writes occur when cpu is powered.
427 smp_call_function_single(drvdata
->cpu
, etm_disable_hw
, drvdata
, 1);
428 drvdata
->enable
= false;
430 spin_unlock(&drvdata
->spinlock
);
433 clk_disable_unprepare(drvdata
->clk
);
435 dev_info(drvdata
->dev
, "ETM tracing disabled\n");
438 static const struct coresight_ops_source etm_source_ops
= {
439 .trace_id
= etm_trace_id
,
440 .enable
= etm_enable
,
441 .disable
= etm_disable
,
444 static const struct coresight_ops etm_cs_ops
= {
445 .source_ops
= &etm_source_ops
,
448 static ssize_t
nr_addr_cmp_show(struct device
*dev
,
449 struct device_attribute
*attr
, char *buf
)
452 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
454 val
= drvdata
->nr_addr_cmp
;
455 return sprintf(buf
, "%#lx\n", val
);
457 static DEVICE_ATTR_RO(nr_addr_cmp
);
459 static ssize_t
nr_cntr_show(struct device
*dev
,
460 struct device_attribute
*attr
, char *buf
)
462 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
464 val
= drvdata
->nr_cntr
;
465 return sprintf(buf
, "%#lx\n", val
);
467 static DEVICE_ATTR_RO(nr_cntr
);
469 static ssize_t
nr_ctxid_cmp_show(struct device
*dev
,
470 struct device_attribute
*attr
, char *buf
)
473 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
475 val
= drvdata
->nr_ctxid_cmp
;
476 return sprintf(buf
, "%#lx\n", val
);
478 static DEVICE_ATTR_RO(nr_ctxid_cmp
);
480 static ssize_t
etmsr_show(struct device
*dev
,
481 struct device_attribute
*attr
, char *buf
)
484 unsigned long flags
, val
;
485 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
487 ret
= clk_prepare_enable(drvdata
->clk
);
491 spin_lock_irqsave(&drvdata
->spinlock
, flags
);
492 CS_UNLOCK(drvdata
->base
);
494 val
= etm_readl(drvdata
, ETMSR
);
496 CS_LOCK(drvdata
->base
);
497 spin_unlock_irqrestore(&drvdata
->spinlock
, flags
);
498 clk_disable_unprepare(drvdata
->clk
);
500 return sprintf(buf
, "%#lx\n", val
);
502 static DEVICE_ATTR_RO(etmsr
);
504 static ssize_t
reset_store(struct device
*dev
,
505 struct device_attribute
*attr
,
506 const char *buf
, size_t size
)
510 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
512 ret
= kstrtoul(buf
, 16, &val
);
517 spin_lock(&drvdata
->spinlock
);
518 drvdata
->mode
= ETM_MODE_EXCLUDE
;
520 drvdata
->trigger_event
= ETM_DEFAULT_EVENT_VAL
;
521 drvdata
->startstop_ctrl
= 0x0;
522 drvdata
->addr_idx
= 0x0;
523 for (i
= 0; i
< drvdata
->nr_addr_cmp
; i
++) {
524 drvdata
->addr_val
[i
] = 0x0;
525 drvdata
->addr_acctype
[i
] = 0x0;
526 drvdata
->addr_type
[i
] = ETM_ADDR_TYPE_NONE
;
528 drvdata
->cntr_idx
= 0x0;
530 etm_set_default(drvdata
);
531 spin_unlock(&drvdata
->spinlock
);
536 static DEVICE_ATTR_WO(reset
);
538 static ssize_t
mode_show(struct device
*dev
,
539 struct device_attribute
*attr
, char *buf
)
542 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
545 return sprintf(buf
, "%#lx\n", val
);
548 static ssize_t
mode_store(struct device
*dev
,
549 struct device_attribute
*attr
,
550 const char *buf
, size_t size
)
554 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
556 ret
= kstrtoul(buf
, 16, &val
);
560 spin_lock(&drvdata
->spinlock
);
561 drvdata
->mode
= val
& ETM_MODE_ALL
;
563 if (drvdata
->mode
& ETM_MODE_EXCLUDE
)
564 drvdata
->enable_ctrl1
|= ETMTECR1_INC_EXC
;
566 drvdata
->enable_ctrl1
&= ~ETMTECR1_INC_EXC
;
568 if (drvdata
->mode
& ETM_MODE_CYCACC
)
569 drvdata
->ctrl
|= ETMCR_CYC_ACC
;
571 drvdata
->ctrl
&= ~ETMCR_CYC_ACC
;
573 if (drvdata
->mode
& ETM_MODE_STALL
) {
574 if (!(drvdata
->etmccr
& ETMCCR_FIFOFULL
)) {
575 dev_warn(drvdata
->dev
, "stall mode not supported\n");
578 drvdata
->ctrl
|= ETMCR_STALL_MODE
;
580 drvdata
->ctrl
&= ~ETMCR_STALL_MODE
;
582 if (drvdata
->mode
& ETM_MODE_TIMESTAMP
) {
583 if (!(drvdata
->etmccer
& ETMCCER_TIMESTAMP
)) {
584 dev_warn(drvdata
->dev
, "timestamp not supported\n");
587 drvdata
->ctrl
|= ETMCR_TIMESTAMP_EN
;
589 drvdata
->ctrl
&= ~ETMCR_TIMESTAMP_EN
;
591 if (drvdata
->mode
& ETM_MODE_CTXID
)
592 drvdata
->ctrl
|= ETMCR_CTXID_SIZE
;
594 drvdata
->ctrl
&= ~ETMCR_CTXID_SIZE
;
595 spin_unlock(&drvdata
->spinlock
);
599 static DEVICE_ATTR_RW(mode
);
601 static ssize_t
trigger_event_show(struct device
*dev
,
602 struct device_attribute
*attr
, char *buf
)
605 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
607 val
= drvdata
->trigger_event
;
608 return sprintf(buf
, "%#lx\n", val
);
611 static ssize_t
trigger_event_store(struct device
*dev
,
612 struct device_attribute
*attr
,
613 const char *buf
, size_t size
)
617 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
619 ret
= kstrtoul(buf
, 16, &val
);
623 drvdata
->trigger_event
= val
& ETM_EVENT_MASK
;
627 static DEVICE_ATTR_RW(trigger_event
);
629 static ssize_t
enable_event_show(struct device
*dev
,
630 struct device_attribute
*attr
, char *buf
)
633 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
635 val
= drvdata
->enable_event
;
636 return sprintf(buf
, "%#lx\n", val
);
639 static ssize_t
enable_event_store(struct device
*dev
,
640 struct device_attribute
*attr
,
641 const char *buf
, size_t size
)
645 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
647 ret
= kstrtoul(buf
, 16, &val
);
651 drvdata
->enable_event
= val
& ETM_EVENT_MASK
;
655 static DEVICE_ATTR_RW(enable_event
);
657 static ssize_t
fifofull_level_show(struct device
*dev
,
658 struct device_attribute
*attr
, char *buf
)
661 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
663 val
= drvdata
->fifofull_level
;
664 return sprintf(buf
, "%#lx\n", val
);
667 static ssize_t
fifofull_level_store(struct device
*dev
,
668 struct device_attribute
*attr
,
669 const char *buf
, size_t size
)
673 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
675 ret
= kstrtoul(buf
, 16, &val
);
679 drvdata
->fifofull_level
= val
;
683 static DEVICE_ATTR_RW(fifofull_level
);
685 static ssize_t
addr_idx_show(struct device
*dev
,
686 struct device_attribute
*attr
, char *buf
)
689 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
691 val
= drvdata
->addr_idx
;
692 return sprintf(buf
, "%#lx\n", val
);
695 static ssize_t
addr_idx_store(struct device
*dev
,
696 struct device_attribute
*attr
,
697 const char *buf
, size_t size
)
701 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
703 ret
= kstrtoul(buf
, 16, &val
);
707 if (val
>= drvdata
->nr_addr_cmp
)
711 * Use spinlock to ensure index doesn't change while it gets
712 * dereferenced multiple times within a spinlock block elsewhere.
714 spin_lock(&drvdata
->spinlock
);
715 drvdata
->addr_idx
= val
;
716 spin_unlock(&drvdata
->spinlock
);
720 static DEVICE_ATTR_RW(addr_idx
);
722 static ssize_t
addr_single_show(struct device
*dev
,
723 struct device_attribute
*attr
, char *buf
)
727 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
729 spin_lock(&drvdata
->spinlock
);
730 idx
= drvdata
->addr_idx
;
731 if (!(drvdata
->addr_type
[idx
] == ETM_ADDR_TYPE_NONE
||
732 drvdata
->addr_type
[idx
] == ETM_ADDR_TYPE_SINGLE
)) {
733 spin_unlock(&drvdata
->spinlock
);
737 val
= drvdata
->addr_val
[idx
];
738 spin_unlock(&drvdata
->spinlock
);
740 return sprintf(buf
, "%#lx\n", val
);
743 static ssize_t
addr_single_store(struct device
*dev
,
744 struct device_attribute
*attr
,
745 const char *buf
, size_t size
)
750 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
752 ret
= kstrtoul(buf
, 16, &val
);
756 spin_lock(&drvdata
->spinlock
);
757 idx
= drvdata
->addr_idx
;
758 if (!(drvdata
->addr_type
[idx
] == ETM_ADDR_TYPE_NONE
||
759 drvdata
->addr_type
[idx
] == ETM_ADDR_TYPE_SINGLE
)) {
760 spin_unlock(&drvdata
->spinlock
);
764 drvdata
->addr_val
[idx
] = val
;
765 drvdata
->addr_type
[idx
] = ETM_ADDR_TYPE_SINGLE
;
766 spin_unlock(&drvdata
->spinlock
);
770 static DEVICE_ATTR_RW(addr_single
);
772 static ssize_t
addr_range_show(struct device
*dev
,
773 struct device_attribute
*attr
, char *buf
)
776 unsigned long val1
, val2
;
777 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
779 spin_lock(&drvdata
->spinlock
);
780 idx
= drvdata
->addr_idx
;
782 spin_unlock(&drvdata
->spinlock
);
785 if (!((drvdata
->addr_type
[idx
] == ETM_ADDR_TYPE_NONE
&&
786 drvdata
->addr_type
[idx
+ 1] == ETM_ADDR_TYPE_NONE
) ||
787 (drvdata
->addr_type
[idx
] == ETM_ADDR_TYPE_RANGE
&&
788 drvdata
->addr_type
[idx
+ 1] == ETM_ADDR_TYPE_RANGE
))) {
789 spin_unlock(&drvdata
->spinlock
);
793 val1
= drvdata
->addr_val
[idx
];
794 val2
= drvdata
->addr_val
[idx
+ 1];
795 spin_unlock(&drvdata
->spinlock
);
797 return sprintf(buf
, "%#lx %#lx\n", val1
, val2
);
800 static ssize_t
addr_range_store(struct device
*dev
,
801 struct device_attribute
*attr
,
802 const char *buf
, size_t size
)
805 unsigned long val1
, val2
;
806 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
808 if (sscanf(buf
, "%lx %lx", &val1
, &val2
) != 2)
810 /* Lower address comparator cannot have a higher address value */
814 spin_lock(&drvdata
->spinlock
);
815 idx
= drvdata
->addr_idx
;
817 spin_unlock(&drvdata
->spinlock
);
820 if (!((drvdata
->addr_type
[idx
] == ETM_ADDR_TYPE_NONE
&&
821 drvdata
->addr_type
[idx
+ 1] == ETM_ADDR_TYPE_NONE
) ||
822 (drvdata
->addr_type
[idx
] == ETM_ADDR_TYPE_RANGE
&&
823 drvdata
->addr_type
[idx
+ 1] == ETM_ADDR_TYPE_RANGE
))) {
824 spin_unlock(&drvdata
->spinlock
);
828 drvdata
->addr_val
[idx
] = val1
;
829 drvdata
->addr_type
[idx
] = ETM_ADDR_TYPE_RANGE
;
830 drvdata
->addr_val
[idx
+ 1] = val2
;
831 drvdata
->addr_type
[idx
+ 1] = ETM_ADDR_TYPE_RANGE
;
832 drvdata
->enable_ctrl1
|= (1 << (idx
/2));
833 spin_unlock(&drvdata
->spinlock
);
837 static DEVICE_ATTR_RW(addr_range
);
839 static ssize_t
addr_start_show(struct device
*dev
,
840 struct device_attribute
*attr
, char *buf
)
844 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
846 spin_lock(&drvdata
->spinlock
);
847 idx
= drvdata
->addr_idx
;
848 if (!(drvdata
->addr_type
[idx
] == ETM_ADDR_TYPE_NONE
||
849 drvdata
->addr_type
[idx
] == ETM_ADDR_TYPE_START
)) {
850 spin_unlock(&drvdata
->spinlock
);
854 val
= drvdata
->addr_val
[idx
];
855 spin_unlock(&drvdata
->spinlock
);
857 return sprintf(buf
, "%#lx\n", val
);
860 static ssize_t
addr_start_store(struct device
*dev
,
861 struct device_attribute
*attr
,
862 const char *buf
, size_t size
)
867 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
869 ret
= kstrtoul(buf
, 16, &val
);
873 spin_lock(&drvdata
->spinlock
);
874 idx
= drvdata
->addr_idx
;
875 if (!(drvdata
->addr_type
[idx
] == ETM_ADDR_TYPE_NONE
||
876 drvdata
->addr_type
[idx
] == ETM_ADDR_TYPE_START
)) {
877 spin_unlock(&drvdata
->spinlock
);
881 drvdata
->addr_val
[idx
] = val
;
882 drvdata
->addr_type
[idx
] = ETM_ADDR_TYPE_START
;
883 drvdata
->startstop_ctrl
|= (1 << idx
);
884 drvdata
->enable_ctrl1
|= BIT(25);
885 spin_unlock(&drvdata
->spinlock
);
889 static DEVICE_ATTR_RW(addr_start
);
891 static ssize_t
addr_stop_show(struct device
*dev
,
892 struct device_attribute
*attr
, char *buf
)
896 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
898 spin_lock(&drvdata
->spinlock
);
899 idx
= drvdata
->addr_idx
;
900 if (!(drvdata
->addr_type
[idx
] == ETM_ADDR_TYPE_NONE
||
901 drvdata
->addr_type
[idx
] == ETM_ADDR_TYPE_STOP
)) {
902 spin_unlock(&drvdata
->spinlock
);
906 val
= drvdata
->addr_val
[idx
];
907 spin_unlock(&drvdata
->spinlock
);
909 return sprintf(buf
, "%#lx\n", val
);
912 static ssize_t
addr_stop_store(struct device
*dev
,
913 struct device_attribute
*attr
,
914 const char *buf
, size_t size
)
919 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
921 ret
= kstrtoul(buf
, 16, &val
);
925 spin_lock(&drvdata
->spinlock
);
926 idx
= drvdata
->addr_idx
;
927 if (!(drvdata
->addr_type
[idx
] == ETM_ADDR_TYPE_NONE
||
928 drvdata
->addr_type
[idx
] == ETM_ADDR_TYPE_STOP
)) {
929 spin_unlock(&drvdata
->spinlock
);
933 drvdata
->addr_val
[idx
] = val
;
934 drvdata
->addr_type
[idx
] = ETM_ADDR_TYPE_STOP
;
935 drvdata
->startstop_ctrl
|= (1 << (idx
+ 16));
936 drvdata
->enable_ctrl1
|= ETMTECR1_START_STOP
;
937 spin_unlock(&drvdata
->spinlock
);
941 static DEVICE_ATTR_RW(addr_stop
);
943 static ssize_t
addr_acctype_show(struct device
*dev
,
944 struct device_attribute
*attr
, char *buf
)
947 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
949 spin_lock(&drvdata
->spinlock
);
950 val
= drvdata
->addr_acctype
[drvdata
->addr_idx
];
951 spin_unlock(&drvdata
->spinlock
);
953 return sprintf(buf
, "%#lx\n", val
);
956 static ssize_t
addr_acctype_store(struct device
*dev
,
957 struct device_attribute
*attr
,
958 const char *buf
, size_t size
)
962 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
964 ret
= kstrtoul(buf
, 16, &val
);
968 spin_lock(&drvdata
->spinlock
);
969 drvdata
->addr_acctype
[drvdata
->addr_idx
] = val
;
970 spin_unlock(&drvdata
->spinlock
);
974 static DEVICE_ATTR_RW(addr_acctype
);
976 static ssize_t
cntr_idx_show(struct device
*dev
,
977 struct device_attribute
*attr
, char *buf
)
980 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
982 val
= drvdata
->cntr_idx
;
983 return sprintf(buf
, "%#lx\n", val
);
986 static ssize_t
cntr_idx_store(struct device
*dev
,
987 struct device_attribute
*attr
,
988 const char *buf
, size_t size
)
992 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
994 ret
= kstrtoul(buf
, 16, &val
);
998 if (val
>= drvdata
->nr_cntr
)
1001 * Use spinlock to ensure index doesn't change while it gets
1002 * dereferenced multiple times within a spinlock block elsewhere.
1004 spin_lock(&drvdata
->spinlock
);
1005 drvdata
->cntr_idx
= val
;
1006 spin_unlock(&drvdata
->spinlock
);
1010 static DEVICE_ATTR_RW(cntr_idx
);
1012 static ssize_t
cntr_rld_val_show(struct device
*dev
,
1013 struct device_attribute
*attr
, char *buf
)
1016 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1018 spin_lock(&drvdata
->spinlock
);
1019 val
= drvdata
->cntr_rld_val
[drvdata
->cntr_idx
];
1020 spin_unlock(&drvdata
->spinlock
);
1022 return sprintf(buf
, "%#lx\n", val
);
1025 static ssize_t
cntr_rld_val_store(struct device
*dev
,
1026 struct device_attribute
*attr
,
1027 const char *buf
, size_t size
)
1031 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1033 ret
= kstrtoul(buf
, 16, &val
);
1037 spin_lock(&drvdata
->spinlock
);
1038 drvdata
->cntr_rld_val
[drvdata
->cntr_idx
] = val
;
1039 spin_unlock(&drvdata
->spinlock
);
1043 static DEVICE_ATTR_RW(cntr_rld_val
);
1045 static ssize_t
cntr_event_show(struct device
*dev
,
1046 struct device_attribute
*attr
, char *buf
)
1049 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1051 spin_lock(&drvdata
->spinlock
);
1052 val
= drvdata
->cntr_event
[drvdata
->cntr_idx
];
1053 spin_unlock(&drvdata
->spinlock
);
1055 return sprintf(buf
, "%#lx\n", val
);
1058 static ssize_t
cntr_event_store(struct device
*dev
,
1059 struct device_attribute
*attr
,
1060 const char *buf
, size_t size
)
1064 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1066 ret
= kstrtoul(buf
, 16, &val
);
1070 spin_lock(&drvdata
->spinlock
);
1071 drvdata
->cntr_event
[drvdata
->cntr_idx
] = val
& ETM_EVENT_MASK
;
1072 spin_unlock(&drvdata
->spinlock
);
1076 static DEVICE_ATTR_RW(cntr_event
);
1078 static ssize_t
cntr_rld_event_show(struct device
*dev
,
1079 struct device_attribute
*attr
, char *buf
)
1082 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1084 spin_lock(&drvdata
->spinlock
);
1085 val
= drvdata
->cntr_rld_event
[drvdata
->cntr_idx
];
1086 spin_unlock(&drvdata
->spinlock
);
1088 return sprintf(buf
, "%#lx\n", val
);
1091 static ssize_t
cntr_rld_event_store(struct device
*dev
,
1092 struct device_attribute
*attr
,
1093 const char *buf
, size_t size
)
1097 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1099 ret
= kstrtoul(buf
, 16, &val
);
1103 spin_lock(&drvdata
->spinlock
);
1104 drvdata
->cntr_rld_event
[drvdata
->cntr_idx
] = val
& ETM_EVENT_MASK
;
1105 spin_unlock(&drvdata
->spinlock
);
1109 static DEVICE_ATTR_RW(cntr_rld_event
);
1111 static ssize_t
cntr_val_show(struct device
*dev
,
1112 struct device_attribute
*attr
, char *buf
)
1116 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1118 if (!drvdata
->enable
) {
1119 spin_lock(&drvdata
->spinlock
);
1120 for (i
= 0; i
< drvdata
->nr_cntr
; i
++)
1121 ret
+= sprintf(buf
, "counter %d: %x\n",
1122 i
, drvdata
->cntr_val
[i
]);
1123 spin_unlock(&drvdata
->spinlock
);
1127 for (i
= 0; i
< drvdata
->nr_cntr
; i
++) {
1128 val
= etm_readl(drvdata
, ETMCNTVRn(i
));
1129 ret
+= sprintf(buf
, "counter %d: %x\n", i
, val
);
1135 static ssize_t
cntr_val_store(struct device
*dev
,
1136 struct device_attribute
*attr
,
1137 const char *buf
, size_t size
)
1141 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1143 ret
= kstrtoul(buf
, 16, &val
);
1147 spin_lock(&drvdata
->spinlock
);
1148 drvdata
->cntr_val
[drvdata
->cntr_idx
] = val
;
1149 spin_unlock(&drvdata
->spinlock
);
1153 static DEVICE_ATTR_RW(cntr_val
);
1155 static ssize_t
seq_12_event_show(struct device
*dev
,
1156 struct device_attribute
*attr
, char *buf
)
1159 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1161 val
= drvdata
->seq_12_event
;
1162 return sprintf(buf
, "%#lx\n", val
);
1165 static ssize_t
seq_12_event_store(struct device
*dev
,
1166 struct device_attribute
*attr
,
1167 const char *buf
, size_t size
)
1171 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1173 ret
= kstrtoul(buf
, 16, &val
);
1177 drvdata
->seq_12_event
= val
& ETM_EVENT_MASK
;
1180 static DEVICE_ATTR_RW(seq_12_event
);
1182 static ssize_t
seq_21_event_show(struct device
*dev
,
1183 struct device_attribute
*attr
, char *buf
)
1186 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1188 val
= drvdata
->seq_21_event
;
1189 return sprintf(buf
, "%#lx\n", val
);
1192 static ssize_t
seq_21_event_store(struct device
*dev
,
1193 struct device_attribute
*attr
,
1194 const char *buf
, size_t size
)
1198 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1200 ret
= kstrtoul(buf
, 16, &val
);
1204 drvdata
->seq_21_event
= val
& ETM_EVENT_MASK
;
1207 static DEVICE_ATTR_RW(seq_21_event
);
1209 static ssize_t
seq_23_event_show(struct device
*dev
,
1210 struct device_attribute
*attr
, char *buf
)
1213 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1215 val
= drvdata
->seq_23_event
;
1216 return sprintf(buf
, "%#lx\n", val
);
1219 static ssize_t
seq_23_event_store(struct device
*dev
,
1220 struct device_attribute
*attr
,
1221 const char *buf
, size_t size
)
1225 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1227 ret
= kstrtoul(buf
, 16, &val
);
1231 drvdata
->seq_23_event
= val
& ETM_EVENT_MASK
;
1234 static DEVICE_ATTR_RW(seq_23_event
);
1236 static ssize_t
seq_31_event_show(struct device
*dev
,
1237 struct device_attribute
*attr
, char *buf
)
1240 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1242 val
= drvdata
->seq_31_event
;
1243 return sprintf(buf
, "%#lx\n", val
);
1246 static ssize_t
seq_31_event_store(struct device
*dev
,
1247 struct device_attribute
*attr
,
1248 const char *buf
, size_t size
)
1252 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1254 ret
= kstrtoul(buf
, 16, &val
);
1258 drvdata
->seq_31_event
= val
& ETM_EVENT_MASK
;
1261 static DEVICE_ATTR_RW(seq_31_event
);
1263 static ssize_t
seq_32_event_show(struct device
*dev
,
1264 struct device_attribute
*attr
, char *buf
)
1267 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1269 val
= drvdata
->seq_32_event
;
1270 return sprintf(buf
, "%#lx\n", val
);
1273 static ssize_t
seq_32_event_store(struct device
*dev
,
1274 struct device_attribute
*attr
,
1275 const char *buf
, size_t size
)
1279 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1281 ret
= kstrtoul(buf
, 16, &val
);
1285 drvdata
->seq_32_event
= val
& ETM_EVENT_MASK
;
1288 static DEVICE_ATTR_RW(seq_32_event
);
1290 static ssize_t
seq_13_event_show(struct device
*dev
,
1291 struct device_attribute
*attr
, char *buf
)
1294 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1296 val
= drvdata
->seq_13_event
;
1297 return sprintf(buf
, "%#lx\n", val
);
1300 static ssize_t
seq_13_event_store(struct device
*dev
,
1301 struct device_attribute
*attr
,
1302 const char *buf
, size_t size
)
1306 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1308 ret
= kstrtoul(buf
, 16, &val
);
1312 drvdata
->seq_13_event
= val
& ETM_EVENT_MASK
;
1315 static DEVICE_ATTR_RW(seq_13_event
);
1317 static ssize_t
seq_curr_state_show(struct device
*dev
,
1318 struct device_attribute
*attr
, char *buf
)
1321 unsigned long val
, flags
;
1322 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1324 if (!drvdata
->enable
) {
1325 val
= drvdata
->seq_curr_state
;
1329 ret
= clk_prepare_enable(drvdata
->clk
);
1333 spin_lock_irqsave(&drvdata
->spinlock
, flags
);
1335 CS_UNLOCK(drvdata
->base
);
1336 val
= (etm_readl(drvdata
, ETMSQR
) & ETM_SQR_MASK
);
1337 CS_LOCK(drvdata
->base
);
1339 spin_unlock_irqrestore(&drvdata
->spinlock
, flags
);
1340 clk_disable_unprepare(drvdata
->clk
);
1342 return sprintf(buf
, "%#lx\n", val
);
1345 static ssize_t
seq_curr_state_store(struct device
*dev
,
1346 struct device_attribute
*attr
,
1347 const char *buf
, size_t size
)
1351 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1353 ret
= kstrtoul(buf
, 16, &val
);
1357 if (val
> ETM_SEQ_STATE_MAX_VAL
)
1360 drvdata
->seq_curr_state
= val
;
1364 static DEVICE_ATTR_RW(seq_curr_state
);
1366 static ssize_t
ctxid_idx_show(struct device
*dev
,
1367 struct device_attribute
*attr
, char *buf
)
1370 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1372 val
= drvdata
->ctxid_idx
;
1373 return sprintf(buf
, "%#lx\n", val
);
1376 static ssize_t
ctxid_idx_store(struct device
*dev
,
1377 struct device_attribute
*attr
,
1378 const char *buf
, size_t size
)
1382 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1384 ret
= kstrtoul(buf
, 16, &val
);
1388 if (val
>= drvdata
->nr_ctxid_cmp
)
1392 * Use spinlock to ensure index doesn't change while it gets
1393 * dereferenced multiple times within a spinlock block elsewhere.
1395 spin_lock(&drvdata
->spinlock
);
1396 drvdata
->ctxid_idx
= val
;
1397 spin_unlock(&drvdata
->spinlock
);
1401 static DEVICE_ATTR_RW(ctxid_idx
);
1403 static ssize_t
ctxid_val_show(struct device
*dev
,
1404 struct device_attribute
*attr
, char *buf
)
1407 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1409 spin_lock(&drvdata
->spinlock
);
1410 val
= drvdata
->ctxid_val
[drvdata
->ctxid_idx
];
1411 spin_unlock(&drvdata
->spinlock
);
1413 return sprintf(buf
, "%#lx\n", val
);
1416 static ssize_t
ctxid_val_store(struct device
*dev
,
1417 struct device_attribute
*attr
,
1418 const char *buf
, size_t size
)
1422 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1424 ret
= kstrtoul(buf
, 16, &val
);
1428 spin_lock(&drvdata
->spinlock
);
1429 drvdata
->ctxid_val
[drvdata
->ctxid_idx
] = val
;
1430 spin_unlock(&drvdata
->spinlock
);
1434 static DEVICE_ATTR_RW(ctxid_val
);
1436 static ssize_t
ctxid_mask_show(struct device
*dev
,
1437 struct device_attribute
*attr
, char *buf
)
1440 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1442 val
= drvdata
->ctxid_mask
;
1443 return sprintf(buf
, "%#lx\n", val
);
1446 static ssize_t
ctxid_mask_store(struct device
*dev
,
1447 struct device_attribute
*attr
,
1448 const char *buf
, size_t size
)
1452 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1454 ret
= kstrtoul(buf
, 16, &val
);
1458 drvdata
->ctxid_mask
= val
;
1461 static DEVICE_ATTR_RW(ctxid_mask
);
1463 static ssize_t
sync_freq_show(struct device
*dev
,
1464 struct device_attribute
*attr
, char *buf
)
1467 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1469 val
= drvdata
->sync_freq
;
1470 return sprintf(buf
, "%#lx\n", val
);
1473 static ssize_t
sync_freq_store(struct device
*dev
,
1474 struct device_attribute
*attr
,
1475 const char *buf
, size_t size
)
1479 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1481 ret
= kstrtoul(buf
, 16, &val
);
1485 drvdata
->sync_freq
= val
& ETM_SYNC_MASK
;
1488 static DEVICE_ATTR_RW(sync_freq
);
1490 static ssize_t
timestamp_event_show(struct device
*dev
,
1491 struct device_attribute
*attr
, char *buf
)
1494 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1496 val
= drvdata
->timestamp_event
;
1497 return sprintf(buf
, "%#lx\n", val
);
1500 static ssize_t
timestamp_event_store(struct device
*dev
,
1501 struct device_attribute
*attr
,
1502 const char *buf
, size_t size
)
1506 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1508 ret
= kstrtoul(buf
, 16, &val
);
1512 drvdata
->timestamp_event
= val
& ETM_EVENT_MASK
;
1515 static DEVICE_ATTR_RW(timestamp_event
);
1517 static ssize_t
status_show(struct device
*dev
,
1518 struct device_attribute
*attr
, char *buf
)
1521 unsigned long flags
;
1522 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1524 ret
= clk_prepare_enable(drvdata
->clk
);
1528 spin_lock_irqsave(&drvdata
->spinlock
, flags
);
1530 CS_UNLOCK(drvdata
->base
);
1537 "ETMTRACEIDR: 0x%08x\n"
1538 "Enable event: 0x%08x\n"
1539 "Enable start/stop: 0x%08x\n"
1540 "Enable control: CR1 0x%08x CR2 0x%08x\n"
1541 "CPU affinity: %d\n",
1542 drvdata
->etmccr
, drvdata
->etmccer
,
1543 etm_readl(drvdata
, ETMSCR
), etm_readl(drvdata
, ETMIDR
),
1544 etm_readl(drvdata
, ETMCR
), etm_trace_id_simple(drvdata
),
1545 etm_readl(drvdata
, ETMTEEVR
),
1546 etm_readl(drvdata
, ETMTSSCR
),
1547 etm_readl(drvdata
, ETMTECR1
),
1548 etm_readl(drvdata
, ETMTECR2
),
1550 CS_LOCK(drvdata
->base
);
1552 spin_unlock_irqrestore(&drvdata
->spinlock
, flags
);
1553 clk_disable_unprepare(drvdata
->clk
);
1557 static DEVICE_ATTR_RO(status
);
1559 static ssize_t
traceid_show(struct device
*dev
,
1560 struct device_attribute
*attr
, char *buf
)
1563 unsigned long val
, flags
;
1564 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1566 if (!drvdata
->enable
) {
1567 val
= drvdata
->traceid
;
1571 ret
= clk_prepare_enable(drvdata
->clk
);
1575 spin_lock_irqsave(&drvdata
->spinlock
, flags
);
1576 CS_UNLOCK(drvdata
->base
);
1578 val
= (etm_readl(drvdata
, ETMTRACEIDR
) & ETM_TRACEID_MASK
);
1580 CS_LOCK(drvdata
->base
);
1581 spin_unlock_irqrestore(&drvdata
->spinlock
, flags
);
1582 clk_disable_unprepare(drvdata
->clk
);
1584 return sprintf(buf
, "%#lx\n", val
);
1587 static ssize_t
traceid_store(struct device
*dev
,
1588 struct device_attribute
*attr
,
1589 const char *buf
, size_t size
)
1593 struct etm_drvdata
*drvdata
= dev_get_drvdata(dev
->parent
);
1595 ret
= kstrtoul(buf
, 16, &val
);
1599 drvdata
->traceid
= val
& ETM_TRACEID_MASK
;
1602 static DEVICE_ATTR_RW(traceid
);
1604 static struct attribute
*coresight_etm_attrs
[] = {
1605 &dev_attr_nr_addr_cmp
.attr
,
1606 &dev_attr_nr_cntr
.attr
,
1607 &dev_attr_nr_ctxid_cmp
.attr
,
1608 &dev_attr_etmsr
.attr
,
1609 &dev_attr_reset
.attr
,
1610 &dev_attr_mode
.attr
,
1611 &dev_attr_trigger_event
.attr
,
1612 &dev_attr_enable_event
.attr
,
1613 &dev_attr_fifofull_level
.attr
,
1614 &dev_attr_addr_idx
.attr
,
1615 &dev_attr_addr_single
.attr
,
1616 &dev_attr_addr_range
.attr
,
1617 &dev_attr_addr_start
.attr
,
1618 &dev_attr_addr_stop
.attr
,
1619 &dev_attr_addr_acctype
.attr
,
1620 &dev_attr_cntr_idx
.attr
,
1621 &dev_attr_cntr_rld_val
.attr
,
1622 &dev_attr_cntr_event
.attr
,
1623 &dev_attr_cntr_rld_event
.attr
,
1624 &dev_attr_cntr_val
.attr
,
1625 &dev_attr_seq_12_event
.attr
,
1626 &dev_attr_seq_21_event
.attr
,
1627 &dev_attr_seq_23_event
.attr
,
1628 &dev_attr_seq_31_event
.attr
,
1629 &dev_attr_seq_32_event
.attr
,
1630 &dev_attr_seq_13_event
.attr
,
1631 &dev_attr_seq_curr_state
.attr
,
1632 &dev_attr_ctxid_idx
.attr
,
1633 &dev_attr_ctxid_val
.attr
,
1634 &dev_attr_ctxid_mask
.attr
,
1635 &dev_attr_sync_freq
.attr
,
1636 &dev_attr_timestamp_event
.attr
,
1637 &dev_attr_status
.attr
,
1638 &dev_attr_traceid
.attr
,
1641 ATTRIBUTE_GROUPS(coresight_etm
);
1643 static int etm_cpu_callback(struct notifier_block
*nfb
, unsigned long action
,
1646 unsigned int cpu
= (unsigned long)hcpu
;
1648 if (!etmdrvdata
[cpu
])
1651 switch (action
& (~CPU_TASKS_FROZEN
)) {
1653 spin_lock(&etmdrvdata
[cpu
]->spinlock
);
1654 if (!etmdrvdata
[cpu
]->os_unlock
) {
1655 etm_os_unlock(etmdrvdata
[cpu
]);
1656 etmdrvdata
[cpu
]->os_unlock
= true;
1659 if (etmdrvdata
[cpu
]->enable
)
1660 etm_enable_hw(etmdrvdata
[cpu
]);
1661 spin_unlock(&etmdrvdata
[cpu
]->spinlock
);
1665 if (etmdrvdata
[cpu
]->boot_enable
&&
1666 !etmdrvdata
[cpu
]->sticky_enable
)
1667 coresight_enable(etmdrvdata
[cpu
]->csdev
);
1671 spin_lock(&etmdrvdata
[cpu
]->spinlock
);
1672 if (etmdrvdata
[cpu
]->enable
)
1673 etm_disable_hw(etmdrvdata
[cpu
]);
1674 spin_unlock(&etmdrvdata
[cpu
]->spinlock
);
1681 static struct notifier_block etm_cpu_notifier
= {
1682 .notifier_call
= etm_cpu_callback
,
1685 static bool etm_arch_supported(u8 arch
)
1702 static void etm_init_arch_data(void *info
)
1706 struct etm_drvdata
*drvdata
= info
;
1708 CS_UNLOCK(drvdata
->base
);
1710 /* First dummy read */
1711 (void)etm_readl(drvdata
, ETMPDSR
);
1712 /* Provide power to ETM: ETMPDCR[3] == 1 */
1713 etm_set_pwrup(drvdata
);
1715 * Clear power down bit since when this bit is set writes to
1716 * certain registers might be ignored.
1718 etm_clr_pwrdwn(drvdata
);
1720 * Set prog bit. It will be set from reset but this is included to
1723 etm_set_prog(drvdata
);
1725 /* Find all capabilities */
1726 etmidr
= etm_readl(drvdata
, ETMIDR
);
1727 drvdata
->arch
= BMVAL(etmidr
, 4, 11);
1728 drvdata
->port_size
= etm_readl(drvdata
, ETMCR
) & PORT_SIZE_MASK
;
1730 drvdata
->etmccer
= etm_readl(drvdata
, ETMCCER
);
1731 etmccr
= etm_readl(drvdata
, ETMCCR
);
1732 drvdata
->etmccr
= etmccr
;
1733 drvdata
->nr_addr_cmp
= BMVAL(etmccr
, 0, 3) * 2;
1734 drvdata
->nr_cntr
= BMVAL(etmccr
, 13, 15);
1735 drvdata
->nr_ext_inp
= BMVAL(etmccr
, 17, 19);
1736 drvdata
->nr_ext_out
= BMVAL(etmccr
, 20, 22);
1737 drvdata
->nr_ctxid_cmp
= BMVAL(etmccr
, 24, 25);
1739 etm_set_pwrdwn(drvdata
);
1740 etm_clr_pwrup(drvdata
);
1741 CS_LOCK(drvdata
->base
);
1744 static void etm_init_default_data(struct etm_drvdata
*drvdata
)
1746 static int etm3x_traceid
;
1748 u32 flags
= (1 << 0 | /* instruction execute*/
1749 3 << 3 | /* ARM instruction */
1750 0 << 5 | /* No data value comparison */
1751 0 << 7 | /* No exact mach */
1752 0 << 8 | /* Ignore context ID */
1753 0 << 10); /* Security ignored */
1756 * Initial configuration only - guarantees sources handled by
1757 * this driver have a unique ID at startup time but not between
1758 * all other types of sources. For that we lean on the core
1761 drvdata
->traceid
= etm3x_traceid
++;
1762 drvdata
->ctrl
= (ETMCR_CYC_ACC
| ETMCR_TIMESTAMP_EN
);
1763 drvdata
->enable_ctrl1
= ETMTECR1_ADDR_COMP_1
;
1764 if (drvdata
->nr_addr_cmp
>= 2) {
1765 drvdata
->addr_val
[0] = (u32
) _stext
;
1766 drvdata
->addr_val
[1] = (u32
) _etext
;
1767 drvdata
->addr_acctype
[0] = flags
;
1768 drvdata
->addr_acctype
[1] = flags
;
1769 drvdata
->addr_type
[0] = ETM_ADDR_TYPE_RANGE
;
1770 drvdata
->addr_type
[1] = ETM_ADDR_TYPE_RANGE
;
1773 etm_set_default(drvdata
);
1776 static int etm_probe(struct amba_device
*adev
, const struct amba_id
*id
)
1780 struct device
*dev
= &adev
->dev
;
1781 struct coresight_platform_data
*pdata
= NULL
;
1782 struct etm_drvdata
*drvdata
;
1783 struct resource
*res
= &adev
->res
;
1784 struct coresight_desc
*desc
;
1785 struct device_node
*np
= adev
->dev
.of_node
;
1787 desc
= devm_kzalloc(dev
, sizeof(*desc
), GFP_KERNEL
);
1791 drvdata
= devm_kzalloc(dev
, sizeof(*drvdata
), GFP_KERNEL
);
1796 pdata
= of_get_coresight_platform_data(dev
, np
);
1798 return PTR_ERR(pdata
);
1800 adev
->dev
.platform_data
= pdata
;
1801 drvdata
->use_cp14
= of_property_read_bool(np
, "arm,cp14");
1804 drvdata
->dev
= &adev
->dev
;
1805 dev_set_drvdata(dev
, drvdata
);
1807 /* Validity for the resource is already checked by the AMBA core */
1808 base
= devm_ioremap_resource(dev
, res
);
1810 return PTR_ERR(base
);
1812 drvdata
->base
= base
;
1814 spin_lock_init(&drvdata
->spinlock
);
1816 drvdata
->clk
= adev
->pclk
;
1817 ret
= clk_prepare_enable(drvdata
->clk
);
1821 drvdata
->cpu
= pdata
? pdata
->cpu
: 0;
1824 etmdrvdata
[drvdata
->cpu
] = drvdata
;
1826 if (!smp_call_function_single(drvdata
->cpu
, etm_os_unlock
, drvdata
, 1))
1827 drvdata
->os_unlock
= true;
1829 if (smp_call_function_single(drvdata
->cpu
,
1830 etm_init_arch_data
, drvdata
, 1))
1831 dev_err(dev
, "ETM arch init failed\n");
1834 register_hotcpu_notifier(&etm_cpu_notifier
);
1838 if (etm_arch_supported(drvdata
->arch
) == false) {
1840 goto err_arch_supported
;
1842 etm_init_default_data(drvdata
);
1844 clk_disable_unprepare(drvdata
->clk
);
1846 desc
->type
= CORESIGHT_DEV_TYPE_SOURCE
;
1847 desc
->subtype
.source_subtype
= CORESIGHT_DEV_SUBTYPE_SOURCE_PROC
;
1848 desc
->ops
= &etm_cs_ops
;
1849 desc
->pdata
= pdata
;
1851 desc
->groups
= coresight_etm_groups
;
1852 drvdata
->csdev
= coresight_register(desc
);
1853 if (IS_ERR(drvdata
->csdev
)) {
1854 ret
= PTR_ERR(drvdata
->csdev
);
1855 goto err_arch_supported
;
1858 dev_info(dev
, "ETM initialized\n");
1861 coresight_enable(drvdata
->csdev
);
1862 drvdata
->boot_enable
= true;
1868 clk_disable_unprepare(drvdata
->clk
);
1869 if (--etm_count
== 0)
1870 unregister_hotcpu_notifier(&etm_cpu_notifier
);
1874 static int etm_remove(struct amba_device
*adev
)
1876 struct etm_drvdata
*drvdata
= amba_get_drvdata(adev
);
1878 coresight_unregister(drvdata
->csdev
);
1879 if (--etm_count
== 0)
1880 unregister_hotcpu_notifier(&etm_cpu_notifier
);
1885 static struct amba_id etm_ids
[] = {
1905 static struct amba_driver etm_driver
= {
1907 .name
= "coresight-etm3x",
1908 .owner
= THIS_MODULE
,
1911 .remove
= etm_remove
,
1912 .id_table
= etm_ids
,
1915 int __init
etm_init(void)
1917 return amba_driver_register(&etm_driver
);
1919 module_init(etm_init
);
1921 void __exit
etm_exit(void)
1923 amba_driver_unregister(&etm_driver
);
1925 module_exit(etm_exit
);
1927 MODULE_LICENSE("GPL v2");
1928 MODULE_DESCRIPTION("CoreSight Program Flow Trace driver");