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dm snapshot: rework writing to origin
[linux-2.6/btrfs-unstable.git] / arch / arm / mach-mx2 / devices.c
blob3d398ce09b310d15cccb907abe01d35c81282dc6
1 /*
2 * Author: MontaVista Software, Inc.
3 * <source@mvista.com>
4 *
5 * Based on the OMAP devices.c
6 *
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
13 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version 2
18 * of the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
27 * MA 02110-1301, USA.
28 */
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/init.h>
32 #include <linux/platform_device.h>
33 #include <linux/gpio.h>
34
35 #include <mach/irqs.h>
36 #include <mach/hardware.h>
37 #include <mach/common.h>
38 #include <mach/mmc.h>
39
40 #include "devices.h"
41
42 /*
43 * SPI master controller
44 *
45 * - i.MX1: 2 channel (slighly different register setting)
46 * - i.MX21: 2 channel
47 * - i.MX27: 3 channel
48 */
49 static struct resource mxc_spi_resources0[] = {
50 {
51 .start = CSPI1_BASE_ADDR,
52 .end = CSPI1_BASE_ADDR + SZ_4K - 1,
53 .flags = IORESOURCE_MEM,
54 }, {
55 .start = MXC_INT_CSPI1,
56 .end = MXC_INT_CSPI1,
57 .flags = IORESOURCE_IRQ,
58 },
59 };
60
61 static struct resource mxc_spi_resources1[] = {
62 {
63 .start = CSPI2_BASE_ADDR,
64 .end = CSPI2_BASE_ADDR + SZ_4K - 1,
65 .flags = IORESOURCE_MEM,
66 }, {
67 .start = MXC_INT_CSPI2,
68 .end = MXC_INT_CSPI2,
69 .flags = IORESOURCE_IRQ,
70 },
71 };
72
73 #ifdef CONFIG_MACH_MX27
74 static struct resource mxc_spi_resources2[] = {
75 {
76 .start = CSPI3_BASE_ADDR,
77 .end = CSPI3_BASE_ADDR + SZ_4K - 1,
78 .flags = IORESOURCE_MEM,
79 }, {
80 .start = MXC_INT_CSPI3,
81 .end = MXC_INT_CSPI3,
82 .flags = IORESOURCE_IRQ,
83 },
84 };
85 #endif
86
87 struct platform_device mxc_spi_device0 = {
88 .name = "spi_imx",
89 .id = 0,
90 .num_resources = ARRAY_SIZE(mxc_spi_resources0),
91 .resource = mxc_spi_resources0,
92 };
93
94 struct platform_device mxc_spi_device1 = {
95 .name = "spi_imx",
96 .id = 1,
97 .num_resources = ARRAY_SIZE(mxc_spi_resources1),
98 .resource = mxc_spi_resources1,
99 };
100
101 #ifdef CONFIG_MACH_MX27
102 struct platform_device mxc_spi_device2 = {
103 .name = "spi_imx",
104 .id = 2,
105 .num_resources = ARRAY_SIZE(mxc_spi_resources2),
106 .resource = mxc_spi_resources2,
107 };
108 #endif
109
110 /*
111 * General Purpose Timer
112 * - i.MX21: 3 timers
113 * - i.MX27: 6 timers
114 */
115
116 /* We use gpt0 as system timer, so do not add a device for this one */
117
118 static struct resource timer1_resources[] = {
119 {
120 .start = GPT2_BASE_ADDR,
121 .end = GPT2_BASE_ADDR + 0x17,
122 .flags = IORESOURCE_MEM,
123 }, {
124 .start = MXC_INT_GPT2,
125 .end = MXC_INT_GPT2,
126 .flags = IORESOURCE_IRQ,
127 }
128 };
129
130 struct platform_device mxc_gpt1 = {
131 .name = "imx_gpt",
132 .id = 1,
133 .num_resources = ARRAY_SIZE(timer1_resources),
134 .resource = timer1_resources,
135 };
136
137 static struct resource timer2_resources[] = {
138 {
139 .start = GPT3_BASE_ADDR,
140 .end = GPT3_BASE_ADDR + 0x17,
141 .flags = IORESOURCE_MEM,
142 }, {
143 .start = MXC_INT_GPT3,
144 .end = MXC_INT_GPT3,
145 .flags = IORESOURCE_IRQ,
146 }
147 };
148
149 struct platform_device mxc_gpt2 = {
150 .name = "imx_gpt",
151 .id = 2,
152 .num_resources = ARRAY_SIZE(timer2_resources),
153 .resource = timer2_resources,
154 };
155
156 #ifdef CONFIG_MACH_MX27
157 static struct resource timer3_resources[] = {
158 {
159 .start = GPT4_BASE_ADDR,
160 .end = GPT4_BASE_ADDR + 0x17,
161 .flags = IORESOURCE_MEM,
162 }, {
163 .start = MXC_INT_GPT4,
164 .end = MXC_INT_GPT4,
165 .flags = IORESOURCE_IRQ,
166 }
167 };
168
169 struct platform_device mxc_gpt3 = {
170 .name = "imx_gpt",
171 .id = 3,
172 .num_resources = ARRAY_SIZE(timer3_resources),
173 .resource = timer3_resources,
174 };
175
176 static struct resource timer4_resources[] = {
177 {
178 .start = GPT5_BASE_ADDR,
179 .end = GPT5_BASE_ADDR + 0x17,
180 .flags = IORESOURCE_MEM,
181 }, {
182 .start = MXC_INT_GPT5,
183 .end = MXC_INT_GPT5,
184 .flags = IORESOURCE_IRQ,
185 }
186 };
187
188 struct platform_device mxc_gpt4 = {
189 .name = "imx_gpt",
190 .id = 4,
191 .num_resources = ARRAY_SIZE(timer4_resources),
192 .resource = timer4_resources,
193 };
194
195 static struct resource timer5_resources[] = {
196 {
197 .start = GPT6_BASE_ADDR,
198 .end = GPT6_BASE_ADDR + 0x17,
199 .flags = IORESOURCE_MEM,
200 }, {
201 .start = MXC_INT_GPT6,
202 .end = MXC_INT_GPT6,
203 .flags = IORESOURCE_IRQ,
204 }
205 };
206
207 struct platform_device mxc_gpt5 = {
208 .name = "imx_gpt",
209 .id = 5,
210 .num_resources = ARRAY_SIZE(timer5_resources),
211 .resource = timer5_resources,
212 };
213 #endif
214
215 /*
216 * Watchdog:
217 * - i.MX1
218 * - i.MX21
219 * - i.MX27
220 */
221 static struct resource mxc_wdt_resources[] = {
222 {
223 .start = WDOG_BASE_ADDR,
224 .end = WDOG_BASE_ADDR + 0x30,
225 .flags = IORESOURCE_MEM,
226 },
227 };
228
229 struct platform_device mxc_wdt = {
230 .name = "mxc_wdt",
231 .id = 0,
232 .num_resources = ARRAY_SIZE(mxc_wdt_resources),
233 .resource = mxc_wdt_resources,
234 };
235
236 static struct resource mxc_w1_master_resources[] = {
237 {
238 .start = OWIRE_BASE_ADDR,
239 .end = OWIRE_BASE_ADDR + SZ_4K - 1,
240 .flags = IORESOURCE_MEM,
241 },
242 };
243
244 struct platform_device mxc_w1_master_device = {
245 .name = "mxc_w1",
246 .id = 0,
247 .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
248 .resource = mxc_w1_master_resources,
249 };
250
251 static struct resource mxc_nand_resources[] = {
252 {
253 .start = NFC_BASE_ADDR,
254 .end = NFC_BASE_ADDR + 0xfff,
255 .flags = IORESOURCE_MEM,
256 }, {
257 .start = MXC_INT_NANDFC,
258 .end = MXC_INT_NANDFC,
259 .flags = IORESOURCE_IRQ,
260 },
261 };
262
263 struct platform_device mxc_nand_device = {
264 .name = "mxc_nand",
265 .id = 0,
266 .num_resources = ARRAY_SIZE(mxc_nand_resources),
267 .resource = mxc_nand_resources,
268 };
269
270 /*
271 * lcdc:
272 * - i.MX1: the basic controller
273 * - i.MX21: to be checked
274 * - i.MX27: like i.MX1, with slightly variations
275 */
276 static struct resource mxc_fb[] = {
277 {
278 .start = LCDC_BASE_ADDR,
279 .end = LCDC_BASE_ADDR + 0xFFF,
280 .flags = IORESOURCE_MEM,
281 }, {
282 .start = MXC_INT_LCDC,
283 .end = MXC_INT_LCDC,
284 .flags = IORESOURCE_IRQ,
285 }
286 };
287
288 /* mxc lcd driver */
289 struct platform_device mxc_fb_device = {
290 .name = "imx-fb",
291 .id = 0,
292 .num_resources = ARRAY_SIZE(mxc_fb),
293 .resource = mxc_fb,
294 .dev = {
295 .coherent_dma_mask = 0xFFFFFFFF,
296 },
297 };
298
299 #ifdef CONFIG_MACH_MX27
300 static struct resource mxc_fec_resources[] = {
301 {
302 .start = FEC_BASE_ADDR,
303 .end = FEC_BASE_ADDR + 0xfff,
304 .flags = IORESOURCE_MEM,
305 }, {
306 .start = MXC_INT_FEC,
307 .end = MXC_INT_FEC,
308 .flags = IORESOURCE_IRQ,
309 },
310 };
311
312 struct platform_device mxc_fec_device = {
313 .name = "fec",
314 .id = 0,
315 .num_resources = ARRAY_SIZE(mxc_fec_resources),
316 .resource = mxc_fec_resources,
317 };
318 #endif
319
320 static struct resource mxc_i2c_1_resources[] = {
321 {
322 .start = I2C_BASE_ADDR,
323 .end = I2C_BASE_ADDR + 0x0fff,
324 .flags = IORESOURCE_MEM,
325 }, {
326 .start = MXC_INT_I2C,
327 .end = MXC_INT_I2C,
328 .flags = IORESOURCE_IRQ,
329 }
330 };
331
332 struct platform_device mxc_i2c_device0 = {
333 .name = "imx-i2c",
334 .id = 0,
335 .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
336 .resource = mxc_i2c_1_resources,
337 };
338
339 #ifdef CONFIG_MACH_MX27
340 static struct resource mxc_i2c_2_resources[] = {
341 {
342 .start = I2C2_BASE_ADDR,
343 .end = I2C2_BASE_ADDR + 0x0fff,
344 .flags = IORESOURCE_MEM,
345 }, {
346 .start = MXC_INT_I2C2,
347 .end = MXC_INT_I2C2,
348 .flags = IORESOURCE_IRQ,
349 }
350 };
351
352 struct platform_device mxc_i2c_device1 = {
353 .name = "imx-i2c",
354 .id = 1,
355 .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
356 .resource = mxc_i2c_2_resources,
357 };
358 #endif
359
360 static struct resource mxc_pwm_resources[] = {
361 {
362 .start = PWM_BASE_ADDR,
363 .end = PWM_BASE_ADDR + 0x0fff,
364 .flags = IORESOURCE_MEM,
365 }, {
366 .start = MXC_INT_PWM,
367 .end = MXC_INT_PWM,
368 .flags = IORESOURCE_IRQ,
369 }
370 };
371
372 struct platform_device mxc_pwm_device = {
373 .name = "mxc_pwm",
374 .id = 0,
375 .num_resources = ARRAY_SIZE(mxc_pwm_resources),
376 .resource = mxc_pwm_resources,
377 };
378
379 /*
380 * Resource definition for the MXC SDHC
381 */
382 static struct resource mxc_sdhc1_resources[] = {
383 {
384 .start = SDHC1_BASE_ADDR,
385 .end = SDHC1_BASE_ADDR + SZ_4K - 1,
386 .flags = IORESOURCE_MEM,
387 }, {
388 .start = MXC_INT_SDHC1,
389 .end = MXC_INT_SDHC1,
390 .flags = IORESOURCE_IRQ,
391 }, {
392 .start = DMA_REQ_SDHC1,
393 .end = DMA_REQ_SDHC1,
394 .flags = IORESOURCE_DMA,
395 },
396 };
397
398 static u64 mxc_sdhc1_dmamask = 0xffffffffUL;
399
400 struct platform_device mxc_sdhc_device0 = {
401 .name = "mxc-mmc",
402 .id = 0,
403 .dev = {
404 .dma_mask = &mxc_sdhc1_dmamask,
405 .coherent_dma_mask = 0xffffffff,
406 },
407 .num_resources = ARRAY_SIZE(mxc_sdhc1_resources),
408 .resource = mxc_sdhc1_resources,
409 };
410
411 static struct resource mxc_sdhc2_resources[] = {
412 {
413 .start = SDHC2_BASE_ADDR,
414 .end = SDHC2_BASE_ADDR + SZ_4K - 1,
415 .flags = IORESOURCE_MEM,
416 }, {
417 .start = MXC_INT_SDHC2,
418 .end = MXC_INT_SDHC2,
419 .flags = IORESOURCE_IRQ,
420 }, {
421 .start = DMA_REQ_SDHC2,
422 .end = DMA_REQ_SDHC2,
423 .flags = IORESOURCE_DMA,
424 },
425 };
426
427 static u64 mxc_sdhc2_dmamask = 0xffffffffUL;
428
429 struct platform_device mxc_sdhc_device1 = {
430 .name = "mxc-mmc",
431 .id = 1,
432 .dev = {
433 .dma_mask = &mxc_sdhc2_dmamask,
434 .coherent_dma_mask = 0xffffffff,
435 },
436 .num_resources = ARRAY_SIZE(mxc_sdhc2_resources),
437 .resource = mxc_sdhc2_resources,
438 };
439
440 #ifdef CONFIG_MACH_MX27
441 static struct resource otg_resources[] = {
442 {
443 .start = OTG_BASE_ADDR,
444 .end = OTG_BASE_ADDR + 0x1ff,
445 .flags = IORESOURCE_MEM,
446 }, {
447 .start = MXC_INT_USB3,
448 .end = MXC_INT_USB3,
449 .flags = IORESOURCE_IRQ,
450 },
451 };
452
453 static u64 otg_dmamask = 0xffffffffUL;
454
455 /* OTG gadget device */
456 struct platform_device mxc_otg_udc_device = {
457 .name = "fsl-usb2-udc",
458 .id = -1,
459 .dev = {
460 .dma_mask = &otg_dmamask,
461 .coherent_dma_mask = 0xffffffffUL,
462 },
463 .resource = otg_resources,
464 .num_resources = ARRAY_SIZE(otg_resources),
465 };
466
467 /* OTG host */
468 struct platform_device mxc_otg_host = {
469 .name = "mxc-ehci",
470 .id = 0,
471 .dev = {
472 .coherent_dma_mask = 0xffffffff,
473 .dma_mask = &otg_dmamask,
474 },
475 .resource = otg_resources,
476 .num_resources = ARRAY_SIZE(otg_resources),
477 };
478
479 /* USB host 1 */
480
481 static u64 usbh1_dmamask = 0xffffffffUL;
482
483 static struct resource mxc_usbh1_resources[] = {
484 {
485 .start = OTG_BASE_ADDR + 0x200,
486 .end = OTG_BASE_ADDR + 0x3ff,
487 .flags = IORESOURCE_MEM,
488 }, {
489 .start = MXC_INT_USB1,
490 .end = MXC_INT_USB1,
491 .flags = IORESOURCE_IRQ,
492 },
493 };
494
495 struct platform_device mxc_usbh1 = {
496 .name = "mxc-ehci",
497 .id = 1,
498 .dev = {
499 .coherent_dma_mask = 0xffffffff,
500 .dma_mask = &usbh1_dmamask,
501 },
502 .resource = mxc_usbh1_resources,
503 .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
504 };
505
506 /* USB host 2 */
507 static u64 usbh2_dmamask = 0xffffffffUL;
508
509 static struct resource mxc_usbh2_resources[] = {
510 {
511 .start = OTG_BASE_ADDR + 0x400,
512 .end = OTG_BASE_ADDR + 0x5ff,
513 .flags = IORESOURCE_MEM,
514 }, {
515 .start = MXC_INT_USB2,
516 .end = MXC_INT_USB2,
517 .flags = IORESOURCE_IRQ,
518 },
519 };
520
521 struct platform_device mxc_usbh2 = {
522 .name = "mxc-ehci",
523 .id = 2,
524 .dev = {
525 .coherent_dma_mask = 0xffffffff,
526 .dma_mask = &usbh2_dmamask,
527 },
528 .resource = mxc_usbh2_resources,
529 .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
530 };
531 #endif
532
533 static struct resource imx_ssi_resources0[] = {
534 {
535 .start = SSI1_BASE_ADDR,
536 .end = SSI1_BASE_ADDR + 0x6F,
537 .flags = IORESOURCE_MEM,
538 }, {
539 .start = MXC_INT_SSI1,
540 .end = MXC_INT_SSI1,
541 .flags = IORESOURCE_IRQ,
542 }, {
543 .name = "tx0",
544 .start = DMA_REQ_SSI1_TX0,
545 .end = DMA_REQ_SSI1_TX0,
546 .flags = IORESOURCE_DMA,
547 }, {
548 .name = "rx0",
549 .start = DMA_REQ_SSI1_RX0,
550 .end = DMA_REQ_SSI1_RX0,
551 .flags = IORESOURCE_DMA,
552 }, {
553 .name = "tx1",
554 .start = DMA_REQ_SSI1_TX1,
555 .end = DMA_REQ_SSI1_TX1,
556 .flags = IORESOURCE_DMA,
557 }, {
558 .name = "rx1",
559 .start = DMA_REQ_SSI1_RX1,
560 .end = DMA_REQ_SSI1_RX1,
561 .flags = IORESOURCE_DMA,
562 },
563 };
564
565 static struct resource imx_ssi_resources1[] = {
566 {
567 .start = SSI2_BASE_ADDR,
568 .end = SSI2_BASE_ADDR + 0x6F,
569 .flags = IORESOURCE_MEM,
570 }, {
571 .start = MXC_INT_SSI2,
572 .end = MXC_INT_SSI2,
573 .flags = IORESOURCE_IRQ,
574 }, {
575 .name = "tx0",
576 .start = DMA_REQ_SSI2_TX0,
577 .end = DMA_REQ_SSI2_TX0,
578 .flags = IORESOURCE_DMA,
579 }, {
580 .name = "rx0",
581 .start = DMA_REQ_SSI2_RX0,
582 .end = DMA_REQ_SSI2_RX0,
583 .flags = IORESOURCE_DMA,
584 }, {
585 .name = "tx1",
586 .start = DMA_REQ_SSI2_TX1,
587 .end = DMA_REQ_SSI2_TX1,
588 .flags = IORESOURCE_DMA,
589 }, {
590 .name = "rx1",
591 .start = DMA_REQ_SSI2_RX1,
592 .end = DMA_REQ_SSI2_RX1,
593 .flags = IORESOURCE_DMA,
594 },
595 };
596
597 struct platform_device imx_ssi_device0 = {
598 .name = "imx-ssi",
599 .id = 0,
600 .num_resources = ARRAY_SIZE(imx_ssi_resources0),
601 .resource = imx_ssi_resources0,
602 };
603
604 struct platform_device imx_ssi_device1 = {
605 .name = "imx-ssi",
606 .id = 1,
607 .num_resources = ARRAY_SIZE(imx_ssi_resources1),
608 .resource = imx_ssi_resources1,
609 };
610
611 /* GPIO port description */
612 static struct mxc_gpio_port imx_gpio_ports[] = {
613 {
614 .chip.label = "gpio-0",
615 .irq = MXC_INT_GPIO,
616 .base = IO_ADDRESS(GPIO_BASE_ADDR),
617 .virtual_irq_start = MXC_GPIO_IRQ_START,
618 }, {
619 .chip.label = "gpio-1",
620 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
621 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
622 }, {
623 .chip.label = "gpio-2",
624 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
625 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
626 }, {
627 .chip.label = "gpio-3",
628 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
629 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
630 }, {
631 .chip.label = "gpio-4",
632 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
633 .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
634 }, {
635 .chip.label = "gpio-5",
636 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
637 .virtual_irq_start = MXC_GPIO_IRQ_START + 160,
638 }
639 };
640
641 int __init mxc_register_gpios(void)
642 {
643 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
644 }
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