2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #include <linux/kernel.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/platform_device.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/interrupt.h>
46 #include <linux/list.h>
47 #include <linux/dma-mapping.h>
49 #include <linux/usb/ch9.h>
50 #include <linux/usb/gadget.h>
51 #include <linux/usb/composite.h>
57 static void __dwc3_ep0_do_control_status(struct dwc3
*dwc
, struct dwc3_ep
*dep
);
58 static void __dwc3_ep0_do_control_data(struct dwc3
*dwc
,
59 struct dwc3_ep
*dep
, struct dwc3_request
*req
);
61 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state
)
70 case EP0_STATUS_PHASE
:
71 return "Status Phase";
77 static int dwc3_ep0_start_trans(struct dwc3
*dwc
, u8 epnum
, dma_addr_t buf_dma
,
80 struct dwc3_gadget_ep_cmd_params params
;
86 dep
= dwc
->eps
[epnum
];
87 if (dep
->flags
& DWC3_EP_BUSY
) {
88 dev_vdbg(dwc
->dev
, "%s: still busy\n", dep
->name
);
94 trb
->bpl
= lower_32_bits(buf_dma
);
95 trb
->bph
= upper_32_bits(buf_dma
);
99 trb
->ctrl
|= (DWC3_TRB_CTRL_HWO
102 | DWC3_TRB_CTRL_ISP_IMI
);
104 memset(¶ms
, 0, sizeof(params
));
105 params
.param0
= upper_32_bits(dwc
->ep0_trb_addr
);
106 params
.param1
= lower_32_bits(dwc
->ep0_trb_addr
);
108 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
109 DWC3_DEPCMD_STARTTRANSFER
, ¶ms
);
111 dev_dbg(dwc
->dev
, "failed to send STARTTRANSFER command\n");
115 dep
->flags
|= DWC3_EP_BUSY
;
116 dep
->resource_index
= dwc3_gadget_ep_get_transfer_index(dwc
,
119 dwc
->ep0_next_event
= DWC3_EP0_COMPLETE
;
124 static int __dwc3_gadget_ep0_queue(struct dwc3_ep
*dep
,
125 struct dwc3_request
*req
)
127 struct dwc3
*dwc
= dep
->dwc
;
130 req
->request
.actual
= 0;
131 req
->request
.status
= -EINPROGRESS
;
132 req
->epnum
= dep
->number
;
134 list_add_tail(&req
->list
, &dep
->request_list
);
137 * Gadget driver might not be quick enough to queue a request
138 * before we get a Transfer Not Ready event on this endpoint.
140 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
141 * flag is set, it's telling us that as soon as Gadget queues the
142 * required request, we should kick the transfer here because the
143 * IRQ we were waiting for is long gone.
145 if (dep
->flags
& DWC3_EP_PENDING_REQUEST
) {
148 direction
= !!(dep
->flags
& DWC3_EP0_DIR_IN
);
150 if (dwc
->ep0state
!= EP0_DATA_PHASE
) {
151 dev_WARN(dwc
->dev
, "Unexpected pending request\n");
155 __dwc3_ep0_do_control_data(dwc
, dwc
->eps
[direction
], req
);
157 dep
->flags
&= ~(DWC3_EP_PENDING_REQUEST
|
159 } else if (dwc
->delayed_status
) {
160 dwc
->delayed_status
= false;
162 if (dwc
->ep0state
== EP0_STATUS_PHASE
)
163 __dwc3_ep0_do_control_status(dwc
, dwc
->eps
[1]);
165 dev_dbg(dwc
->dev
, "too early for delayed status\n");
171 int dwc3_gadget_ep0_queue(struct usb_ep
*ep
, struct usb_request
*request
,
174 struct dwc3_request
*req
= to_dwc3_request(request
);
175 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
176 struct dwc3
*dwc
= dep
->dwc
;
182 spin_lock_irqsave(&dwc
->lock
, flags
);
183 if (!dep
->endpoint
.desc
) {
184 dev_dbg(dwc
->dev
, "trying to queue request %p to disabled %s\n",
190 /* we share one TRB for ep0/1 */
191 if (!list_empty(&dep
->request_list
)) {
196 dev_vdbg(dwc
->dev
, "queueing request %p to %s length %d, state '%s'\n",
197 request
, dep
->name
, request
->length
,
198 dwc3_ep0_state_string(dwc
->ep0state
));
200 ret
= __dwc3_gadget_ep0_queue(dep
, req
);
203 spin_unlock_irqrestore(&dwc
->lock
, flags
);
208 static void dwc3_ep0_stall_and_restart(struct dwc3
*dwc
)
210 struct dwc3_ep
*dep
= dwc
->eps
[0];
212 /* stall is always issued on EP0 */
213 __dwc3_gadget_ep_set_halt(dep
, 1);
214 dep
->flags
= DWC3_EP_ENABLED
;
215 dwc
->delayed_status
= false;
217 if (!list_empty(&dep
->request_list
)) {
218 struct dwc3_request
*req
;
220 req
= next_request(&dep
->request_list
);
221 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
224 dwc
->ep0state
= EP0_SETUP_PHASE
;
225 dwc3_ep0_out_start(dwc
);
228 int dwc3_gadget_ep0_set_halt(struct usb_ep
*ep
, int value
)
230 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
231 struct dwc3
*dwc
= dep
->dwc
;
233 dwc3_ep0_stall_and_restart(dwc
);
238 void dwc3_ep0_out_start(struct dwc3
*dwc
)
242 ret
= dwc3_ep0_start_trans(dwc
, 0, dwc
->ctrl_req_addr
, 8,
243 DWC3_TRBCTL_CONTROL_SETUP
);
247 static struct dwc3_ep
*dwc3_wIndex_to_dep(struct dwc3
*dwc
, __le16 wIndex_le
)
250 u32 windex
= le16_to_cpu(wIndex_le
);
253 epnum
= (windex
& USB_ENDPOINT_NUMBER_MASK
) << 1;
254 if ((windex
& USB_ENDPOINT_DIR_MASK
) == USB_DIR_IN
)
257 dep
= dwc
->eps
[epnum
];
258 if (dep
->flags
& DWC3_EP_ENABLED
)
264 static void dwc3_ep0_status_cmpl(struct usb_ep
*ep
, struct usb_request
*req
)
270 static int dwc3_ep0_handle_status(struct dwc3
*dwc
,
271 struct usb_ctrlrequest
*ctrl
)
277 __le16
*response_pkt
;
279 recip
= ctrl
->bRequestType
& USB_RECIP_MASK
;
281 case USB_RECIP_DEVICE
:
283 * LTM will be set once we know how to set this in HW.
285 usb_status
|= dwc
->is_selfpowered
<< USB_DEVICE_SELF_POWERED
;
287 if (dwc
->speed
== DWC3_DSTS_SUPERSPEED
) {
288 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
289 if (reg
& DWC3_DCTL_INITU1ENA
)
290 usb_status
|= 1 << USB_DEV_STAT_U1_ENABLED
;
291 if (reg
& DWC3_DCTL_INITU2ENA
)
292 usb_status
|= 1 << USB_DEV_STAT_U2_ENABLED
;
297 case USB_RECIP_INTERFACE
:
299 * Function Remote Wake Capable D0
300 * Function Remote Wakeup D1
304 case USB_RECIP_ENDPOINT
:
305 dep
= dwc3_wIndex_to_dep(dwc
, ctrl
->wIndex
);
309 if (dep
->flags
& DWC3_EP_STALL
)
310 usb_status
= 1 << USB_ENDPOINT_HALT
;
316 response_pkt
= (__le16
*) dwc
->setup_buf
;
317 *response_pkt
= cpu_to_le16(usb_status
);
320 dwc
->ep0_usb_req
.dep
= dep
;
321 dwc
->ep0_usb_req
.request
.length
= sizeof(*response_pkt
);
322 dwc
->ep0_usb_req
.request
.buf
= dwc
->setup_buf
;
323 dwc
->ep0_usb_req
.request
.complete
= dwc3_ep0_status_cmpl
;
325 return __dwc3_gadget_ep0_queue(dep
, &dwc
->ep0_usb_req
);
328 static int dwc3_ep0_handle_feature(struct dwc3
*dwc
,
329 struct usb_ctrlrequest
*ctrl
, int set
)
338 wValue
= le16_to_cpu(ctrl
->wValue
);
339 wIndex
= le16_to_cpu(ctrl
->wIndex
);
340 recip
= ctrl
->bRequestType
& USB_RECIP_MASK
;
342 case USB_RECIP_DEVICE
:
345 case USB_DEVICE_REMOTE_WAKEUP
:
348 * 9.4.1 says only only for SS, in AddressState only for
349 * default control pipe
351 case USB_DEVICE_U1_ENABLE
:
352 if (dwc
->dev_state
!= DWC3_CONFIGURED_STATE
)
354 if (dwc
->speed
!= DWC3_DSTS_SUPERSPEED
)
357 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
359 reg
|= DWC3_DCTL_INITU1ENA
;
361 reg
&= ~DWC3_DCTL_INITU1ENA
;
362 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
365 case USB_DEVICE_U2_ENABLE
:
366 if (dwc
->dev_state
!= DWC3_CONFIGURED_STATE
)
368 if (dwc
->speed
!= DWC3_DSTS_SUPERSPEED
)
371 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
373 reg
|= DWC3_DCTL_INITU2ENA
;
375 reg
&= ~DWC3_DCTL_INITU2ENA
;
376 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
379 case USB_DEVICE_LTM_ENABLE
:
383 case USB_DEVICE_TEST_MODE
:
384 if ((wIndex
& 0xff) != 0)
389 dwc
->test_mode_nr
= wIndex
>> 8;
390 dwc
->test_mode
= true;
397 case USB_RECIP_INTERFACE
:
399 case USB_INTRF_FUNC_SUSPEND
:
400 if (wIndex
& USB_INTRF_FUNC_SUSPEND_LP
)
401 /* XXX enable Low power suspend */
403 if (wIndex
& USB_INTRF_FUNC_SUSPEND_RW
)
404 /* XXX enable remote wakeup */
412 case USB_RECIP_ENDPOINT
:
414 case USB_ENDPOINT_HALT
:
415 dep
= dwc3_wIndex_to_dep(dwc
, wIndex
);
418 ret
= __dwc3_gadget_ep_set_halt(dep
, set
);
434 static int dwc3_ep0_set_address(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
439 addr
= le16_to_cpu(ctrl
->wValue
);
441 dev_dbg(dwc
->dev
, "invalid device address %d\n", addr
);
445 if (dwc
->dev_state
== DWC3_CONFIGURED_STATE
) {
446 dev_dbg(dwc
->dev
, "trying to set address when configured\n");
450 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
451 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
452 reg
|= DWC3_DCFG_DEVADDR(addr
);
453 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
456 dwc
->dev_state
= DWC3_ADDRESS_STATE
;
458 dwc
->dev_state
= DWC3_DEFAULT_STATE
;
463 static int dwc3_ep0_delegate_req(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
467 spin_unlock(&dwc
->lock
);
468 ret
= dwc
->gadget_driver
->setup(&dwc
->gadget
, ctrl
);
469 spin_lock(&dwc
->lock
);
473 static int dwc3_ep0_set_config(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
479 dwc
->start_config_issued
= false;
480 cfg
= le16_to_cpu(ctrl
->wValue
);
482 switch (dwc
->dev_state
) {
483 case DWC3_DEFAULT_STATE
:
487 case DWC3_ADDRESS_STATE
:
488 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
489 /* if the cfg matches and the cfg is non zero */
490 if (cfg
&& (!ret
|| (ret
== USB_GADGET_DELAYED_STATUS
))) {
491 dwc
->dev_state
= DWC3_CONFIGURED_STATE
;
493 * Enable transition to U1/U2 state when
494 * nothing is pending from application.
496 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
497 reg
|= (DWC3_DCTL_ACCEPTU1ENA
| DWC3_DCTL_ACCEPTU2ENA
);
498 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
500 dwc
->resize_fifos
= true;
501 dev_dbg(dwc
->dev
, "resize fifos flag SET\n");
505 case DWC3_CONFIGURED_STATE
:
506 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
508 dwc
->dev_state
= DWC3_ADDRESS_STATE
;
516 static void dwc3_ep0_set_sel_cmpl(struct usb_ep
*ep
, struct usb_request
*req
)
518 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
519 struct dwc3
*dwc
= dep
->dwc
;
533 memcpy(&timing
, req
->buf
, sizeof(timing
));
535 dwc
->u1sel
= timing
.u1sel
;
536 dwc
->u1pel
= timing
.u1pel
;
537 dwc
->u2sel
= le16_to_cpu(timing
.u2sel
);
538 dwc
->u2pel
= le16_to_cpu(timing
.u2pel
);
540 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
541 if (reg
& DWC3_DCTL_INITU2ENA
)
543 if (reg
& DWC3_DCTL_INITU1ENA
)
547 * According to Synopsys Databook, if parameter is
548 * greater than 125, a value of zero should be
549 * programmed in the register.
554 /* now that we have the time, issue DGCMD Set Sel */
555 ret
= dwc3_send_gadget_generic_command(dwc
,
556 DWC3_DGCMD_SET_PERIODIC_PAR
, param
);
560 static int dwc3_ep0_set_sel(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
566 if (dwc
->dev_state
== DWC3_DEFAULT_STATE
)
569 wValue
= le16_to_cpu(ctrl
->wValue
);
570 wLength
= le16_to_cpu(ctrl
->wLength
);
573 dev_err(dwc
->dev
, "Set SEL should be 6 bytes, got %d\n",
579 * To handle Set SEL we need to receive 6 bytes from Host. So let's
580 * queue a usb_request for 6 bytes.
582 * Remember, though, this controller can't handle non-wMaxPacketSize
583 * aligned transfers on the OUT direction, so we queue a request for
584 * wMaxPacketSize instead.
587 dwc
->ep0_usb_req
.dep
= dep
;
588 dwc
->ep0_usb_req
.request
.length
= dep
->endpoint
.maxpacket
;
589 dwc
->ep0_usb_req
.request
.buf
= dwc
->setup_buf
;
590 dwc
->ep0_usb_req
.request
.complete
= dwc3_ep0_set_sel_cmpl
;
592 return __dwc3_gadget_ep0_queue(dep
, &dwc
->ep0_usb_req
);
595 static int dwc3_ep0_set_isoch_delay(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
601 wValue
= le16_to_cpu(ctrl
->wValue
);
602 wLength
= le16_to_cpu(ctrl
->wLength
);
603 wIndex
= le16_to_cpu(ctrl
->wIndex
);
605 if (wIndex
|| wLength
)
609 * REVISIT It's unclear from Databook what to do with this
610 * value. For now, just cache it.
612 dwc
->isoch_delay
= wValue
;
617 static int dwc3_ep0_std_request(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
621 switch (ctrl
->bRequest
) {
622 case USB_REQ_GET_STATUS
:
623 dev_vdbg(dwc
->dev
, "USB_REQ_GET_STATUS\n");
624 ret
= dwc3_ep0_handle_status(dwc
, ctrl
);
626 case USB_REQ_CLEAR_FEATURE
:
627 dev_vdbg(dwc
->dev
, "USB_REQ_CLEAR_FEATURE\n");
628 ret
= dwc3_ep0_handle_feature(dwc
, ctrl
, 0);
630 case USB_REQ_SET_FEATURE
:
631 dev_vdbg(dwc
->dev
, "USB_REQ_SET_FEATURE\n");
632 ret
= dwc3_ep0_handle_feature(dwc
, ctrl
, 1);
634 case USB_REQ_SET_ADDRESS
:
635 dev_vdbg(dwc
->dev
, "USB_REQ_SET_ADDRESS\n");
636 ret
= dwc3_ep0_set_address(dwc
, ctrl
);
638 case USB_REQ_SET_CONFIGURATION
:
639 dev_vdbg(dwc
->dev
, "USB_REQ_SET_CONFIGURATION\n");
640 ret
= dwc3_ep0_set_config(dwc
, ctrl
);
642 case USB_REQ_SET_SEL
:
643 dev_vdbg(dwc
->dev
, "USB_REQ_SET_SEL\n");
644 ret
= dwc3_ep0_set_sel(dwc
, ctrl
);
646 case USB_REQ_SET_ISOCH_DELAY
:
647 dev_vdbg(dwc
->dev
, "USB_REQ_SET_ISOCH_DELAY\n");
648 ret
= dwc3_ep0_set_isoch_delay(dwc
, ctrl
);
651 dev_vdbg(dwc
->dev
, "Forwarding to gadget driver\n");
652 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
659 static void dwc3_ep0_inspect_setup(struct dwc3
*dwc
,
660 const struct dwc3_event_depevt
*event
)
662 struct usb_ctrlrequest
*ctrl
= dwc
->ctrl_req
;
666 if (!dwc
->gadget_driver
)
669 len
= le16_to_cpu(ctrl
->wLength
);
671 dwc
->three_stage_setup
= false;
672 dwc
->ep0_expect_in
= false;
673 dwc
->ep0_next_event
= DWC3_EP0_NRDY_STATUS
;
675 dwc
->three_stage_setup
= true;
676 dwc
->ep0_expect_in
= !!(ctrl
->bRequestType
& USB_DIR_IN
);
677 dwc
->ep0_next_event
= DWC3_EP0_NRDY_DATA
;
680 if ((ctrl
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
)
681 ret
= dwc3_ep0_std_request(dwc
, ctrl
);
683 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
685 if (ret
== USB_GADGET_DELAYED_STATUS
)
686 dwc
->delayed_status
= true;
690 dwc3_ep0_stall_and_restart(dwc
);
693 static void dwc3_ep0_complete_data(struct dwc3
*dwc
,
694 const struct dwc3_event_depevt
*event
)
696 struct dwc3_request
*r
= NULL
;
697 struct usb_request
*ur
;
698 struct dwc3_trb
*trb
;
704 epnum
= event
->endpoint_number
;
707 dwc
->ep0_next_event
= DWC3_EP0_NRDY_STATUS
;
709 r
= next_request(&ep0
->request_list
);
713 length
= trb
->size
& DWC3_TRB_SIZE_MASK
;
715 if (dwc
->ep0_bounced
) {
716 unsigned transfer_size
= ur
->length
;
717 unsigned maxp
= ep0
->endpoint
.maxpacket
;
719 transfer_size
+= (maxp
- (transfer_size
% maxp
));
720 transferred
= min_t(u32
, ur
->length
,
721 transfer_size
- length
);
722 memcpy(ur
->buf
, dwc
->ep0_bounce
, transferred
);
723 dwc
->ep0_bounced
= false;
725 transferred
= ur
->length
- length
;
728 ur
->actual
+= transferred
;
730 if ((epnum
& 1) && ur
->actual
< ur
->length
) {
731 /* for some reason we did not get everything out */
733 dwc3_ep0_stall_and_restart(dwc
);
736 * handle the case where we have to send a zero packet. This
737 * seems to be case when req.length > maxpacket. Could it be?
740 dwc3_gadget_giveback(ep0
, r
, 0);
744 static void dwc3_ep0_complete_status(struct dwc3
*dwc
,
745 const struct dwc3_event_depevt
*event
)
747 struct dwc3_request
*r
;
752 if (!list_empty(&dep
->request_list
)) {
753 r
= next_request(&dep
->request_list
);
755 dwc3_gadget_giveback(dep
, r
, 0);
758 if (dwc
->test_mode
) {
761 ret
= dwc3_gadget_set_test_mode(dwc
, dwc
->test_mode_nr
);
763 dev_dbg(dwc
->dev
, "Invalid Test #%d\n",
765 dwc3_ep0_stall_and_restart(dwc
);
770 dwc
->ep0state
= EP0_SETUP_PHASE
;
771 dwc3_ep0_out_start(dwc
);
774 static void dwc3_ep0_xfer_complete(struct dwc3
*dwc
,
775 const struct dwc3_event_depevt
*event
)
777 struct dwc3_ep
*dep
= dwc
->eps
[event
->endpoint_number
];
779 dep
->flags
&= ~DWC3_EP_BUSY
;
780 dep
->resource_index
= 0;
781 dwc
->setup_packet_pending
= false;
783 switch (dwc
->ep0state
) {
784 case EP0_SETUP_PHASE
:
785 dev_vdbg(dwc
->dev
, "Inspecting Setup Bytes\n");
786 dwc3_ep0_inspect_setup(dwc
, event
);
790 dev_vdbg(dwc
->dev
, "Data Phase\n");
791 dwc3_ep0_complete_data(dwc
, event
);
794 case EP0_STATUS_PHASE
:
795 dev_vdbg(dwc
->dev
, "Status Phase\n");
796 dwc3_ep0_complete_status(dwc
, event
);
799 WARN(true, "UNKNOWN ep0state %d\n", dwc
->ep0state
);
803 static void dwc3_ep0_do_control_setup(struct dwc3
*dwc
,
804 const struct dwc3_event_depevt
*event
)
806 dwc3_ep0_out_start(dwc
);
809 static void __dwc3_ep0_do_control_data(struct dwc3
*dwc
,
810 struct dwc3_ep
*dep
, struct dwc3_request
*req
)
814 req
->direction
= !!dep
->number
;
816 if (req
->request
.length
== 0) {
817 ret
= dwc3_ep0_start_trans(dwc
, dep
->number
,
818 dwc
->ctrl_req_addr
, 0,
819 DWC3_TRBCTL_CONTROL_DATA
);
820 } else if (!IS_ALIGNED(req
->request
.length
, dep
->endpoint
.maxpacket
)
821 && (dep
->number
== 0)) {
824 ret
= usb_gadget_map_request(&dwc
->gadget
, &req
->request
,
827 dev_dbg(dwc
->dev
, "failed to map request\n");
831 WARN_ON(req
->request
.length
> DWC3_EP0_BOUNCE_SIZE
);
833 transfer_size
= roundup(req
->request
.length
,
834 (u32
) dep
->endpoint
.maxpacket
);
836 dwc
->ep0_bounced
= true;
839 * REVISIT in case request length is bigger than
840 * DWC3_EP0_BOUNCE_SIZE we will need two chained
841 * TRBs to handle the transfer.
843 ret
= dwc3_ep0_start_trans(dwc
, dep
->number
,
844 dwc
->ep0_bounce_addr
, transfer_size
,
845 DWC3_TRBCTL_CONTROL_DATA
);
847 ret
= usb_gadget_map_request(&dwc
->gadget
, &req
->request
,
850 dev_dbg(dwc
->dev
, "failed to map request\n");
854 ret
= dwc3_ep0_start_trans(dwc
, dep
->number
, req
->request
.dma
,
855 req
->request
.length
, DWC3_TRBCTL_CONTROL_DATA
);
861 static void dwc3_ep0_do_control_data(struct dwc3
*dwc
,
862 const struct dwc3_event_depevt
*event
)
865 struct dwc3_request
*req
;
869 if (list_empty(&dep
->request_list
)) {
870 dev_vdbg(dwc
->dev
, "pending request for EP0 Data phase\n");
871 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
873 if (event
->endpoint_number
)
874 dep
->flags
|= DWC3_EP0_DIR_IN
;
878 req
= next_request(&dep
->request_list
);
879 dep
= dwc
->eps
[event
->endpoint_number
];
881 __dwc3_ep0_do_control_data(dwc
, dep
, req
);
884 static int dwc3_ep0_start_control_status(struct dwc3_ep
*dep
)
886 struct dwc3
*dwc
= dep
->dwc
;
889 type
= dwc
->three_stage_setup
? DWC3_TRBCTL_CONTROL_STATUS3
890 : DWC3_TRBCTL_CONTROL_STATUS2
;
892 return dwc3_ep0_start_trans(dwc
, dep
->number
,
893 dwc
->ctrl_req_addr
, 0, type
);
896 static void __dwc3_ep0_do_control_status(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
898 if (dwc
->resize_fifos
) {
899 dev_dbg(dwc
->dev
, "starting to resize fifos\n");
900 dwc3_gadget_resize_tx_fifos(dwc
);
901 dwc
->resize_fifos
= 0;
904 WARN_ON(dwc3_ep0_start_control_status(dep
));
907 static void dwc3_ep0_do_control_status(struct dwc3
*dwc
,
908 const struct dwc3_event_depevt
*event
)
910 struct dwc3_ep
*dep
= dwc
->eps
[event
->endpoint_number
];
912 __dwc3_ep0_do_control_status(dwc
, dep
);
915 static void dwc3_ep0_xfernotready(struct dwc3
*dwc
,
916 const struct dwc3_event_depevt
*event
)
918 dwc
->setup_packet_pending
= true;
921 * This part is very tricky: If we have just handled
922 * XferNotReady(Setup) and we're now expecting a
923 * XferComplete but, instead, we receive another
924 * XferNotReady(Setup), we should STALL and restart
927 * In all other cases, we just continue waiting
928 * for the XferComplete event.
930 * We are a little bit unsafe here because we're
931 * not trying to ensure that last event was, indeed,
932 * XferNotReady(Setup).
934 * Still, we don't expect any condition where that
935 * should happen and, even if it does, it would be
936 * another error condition.
938 if (dwc
->ep0_next_event
== DWC3_EP0_COMPLETE
) {
939 switch (event
->status
) {
940 case DEPEVT_STATUS_CONTROL_SETUP
:
941 dev_vdbg(dwc
->dev
, "Unexpected XferNotReady(Setup)\n");
942 dwc3_ep0_stall_and_restart(dwc
);
944 case DEPEVT_STATUS_CONTROL_DATA
:
946 case DEPEVT_STATUS_CONTROL_STATUS
:
949 dev_vdbg(dwc
->dev
, "waiting for XferComplete\n");
955 switch (event
->status
) {
956 case DEPEVT_STATUS_CONTROL_SETUP
:
957 dev_vdbg(dwc
->dev
, "Control Setup\n");
959 dwc
->ep0state
= EP0_SETUP_PHASE
;
961 dwc3_ep0_do_control_setup(dwc
, event
);
964 case DEPEVT_STATUS_CONTROL_DATA
:
965 dev_vdbg(dwc
->dev
, "Control Data\n");
967 dwc
->ep0state
= EP0_DATA_PHASE
;
969 if (dwc
->ep0_next_event
!= DWC3_EP0_NRDY_DATA
) {
970 dev_vdbg(dwc
->dev
, "Expected %d got %d\n",
974 dwc3_ep0_stall_and_restart(dwc
);
979 * One of the possible error cases is when Host _does_
980 * request for Data Phase, but it does so on the wrong
983 * Here, we already know ep0_next_event is DATA (see above),
984 * so we only need to check for direction.
986 if (dwc
->ep0_expect_in
!= event
->endpoint_number
) {
987 dev_vdbg(dwc
->dev
, "Wrong direction for Data phase\n");
988 dwc3_ep0_stall_and_restart(dwc
);
992 dwc3_ep0_do_control_data(dwc
, event
);
995 case DEPEVT_STATUS_CONTROL_STATUS
:
996 dev_vdbg(dwc
->dev
, "Control Status\n");
998 dwc
->ep0state
= EP0_STATUS_PHASE
;
1000 if (dwc
->ep0_next_event
!= DWC3_EP0_NRDY_STATUS
) {
1001 dev_vdbg(dwc
->dev
, "Expected %d got %d\n",
1002 dwc
->ep0_next_event
,
1003 DWC3_EP0_NRDY_STATUS
);
1005 dwc3_ep0_stall_and_restart(dwc
);
1009 if (dwc
->delayed_status
) {
1010 WARN_ON_ONCE(event
->endpoint_number
!= 1);
1011 dev_vdbg(dwc
->dev
, "Mass Storage delayed status\n");
1015 dwc3_ep0_do_control_status(dwc
, event
);
1019 void dwc3_ep0_interrupt(struct dwc3
*dwc
,
1020 const struct dwc3_event_depevt
*event
)
1022 u8 epnum
= event
->endpoint_number
;
1024 dev_dbg(dwc
->dev
, "%s while ep%d%s in state '%s'\n",
1025 dwc3_ep_event_string(event
->endpoint_event
),
1026 epnum
>> 1, (epnum
& 1) ? "in" : "out",
1027 dwc3_ep0_state_string(dwc
->ep0state
));
1029 switch (event
->endpoint_event
) {
1030 case DWC3_DEPEVT_XFERCOMPLETE
:
1031 dwc3_ep0_xfer_complete(dwc
, event
);
1034 case DWC3_DEPEVT_XFERNOTREADY
:
1035 dwc3_ep0_xfernotready(dwc
, event
);
1038 case DWC3_DEPEVT_XFERINPROGRESS
:
1039 case DWC3_DEPEVT_RXTXFIFOEVT
:
1040 case DWC3_DEPEVT_STREAMEVT
:
1041 case DWC3_DEPEVT_EPCMDCMPLT
: