drivers/spi/spi-mt65xx.c

   1 /*
   2  * Copyright (c) 2015 MediaTek Inc.
   3  * Author: Leilk Liu <leilk.liu@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/device.h>
  17 #include <linux/err.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/io.h>
  20 #include <linux/ioport.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/platform_data/spi-mt65xx.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/spi/spi.h>
  27
  28 #define SPI_CFG0_REG                      0x0000
  29 #define SPI_CFG1_REG                      0x0004
  30 #define SPI_TX_SRC_REG                    0x0008
  31 #define SPI_RX_DST_REG                    0x000c
  32 #define SPI_TX_DATA_REG                   0x0010
  33 #define SPI_RX_DATA_REG                   0x0014
  34 #define SPI_CMD_REG                       0x0018
  35 #define SPI_STATUS0_REG                   0x001c
  36 #define SPI_PAD_SEL_REG                   0x0024
  37
  38 #define SPI_CFG0_SCK_HIGH_OFFSET          0
  39 #define SPI_CFG0_SCK_LOW_OFFSET           8
  40 #define SPI_CFG0_CS_HOLD_OFFSET           16
  41 #define SPI_CFG0_CS_SETUP_OFFSET          24
  42
  43 #define SPI_CFG1_CS_IDLE_OFFSET           0
  44 #define SPI_CFG1_PACKET_LOOP_OFFSET       8
  45 #define SPI_CFG1_PACKET_LENGTH_OFFSET     16
  46 #define SPI_CFG1_GET_TICK_DLY_OFFSET      30
  47
  48 #define SPI_CFG1_CS_IDLE_MASK             0xff
  49 #define SPI_CFG1_PACKET_LOOP_MASK         0xff00
  50 #define SPI_CFG1_PACKET_LENGTH_MASK       0x3ff0000
  51
  52 #define SPI_CMD_ACT                  BIT(0)
  53 #define SPI_CMD_RESUME               BIT(1)
  54 #define SPI_CMD_RST                  BIT(2)
  55 #define SPI_CMD_PAUSE_EN             BIT(4)
  56 #define SPI_CMD_DEASSERT             BIT(5)
  57 #define SPI_CMD_CPHA                 BIT(8)
  58 #define SPI_CMD_CPOL                 BIT(9)
  59 #define SPI_CMD_RX_DMA               BIT(10)
  60 #define SPI_CMD_TX_DMA               BIT(11)
  61 #define SPI_CMD_TXMSBF               BIT(12)
  62 #define SPI_CMD_RXMSBF               BIT(13)
  63 #define SPI_CMD_RX_ENDIAN            BIT(14)
  64 #define SPI_CMD_TX_ENDIAN            BIT(15)
  65 #define SPI_CMD_FINISH_IE            BIT(16)
  66 #define SPI_CMD_PAUSE_IE             BIT(17)
  67
  68 #define MT8173_SPI_MAX_PAD_SEL 3
  69
  70 #define MTK_SPI_PAUSE_INT_STATUS 0x2
  71
  72 #define MTK_SPI_IDLE 0
  73 #define MTK_SPI_PAUSED 1
  74
  75 #define MTK_SPI_MAX_FIFO_SIZE 32
  76 #define MTK_SPI_PACKET_SIZE 1024
  77
  78 struct mtk_spi_compatible {
  79         bool need_pad_sel;
  80         /* Must explicitly send dummy Tx bytes to do Rx only transfer */
  81         bool must_tx;
  82 };
  83
  84 struct mtk_spi {
  85         void __iomem *base;
  86         u32 state;
  87         u32 pad_sel;
  88         struct clk *spi_clk, *parent_clk;
  89         struct spi_transfer *cur_transfer;
  90         u32 xfer_len;
  91         struct scatterlist *tx_sgl, *rx_sgl;
  92         u32 tx_sgl_len, rx_sgl_len;
  93         const struct mtk_spi_compatible *dev_comp;
  94 };
  95
  96 static const struct mtk_spi_compatible mt6589_compat;
  97 static const struct mtk_spi_compatible mt8135_compat;
  98 static const struct mtk_spi_compatible mt8173_compat = {
  99         .need_pad_sel = true,
 100         .must_tx = true,
 101 };
 102
 103 /*
 104  * A piece of default chip info unless the platform
 105  * supplies it.
 106  */
 107 static const struct mtk_chip_config mtk_default_chip_info = {
 108         .rx_mlsb = 1,
 109         .tx_mlsb = 1,
 110 };
 111
 112 static const struct of_device_id mtk_spi_of_match[] = {
 113         { .compatible = "mediatek,mt6589-spi", .data = (void *)&mt6589_compat },
 114         { .compatible = "mediatek,mt8135-spi", .data = (void *)&mt8135_compat },
 115         { .compatible = "mediatek,mt8173-spi", .data = (void *)&mt8173_compat },
 116         {}
 117 };
 118 MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
 119
 120 static void mtk_spi_reset(struct mtk_spi *mdata)
 121 {
 122         u32 reg_val;
 123
 124         /* set the software reset bit in SPI_CMD_REG. */
 125         reg_val = readl(mdata->base + SPI_CMD_REG);
 126         reg_val |= SPI_CMD_RST;
 127         writel(reg_val, mdata->base + SPI_CMD_REG);
 128
 129         reg_val = readl(mdata->base + SPI_CMD_REG);
 130         reg_val &= ~SPI_CMD_RST;
 131         writel(reg_val, mdata->base + SPI_CMD_REG);
 132 }
 133
 134 static void mtk_spi_config(struct mtk_spi *mdata,
 135                            struct mtk_chip_config *chip_config)
 136 {
 137         u32 reg_val;
 138
 139         reg_val = readl(mdata->base + SPI_CMD_REG);
 140
 141         /* set the mlsbx and mlsbtx */
 142         if (chip_config->tx_mlsb)
 143                 reg_val |= SPI_CMD_TXMSBF;
 144         else
 145                 reg_val &= ~SPI_CMD_TXMSBF;
 146         if (chip_config->rx_mlsb)
 147                 reg_val |= SPI_CMD_RXMSBF;
 148         else
 149                 reg_val &= ~SPI_CMD_RXMSBF;
 150
 151         /* set the tx/rx endian */
 152 #ifdef __LITTLE_ENDIAN
 153         reg_val &= ~SPI_CMD_TX_ENDIAN;
 154         reg_val &= ~SPI_CMD_RX_ENDIAN;
 155 #else
 156         reg_val |= SPI_CMD_TX_ENDIAN;
 157         reg_val |= SPI_CMD_RX_ENDIAN;
 158 #endif
 159
 160         /* set finish and pause interrupt always enable */
 161         reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_EN;
 162
 163         /* disable dma mode */
 164         reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
 165
 166         /* disable deassert mode */
 167         reg_val &= ~SPI_CMD_DEASSERT;
 168
 169         writel(reg_val, mdata->base + SPI_CMD_REG);
 170
 171         /* pad select */
 172         if (mdata->dev_comp->need_pad_sel)
 173                 writel(mdata->pad_sel, mdata->base + SPI_PAD_SEL_REG);
 174 }
 175
 176 static int mtk_spi_prepare_hardware(struct spi_master *master)
 177 {
 178         struct spi_transfer *trans;
 179         struct mtk_spi *mdata = spi_master_get_devdata(master);
 180         struct spi_message *msg = master->cur_msg;
 181
 182         trans = list_first_entry(&msg->transfers, struct spi_transfer,
 183                                  transfer_list);
 184         if (!trans->cs_change) {
 185                 mdata->state = MTK_SPI_IDLE;
 186                 mtk_spi_reset(mdata);
 187         }
 188
 189         return 0;
 190 }
 191
 192 static int mtk_spi_prepare_message(struct spi_master *master,
 193                                    struct spi_message *msg)
 194 {
 195         u32 reg_val;
 196         u8 cpha, cpol;
 197         struct mtk_chip_config *chip_config;
 198         struct spi_device *spi = msg->spi;
 199         struct mtk_spi *mdata = spi_master_get_devdata(master);
 200
 201         cpha = spi->mode & SPI_CPHA ? 1 : 0;
 202         cpol = spi->mode & SPI_CPOL ? 1 : 0;
 203
 204         reg_val = readl(mdata->base + SPI_CMD_REG);
 205         if (cpha)
 206                 reg_val |= SPI_CMD_CPHA;
 207         else
 208                 reg_val &= ~SPI_CMD_CPHA;
 209         if (cpol)
 210                 reg_val |= SPI_CMD_CPOL;
 211         else
 212                 reg_val &= ~SPI_CMD_CPOL;
 213         writel(reg_val, mdata->base + SPI_CMD_REG);
 214
 215         chip_config = spi->controller_data;
 216         if (!chip_config) {
 217                 chip_config = (void *)&mtk_default_chip_info;
 218                 spi->controller_data = chip_config;
 219         }
 220         mtk_spi_config(mdata, chip_config);
 221
 222         return 0;
 223 }
 224
 225 static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
 226 {
 227         u32 reg_val;
 228         struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
 229
 230         reg_val = readl(mdata->base + SPI_CMD_REG);
 231         if (!enable)
 232                 reg_val |= SPI_CMD_PAUSE_EN;
 233         else
 234                 reg_val &= ~SPI_CMD_PAUSE_EN;
 235         writel(reg_val, mdata->base + SPI_CMD_REG);
 236 }
 237
 238 static void mtk_spi_prepare_transfer(struct spi_master *master,
 239                                      struct spi_transfer *xfer)
 240 {
 241         u32 spi_clk_hz, div, high_time, low_time, holdtime,
 242             setuptime, cs_idletime, reg_val = 0;
 243         struct mtk_spi *mdata = spi_master_get_devdata(master);
 244
 245         spi_clk_hz = clk_get_rate(mdata->spi_clk);
 246         if (xfer->speed_hz < spi_clk_hz / 2)
 247                 div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz);
 248         else
 249                 div = 1;
 250
 251         high_time = (div + 1) / 2;
 252         low_time = (div + 1) / 2;
 253         holdtime = (div + 1) / 2 * 2;
 254         setuptime = (div + 1) / 2 * 2;
 255         cs_idletime = (div + 1) / 2 * 2;
 256
 257         reg_val |= (((high_time - 1) & 0xff) << SPI_CFG0_SCK_HIGH_OFFSET);
 258         reg_val |= (((low_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
 259         reg_val |= (((holdtime - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
 260         reg_val |= (((setuptime - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET);
 261         writel(reg_val, mdata->base + SPI_CFG0_REG);
 262
 263         reg_val = readl(mdata->base + SPI_CFG1_REG);
 264         reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
 265         reg_val |= (((cs_idletime - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
 266         writel(reg_val, mdata->base + SPI_CFG1_REG);
 267 }
 268
 269 static void mtk_spi_setup_packet(struct spi_master *master)
 270 {
 271         u32 packet_size, packet_loop, reg_val;
 272         struct mtk_spi *mdata = spi_master_get_devdata(master);
 273
 274         packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
 275         packet_loop = mdata->xfer_len / packet_size;
 276
 277         reg_val = readl(mdata->base + SPI_CFG1_REG);
 278         reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);
 279         reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
 280         reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
 281         writel(reg_val, mdata->base + SPI_CFG1_REG);
 282 }
 283
 284 static void mtk_spi_enable_transfer(struct spi_master *master)
 285 {
 286         u32 cmd;
 287         struct mtk_spi *mdata = spi_master_get_devdata(master);
 288
 289         cmd = readl(mdata->base + SPI_CMD_REG);
 290         if (mdata->state == MTK_SPI_IDLE)
 291                 cmd |= SPI_CMD_ACT;
 292         else
 293                 cmd |= SPI_CMD_RESUME;
 294         writel(cmd, mdata->base + SPI_CMD_REG);
 295 }
 296
 297 static int mtk_spi_get_mult_delta(u32 xfer_len)
 298 {
 299         u32 mult_delta;
 300
 301         if (xfer_len > MTK_SPI_PACKET_SIZE)
 302                 mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
 303         else
 304                 mult_delta = 0;
 305
 306         return mult_delta;
 307 }
 308
 309 static void mtk_spi_update_mdata_len(struct spi_master *master)
 310 {
 311         int mult_delta;
 312         struct mtk_spi *mdata = spi_master_get_devdata(master);
 313
 314         if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
 315                 if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
 316                         mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
 317                         mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
 318                         mdata->rx_sgl_len = mult_delta;
 319                         mdata->tx_sgl_len -= mdata->xfer_len;
 320                 } else {
 321                         mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
 322                         mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
 323                         mdata->tx_sgl_len = mult_delta;
 324                         mdata->rx_sgl_len -= mdata->xfer_len;
 325                 }
 326         } else if (mdata->tx_sgl_len) {
 327                 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
 328                 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
 329                 mdata->tx_sgl_len = mult_delta;
 330         } else if (mdata->rx_sgl_len) {
 331                 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
 332                 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
 333                 mdata->rx_sgl_len = mult_delta;
 334         }
 335 }
 336
 337 static void mtk_spi_setup_dma_addr(struct spi_master *master,
 338                                    struct spi_transfer *xfer)
 339 {
 340         struct mtk_spi *mdata = spi_master_get_devdata(master);
 341
 342         if (mdata->tx_sgl)
 343                 writel(xfer->tx_dma, mdata->base + SPI_TX_SRC_REG);
 344         if (mdata->rx_sgl)
 345                 writel(xfer->rx_dma, mdata->base + SPI_RX_DST_REG);
 346 }
 347
 348 static int mtk_spi_fifo_transfer(struct spi_master *master,
 349                                  struct spi_device *spi,
 350                                  struct spi_transfer *xfer)
 351 {
 352         int cnt;
 353         struct mtk_spi *mdata = spi_master_get_devdata(master);
 354
 355         mdata->cur_transfer = xfer;
 356         mdata->xfer_len = xfer->len;
 357         mtk_spi_prepare_transfer(master, xfer);
 358         mtk_spi_setup_packet(master);
 359
 360         if (xfer->len % 4)
 361                 cnt = xfer->len / 4 + 1;
 362         else
 363                 cnt = xfer->len / 4;
 364         iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
 365
 366         mtk_spi_enable_transfer(master);
 367
 368         return 1;
 369 }
 370
 371 static int mtk_spi_dma_transfer(struct spi_master *master,
 372                                 struct spi_device *spi,
 373                                 struct spi_transfer *xfer)
 374 {
 375         int cmd;
 376         struct mtk_spi *mdata = spi_master_get_devdata(master);
 377
 378         mdata->tx_sgl = NULL;
 379         mdata->rx_sgl = NULL;
 380         mdata->tx_sgl_len = 0;
 381         mdata->rx_sgl_len = 0;
 382         mdata->cur_transfer = xfer;
 383
 384         mtk_spi_prepare_transfer(master, xfer);
 385
 386         cmd = readl(mdata->base + SPI_CMD_REG);
 387         if (xfer->tx_buf)
 388                 cmd |= SPI_CMD_TX_DMA;
 389         if (xfer->rx_buf)
 390                 cmd |= SPI_CMD_RX_DMA;
 391         writel(cmd, mdata->base + SPI_CMD_REG);
 392
 393         if (xfer->tx_buf)
 394                 mdata->tx_sgl = xfer->tx_sg.sgl;
 395         if (xfer->rx_buf)
 396                 mdata->rx_sgl = xfer->rx_sg.sgl;
 397
 398         if (mdata->tx_sgl) {
 399                 xfer->tx_dma = sg_dma_address(mdata->tx_sgl);
 400                 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
 401         }
 402         if (mdata->rx_sgl) {
 403                 xfer->rx_dma = sg_dma_address(mdata->rx_sgl);
 404                 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
 405         }
 406
 407         mtk_spi_update_mdata_len(master);
 408         mtk_spi_setup_packet(master);
 409         mtk_spi_setup_dma_addr(master, xfer);
 410         mtk_spi_enable_transfer(master);
 411
 412         return 1;
 413 }
 414
 415 static int mtk_spi_transfer_one(struct spi_master *master,
 416                                 struct spi_device *spi,
 417                                 struct spi_transfer *xfer)
 418 {
 419         if (master->can_dma(master, spi, xfer))
 420                 return mtk_spi_dma_transfer(master, spi, xfer);
 421         else
 422                 return mtk_spi_fifo_transfer(master, spi, xfer);
 423 }
 424
 425 static bool mtk_spi_can_dma(struct spi_master *master,
 426                             struct spi_device *spi,
 427                             struct spi_transfer *xfer)
 428 {
 429         return xfer->len > MTK_SPI_MAX_FIFO_SIZE;
 430 }
 431
 432 static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
 433 {
 434         u32 cmd, reg_val, cnt;
 435         struct spi_master *master = dev_id;
 436         struct mtk_spi *mdata = spi_master_get_devdata(master);
 437         struct spi_transfer *trans = mdata->cur_transfer;
 438
 439         reg_val = readl(mdata->base + SPI_STATUS0_REG);
 440         if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
 441                 mdata->state = MTK_SPI_PAUSED;
 442         else
 443                 mdata->state = MTK_SPI_IDLE;
 444
 445         if (!master->can_dma(master, master->cur_msg->spi, trans)) {
 446                 if (trans->rx_buf) {
 447                         if (mdata->xfer_len % 4)
 448                                 cnt = mdata->xfer_len / 4 + 1;
 449                         else
 450                                 cnt = mdata->xfer_len / 4;
 451                         ioread32_rep(mdata->base + SPI_RX_DATA_REG,
 452                                      trans->rx_buf, cnt);
 453                 }
 454                 spi_finalize_current_transfer(master);
 455                 return IRQ_HANDLED;
 456         }
 457
 458         if (mdata->tx_sgl)
 459                 trans->tx_dma += mdata->xfer_len;
 460         if (mdata->rx_sgl)
 461                 trans->rx_dma += mdata->xfer_len;
 462
 463         if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) {
 464                 mdata->tx_sgl = sg_next(mdata->tx_sgl);
 465                 if (mdata->tx_sgl) {
 466                         trans->tx_dma = sg_dma_address(mdata->tx_sgl);
 467                         mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
 468                 }
 469         }
 470         if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) {
 471                 mdata->rx_sgl = sg_next(mdata->rx_sgl);
 472                 if (mdata->rx_sgl) {
 473                         trans->rx_dma = sg_dma_address(mdata->rx_sgl);
 474                         mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
 475                 }
 476         }
 477
 478         if (!mdata->tx_sgl && !mdata->rx_sgl) {
 479                 /* spi disable dma */
 480                 cmd = readl(mdata->base + SPI_CMD_REG);
 481                 cmd &= ~SPI_CMD_TX_DMA;
 482                 cmd &= ~SPI_CMD_RX_DMA;
 483                 writel(cmd, mdata->base + SPI_CMD_REG);
 484
 485                 spi_finalize_current_transfer(master);
 486                 return IRQ_HANDLED;
 487         }
 488
 489         mtk_spi_update_mdata_len(master);
 490         mtk_spi_setup_packet(master);
 491         mtk_spi_setup_dma_addr(master, trans);
 492         mtk_spi_enable_transfer(master);
 493
 494         return IRQ_HANDLED;
 495 }
 496
 497 static int mtk_spi_probe(struct platform_device *pdev)
 498 {
 499         struct spi_master *master;
 500         struct mtk_spi *mdata;
 501         const struct of_device_id *of_id;
 502         struct resource *res;
 503         int irq, ret;
 504
 505         master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
 506         if (!master) {
 507                 dev_err(&pdev->dev, "failed to alloc spi master\n");
 508                 return -ENOMEM;
 509         }
 510
 511         master->auto_runtime_pm = true;
 512         master->dev.of_node = pdev->dev.of_node;
 513         master->mode_bits = SPI_CPOL | SPI_CPHA;
 514
 515         master->set_cs = mtk_spi_set_cs;
 516         master->prepare_transfer_hardware = mtk_spi_prepare_hardware;
 517         master->prepare_message = mtk_spi_prepare_message;
 518         master->transfer_one = mtk_spi_transfer_one;
 519         master->can_dma = mtk_spi_can_dma;
 520
 521         of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
 522         if (!of_id) {
 523                 dev_err(&pdev->dev, "failed to probe of_node\n");
 524                 ret = -EINVAL;
 525                 goto err_put_master;
 526         }
 527
 528         mdata = spi_master_get_devdata(master);
 529         mdata->dev_comp = of_id->data;
 530         if (mdata->dev_comp->must_tx)
 531                 master->flags = SPI_MASTER_MUST_TX;
 532
 533         if (mdata->dev_comp->need_pad_sel) {
 534                 ret = of_property_read_u32(pdev->dev.of_node,
 535                                            "mediatek,pad-select",
 536                                            &mdata->pad_sel);
 537                 if (ret) {
 538                         dev_err(&pdev->dev, "failed to read pad select: %d\n",
 539                                 ret);
 540                         goto err_put_master;
 541                 }
 542
 543                 if (mdata->pad_sel > MT8173_SPI_MAX_PAD_SEL) {
 544                         dev_err(&pdev->dev, "wrong pad-select: %u\n",
 545                                 mdata->pad_sel);
 546                         ret = -EINVAL;
 547                         goto err_put_master;
 548                 }
 549         }
 550
 551         platform_set_drvdata(pdev, master);
 552
 553         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 554         if (!res) {
 555                 ret = -ENODEV;
 556                 dev_err(&pdev->dev, "failed to determine base address\n");
 557                 goto err_put_master;
 558         }
 559
 560         mdata->base = devm_ioremap_resource(&pdev->dev, res);
 561         if (IS_ERR(mdata->base)) {
 562                 ret = PTR_ERR(mdata->base);
 563                 goto err_put_master;
 564         }
 565
 566         irq = platform_get_irq(pdev, 0);
 567         if (irq < 0) {
 568                 dev_err(&pdev->dev, "failed to get irq (%d)\n", irq);
 569                 ret = irq;
 570                 goto err_put_master;
 571         }
 572
 573         if (!pdev->dev.dma_mask)
 574                 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
 575
 576         ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt,
 577                                IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master);
 578         if (ret) {
 579                 dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
 580                 goto err_put_master;
 581         }
 582
 583         mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
 584         if (IS_ERR(mdata->spi_clk)) {
 585                 ret = PTR_ERR(mdata->spi_clk);
 586                 dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
 587                 goto err_put_master;
 588         }
 589
 590         mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
 591         if (IS_ERR(mdata->parent_clk)) {
 592                 ret = PTR_ERR(mdata->parent_clk);
 593                 dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret);
 594                 goto err_put_master;
 595         }
 596
 597         ret = clk_prepare_enable(mdata->spi_clk);
 598         if (ret < 0) {
 599                 dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
 600                 goto err_put_master;
 601         }
 602
 603         ret = clk_set_parent(mdata->spi_clk, mdata->parent_clk);
 604         if (ret < 0) {
 605                 dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
 606                 goto err_disable_clk;
 607         }
 608
 609         clk_disable_unprepare(mdata->spi_clk);
 610
 611         pm_runtime_enable(&pdev->dev);
 612
 613         ret = devm_spi_register_master(&pdev->dev, master);
 614         if (ret) {
 615                 dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
 616                 goto err_put_master;
 617         }
 618
 619         return 0;
 620
 621 err_disable_clk:
 622         clk_disable_unprepare(mdata->spi_clk);
 623 err_put_master:
 624         spi_master_put(master);
 625
 626         return ret;
 627 }
 628
 629 static int mtk_spi_remove(struct platform_device *pdev)
 630 {
 631         struct spi_master *master = platform_get_drvdata(pdev);
 632         struct mtk_spi *mdata = spi_master_get_devdata(master);
 633
 634         pm_runtime_disable(&pdev->dev);
 635
 636         mtk_spi_reset(mdata);
 637         clk_disable_unprepare(mdata->spi_clk);
 638         spi_master_put(master);
 639
 640         return 0;
 641 }
 642
 643 #ifdef CONFIG_PM_SLEEP
 644 static int mtk_spi_suspend(struct device *dev)
 645 {
 646         int ret;
 647         struct spi_master *master = dev_get_drvdata(dev);
 648         struct mtk_spi *mdata = spi_master_get_devdata(master);
 649
 650         ret = spi_master_suspend(master);
 651         if (ret)
 652                 return ret;
 653
 654         if (!pm_runtime_suspended(dev))
 655                 clk_disable_unprepare(mdata->spi_clk);
 656
 657         return ret;
 658 }
 659
 660 static int mtk_spi_resume(struct device *dev)
 661 {
 662         int ret;
 663         struct spi_master *master = dev_get_drvdata(dev);
 664         struct mtk_spi *mdata = spi_master_get_devdata(master);
 665
 666         if (!pm_runtime_suspended(dev)) {
 667                 ret = clk_prepare_enable(mdata->spi_clk);
 668                 if (ret < 0)
 669                         return ret;
 670         }
 671
 672         ret = spi_master_resume(master);
 673         if (ret < 0)
 674                 clk_disable_unprepare(mdata->spi_clk);
 675
 676         return ret;
 677 }
 678 #endif /* CONFIG_PM_SLEEP */
 679
 680 #ifdef CONFIG_PM
 681 static int mtk_spi_runtime_suspend(struct device *dev)
 682 {
 683         struct spi_master *master = dev_get_drvdata(dev);
 684         struct mtk_spi *mdata = spi_master_get_devdata(master);
 685
 686         clk_disable_unprepare(mdata->spi_clk);
 687
 688         return 0;
 689 }
 690
 691 static int mtk_spi_runtime_resume(struct device *dev)
 692 {
 693         struct spi_master *master = dev_get_drvdata(dev);
 694         struct mtk_spi *mdata = spi_master_get_devdata(master);
 695
 696         return clk_prepare_enable(mdata->spi_clk);
 697 }
 698 #endif /* CONFIG_PM */
 699
 700 static const struct dev_pm_ops mtk_spi_pm = {
 701         SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume)
 702         SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend,
 703                            mtk_spi_runtime_resume, NULL)
 704 };
 705
 706 static struct platform_driver mtk_spi_driver = {
 707         .driver = {
 708                 .name = "mtk-spi",
 709                 .pm     = &mtk_spi_pm,
 710                 .of_match_table = mtk_spi_of_match,
 711         },
 712         .probe = mtk_spi_probe,
 713         .remove = mtk_spi_remove,
 714 };
 715
 716 module_platform_driver(mtk_spi_driver);
 717
 718 MODULE_DESCRIPTION("MTK SPI Controller driver");
 719 MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
 720 MODULE_LICENSE("GPL v2");
 721 MODULE_ALIAS("platform:mtk-spi");