2 * linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
4 * Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
6 * Current driver maintained by Ben Dooks and Simtec Electronics
7 * Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/clk.h>
17 #include <linux/mmc/host.h>
18 #include <linux/platform_device.h>
19 #include <linux/cpufreq.h>
20 #include <linux/gpio.h>
21 #include <linux/irq.h>
26 #include <mach/regs-sdi.h>
27 #include <mach/regs-gpio.h>
33 #define DRIVER_NAME "s3c-mci"
47 static const int dbgmap_err
= dbg_fail
;
48 static const int dbgmap_info
= dbg_info
| dbg_conf
;
49 static const int dbgmap_debug
= dbg_err
| dbg_debug
;
51 #define dbg(host, channels, args...) \
53 if (dbgmap_err & channels) \
54 dev_err(&host->pdev->dev, args); \
55 else if (dbgmap_info & channels) \
56 dev_info(&host->pdev->dev, args); \
57 else if (dbgmap_debug & channels) \
58 dev_dbg(&host->pdev->dev, args); \
61 static struct s3c2410_dma_client s3cmci_dma_client
= {
65 static void finalize_request(struct s3cmci_host
*host
);
66 static void s3cmci_send_request(struct mmc_host
*mmc
);
67 static void s3cmci_reset(struct s3cmci_host
*host
);
69 #ifdef CONFIG_MMC_DEBUG
71 static void dbg_dumpregs(struct s3cmci_host
*host
, char *prefix
)
73 u32 con
, pre
, cmdarg
, cmdcon
, cmdsta
, r0
, r1
, r2
, r3
, timer
, bsize
;
74 u32 datcon
, datcnt
, datsta
, fsta
, imask
;
76 con
= readl(host
->base
+ S3C2410_SDICON
);
77 pre
= readl(host
->base
+ S3C2410_SDIPRE
);
78 cmdarg
= readl(host
->base
+ S3C2410_SDICMDARG
);
79 cmdcon
= readl(host
->base
+ S3C2410_SDICMDCON
);
80 cmdsta
= readl(host
->base
+ S3C2410_SDICMDSTAT
);
81 r0
= readl(host
->base
+ S3C2410_SDIRSP0
);
82 r1
= readl(host
->base
+ S3C2410_SDIRSP1
);
83 r2
= readl(host
->base
+ S3C2410_SDIRSP2
);
84 r3
= readl(host
->base
+ S3C2410_SDIRSP3
);
85 timer
= readl(host
->base
+ S3C2410_SDITIMER
);
86 bsize
= readl(host
->base
+ S3C2410_SDIBSIZE
);
87 datcon
= readl(host
->base
+ S3C2410_SDIDCON
);
88 datcnt
= readl(host
->base
+ S3C2410_SDIDCNT
);
89 datsta
= readl(host
->base
+ S3C2410_SDIDSTA
);
90 fsta
= readl(host
->base
+ S3C2410_SDIFSTA
);
91 imask
= readl(host
->base
+ host
->sdiimsk
);
93 dbg(host
, dbg_debug
, "%s CON:[%08x] PRE:[%08x] TMR:[%08x]\n",
94 prefix
, con
, pre
, timer
);
96 dbg(host
, dbg_debug
, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
97 prefix
, cmdcon
, cmdarg
, cmdsta
);
99 dbg(host
, dbg_debug
, "%s DCON:[%08x] FSTA:[%08x]"
100 " DSTA:[%08x] DCNT:[%08x]\n",
101 prefix
, datcon
, fsta
, datsta
, datcnt
);
103 dbg(host
, dbg_debug
, "%s R0:[%08x] R1:[%08x]"
104 " R2:[%08x] R3:[%08x]\n",
105 prefix
, r0
, r1
, r2
, r3
);
108 static void prepare_dbgmsg(struct s3cmci_host
*host
, struct mmc_command
*cmd
,
111 snprintf(host
->dbgmsg_cmd
, 300,
112 "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u",
113 host
->ccnt
, (stop
? " (STOP)" : ""),
114 cmd
->opcode
, cmd
->arg
, cmd
->flags
, cmd
->retries
);
117 snprintf(host
->dbgmsg_dat
, 300,
118 "#%u bsize:%u blocks:%u bytes:%u",
119 host
->dcnt
, cmd
->data
->blksz
,
121 cmd
->data
->blocks
* cmd
->data
->blksz
);
123 host
->dbgmsg_dat
[0] = '\0';
127 static void dbg_dumpcmd(struct s3cmci_host
*host
, struct mmc_command
*cmd
,
130 unsigned int dbglvl
= fail
? dbg_fail
: dbg_debug
;
135 if (cmd
->error
== 0) {
136 dbg(host
, dbglvl
, "CMD[OK] %s R0:0x%08x\n",
137 host
->dbgmsg_cmd
, cmd
->resp
[0]);
139 dbg(host
, dbglvl
, "CMD[ERR %i] %s Status:%s\n",
140 cmd
->error
, host
->dbgmsg_cmd
, host
->status
);
146 if (cmd
->data
->error
== 0) {
147 dbg(host
, dbglvl
, "DAT[OK] %s\n", host
->dbgmsg_dat
);
149 dbg(host
, dbglvl
, "DAT[ERR %i] %s DCNT:0x%08x\n",
150 cmd
->data
->error
, host
->dbgmsg_dat
,
151 readl(host
->base
+ S3C2410_SDIDCNT
));
155 static void dbg_dumpcmd(struct s3cmci_host
*host
,
156 struct mmc_command
*cmd
, int fail
) { }
158 static void prepare_dbgmsg(struct s3cmci_host
*host
, struct mmc_command
*cmd
,
161 static void dbg_dumpregs(struct s3cmci_host
*host
, char *prefix
) { }
163 #endif /* CONFIG_MMC_DEBUG */
165 static inline u32
enable_imask(struct s3cmci_host
*host
, u32 imask
)
169 newmask
= readl(host
->base
+ host
->sdiimsk
);
172 writel(newmask
, host
->base
+ host
->sdiimsk
);
177 static inline u32
disable_imask(struct s3cmci_host
*host
, u32 imask
)
181 newmask
= readl(host
->base
+ host
->sdiimsk
);
184 writel(newmask
, host
->base
+ host
->sdiimsk
);
189 static inline void clear_imask(struct s3cmci_host
*host
)
191 writel(0, host
->base
+ host
->sdiimsk
);
194 static inline int get_data_buffer(struct s3cmci_host
*host
,
195 u32
*bytes
, u32
**pointer
)
197 struct scatterlist
*sg
;
199 if (host
->pio_active
== XFER_NONE
)
202 if ((!host
->mrq
) || (!host
->mrq
->data
))
205 if (host
->pio_sgptr
>= host
->mrq
->data
->sg_len
) {
206 dbg(host
, dbg_debug
, "no more buffers (%i/%i)\n",
207 host
->pio_sgptr
, host
->mrq
->data
->sg_len
);
210 sg
= &host
->mrq
->data
->sg
[host
->pio_sgptr
];
213 *pointer
= sg_virt(sg
);
217 dbg(host
, dbg_sg
, "new buffer (%i/%i)\n",
218 host
->pio_sgptr
, host
->mrq
->data
->sg_len
);
223 static inline u32
fifo_count(struct s3cmci_host
*host
)
225 u32 fifostat
= readl(host
->base
+ S3C2410_SDIFSTA
);
227 fifostat
&= S3C2410_SDIFSTA_COUNTMASK
;
231 static inline u32
fifo_free(struct s3cmci_host
*host
)
233 u32 fifostat
= readl(host
->base
+ S3C2410_SDIFSTA
);
235 fifostat
&= S3C2410_SDIFSTA_COUNTMASK
;
236 return 63 - fifostat
;
239 static void do_pio_read(struct s3cmci_host
*host
)
245 void __iomem
*from_ptr
;
247 /* write real prescaler to host, it might be set slow to fix */
248 writel(host
->prescaler
, host
->base
+ S3C2410_SDIPRE
);
250 from_ptr
= host
->base
+ host
->sdidata
;
252 while ((fifo
= fifo_count(host
))) {
253 if (!host
->pio_bytes
) {
254 res
= get_data_buffer(host
, &host
->pio_bytes
,
257 host
->pio_active
= XFER_NONE
;
258 host
->complete_what
= COMPLETION_FINALIZE
;
260 dbg(host
, dbg_pio
, "pio_read(): "
261 "complete (no more data).\n");
266 "pio_read(): new target: [%i]@[%p]\n",
267 host
->pio_bytes
, host
->pio_ptr
);
271 "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n",
272 fifo
, host
->pio_bytes
,
273 readl(host
->base
+ S3C2410_SDIDCNT
));
275 /* If we have reached the end of the block, we can
276 * read a word and get 1 to 3 bytes. If we in the
277 * middle of the block, we have to read full words,
278 * otherwise we will write garbage, so round down to
279 * an even multiple of 4. */
280 if (fifo
>= host
->pio_bytes
)
281 fifo
= host
->pio_bytes
;
285 host
->pio_bytes
-= fifo
;
286 host
->pio_count
+= fifo
;
288 fifo_words
= fifo
>> 2;
291 *ptr
++ = readl(from_ptr
);
296 u32 data
= readl(from_ptr
);
297 u8
*p
= (u8
*)host
->pio_ptr
;
306 if (!host
->pio_bytes
) {
307 res
= get_data_buffer(host
, &host
->pio_bytes
, &host
->pio_ptr
);
310 "pio_read(): complete (no more buffers).\n");
311 host
->pio_active
= XFER_NONE
;
312 host
->complete_what
= COMPLETION_FINALIZE
;
319 S3C2410_SDIIMSK_RXFIFOHALF
| S3C2410_SDIIMSK_RXFIFOLAST
);
322 static void do_pio_write(struct s3cmci_host
*host
)
324 void __iomem
*to_ptr
;
329 to_ptr
= host
->base
+ host
->sdidata
;
331 while ((fifo
= fifo_free(host
)) > 3) {
332 if (!host
->pio_bytes
) {
333 res
= get_data_buffer(host
, &host
->pio_bytes
,
337 "pio_write(): complete (no more data).\n");
338 host
->pio_active
= XFER_NONE
;
344 "pio_write(): new source: [%i]@[%p]\n",
345 host
->pio_bytes
, host
->pio_ptr
);
349 /* If we have reached the end of the block, we have to
350 * write exactly the remaining number of bytes. If we
351 * in the middle of the block, we have to write full
352 * words, so round down to an even multiple of 4. */
353 if (fifo
>= host
->pio_bytes
)
354 fifo
= host
->pio_bytes
;
358 host
->pio_bytes
-= fifo
;
359 host
->pio_count
+= fifo
;
361 fifo
= (fifo
+ 3) >> 2;
364 writel(*ptr
++, to_ptr
);
368 enable_imask(host
, S3C2410_SDIIMSK_TXFIFOHALF
);
371 static void pio_tasklet(unsigned long data
)
373 struct s3cmci_host
*host
= (struct s3cmci_host
*) data
;
376 disable_irq(host
->irq
);
378 if (host
->pio_active
== XFER_WRITE
)
381 if (host
->pio_active
== XFER_READ
)
384 if (host
->complete_what
== COMPLETION_FINALIZE
) {
386 if (host
->pio_active
!= XFER_NONE
) {
387 dbg(host
, dbg_err
, "unfinished %s "
388 "- pio_count:[%u] pio_bytes:[%u]\n",
389 (host
->pio_active
== XFER_READ
) ? "read" : "write",
390 host
->pio_count
, host
->pio_bytes
);
393 host
->mrq
->data
->error
= -EINVAL
;
396 finalize_request(host
);
398 enable_irq(host
->irq
);
402 * ISR for SDI Interface IRQ
403 * Communication between driver and ISR works as follows:
404 * host->mrq points to current request
405 * host->complete_what Indicates when the request is considered done
406 * COMPLETION_CMDSENT when the command was sent
407 * COMPLETION_RSPFIN when a response was received
408 * COMPLETION_XFERFINISH when the data transfer is finished
409 * COMPLETION_XFERFINISH_RSPFIN both of the above.
410 * host->complete_request is the completion-object the driver waits for
412 * 1) Driver sets up host->mrq and host->complete_what
413 * 2) Driver prepares the transfer
414 * 3) Driver enables interrupts
415 * 4) Driver starts transfer
416 * 5) Driver waits for host->complete_rquest
417 * 6) ISR checks for request status (errors and success)
418 * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
419 * 7) ISR completes host->complete_request
420 * 8) ISR disables interrupts
421 * 9) Driver wakes up and takes care of the request
423 * Note: "->error"-fields are expected to be set to 0 before the request
424 * was issued by mmc.c - therefore they are only set, when an error
428 static irqreturn_t
s3cmci_irq(int irq
, void *dev_id
)
430 struct s3cmci_host
*host
= dev_id
;
431 struct mmc_command
*cmd
;
432 u32 mci_csta
, mci_dsta
, mci_fsta
, mci_dcnt
, mci_imsk
;
433 u32 mci_cclear
, mci_dclear
;
434 unsigned long iflags
;
436 spin_lock_irqsave(&host
->complete_lock
, iflags
);
438 mci_csta
= readl(host
->base
+ S3C2410_SDICMDSTAT
);
439 mci_dsta
= readl(host
->base
+ S3C2410_SDIDSTA
);
440 mci_dcnt
= readl(host
->base
+ S3C2410_SDIDCNT
);
441 mci_fsta
= readl(host
->base
+ S3C2410_SDIFSTA
);
442 mci_imsk
= readl(host
->base
+ host
->sdiimsk
);
446 if ((host
->complete_what
== COMPLETION_NONE
) ||
447 (host
->complete_what
== COMPLETION_FINALIZE
)) {
448 host
->status
= "nothing to complete";
454 host
->status
= "no active mrq";
459 cmd
= host
->cmd_is_stop
? host
->mrq
->stop
: host
->mrq
->cmd
;
462 host
->status
= "no active cmd";
468 if ((host
->pio_active
== XFER_WRITE
) &&
469 (mci_fsta
& S3C2410_SDIFSTA_TFDET
)) {
471 disable_imask(host
, S3C2410_SDIIMSK_TXFIFOHALF
);
472 tasklet_schedule(&host
->pio_tasklet
);
473 host
->status
= "pio tx";
476 if ((host
->pio_active
== XFER_READ
) &&
477 (mci_fsta
& S3C2410_SDIFSTA_RFDET
)) {
480 S3C2410_SDIIMSK_RXFIFOHALF
|
481 S3C2410_SDIIMSK_RXFIFOLAST
);
483 tasklet_schedule(&host
->pio_tasklet
);
484 host
->status
= "pio rx";
488 if (mci_csta
& S3C2410_SDICMDSTAT_CMDTIMEOUT
) {
489 dbg(host
, dbg_err
, "CMDSTAT: error CMDTIMEOUT\n");
490 cmd
->error
= -ETIMEDOUT
;
491 host
->status
= "error: command timeout";
495 if (mci_csta
& S3C2410_SDICMDSTAT_CMDSENT
) {
496 if (host
->complete_what
== COMPLETION_CMDSENT
) {
497 host
->status
= "ok: command sent";
501 mci_cclear
|= S3C2410_SDICMDSTAT_CMDSENT
;
504 if (mci_csta
& S3C2410_SDICMDSTAT_CRCFAIL
) {
505 if (cmd
->flags
& MMC_RSP_CRC
) {
506 if (host
->mrq
->cmd
->flags
& MMC_RSP_136
) {
508 "fixup: ignore CRC fail with long rsp\n");
510 /* note, we used to fail the transfer
511 * here, but it seems that this is just
512 * the hardware getting it wrong.
514 * cmd->error = -EILSEQ;
515 * host->status = "error: bad command crc";
516 * goto fail_transfer;
521 mci_cclear
|= S3C2410_SDICMDSTAT_CRCFAIL
;
524 if (mci_csta
& S3C2410_SDICMDSTAT_RSPFIN
) {
525 if (host
->complete_what
== COMPLETION_RSPFIN
) {
526 host
->status
= "ok: command response received";
530 if (host
->complete_what
== COMPLETION_XFERFINISH_RSPFIN
)
531 host
->complete_what
= COMPLETION_XFERFINISH
;
533 mci_cclear
|= S3C2410_SDICMDSTAT_RSPFIN
;
536 /* errors handled after this point are only relevant
537 when a data transfer is in progress */
540 goto clear_status_bits
;
542 /* Check for FIFO failure */
544 if (mci_fsta
& S3C2440_SDIFSTA_FIFOFAIL
) {
545 dbg(host
, dbg_err
, "FIFO failure\n");
546 host
->mrq
->data
->error
= -EILSEQ
;
547 host
->status
= "error: 2440 fifo failure";
551 if (mci_dsta
& S3C2410_SDIDSTA_FIFOFAIL
) {
552 dbg(host
, dbg_err
, "FIFO failure\n");
553 cmd
->data
->error
= -EILSEQ
;
554 host
->status
= "error: fifo failure";
559 if (mci_dsta
& S3C2410_SDIDSTA_RXCRCFAIL
) {
560 dbg(host
, dbg_err
, "bad data crc (outgoing)\n");
561 cmd
->data
->error
= -EILSEQ
;
562 host
->status
= "error: bad data crc (outgoing)";
566 if (mci_dsta
& S3C2410_SDIDSTA_CRCFAIL
) {
567 dbg(host
, dbg_err
, "bad data crc (incoming)\n");
568 cmd
->data
->error
= -EILSEQ
;
569 host
->status
= "error: bad data crc (incoming)";
573 if (mci_dsta
& S3C2410_SDIDSTA_DATATIMEOUT
) {
574 dbg(host
, dbg_err
, "data timeout\n");
575 cmd
->data
->error
= -ETIMEDOUT
;
576 host
->status
= "error: data timeout";
580 if (mci_dsta
& S3C2410_SDIDSTA_XFERFINISH
) {
581 if (host
->complete_what
== COMPLETION_XFERFINISH
) {
582 host
->status
= "ok: data transfer completed";
586 if (host
->complete_what
== COMPLETION_XFERFINISH_RSPFIN
)
587 host
->complete_what
= COMPLETION_RSPFIN
;
589 mci_dclear
|= S3C2410_SDIDSTA_XFERFINISH
;
593 writel(mci_cclear
, host
->base
+ S3C2410_SDICMDSTAT
);
594 writel(mci_dclear
, host
->base
+ S3C2410_SDIDSTA
);
599 host
->pio_active
= XFER_NONE
;
602 host
->complete_what
= COMPLETION_FINALIZE
;
605 tasklet_schedule(&host
->pio_tasklet
);
611 "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n",
612 mci_csta
, mci_dsta
, mci_fsta
, mci_dcnt
, host
->status
);
614 spin_unlock_irqrestore(&host
->complete_lock
, iflags
);
620 * ISR for the CardDetect Pin
623 static irqreturn_t
s3cmci_irq_cd(int irq
, void *dev_id
)
625 struct s3cmci_host
*host
= (struct s3cmci_host
*)dev_id
;
627 dbg(host
, dbg_irq
, "card detect\n");
629 mmc_detect_change(host
->mmc
, msecs_to_jiffies(500));
634 static void s3cmci_dma_done_callback(struct s3c2410_dma_chan
*dma_ch
,
635 void *buf_id
, int size
,
636 enum s3c2410_dma_buffresult result
)
638 struct s3cmci_host
*host
= buf_id
;
639 unsigned long iflags
;
640 u32 mci_csta
, mci_dsta
, mci_fsta
, mci_dcnt
;
642 mci_csta
= readl(host
->base
+ S3C2410_SDICMDSTAT
);
643 mci_dsta
= readl(host
->base
+ S3C2410_SDIDSTA
);
644 mci_fsta
= readl(host
->base
+ S3C2410_SDIFSTA
);
645 mci_dcnt
= readl(host
->base
+ S3C2410_SDIDCNT
);
648 BUG_ON(!host
->mrq
->data
);
649 BUG_ON(!host
->dmatogo
);
651 spin_lock_irqsave(&host
->complete_lock
, iflags
);
653 if (result
!= S3C2410_RES_OK
) {
654 dbg(host
, dbg_fail
, "DMA FAILED: csta=0x%08x dsta=0x%08x "
655 "fsta=0x%08x dcnt:0x%08x result:0x%08x toGo:%u\n",
656 mci_csta
, mci_dsta
, mci_fsta
,
657 mci_dcnt
, result
, host
->dmatogo
);
664 dbg(host
, dbg_dma
, "DMA DONE Size:%i DSTA:[%08x] "
665 "DCNT:[%08x] toGo:%u\n",
666 size
, mci_dsta
, mci_dcnt
, host
->dmatogo
);
671 dbg(host
, dbg_dma
, "DMA FINISHED Size:%i DSTA:%08x DCNT:%08x\n",
672 size
, mci_dsta
, mci_dcnt
);
674 host
->complete_what
= COMPLETION_FINALIZE
;
677 tasklet_schedule(&host
->pio_tasklet
);
678 spin_unlock_irqrestore(&host
->complete_lock
, iflags
);
682 host
->mrq
->data
->error
= -EINVAL
;
683 host
->complete_what
= COMPLETION_FINALIZE
;
684 writel(0, host
->base
+ host
->sdiimsk
);
689 static void finalize_request(struct s3cmci_host
*host
)
691 struct mmc_request
*mrq
= host
->mrq
;
692 struct mmc_command
*cmd
= host
->cmd_is_stop
? mrq
->stop
: mrq
->cmd
;
693 int debug_as_failure
= 0;
695 if (host
->complete_what
!= COMPLETION_FINALIZE
)
701 if (cmd
->data
&& (cmd
->error
== 0) &&
702 (cmd
->data
->error
== 0)) {
703 if (host
->dodma
&& (!host
->dma_complete
)) {
704 dbg(host
, dbg_dma
, "DMA Missing!\n");
709 /* Read response from controller. */
710 cmd
->resp
[0] = readl(host
->base
+ S3C2410_SDIRSP0
);
711 cmd
->resp
[1] = readl(host
->base
+ S3C2410_SDIRSP1
);
712 cmd
->resp
[2] = readl(host
->base
+ S3C2410_SDIRSP2
);
713 cmd
->resp
[3] = readl(host
->base
+ S3C2410_SDIRSP3
);
715 writel(host
->prescaler
, host
->base
+ S3C2410_SDIPRE
);
718 debug_as_failure
= 1;
720 if (cmd
->data
&& cmd
->data
->error
)
721 debug_as_failure
= 1;
723 dbg_dumpcmd(host
, cmd
, debug_as_failure
);
725 /* Cleanup controller */
726 writel(0, host
->base
+ S3C2410_SDICMDARG
);
727 writel(S3C2410_SDIDCON_STOP
, host
->base
+ S3C2410_SDIDCON
);
728 writel(0, host
->base
+ S3C2410_SDICMDCON
);
729 writel(0, host
->base
+ host
->sdiimsk
);
731 if (cmd
->data
&& cmd
->error
)
732 cmd
->data
->error
= cmd
->error
;
734 if (cmd
->data
&& cmd
->data
->stop
&& (!host
->cmd_is_stop
)) {
735 host
->cmd_is_stop
= 1;
736 s3cmci_send_request(host
->mmc
);
740 /* If we have no data transfer we are finished here */
744 /* Calulate the amout of bytes transfer if there was no error */
745 if (mrq
->data
->error
== 0) {
746 mrq
->data
->bytes_xfered
=
747 (mrq
->data
->blocks
* mrq
->data
->blksz
);
749 mrq
->data
->bytes_xfered
= 0;
752 /* If we had an error while transfering data we flush the
753 * DMA channel and the fifo to clear out any garbage. */
754 if (mrq
->data
->error
!= 0) {
756 s3c2410_dma_ctrl(host
->dma
, S3C2410_DMAOP_FLUSH
);
759 /* Clear failure register and reset fifo. */
760 writel(S3C2440_SDIFSTA_FIFORESET
|
761 S3C2440_SDIFSTA_FIFOFAIL
,
762 host
->base
+ S3C2410_SDIFSTA
);
767 mci_con
= readl(host
->base
+ S3C2410_SDICON
);
768 mci_con
|= S3C2410_SDICON_FIFORESET
;
770 writel(mci_con
, host
->base
+ S3C2410_SDICON
);
775 host
->complete_what
= COMPLETION_NONE
;
777 mmc_request_done(host
->mmc
, mrq
);
780 static void s3cmci_dma_setup(struct s3cmci_host
*host
,
781 enum s3c2410_dmasrc source
)
783 static enum s3c2410_dmasrc last_source
= -1;
786 if (last_source
== source
)
789 last_source
= source
;
791 s3c2410_dma_devconfig(host
->dma
, source
,
792 host
->mem
->start
+ host
->sdidata
);
795 s3c2410_dma_config(host
->dma
, 4);
796 s3c2410_dma_set_buffdone_fn(host
->dma
,
797 s3cmci_dma_done_callback
);
798 s3c2410_dma_setflags(host
->dma
, S3C2410_DMAF_AUTOSTART
);
803 static void s3cmci_send_command(struct s3cmci_host
*host
,
804 struct mmc_command
*cmd
)
808 imsk
= S3C2410_SDIIMSK_CRCSTATUS
| S3C2410_SDIIMSK_CMDTIMEOUT
|
809 S3C2410_SDIIMSK_RESPONSEND
| S3C2410_SDIIMSK_CMDSENT
|
810 S3C2410_SDIIMSK_RESPONSECRC
;
812 enable_imask(host
, imsk
);
815 host
->complete_what
= COMPLETION_XFERFINISH_RSPFIN
;
816 else if (cmd
->flags
& MMC_RSP_PRESENT
)
817 host
->complete_what
= COMPLETION_RSPFIN
;
819 host
->complete_what
= COMPLETION_CMDSENT
;
821 writel(cmd
->arg
, host
->base
+ S3C2410_SDICMDARG
);
823 ccon
= cmd
->opcode
& S3C2410_SDICMDCON_INDEX
;
824 ccon
|= S3C2410_SDICMDCON_SENDERHOST
| S3C2410_SDICMDCON_CMDSTART
;
826 if (cmd
->flags
& MMC_RSP_PRESENT
)
827 ccon
|= S3C2410_SDICMDCON_WAITRSP
;
829 if (cmd
->flags
& MMC_RSP_136
)
830 ccon
|= S3C2410_SDICMDCON_LONGRSP
;
832 writel(ccon
, host
->base
+ S3C2410_SDICMDCON
);
835 static int s3cmci_setup_data(struct s3cmci_host
*host
, struct mmc_data
*data
)
837 u32 dcon
, imsk
, stoptries
= 3;
839 /* write DCON register */
842 writel(0, host
->base
+ S3C2410_SDIDCON
);
846 if ((data
->blksz
& 3) != 0) {
847 /* We cannot deal with unaligned blocks with more than
848 * one block being transfered. */
850 if (data
->blocks
> 1) {
851 pr_warning("%s: can't do non-word sized block transfers (blksz %d)\n", __func__
, data
->blksz
);
856 while (readl(host
->base
+ S3C2410_SDIDSTA
) &
857 (S3C2410_SDIDSTA_TXDATAON
| S3C2410_SDIDSTA_RXDATAON
)) {
860 "mci_setup_data() transfer stillin progress.\n");
862 writel(S3C2410_SDIDCON_STOP
, host
->base
+ S3C2410_SDIDCON
);
865 if ((stoptries
--) == 0) {
866 dbg_dumpregs(host
, "DRF");
871 dcon
= data
->blocks
& S3C2410_SDIDCON_BLKNUM_MASK
;
874 dcon
|= S3C2410_SDIDCON_DMAEN
;
876 if (host
->bus_width
== MMC_BUS_WIDTH_4
)
877 dcon
|= S3C2410_SDIDCON_WIDEBUS
;
879 if (!(data
->flags
& MMC_DATA_STREAM
))
880 dcon
|= S3C2410_SDIDCON_BLOCKMODE
;
882 if (data
->flags
& MMC_DATA_WRITE
) {
883 dcon
|= S3C2410_SDIDCON_TXAFTERRESP
;
884 dcon
|= S3C2410_SDIDCON_XFER_TXSTART
;
887 if (data
->flags
& MMC_DATA_READ
) {
888 dcon
|= S3C2410_SDIDCON_RXAFTERCMD
;
889 dcon
|= S3C2410_SDIDCON_XFER_RXSTART
;
893 dcon
|= S3C2440_SDIDCON_DS_WORD
;
894 dcon
|= S3C2440_SDIDCON_DATSTART
;
897 writel(dcon
, host
->base
+ S3C2410_SDIDCON
);
899 /* write BSIZE register */
901 writel(data
->blksz
, host
->base
+ S3C2410_SDIBSIZE
);
903 /* add to IMASK register */
904 imsk
= S3C2410_SDIIMSK_FIFOFAIL
| S3C2410_SDIIMSK_DATACRC
|
905 S3C2410_SDIIMSK_DATATIMEOUT
| S3C2410_SDIIMSK_DATAFINISH
;
907 enable_imask(host
, imsk
);
909 /* write TIMER register */
912 writel(0x007FFFFF, host
->base
+ S3C2410_SDITIMER
);
914 writel(0x0000FFFF, host
->base
+ S3C2410_SDITIMER
);
916 /* FIX: set slow clock to prevent timeouts on read */
917 if (data
->flags
& MMC_DATA_READ
)
918 writel(0xFF, host
->base
+ S3C2410_SDIPRE
);
924 #define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
926 static int s3cmci_prepare_pio(struct s3cmci_host
*host
, struct mmc_data
*data
)
928 int rw
= (data
->flags
& MMC_DATA_WRITE
) ? 1 : 0;
930 BUG_ON((data
->flags
& BOTH_DIR
) == BOTH_DIR
);
935 host
->pio_active
= rw
? XFER_WRITE
: XFER_READ
;
939 enable_imask(host
, S3C2410_SDIIMSK_TXFIFOHALF
);
941 enable_imask(host
, S3C2410_SDIIMSK_RXFIFOHALF
942 | S3C2410_SDIIMSK_RXFIFOLAST
);
948 static int s3cmci_prepare_dma(struct s3cmci_host
*host
, struct mmc_data
*data
)
951 int rw
= (data
->flags
& MMC_DATA_WRITE
) ? 1 : 0;
953 BUG_ON((data
->flags
& BOTH_DIR
) == BOTH_DIR
);
955 s3cmci_dma_setup(host
, rw
? S3C2410_DMASRC_MEM
: S3C2410_DMASRC_HW
);
956 s3c2410_dma_ctrl(host
->dma
, S3C2410_DMAOP_FLUSH
);
958 dma_len
= dma_map_sg(mmc_dev(host
->mmc
), data
->sg
, data
->sg_len
,
959 (rw
) ? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
964 host
->dma_complete
= 0;
965 host
->dmatogo
= dma_len
;
967 for (i
= 0; i
< dma_len
; i
++) {
970 dbg(host
, dbg_dma
, "enqueue %i:%u@%u\n", i
,
971 sg_dma_address(&data
->sg
[i
]),
972 sg_dma_len(&data
->sg
[i
]));
974 res
= s3c2410_dma_enqueue(host
->dma
, (void *) host
,
975 sg_dma_address(&data
->sg
[i
]),
976 sg_dma_len(&data
->sg
[i
]));
979 s3c2410_dma_ctrl(host
->dma
, S3C2410_DMAOP_FLUSH
);
984 s3c2410_dma_ctrl(host
->dma
, S3C2410_DMAOP_START
);
989 static void s3cmci_send_request(struct mmc_host
*mmc
)
991 struct s3cmci_host
*host
= mmc_priv(mmc
);
992 struct mmc_request
*mrq
= host
->mrq
;
993 struct mmc_command
*cmd
= host
->cmd_is_stop
? mrq
->stop
: mrq
->cmd
;
996 prepare_dbgmsg(host
, cmd
, host
->cmd_is_stop
);
998 /* Clear command, data and fifo status registers
999 Fifo clear only necessary on 2440, but doesn't hurt on 2410
1001 writel(0xFFFFFFFF, host
->base
+ S3C2410_SDICMDSTAT
);
1002 writel(0xFFFFFFFF, host
->base
+ S3C2410_SDIDSTA
);
1003 writel(0xFFFFFFFF, host
->base
+ S3C2410_SDIFSTA
);
1006 int res
= s3cmci_setup_data(host
, cmd
->data
);
1011 dbg(host
, dbg_err
, "setup data error %d\n", res
);
1013 cmd
->data
->error
= res
;
1015 mmc_request_done(mmc
, mrq
);
1020 res
= s3cmci_prepare_dma(host
, cmd
->data
);
1022 res
= s3cmci_prepare_pio(host
, cmd
->data
);
1025 dbg(host
, dbg_err
, "data prepare error %d\n", res
);
1027 cmd
->data
->error
= res
;
1029 mmc_request_done(mmc
, mrq
);
1035 s3cmci_send_command(host
, cmd
);
1037 /* Enable Interrupt */
1038 enable_irq(host
->irq
);
1041 static int s3cmci_card_present(struct mmc_host
*mmc
)
1043 struct s3cmci_host
*host
= mmc_priv(mmc
);
1044 struct s3c24xx_mci_pdata
*pdata
= host
->pdata
;
1047 if (pdata
->gpio_detect
== 0)
1050 ret
= gpio_get_value(pdata
->gpio_detect
) ? 0 : 1;
1051 return ret
^ pdata
->detect_invert
;
1054 static void s3cmci_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
1056 struct s3cmci_host
*host
= mmc_priv(mmc
);
1058 host
->status
= "mmc request";
1059 host
->cmd_is_stop
= 0;
1062 if (s3cmci_card_present(mmc
) == 0) {
1063 dbg(host
, dbg_err
, "%s: no medium present\n", __func__
);
1064 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
1065 mmc_request_done(mmc
, mrq
);
1067 s3cmci_send_request(mmc
);
1070 static void s3cmci_set_clk(struct s3cmci_host
*host
, struct mmc_ios
*ios
)
1075 for (mci_psc
= 0; mci_psc
< 255; mci_psc
++) {
1076 host
->real_rate
= host
->clk_rate
/ (host
->clk_div
*(mci_psc
+1));
1078 if (host
->real_rate
<= ios
->clock
)
1085 host
->prescaler
= mci_psc
;
1086 writel(host
->prescaler
, host
->base
+ S3C2410_SDIPRE
);
1088 /* If requested clock is 0, real_rate will be 0, too */
1089 if (ios
->clock
== 0)
1090 host
->real_rate
= 0;
1093 static void s3cmci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1095 struct s3cmci_host
*host
= mmc_priv(mmc
);
1098 /* Set the power state */
1100 mci_con
= readl(host
->base
+ S3C2410_SDICON
);
1102 switch (ios
->power_mode
) {
1105 s3c2410_gpio_cfgpin(S3C2410_GPE(5), S3C2410_GPE5_SDCLK
);
1106 s3c2410_gpio_cfgpin(S3C2410_GPE(6), S3C2410_GPE6_SDCMD
);
1107 s3c2410_gpio_cfgpin(S3C2410_GPE(7), S3C2410_GPE7_SDDAT0
);
1108 s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1
);
1109 s3c2410_gpio_cfgpin(S3C2410_GPE(9), S3C2410_GPE9_SDDAT2
);
1110 s3c2410_gpio_cfgpin(S3C2410_GPE(10), S3C2410_GPE10_SDDAT3
);
1112 if (host
->pdata
->set_power
)
1113 host
->pdata
->set_power(ios
->power_mode
, ios
->vdd
);
1116 mci_con
|= S3C2410_SDICON_FIFORESET
;
1122 gpio_direction_output(S3C2410_GPE(5), 0);
1125 mci_con
|= S3C2440_SDICON_SDRESET
;
1127 if (host
->pdata
->set_power
)
1128 host
->pdata
->set_power(ios
->power_mode
, ios
->vdd
);
1133 s3cmci_set_clk(host
, ios
);
1135 /* Set CLOCK_ENABLE */
1137 mci_con
|= S3C2410_SDICON_CLOCKTYPE
;
1139 mci_con
&= ~S3C2410_SDICON_CLOCKTYPE
;
1141 writel(mci_con
, host
->base
+ S3C2410_SDICON
);
1143 if ((ios
->power_mode
== MMC_POWER_ON
) ||
1144 (ios
->power_mode
== MMC_POWER_UP
)) {
1145 dbg(host
, dbg_conf
, "running at %lukHz (requested: %ukHz).\n",
1146 host
->real_rate
/1000, ios
->clock
/1000);
1148 dbg(host
, dbg_conf
, "powered down.\n");
1151 host
->bus_width
= ios
->bus_width
;
1154 static void s3cmci_reset(struct s3cmci_host
*host
)
1156 u32 con
= readl(host
->base
+ S3C2410_SDICON
);
1158 con
|= S3C2440_SDICON_SDRESET
;
1159 writel(con
, host
->base
+ S3C2410_SDICON
);
1162 static int s3cmci_get_ro(struct mmc_host
*mmc
)
1164 struct s3cmci_host
*host
= mmc_priv(mmc
);
1165 struct s3c24xx_mci_pdata
*pdata
= host
->pdata
;
1168 if (pdata
->gpio_wprotect
== 0)
1171 ret
= s3c2410_gpio_getpin(pdata
->gpio_wprotect
);
1173 if (pdata
->wprotect_invert
)
1179 static struct mmc_host_ops s3cmci_ops
= {
1180 .request
= s3cmci_request
,
1181 .set_ios
= s3cmci_set_ios
,
1182 .get_ro
= s3cmci_get_ro
,
1183 .get_cd
= s3cmci_card_present
,
1186 static struct s3c24xx_mci_pdata s3cmci_def_pdata
= {
1187 /* This is currently here to avoid a number of if (host->pdata)
1188 * checks. Any zero fields to ensure reaonable defaults are picked. */
1191 #ifdef CONFIG_CPU_FREQ
1193 static int s3cmci_cpufreq_transition(struct notifier_block
*nb
,
1194 unsigned long val
, void *data
)
1196 struct s3cmci_host
*host
;
1197 struct mmc_host
*mmc
;
1198 unsigned long newclk
;
1199 unsigned long flags
;
1201 host
= container_of(nb
, struct s3cmci_host
, freq_transition
);
1202 newclk
= clk_get_rate(host
->clk
);
1205 if ((val
== CPUFREQ_PRECHANGE
&& newclk
> host
->clk_rate
) ||
1206 (val
== CPUFREQ_POSTCHANGE
&& newclk
< host
->clk_rate
)) {
1207 spin_lock_irqsave(&mmc
->lock
, flags
);
1209 host
->clk_rate
= newclk
;
1211 if (mmc
->ios
.power_mode
!= MMC_POWER_OFF
&&
1212 mmc
->ios
.clock
!= 0)
1213 s3cmci_set_clk(host
, &mmc
->ios
);
1215 spin_unlock_irqrestore(&mmc
->lock
, flags
);
1221 static inline int s3cmci_cpufreq_register(struct s3cmci_host
*host
)
1223 host
->freq_transition
.notifier_call
= s3cmci_cpufreq_transition
;
1225 return cpufreq_register_notifier(&host
->freq_transition
,
1226 CPUFREQ_TRANSITION_NOTIFIER
);
1229 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host
*host
)
1231 cpufreq_unregister_notifier(&host
->freq_transition
,
1232 CPUFREQ_TRANSITION_NOTIFIER
);
1236 static inline int s3cmci_cpufreq_register(struct s3cmci_host
*host
)
1241 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host
*host
)
1247 static int __devinit
s3cmci_probe(struct platform_device
*pdev
)
1249 struct s3cmci_host
*host
;
1250 struct mmc_host
*mmc
;
1255 is2440
= platform_get_device_id(pdev
)->driver_data
;
1257 mmc
= mmc_alloc_host(sizeof(struct s3cmci_host
), &pdev
->dev
);
1263 for (i
= S3C2410_GPE(5); i
<= S3C2410_GPE(10); i
++) {
1264 ret
= gpio_request(i
, dev_name(&pdev
->dev
));
1266 dev_err(&pdev
->dev
, "failed to get gpio %d\n", i
);
1268 for (i
--; i
>= S3C2410_GPE(5); i
--)
1271 goto probe_free_host
;
1275 host
= mmc_priv(mmc
);
1278 host
->is2440
= is2440
;
1280 host
->pdata
= pdev
->dev
.platform_data
;
1282 pdev
->dev
.platform_data
= &s3cmci_def_pdata
;
1283 host
->pdata
= &s3cmci_def_pdata
;
1286 spin_lock_init(&host
->complete_lock
);
1287 tasklet_init(&host
->pio_tasklet
, pio_tasklet
, (unsigned long) host
);
1290 host
->sdiimsk
= S3C2440_SDIIMSK
;
1291 host
->sdidata
= S3C2440_SDIDATA
;
1294 host
->sdiimsk
= S3C2410_SDIIMSK
;
1295 host
->sdidata
= S3C2410_SDIDATA
;
1300 host
->complete_what
= COMPLETION_NONE
;
1301 host
->pio_active
= XFER_NONE
;
1303 host
->dma
= S3CMCI_DMA
;
1305 host
->mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1308 "failed to get io memory region resouce.\n");
1311 goto probe_free_gpio
;
1314 host
->mem
= request_mem_region(host
->mem
->start
,
1315 resource_size(host
->mem
), pdev
->name
);
1318 dev_err(&pdev
->dev
, "failed to request io memory region.\n");
1320 goto probe_free_gpio
;
1323 host
->base
= ioremap(host
->mem
->start
, resource_size(host
->mem
));
1325 dev_err(&pdev
->dev
, "failed to ioremap() io memory region.\n");
1327 goto probe_free_mem_region
;
1330 host
->irq
= platform_get_irq(pdev
, 0);
1331 if (host
->irq
== 0) {
1332 dev_err(&pdev
->dev
, "failed to get interrupt resouce.\n");
1337 if (request_irq(host
->irq
, s3cmci_irq
, 0, DRIVER_NAME
, host
)) {
1338 dev_err(&pdev
->dev
, "failed to request mci interrupt.\n");
1343 /* We get spurious interrupts even when we have set the IMSK
1344 * register to ignore everything, so use disable_irq() to make
1345 * ensure we don't lock the system with un-serviceable requests. */
1347 disable_irq(host
->irq
);
1349 if (host
->pdata
->gpio_detect
) {
1350 ret
= gpio_request(host
->pdata
->gpio_detect
, "s3cmci detect");
1352 dev_err(&pdev
->dev
, "failed to get detect gpio\n");
1353 goto probe_free_irq
;
1357 host
->irq_cd
= s3c2410_gpio_getirq(host
->pdata
->gpio_detect
);
1359 if (host
->irq_cd
>= 0) {
1360 if (request_irq(host
->irq_cd
, s3cmci_irq_cd
,
1361 IRQF_TRIGGER_RISING
| IRQF_TRIGGER_FALLING
,
1362 DRIVER_NAME
, host
)) {
1363 dev_err(&pdev
->dev
, "can't get card detect irq.\n");
1365 goto probe_free_gpio_cd
;
1368 dev_warn(&pdev
->dev
, "host detect has no irq available\n");
1369 gpio_direction_input(host
->pdata
->gpio_detect
);
1372 if (host
->pdata
->gpio_wprotect
) {
1373 ret
= gpio_request(host
->pdata
->gpio_wprotect
, "s3cmci wp");
1375 dev_err(&pdev
->dev
, "failed to get writeprotect\n");
1376 goto probe_free_irq_cd
;
1379 gpio_direction_input(host
->pdata
->gpio_wprotect
);
1382 if (s3c2410_dma_request(S3CMCI_DMA
, &s3cmci_dma_client
, NULL
) < 0) {
1383 dev_err(&pdev
->dev
, "unable to get DMA channel.\n");
1385 goto probe_free_gpio_wp
;
1388 host
->clk
= clk_get(&pdev
->dev
, "sdi");
1389 if (IS_ERR(host
->clk
)) {
1390 dev_err(&pdev
->dev
, "failed to find clock source.\n");
1391 ret
= PTR_ERR(host
->clk
);
1393 goto probe_free_host
;
1396 ret
= clk_enable(host
->clk
);
1398 dev_err(&pdev
->dev
, "failed to enable clock source.\n");
1402 host
->clk_rate
= clk_get_rate(host
->clk
);
1404 mmc
->ops
= &s3cmci_ops
;
1405 mmc
->ocr_avail
= MMC_VDD_32_33
| MMC_VDD_33_34
;
1406 mmc
->caps
= MMC_CAP_4_BIT_DATA
;
1407 mmc
->f_min
= host
->clk_rate
/ (host
->clk_div
* 256);
1408 mmc
->f_max
= host
->clk_rate
/ host
->clk_div
;
1410 if (host
->pdata
->ocr_avail
)
1411 mmc
->ocr_avail
= host
->pdata
->ocr_avail
;
1413 mmc
->max_blk_count
= 4095;
1414 mmc
->max_blk_size
= 4095;
1415 mmc
->max_req_size
= 4095 * 512;
1416 mmc
->max_seg_size
= mmc
->max_req_size
;
1418 mmc
->max_phys_segs
= 128;
1419 mmc
->max_hw_segs
= 128;
1421 dbg(host
, dbg_debug
,
1422 "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%u.\n",
1423 (host
->is2440
?"2440":""),
1424 host
->base
, host
->irq
, host
->irq_cd
, host
->dma
);
1426 ret
= s3cmci_cpufreq_register(host
);
1428 dev_err(&pdev
->dev
, "failed to register cpufreq\n");
1432 ret
= mmc_add_host(mmc
);
1434 dev_err(&pdev
->dev
, "failed to add mmc host.\n");
1438 platform_set_drvdata(pdev
, mmc
);
1439 dev_info(&pdev
->dev
, "initialisation done.\n");
1444 s3cmci_cpufreq_deregister(host
);
1447 clk_disable(host
->clk
);
1453 if (host
->pdata
->gpio_wprotect
)
1454 gpio_free(host
->pdata
->gpio_wprotect
);
1457 if (host
->pdata
->gpio_detect
)
1458 gpio_free(host
->pdata
->gpio_detect
);
1461 if (host
->irq_cd
>= 0)
1462 free_irq(host
->irq_cd
, host
);
1465 free_irq(host
->irq
, host
);
1468 iounmap(host
->base
);
1470 probe_free_mem_region
:
1471 release_mem_region(host
->mem
->start
, resource_size(host
->mem
));
1474 for (i
= S3C2410_GPE(5); i
<= S3C2410_GPE(10); i
++)
1484 static void s3cmci_shutdown(struct platform_device
*pdev
)
1486 struct mmc_host
*mmc
= platform_get_drvdata(pdev
);
1487 struct s3cmci_host
*host
= mmc_priv(mmc
);
1489 if (host
->irq_cd
>= 0)
1490 free_irq(host
->irq_cd
, host
);
1492 s3cmci_cpufreq_deregister(host
);
1493 mmc_remove_host(mmc
);
1494 clk_disable(host
->clk
);
1497 static int __devexit
s3cmci_remove(struct platform_device
*pdev
)
1499 struct mmc_host
*mmc
= platform_get_drvdata(pdev
);
1500 struct s3cmci_host
*host
= mmc_priv(mmc
);
1501 struct s3c24xx_mci_pdata
*pd
= host
->pdata
;
1504 s3cmci_shutdown(pdev
);
1508 tasklet_disable(&host
->pio_tasklet
);
1509 s3c2410_dma_free(S3CMCI_DMA
, &s3cmci_dma_client
);
1511 free_irq(host
->irq
, host
);
1513 if (pd
->gpio_wprotect
)
1514 gpio_free(pd
->gpio_wprotect
);
1516 if (pd
->gpio_detect
)
1517 gpio_free(pd
->gpio_detect
);
1519 for (i
= S3C2410_GPE(5); i
<= S3C2410_GPE(10); i
++)
1523 iounmap(host
->base
);
1524 release_mem_region(host
->mem
->start
, resource_size(host
->mem
));
1530 static struct platform_device_id s3cmci_driver_ids
[] = {
1532 .name
= "s3c2410-sdi",
1535 .name
= "s3c2412-sdi",
1538 .name
= "s3c2440-sdi",
1544 MODULE_DEVICE_TABLE(platform
, s3cmci_driver_ids
);
1549 static int s3cmci_suspend(struct device
*dev
)
1551 struct mmc_host
*mmc
= platform_get_drvdata(to_platform_device(dev
));
1552 struct pm_message event
= { PM_EVENT_SUSPEND
};
1554 return mmc_suspend_host(mmc
, event
);
1557 static int s3cmci_resume(struct device
*dev
)
1559 struct mmc_host
*mmc
= platform_get_drvdata(to_platform_device(dev
));
1561 return mmc_resume_host(mmc
);
1564 static struct dev_pm_ops s3cmci_pm
= {
1565 .suspend
= s3cmci_suspend
,
1566 .resume
= s3cmci_resume
,
1569 #define s3cmci_pm_ops &s3cmci_pm
1570 #else /* CONFIG_PM */
1571 #define s3cmci_pm_ops NULL
1572 #endif /* CONFIG_PM */
1575 static struct platform_driver s3cmci_driver
= {
1578 .owner
= THIS_MODULE
,
1579 .pm
= s3cmci_pm_ops
,
1581 .id_table
= s3cmci_driver_ids
,
1582 .probe
= s3cmci_probe
,
1583 .remove
= __devexit_p(s3cmci_remove
),
1584 .shutdown
= s3cmci_shutdown
,
1587 static int __init
s3cmci_init(void)
1589 return platform_driver_register(&s3cmci_driver
);
1592 static void __exit
s3cmci_exit(void)
1594 platform_driver_unregister(&s3cmci_driver
);
1597 module_init(s3cmci_init
);
1598 module_exit(s3cmci_exit
);
1600 MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
1601 MODULE_LICENSE("GPL v2");
1602 MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>");