arch/x86/include/asm/io_apic.h

   1 #ifndef _ASM_X86_IO_APIC_H
   2 #define _ASM_X86_IO_APIC_H
   3
   4 #include <linux/types.h>
   5 #include <asm/mpspec.h>
   6 #include <asm/apicdef.h>
   7 #include <asm/irq_vectors.h>
   8 #include <asm/x86_init.h>
   9 /*
  10  * Intel IO-APIC support for SMP and UP systems.
  11  *
  12  * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
  13  */
  14
  15 /* I/O Unit Redirection Table */
  16 #define IO_APIC_REDIR_VECTOR_MASK       0x000FF
  17 #define IO_APIC_REDIR_DEST_LOGICAL      0x00800
  18 #define IO_APIC_REDIR_DEST_PHYSICAL     0x00000
  19 #define IO_APIC_REDIR_SEND_PENDING      (1 << 12)
  20 #define IO_APIC_REDIR_REMOTE_IRR        (1 << 14)
  21 #define IO_APIC_REDIR_LEVEL_TRIGGER     (1 << 15)
  22 #define IO_APIC_REDIR_MASKED            (1 << 16)
  23
  24 /*
  25  * The structure of the IO-APIC:
  26  */
  27 union IO_APIC_reg_00 {
  28         u32     raw;
  29         struct {
  30                 u32     __reserved_2    : 14,
  31                         LTS             :  1,
  32                         delivery_type   :  1,
  33                         __reserved_1    :  8,
  34                         ID              :  8;
  35         } __attribute__ ((packed)) bits;
  36 };
  37
  38 union IO_APIC_reg_01 {
  39         u32     raw;
  40         struct {
  41                 u32     version         :  8,
  42                         __reserved_2    :  7,
  43                         PRQ             :  1,
  44                         entries         :  8,
  45                         __reserved_1    :  8;
  46         } __attribute__ ((packed)) bits;
  47 };
  48
  49 union IO_APIC_reg_02 {
  50         u32     raw;
  51         struct {
  52                 u32     __reserved_2    : 24,
  53                         arbitration     :  4,
  54                         __reserved_1    :  4;
  55         } __attribute__ ((packed)) bits;
  56 };
  57
  58 union IO_APIC_reg_03 {
  59         u32     raw;
  60         struct {
  61                 u32     boot_DT         :  1,
  62                         __reserved_1    : 31;
  63         } __attribute__ ((packed)) bits;
  64 };
  65
  66 struct IO_APIC_route_entry {
  67         __u32   vector          :  8,
  68                 delivery_mode   :  3,   /* 000: FIXED
  69                                          * 001: lowest prio
  70                                          * 111: ExtINT
  71                                          */
  72                 dest_mode       :  1,   /* 0: physical, 1: logical */
  73                 delivery_status :  1,
  74                 polarity        :  1,
  75                 irr             :  1,
  76                 trigger         :  1,   /* 0: edge, 1: level */
  77                 mask            :  1,   /* 0: enabled, 1: disabled */
  78                 __reserved_2    : 15;
  79
  80         __u32   __reserved_3    : 24,
  81                 dest            :  8;
  82 } __attribute__ ((packed));
  83
  84 struct IR_IO_APIC_route_entry {
  85         __u64   vector          : 8,
  86                 zero            : 3,
  87                 index2          : 1,
  88                 delivery_status : 1,
  89                 polarity        : 1,
  90                 irr             : 1,
  91                 trigger         : 1,
  92                 mask            : 1,
  93                 reserved        : 31,
  94                 format          : 1,
  95                 index           : 15;
  96 } __attribute__ ((packed));
  97
  98 struct irq_alloc_info;
  99 struct irq_data;
 100
 101 #define IOAPIC_AUTO     -1
 102 #define IOAPIC_EDGE     0
 103 #define IOAPIC_LEVEL    1
 104 #define IOAPIC_MAP_ALLOC                0x1
 105 #define IOAPIC_MAP_CHECK                0x2
 106
 107 #ifdef CONFIG_X86_IO_APIC
 108
 109 /*
 110  * # of IO-APICs and # of IRQ routing registers
 111  */
 112 extern int nr_ioapics;
 113
 114 extern int mpc_ioapic_id(int ioapic);
 115 extern unsigned int mpc_ioapic_addr(int ioapic);
 116 extern struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic);
 117
 118 #define MP_MAX_IOAPIC_PIN 127
 119
 120 /* # of MP IRQ source entries */
 121 extern int mp_irq_entries;
 122
 123 /* MP IRQ source entries */
 124 extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
 125
 126 /* Older SiS APIC requires we rewrite the index register */
 127 extern int sis_apic_bug;
 128
 129 /* 1 if "noapic" boot option passed */
 130 extern int skip_ioapic_setup;
 131
 132 /* 1 if "noapic" boot option passed */
 133 extern int noioapicquirk;
 134
 135 /* -1 if "noapic" boot option passed */
 136 extern int noioapicreroute;
 137
 138 extern unsigned long io_apic_irqs;
 139
 140 #define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1 << (x)) & io_apic_irqs))
 141
 142 /*
 143  * If we use the IO-APIC for IRQ routing, disable automatic
 144  * assignment of PCI IRQ's.
 145  */
 146 #define io_apic_assign_pci_irqs \
 147         (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
 148
 149 struct irq_cfg;
 150 extern void ioapic_insert_resources(void);
 151 extern int arch_early_ioapic_init(void);
 152
 153 extern int save_ioapic_entries(void);
 154 extern void mask_ioapic_entries(void);
 155 extern int restore_ioapic_entries(void);
 156
 157 extern void setup_ioapic_ids_from_mpc(void);
 158 extern void setup_ioapic_ids_from_mpc_nocheck(void);
 159
 160 enum ioapic_domain_type {
 161         IOAPIC_DOMAIN_INVALID,
 162         IOAPIC_DOMAIN_LEGACY,
 163         IOAPIC_DOMAIN_STRICT,
 164         IOAPIC_DOMAIN_DYNAMIC,
 165 };
 166
 167 struct device_node;
 168 struct irq_domain;
 169 struct irq_domain_ops;
 170
 171 struct ioapic_domain_cfg {
 172         enum ioapic_domain_type         type;
 173         const struct irq_domain_ops     *ops;
 174         struct device_node              *dev;
 175 };
 176
 177 struct mp_ioapic_gsi{
 178         u32 gsi_base;
 179         u32 gsi_end;
 180 };
 181 extern u32 gsi_top;
 182
 183 extern int mp_find_ioapic(u32 gsi);
 184 extern int mp_find_ioapic_pin(int ioapic, u32 gsi);
 185 extern u32 mp_pin_to_gsi(int ioapic, int pin);
 186 extern int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
 187                              struct irq_alloc_info *info);
 188 extern void mp_unmap_irq(int irq);
 189 extern int mp_register_ioapic(int id, u32 address, u32 gsi_base,
 190                               struct ioapic_domain_cfg *cfg);
 191 extern int mp_unregister_ioapic(u32 gsi_base);
 192 extern int mp_ioapic_registered(u32 gsi_base);
 193 extern int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
 194                               unsigned int nr_irqs, void *arg);
 195 extern void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
 196                               unsigned int nr_irqs);
 197 extern void mp_irqdomain_activate(struct irq_domain *domain,
 198                                   struct irq_data *irq_data);
 199 extern void mp_irqdomain_deactivate(struct irq_domain *domain,
 200                                     struct irq_data *irq_data);
 201 extern int mp_irqdomain_ioapic_idx(struct irq_domain *domain);
 202 extern void ioapic_set_alloc_attr(struct irq_alloc_info *info,
 203                                   int node, int trigger, int polarity);
 204
 205 extern void mp_save_irq(struct mpc_intsrc *m);
 206
 207 extern void disable_ioapic_support(void);
 208
 209 extern void __init native_io_apic_init_mappings(void);
 210 extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg);
 211 extern void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int val);
 212 extern void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int val);
 213 extern void native_disable_io_apic(void);
 214
 215 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 216 {
 217         return x86_io_apic_ops.read(apic, reg);
 218 }
 219
 220 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 221 {
 222         x86_io_apic_ops.write(apic, reg, value);
 223 }
 224 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
 225 {
 226         x86_io_apic_ops.modify(apic, reg, value);
 227 }
 228
 229 extern void setup_IO_APIC(void);
 230 extern void enable_IO_APIC(void);
 231 extern void disable_IO_APIC(void);
 232 extern void setup_ioapic_dest(void);
 233 extern int IO_APIC_get_PCI_irq_vector(int bus, int devfn, int pin);
 234 extern void print_IO_APICs(void);
 235 #else  /* !CONFIG_X86_IO_APIC */
 236
 237 #define IO_APIC_IRQ(x)          0
 238 #define io_apic_assign_pci_irqs 0
 239 #define setup_ioapic_ids_from_mpc x86_init_noop
 240 static inline void ioapic_insert_resources(void) { }
 241 static inline int arch_early_ioapic_init(void) { return 0; }
 242 static inline void print_IO_APICs(void) {}
 243 #define gsi_top (NR_IRQS_LEGACY)
 244 static inline int mp_find_ioapic(u32 gsi) { return 0; }
 245 static inline u32 mp_pin_to_gsi(int ioapic, int pin) { return UINT_MAX; }
 246 static inline int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
 247                                     struct irq_alloc_info *info)
 248 {
 249         return gsi;
 250 }
 251
 252 static inline void mp_unmap_irq(int irq) { }
 253
 254 static inline int save_ioapic_entries(void)
 255 {
 256         return -ENOMEM;
 257 }
 258
 259 static inline void mask_ioapic_entries(void) { }
 260 static inline int restore_ioapic_entries(void)
 261 {
 262         return -ENOMEM;
 263 }
 264
 265 static inline void mp_save_irq(struct mpc_intsrc *m) { };
 266 static inline void disable_ioapic_support(void) { }
 267 #define native_io_apic_init_mappings    NULL
 268 #define native_io_apic_read             NULL
 269 #define native_io_apic_write            NULL
 270 #define native_io_apic_modify           NULL
 271 #define native_disable_io_apic          NULL
 272
 273 static inline void setup_IO_APIC(void) { }
 274 static inline void enable_IO_APIC(void) { }
 275 static inline void setup_ioapic_dest(void) { }
 276
 277 #endif
 278
 279 #endif /* _ASM_X86_IO_APIC_H */