1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
23 #include <linux/pci.h>
24 #include <linux/module.h>
25 #include <linux/slab.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/highmem.h>
28 #include <linux/interrupt.h>
29 #include <linux/delay.h>
30 #include <linux/idr.h>
31 #include <linux/platform_device.h>
32 #include <linux/mfd/core.h>
33 #include <linux/mfd/rtsx_pci.h>
34 #include <asm/unaligned.h>
38 static bool msi_en
= true;
39 module_param(msi_en
, bool, S_IRUGO
| S_IWUSR
);
40 MODULE_PARM_DESC(msi_en
, "Enable MSI");
42 static DEFINE_IDR(rtsx_pci_idr
);
43 static DEFINE_SPINLOCK(rtsx_pci_lock
);
45 static struct mfd_cell rtsx_pcr_cells
[] = {
47 .name
= DRV_NAME_RTSX_PCI_SDMMC
,
50 .name
= DRV_NAME_RTSX_PCI_MS
,
54 static DEFINE_PCI_DEVICE_TABLE(rtsx_pci_ids
) = {
55 { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
56 { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
57 { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
61 MODULE_DEVICE_TABLE(pci
, rtsx_pci_ids
);
63 void rtsx_pci_start_run(struct rtsx_pcr
*pcr
)
65 /* If pci device removed, don't queue idle work any more */
69 if (pcr
->state
!= PDEV_STAT_RUN
) {
70 pcr
->state
= PDEV_STAT_RUN
;
71 if (pcr
->ops
->enable_auto_blink
)
72 pcr
->ops
->enable_auto_blink(pcr
);
75 mod_delayed_work(system_wq
, &pcr
->idle_work
, msecs_to_jiffies(200));
77 EXPORT_SYMBOL_GPL(rtsx_pci_start_run
);
79 int rtsx_pci_write_register(struct rtsx_pcr
*pcr
, u16 addr
, u8 mask
, u8 data
)
82 u32 val
= HAIMR_WRITE_START
;
84 val
|= (u32
)(addr
& 0x3FFF) << 16;
85 val
|= (u32
)mask
<< 8;
88 rtsx_pci_writel(pcr
, RTSX_HAIMR
, val
);
90 for (i
= 0; i
< MAX_RW_REG_CNT
; i
++) {
91 val
= rtsx_pci_readl(pcr
, RTSX_HAIMR
);
92 if ((val
& HAIMR_TRANS_END
) == 0) {
101 EXPORT_SYMBOL_GPL(rtsx_pci_write_register
);
103 int rtsx_pci_read_register(struct rtsx_pcr
*pcr
, u16 addr
, u8
*data
)
105 u32 val
= HAIMR_READ_START
;
108 val
|= (u32
)(addr
& 0x3FFF) << 16;
109 rtsx_pci_writel(pcr
, RTSX_HAIMR
, val
);
111 for (i
= 0; i
< MAX_RW_REG_CNT
; i
++) {
112 val
= rtsx_pci_readl(pcr
, RTSX_HAIMR
);
113 if ((val
& HAIMR_TRANS_END
) == 0)
117 if (i
>= MAX_RW_REG_CNT
)
121 *data
= (u8
)(val
& 0xFF);
125 EXPORT_SYMBOL_GPL(rtsx_pci_read_register
);
127 int rtsx_pci_write_phy_register(struct rtsx_pcr
*pcr
, u8 addr
, u16 val
)
129 int err
, i
, finished
= 0;
132 rtsx_pci_init_cmd(pcr
);
134 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYDATA0
, 0xFF, (u8
)val
);
135 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYDATA1
, 0xFF, (u8
)(val
>> 8));
136 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYADDR
, 0xFF, addr
);
137 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYRWCTL
, 0xFF, 0x81);
139 err
= rtsx_pci_send_cmd(pcr
, 100);
143 for (i
= 0; i
< 100000; i
++) {
144 err
= rtsx_pci_read_register(pcr
, PHYRWCTL
, &tmp
);
159 EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register
);
161 int rtsx_pci_read_phy_register(struct rtsx_pcr
*pcr
, u8 addr
, u16
*val
)
163 int err
, i
, finished
= 0;
167 rtsx_pci_init_cmd(pcr
);
169 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYADDR
, 0xFF, addr
);
170 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYRWCTL
, 0xFF, 0x80);
172 err
= rtsx_pci_send_cmd(pcr
, 100);
176 for (i
= 0; i
< 100000; i
++) {
177 err
= rtsx_pci_read_register(pcr
, PHYRWCTL
, &tmp
);
190 rtsx_pci_init_cmd(pcr
);
192 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, PHYDATA0
, 0, 0);
193 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, PHYDATA1
, 0, 0);
195 err
= rtsx_pci_send_cmd(pcr
, 100);
199 ptr
= rtsx_pci_get_cmd_data(pcr
);
200 data
= ((u16
)ptr
[1] << 8) | ptr
[0];
207 EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register
);
209 void rtsx_pci_stop_cmd(struct rtsx_pcr
*pcr
)
211 rtsx_pci_writel(pcr
, RTSX_HCBCTLR
, STOP_CMD
);
212 rtsx_pci_writel(pcr
, RTSX_HDBCTLR
, STOP_DMA
);
214 rtsx_pci_write_register(pcr
, DMACTL
, 0x80, 0x80);
215 rtsx_pci_write_register(pcr
, RBCTL
, 0x80, 0x80);
217 EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd
);
219 void rtsx_pci_add_cmd(struct rtsx_pcr
*pcr
,
220 u8 cmd_type
, u16 reg_addr
, u8 mask
, u8 data
)
224 u32
*ptr
= (u32
*)(pcr
->host_cmds_ptr
);
226 val
|= (u32
)(cmd_type
& 0x03) << 30;
227 val
|= (u32
)(reg_addr
& 0x3FFF) << 16;
228 val
|= (u32
)mask
<< 8;
231 spin_lock_irqsave(&pcr
->lock
, flags
);
233 if (pcr
->ci
< (HOST_CMDS_BUF_LEN
/ 4)) {
234 put_unaligned_le32(val
, ptr
);
238 spin_unlock_irqrestore(&pcr
->lock
, flags
);
240 EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd
);
242 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr
*pcr
)
246 rtsx_pci_writel(pcr
, RTSX_HCBAR
, pcr
->host_cmds_addr
);
248 val
|= (u32
)(pcr
->ci
* 4) & 0x00FFFFFF;
249 /* Hardware Auto Response */
251 rtsx_pci_writel(pcr
, RTSX_HCBCTLR
, val
);
253 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait
);
255 int rtsx_pci_send_cmd(struct rtsx_pcr
*pcr
, int timeout
)
257 struct completion trans_done
;
263 spin_lock_irqsave(&pcr
->lock
, flags
);
265 /* set up data structures for the wakeup system */
266 pcr
->done
= &trans_done
;
267 pcr
->trans_result
= TRANS_NOT_READY
;
268 init_completion(&trans_done
);
270 rtsx_pci_writel(pcr
, RTSX_HCBAR
, pcr
->host_cmds_addr
);
272 val
|= (u32
)(pcr
->ci
* 4) & 0x00FFFFFF;
273 /* Hardware Auto Response */
275 rtsx_pci_writel(pcr
, RTSX_HCBCTLR
, val
);
277 spin_unlock_irqrestore(&pcr
->lock
, flags
);
279 /* Wait for TRANS_OK_INT */
280 timeleft
= wait_for_completion_interruptible_timeout(
281 &trans_done
, msecs_to_jiffies(timeout
));
283 dev_dbg(&(pcr
->pci
->dev
), "Timeout (%s %d)\n",
286 goto finish_send_cmd
;
289 spin_lock_irqsave(&pcr
->lock
, flags
);
290 if (pcr
->trans_result
== TRANS_RESULT_FAIL
)
292 else if (pcr
->trans_result
== TRANS_RESULT_OK
)
294 else if (pcr
->trans_result
== TRANS_NO_DEVICE
)
296 spin_unlock_irqrestore(&pcr
->lock
, flags
);
299 spin_lock_irqsave(&pcr
->lock
, flags
);
301 spin_unlock_irqrestore(&pcr
->lock
, flags
);
303 if ((err
< 0) && (err
!= -ENODEV
))
304 rtsx_pci_stop_cmd(pcr
);
307 complete(pcr
->finish_me
);
311 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd
);
313 static void rtsx_pci_add_sg_tbl(struct rtsx_pcr
*pcr
,
314 dma_addr_t addr
, unsigned int len
, int end
)
316 u64
*ptr
= (u64
*)(pcr
->host_sg_tbl_ptr
) + pcr
->sgi
;
318 u8 option
= SG_VALID
| SG_TRANS_DATA
;
320 dev_dbg(&(pcr
->pci
->dev
), "DMA addr: 0x%x, Len: 0x%x\n",
321 (unsigned int)addr
, len
);
325 val
= ((u64
)addr
<< 32) | ((u64
)len
<< 12) | option
;
327 put_unaligned_le64(val
, ptr
);
331 int rtsx_pci_transfer_data(struct rtsx_pcr
*pcr
, struct scatterlist
*sglist
,
332 int num_sg
, bool read
, int timeout
)
334 struct completion trans_done
;
336 int err
= 0, i
, count
;
339 struct scatterlist
*sg
;
340 enum dma_data_direction dma_dir
;
345 dev_dbg(&(pcr
->pci
->dev
), "--> %s: num_sg = %d\n", __func__
, num_sg
);
347 /* don't transfer data during abort processing */
351 if ((sglist
== NULL
) || (num_sg
<= 0))
355 dir
= DEVICE_TO_HOST
;
356 dma_dir
= DMA_FROM_DEVICE
;
358 dir
= HOST_TO_DEVICE
;
359 dma_dir
= DMA_TO_DEVICE
;
362 count
= dma_map_sg(&(pcr
->pci
->dev
), sglist
, num_sg
, dma_dir
);
364 dev_err(&(pcr
->pci
->dev
), "scatterlist map failed\n");
367 dev_dbg(&(pcr
->pci
->dev
), "DMA mapping count: %d\n", count
);
369 val
= ((u32
)(dir
& 0x01) << 29) | TRIG_DMA
| ADMA_MODE
;
371 for_each_sg(sglist
, sg
, count
, i
) {
372 addr
= sg_dma_address(sg
);
373 len
= sg_dma_len(sg
);
374 rtsx_pci_add_sg_tbl(pcr
, addr
, len
, i
== count
- 1);
377 spin_lock_irqsave(&pcr
->lock
, flags
);
379 pcr
->done
= &trans_done
;
380 pcr
->trans_result
= TRANS_NOT_READY
;
381 init_completion(&trans_done
);
382 rtsx_pci_writel(pcr
, RTSX_HDBAR
, pcr
->host_sg_tbl_addr
);
383 rtsx_pci_writel(pcr
, RTSX_HDBCTLR
, val
);
385 spin_unlock_irqrestore(&pcr
->lock
, flags
);
387 timeleft
= wait_for_completion_interruptible_timeout(
388 &trans_done
, msecs_to_jiffies(timeout
));
390 dev_dbg(&(pcr
->pci
->dev
), "Timeout (%s %d)\n",
396 spin_lock_irqsave(&pcr
->lock
, flags
);
398 if (pcr
->trans_result
== TRANS_RESULT_FAIL
)
400 else if (pcr
->trans_result
== TRANS_NO_DEVICE
)
403 spin_unlock_irqrestore(&pcr
->lock
, flags
);
406 spin_lock_irqsave(&pcr
->lock
, flags
);
408 spin_unlock_irqrestore(&pcr
->lock
, flags
);
410 dma_unmap_sg(&(pcr
->pci
->dev
), sglist
, num_sg
, dma_dir
);
412 if ((err
< 0) && (err
!= -ENODEV
))
413 rtsx_pci_stop_cmd(pcr
);
416 complete(pcr
->finish_me
);
420 EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data
);
422 int rtsx_pci_read_ppbuf(struct rtsx_pcr
*pcr
, u8
*buf
, int buf_len
)
434 for (i
= 0; i
< buf_len
/ 256; i
++) {
435 rtsx_pci_init_cmd(pcr
);
437 for (j
= 0; j
< 256; j
++)
438 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, reg
++, 0, 0);
440 err
= rtsx_pci_send_cmd(pcr
, 250);
444 memcpy(ptr
, rtsx_pci_get_cmd_data(pcr
), 256);
449 rtsx_pci_init_cmd(pcr
);
451 for (j
= 0; j
< buf_len
% 256; j
++)
452 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, reg
++, 0, 0);
454 err
= rtsx_pci_send_cmd(pcr
, 250);
459 memcpy(ptr
, rtsx_pci_get_cmd_data(pcr
), buf_len
% 256);
463 EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf
);
465 int rtsx_pci_write_ppbuf(struct rtsx_pcr
*pcr
, u8
*buf
, int buf_len
)
477 for (i
= 0; i
< buf_len
/ 256; i
++) {
478 rtsx_pci_init_cmd(pcr
);
480 for (j
= 0; j
< 256; j
++) {
481 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
,
486 err
= rtsx_pci_send_cmd(pcr
, 250);
492 rtsx_pci_init_cmd(pcr
);
494 for (j
= 0; j
< buf_len
% 256; j
++) {
495 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
,
500 err
= rtsx_pci_send_cmd(pcr
, 250);
507 EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf
);
509 static int rtsx_pci_set_pull_ctl(struct rtsx_pcr
*pcr
, const u32
*tbl
)
513 rtsx_pci_init_cmd(pcr
);
515 while (*tbl
& 0xFFFF0000) {
516 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
,
517 (u16
)(*tbl
>> 16), 0xFF, (u8
)(*tbl
));
521 err
= rtsx_pci_send_cmd(pcr
, 100);
528 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr
*pcr
, int card
)
532 if (card
== RTSX_SD_CARD
)
533 tbl
= pcr
->sd_pull_ctl_enable_tbl
;
534 else if (card
== RTSX_MS_CARD
)
535 tbl
= pcr
->ms_pull_ctl_enable_tbl
;
539 return rtsx_pci_set_pull_ctl(pcr
, tbl
);
541 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable
);
543 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr
*pcr
, int card
)
547 if (card
== RTSX_SD_CARD
)
548 tbl
= pcr
->sd_pull_ctl_disable_tbl
;
549 else if (card
== RTSX_MS_CARD
)
550 tbl
= pcr
->ms_pull_ctl_disable_tbl
;
555 return rtsx_pci_set_pull_ctl(pcr
, tbl
);
557 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable
);
559 static void rtsx_pci_enable_bus_int(struct rtsx_pcr
*pcr
)
561 pcr
->bier
= TRANS_OK_INT_EN
| TRANS_FAIL_INT_EN
| SD_INT_EN
;
563 if (pcr
->num_slots
> 1)
564 pcr
->bier
|= MS_INT_EN
;
566 /* Enable Bus Interrupt */
567 rtsx_pci_writel(pcr
, RTSX_BIER
, pcr
->bier
);
569 dev_dbg(&(pcr
->pci
->dev
), "RTSX_BIER: 0x%08x\n", pcr
->bier
);
572 static inline u8
double_ssc_depth(u8 depth
)
574 return ((depth
> 1) ? (depth
- 1) : depth
);
577 static u8
revise_ssc_depth(u8 ssc_depth
, u8 div
)
579 if (div
> CLK_DIV_1
) {
580 if (ssc_depth
> (div
- 1))
581 ssc_depth
-= (div
- 1);
583 ssc_depth
= SSC_DEPTH_4M
;
589 int rtsx_pci_switch_clock(struct rtsx_pcr
*pcr
, unsigned int card_clock
,
590 u8 ssc_depth
, bool initial_mode
, bool double_clk
, bool vpclk
)
593 u8 n
, clk_divider
, mcu_cnt
, div
;
595 [RTSX_SSC_DEPTH_4M
] = SSC_DEPTH_4M
,
596 [RTSX_SSC_DEPTH_2M
] = SSC_DEPTH_2M
,
597 [RTSX_SSC_DEPTH_1M
] = SSC_DEPTH_1M
,
598 [RTSX_SSC_DEPTH_500K
] = SSC_DEPTH_500K
,
599 [RTSX_SSC_DEPTH_250K
] = SSC_DEPTH_250K
,
603 /* We use 250k(around) here, in initial stage */
604 clk_divider
= SD_CLK_DIVIDE_128
;
605 card_clock
= 30000000;
607 clk_divider
= SD_CLK_DIVIDE_0
;
609 err
= rtsx_pci_write_register(pcr
, SD_CFG1
,
610 SD_CLK_DIVIDE_MASK
, clk_divider
);
614 card_clock
/= 1000000;
615 dev_dbg(&(pcr
->pci
->dev
), "Switch card clock to %dMHz\n", card_clock
);
618 if (!initial_mode
&& double_clk
)
619 clk
= card_clock
* 2;
620 dev_dbg(&(pcr
->pci
->dev
),
621 "Internal SSC clock: %dMHz (cur_clock = %d)\n",
622 clk
, pcr
->cur_clock
);
624 if (clk
== pcr
->cur_clock
)
627 if (pcr
->ops
->conv_clk_and_div_n
)
628 n
= (u8
)pcr
->ops
->conv_clk_and_div_n(clk
, CLK_TO_DIV_N
);
631 if ((clk
<= 2) || (n
> MAX_DIV_N_PCR
))
634 mcu_cnt
= (u8
)(125/clk
+ 3);
638 /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
640 while ((n
< MIN_DIV_N_PCR
) && (div
< CLK_DIV_8
)) {
641 if (pcr
->ops
->conv_clk_and_div_n
) {
642 int dbl_clk
= pcr
->ops
->conv_clk_and_div_n(n
,
644 n
= (u8
)pcr
->ops
->conv_clk_and_div_n(dbl_clk
,
651 dev_dbg(&(pcr
->pci
->dev
), "n = %d, div = %d\n", n
, div
);
653 ssc_depth
= depth
[ssc_depth
];
655 ssc_depth
= double_ssc_depth(ssc_depth
);
657 ssc_depth
= revise_ssc_depth(ssc_depth
, div
);
658 dev_dbg(&(pcr
->pci
->dev
), "ssc_depth = %d\n", ssc_depth
);
660 rtsx_pci_init_cmd(pcr
);
661 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_CTL
,
662 CLK_LOW_FREQ
, CLK_LOW_FREQ
);
663 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_DIV
,
664 0xFF, (div
<< 4) | mcu_cnt
);
665 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL1
, SSC_RSTB
, 0);
666 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL2
,
667 SSC_DEPTH_MASK
, ssc_depth
);
668 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_DIV_N_0
, 0xFF, n
);
669 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL1
, SSC_RSTB
, SSC_RSTB
);
671 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_VPCLK0_CTL
,
673 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_VPCLK0_CTL
,
674 PHASE_NOT_RESET
, PHASE_NOT_RESET
);
677 err
= rtsx_pci_send_cmd(pcr
, 2000);
681 /* Wait SSC clock stable */
683 err
= rtsx_pci_write_register(pcr
, CLK_CTL
, CLK_LOW_FREQ
, 0);
687 pcr
->cur_clock
= clk
;
690 EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock
);
692 int rtsx_pci_card_power_on(struct rtsx_pcr
*pcr
, int card
)
694 if (pcr
->ops
->card_power_on
)
695 return pcr
->ops
->card_power_on(pcr
, card
);
699 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on
);
701 int rtsx_pci_card_power_off(struct rtsx_pcr
*pcr
, int card
)
703 if (pcr
->ops
->card_power_off
)
704 return pcr
->ops
->card_power_off(pcr
, card
);
708 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off
);
710 int rtsx_pci_switch_output_voltage(struct rtsx_pcr
*pcr
, u8 voltage
)
712 if (pcr
->ops
->switch_output_voltage
)
713 return pcr
->ops
->switch_output_voltage(pcr
, voltage
);
717 EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage
);
719 unsigned int rtsx_pci_card_exist(struct rtsx_pcr
*pcr
)
723 val
= rtsx_pci_readl(pcr
, RTSX_BIPR
);
724 if (pcr
->ops
->cd_deglitch
)
725 val
= pcr
->ops
->cd_deglitch(pcr
);
729 EXPORT_SYMBOL_GPL(rtsx_pci_card_exist
);
731 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr
*pcr
)
733 struct completion finish
;
735 pcr
->finish_me
= &finish
;
736 init_completion(&finish
);
741 if (!pcr
->remove_pci
)
742 rtsx_pci_stop_cmd(pcr
);
744 wait_for_completion_interruptible_timeout(&finish
,
745 msecs_to_jiffies(2));
746 pcr
->finish_me
= NULL
;
748 EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer
);
750 static void rtsx_pci_card_detect(struct work_struct
*work
)
752 struct delayed_work
*dwork
;
753 struct rtsx_pcr
*pcr
;
755 unsigned int card_detect
= 0, card_inserted
, card_removed
;
758 dwork
= to_delayed_work(work
);
759 pcr
= container_of(dwork
, struct rtsx_pcr
, carddet_work
);
761 dev_dbg(&(pcr
->pci
->dev
), "--> %s\n", __func__
);
763 mutex_lock(&pcr
->pcr_mutex
);
764 spin_lock_irqsave(&pcr
->lock
, flags
);
766 irq_status
= rtsx_pci_readl(pcr
, RTSX_BIPR
);
767 dev_dbg(&(pcr
->pci
->dev
), "irq_status: 0x%08x\n", irq_status
);
769 irq_status
&= CARD_EXIST
;
770 card_inserted
= pcr
->card_inserted
& irq_status
;
771 card_removed
= pcr
->card_removed
;
772 pcr
->card_inserted
= 0;
773 pcr
->card_removed
= 0;
775 spin_unlock_irqrestore(&pcr
->lock
, flags
);
777 if (card_inserted
|| card_removed
) {
778 dev_dbg(&(pcr
->pci
->dev
),
779 "card_inserted: 0x%x, card_removed: 0x%x\n",
780 card_inserted
, card_removed
);
782 if (pcr
->ops
->cd_deglitch
)
783 card_inserted
= pcr
->ops
->cd_deglitch(pcr
);
785 card_detect
= card_inserted
| card_removed
;
788 mutex_unlock(&pcr
->pcr_mutex
);
790 if ((card_detect
& SD_EXIST
) && pcr
->slots
[RTSX_SD_CARD
].card_event
)
791 pcr
->slots
[RTSX_SD_CARD
].card_event(
792 pcr
->slots
[RTSX_SD_CARD
].p_dev
);
793 if ((card_detect
& MS_EXIST
) && pcr
->slots
[RTSX_MS_CARD
].card_event
)
794 pcr
->slots
[RTSX_MS_CARD
].card_event(
795 pcr
->slots
[RTSX_MS_CARD
].p_dev
);
798 static irqreturn_t
rtsx_pci_isr(int irq
, void *dev_id
)
800 struct rtsx_pcr
*pcr
= dev_id
;
806 spin_lock(&pcr
->lock
);
808 int_reg
= rtsx_pci_readl(pcr
, RTSX_BIPR
);
809 /* Clear interrupt flag */
810 rtsx_pci_writel(pcr
, RTSX_BIPR
, int_reg
);
811 if ((int_reg
& pcr
->bier
) == 0) {
812 spin_unlock(&pcr
->lock
);
815 if (int_reg
== 0xFFFFFFFF) {
816 spin_unlock(&pcr
->lock
);
820 int_reg
&= (pcr
->bier
| 0x7FFFFF);
822 if (int_reg
& SD_INT
) {
823 if (int_reg
& SD_EXIST
) {
824 pcr
->card_inserted
|= SD_EXIST
;
826 pcr
->card_removed
|= SD_EXIST
;
827 pcr
->card_inserted
&= ~SD_EXIST
;
831 if (int_reg
& MS_INT
) {
832 if (int_reg
& MS_EXIST
) {
833 pcr
->card_inserted
|= MS_EXIST
;
835 pcr
->card_removed
|= MS_EXIST
;
836 pcr
->card_inserted
&= ~MS_EXIST
;
840 if (int_reg
& (NEED_COMPLETE_INT
| DELINK_INT
)) {
841 if (int_reg
& (TRANS_FAIL_INT
| DELINK_INT
)) {
842 pcr
->trans_result
= TRANS_RESULT_FAIL
;
845 } else if (int_reg
& TRANS_OK_INT
) {
846 pcr
->trans_result
= TRANS_RESULT_OK
;
852 if (pcr
->card_inserted
|| pcr
->card_removed
)
853 schedule_delayed_work(&pcr
->carddet_work
,
854 msecs_to_jiffies(200));
856 spin_unlock(&pcr
->lock
);
860 static int rtsx_pci_acquire_irq(struct rtsx_pcr
*pcr
)
862 dev_info(&(pcr
->pci
->dev
), "%s: pcr->msi_en = %d, pci->irq = %d\n",
863 __func__
, pcr
->msi_en
, pcr
->pci
->irq
);
865 if (request_irq(pcr
->pci
->irq
, rtsx_pci_isr
,
866 pcr
->msi_en
? 0 : IRQF_SHARED
,
867 DRV_NAME_RTSX_PCI
, pcr
)) {
868 dev_err(&(pcr
->pci
->dev
),
869 "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
874 pcr
->irq
= pcr
->pci
->irq
;
875 pci_intx(pcr
->pci
, !pcr
->msi_en
);
880 static void rtsx_pci_idle_work(struct work_struct
*work
)
882 struct delayed_work
*dwork
= to_delayed_work(work
);
883 struct rtsx_pcr
*pcr
= container_of(dwork
, struct rtsx_pcr
, idle_work
);
885 dev_dbg(&(pcr
->pci
->dev
), "--> %s\n", __func__
);
887 mutex_lock(&pcr
->pcr_mutex
);
889 pcr
->state
= PDEV_STAT_IDLE
;
891 if (pcr
->ops
->disable_auto_blink
)
892 pcr
->ops
->disable_auto_blink(pcr
);
893 if (pcr
->ops
->turn_off_led
)
894 pcr
->ops
->turn_off_led(pcr
);
896 mutex_unlock(&pcr
->pcr_mutex
);
899 static int rtsx_pci_init_hw(struct rtsx_pcr
*pcr
)
903 rtsx_pci_writel(pcr
, RTSX_HCBAR
, pcr
->host_cmds_addr
);
905 rtsx_pci_enable_bus_int(pcr
);
908 err
= rtsx_pci_write_register(pcr
, FPDCTL
, SSC_POWER_DOWN
, 0);
912 /* Wait SSC power stable */
915 if (pcr
->ops
->optimize_phy
) {
916 err
= pcr
->ops
->optimize_phy(pcr
);
921 rtsx_pci_init_cmd(pcr
);
923 /* Set mcu_cnt to 7 to ensure data can be sampled properly */
924 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_DIV
, 0x07, 0x07);
926 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, HOST_SLEEP_STATE
, 0x03, 0x00);
927 /* Disable card clock */
928 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CARD_CLK_EN
, 0x1E, 0);
929 /* Reset ASPM state to default value */
930 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, ASPM_FORCE_CTL
, 0x3F, 0);
931 /* Reset delink mode */
932 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CHANGE_LINK_STATE
, 0x0A, 0);
933 /* Card driving select */
934 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD30_DRIVE_SEL
,
935 0x07, DRIVER_TYPE_D
);
936 /* Enable SSC Clock */
937 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL1
,
938 0xFF, SSC_8X_EN
| SSC_SEL_4M
);
939 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL2
, 0xFF, 0x12);
940 /* Disable cd_pwr_save */
941 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CHANGE_LINK_STATE
, 0x16, 0x10);
942 /* Clear Link Ready Interrupt */
943 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, IRQSTAT0
,
944 LINK_RDY_INT
, LINK_RDY_INT
);
945 /* Enlarge the estimation window of PERST# glitch
946 * to reduce the chance of invalid card interrupt
948 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PERST_GLITCH_WIDTH
, 0xFF, 0x80);
949 /* Update RC oscillator to 400k
950 * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
953 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, RCCTL
, 0x01, 0x00);
954 /* Set interrupt write clear
955 * bit 1: U_elbi_if_rd_clr_en
956 * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
957 * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
959 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, NFTS_TX_CTRL
, 0x02, 0);
960 /* Force CLKREQ# PIN to drive 0 to request clock */
961 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PETXCFG
, 0x08, 0x08);
963 err
= rtsx_pci_send_cmd(pcr
, 100);
967 /* Enable clk_request_n to enable clock power management */
968 rtsx_pci_write_config_byte(pcr
, 0x81, 1);
969 /* Enter L1 when host tx idle */
970 rtsx_pci_write_config_byte(pcr
, 0x70F, 0x5B);
972 if (pcr
->ops
->extra_init_hw
) {
973 err
= pcr
->ops
->extra_init_hw(pcr
);
981 static int rtsx_pci_init_chip(struct rtsx_pcr
*pcr
)
985 spin_lock_init(&pcr
->lock
);
986 mutex_init(&pcr
->pcr_mutex
);
988 switch (PCI_PID(pcr
)) {
991 rts5209_init_params(pcr
);
995 rts5229_init_params(pcr
);
999 rtl8411_init_params(pcr
);
1003 dev_dbg(&(pcr
->pci
->dev
), "PID: 0x%04x, IC version: 0x%02x\n",
1004 PCI_PID(pcr
), pcr
->ic_version
);
1006 pcr
->slots
= kcalloc(pcr
->num_slots
, sizeof(struct rtsx_slot
),
1011 pcr
->state
= PDEV_STAT_IDLE
;
1012 err
= rtsx_pci_init_hw(pcr
);
1021 static int rtsx_pci_probe(struct pci_dev
*pcidev
,
1022 const struct pci_device_id
*id
)
1024 struct rtsx_pcr
*pcr
;
1025 struct pcr_handle
*handle
;
1029 dev_dbg(&(pcidev
->dev
),
1030 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1031 pci_name(pcidev
), (int)pcidev
->vendor
, (int)pcidev
->device
,
1032 (int)pcidev
->revision
);
1034 ret
= pci_set_dma_mask(pcidev
, DMA_BIT_MASK(32));
1038 ret
= pci_enable_device(pcidev
);
1042 ret
= pci_request_regions(pcidev
, DRV_NAME_RTSX_PCI
);
1046 pcr
= kzalloc(sizeof(*pcr
), GFP_KERNEL
);
1052 handle
= kzalloc(sizeof(*handle
), GFP_KERNEL
);
1059 if (!idr_pre_get(&rtsx_pci_idr
, GFP_KERNEL
)) {
1064 spin_lock(&rtsx_pci_lock
);
1065 ret
= idr_get_new(&rtsx_pci_idr
, pcr
, &pcr
->id
);
1066 spin_unlock(&rtsx_pci_lock
);
1071 dev_set_drvdata(&pcidev
->dev
, handle
);
1073 len
= pci_resource_len(pcidev
, 0);
1074 base
= pci_resource_start(pcidev
, 0);
1075 pcr
->remap_addr
= ioremap_nocache(base
, len
);
1076 if (!pcr
->remap_addr
) {
1081 pcr
->rtsx_resv_buf
= dma_alloc_coherent(&(pcidev
->dev
),
1082 RTSX_RESV_BUF_LEN
, &(pcr
->rtsx_resv_buf_addr
),
1084 if (pcr
->rtsx_resv_buf
== NULL
) {
1088 pcr
->host_cmds_ptr
= pcr
->rtsx_resv_buf
;
1089 pcr
->host_cmds_addr
= pcr
->rtsx_resv_buf_addr
;
1090 pcr
->host_sg_tbl_ptr
= pcr
->rtsx_resv_buf
+ HOST_CMDS_BUF_LEN
;
1091 pcr
->host_sg_tbl_addr
= pcr
->rtsx_resv_buf_addr
+ HOST_CMDS_BUF_LEN
;
1093 pcr
->card_inserted
= 0;
1094 pcr
->card_removed
= 0;
1095 INIT_DELAYED_WORK(&pcr
->carddet_work
, rtsx_pci_card_detect
);
1096 INIT_DELAYED_WORK(&pcr
->idle_work
, rtsx_pci_idle_work
);
1098 pcr
->msi_en
= msi_en
;
1100 ret
= pci_enable_msi(pcidev
);
1102 pcr
->msi_en
= false;
1105 ret
= rtsx_pci_acquire_irq(pcr
);
1109 pci_set_master(pcidev
);
1110 synchronize_irq(pcr
->irq
);
1112 ret
= rtsx_pci_init_chip(pcr
);
1116 for (i
= 0; i
< ARRAY_SIZE(rtsx_pcr_cells
); i
++) {
1117 rtsx_pcr_cells
[i
].platform_data
= handle
;
1118 rtsx_pcr_cells
[i
].pdata_size
= sizeof(*handle
);
1120 ret
= mfd_add_devices(&pcidev
->dev
, pcr
->id
, rtsx_pcr_cells
,
1121 ARRAY_SIZE(rtsx_pcr_cells
), NULL
, 0, NULL
);
1125 schedule_delayed_work(&pcr
->idle_work
, msecs_to_jiffies(200));
1130 free_irq(pcr
->irq
, (void *)pcr
);
1132 dma_free_coherent(&(pcr
->pci
->dev
), RTSX_RESV_BUF_LEN
,
1133 pcr
->rtsx_resv_buf
, pcr
->rtsx_resv_buf_addr
);
1135 iounmap(pcr
->remap_addr
);
1137 dev_set_drvdata(&pcidev
->dev
, NULL
);
1143 pci_release_regions(pcidev
);
1145 pci_disable_device(pcidev
);
1150 static void rtsx_pci_remove(struct pci_dev
*pcidev
)
1152 struct pcr_handle
*handle
= pci_get_drvdata(pcidev
);
1153 struct rtsx_pcr
*pcr
= handle
->pcr
;
1155 pcr
->remove_pci
= true;
1157 cancel_delayed_work(&pcr
->carddet_work
);
1158 cancel_delayed_work(&pcr
->idle_work
);
1160 mfd_remove_devices(&pcidev
->dev
);
1162 dma_free_coherent(&(pcr
->pci
->dev
), RTSX_RESV_BUF_LEN
,
1163 pcr
->rtsx_resv_buf
, pcr
->rtsx_resv_buf_addr
);
1164 free_irq(pcr
->irq
, (void *)pcr
);
1166 pci_disable_msi(pcr
->pci
);
1167 iounmap(pcr
->remap_addr
);
1169 dev_set_drvdata(&pcidev
->dev
, NULL
);
1170 pci_release_regions(pcidev
);
1171 pci_disable_device(pcidev
);
1173 spin_lock(&rtsx_pci_lock
);
1174 idr_remove(&rtsx_pci_idr
, pcr
->id
);
1175 spin_unlock(&rtsx_pci_lock
);
1181 dev_dbg(&(pcidev
->dev
),
1182 ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1183 pci_name(pcidev
), (int)pcidev
->vendor
, (int)pcidev
->device
);
1188 static int rtsx_pci_suspend(struct pci_dev
*pcidev
, pm_message_t state
)
1190 struct pcr_handle
*handle
;
1191 struct rtsx_pcr
*pcr
;
1194 dev_dbg(&(pcidev
->dev
), "--> %s\n", __func__
);
1196 handle
= pci_get_drvdata(pcidev
);
1199 cancel_delayed_work(&pcr
->carddet_work
);
1200 cancel_delayed_work(&pcr
->idle_work
);
1202 mutex_lock(&pcr
->pcr_mutex
);
1204 if (pcr
->ops
->turn_off_led
)
1205 pcr
->ops
->turn_off_led(pcr
);
1207 rtsx_pci_writel(pcr
, RTSX_BIER
, 0);
1210 rtsx_pci_write_register(pcr
, PETXCFG
, 0x08, 0x08);
1211 rtsx_pci_write_register(pcr
, HOST_SLEEP_STATE
, 0x03, 0x02);
1213 pci_save_state(pcidev
);
1214 pci_enable_wake(pcidev
, pci_choose_state(pcidev
, state
), 0);
1215 pci_disable_device(pcidev
);
1216 pci_set_power_state(pcidev
, pci_choose_state(pcidev
, state
));
1218 mutex_unlock(&pcr
->pcr_mutex
);
1222 static int rtsx_pci_resume(struct pci_dev
*pcidev
)
1224 struct pcr_handle
*handle
;
1225 struct rtsx_pcr
*pcr
;
1228 dev_dbg(&(pcidev
->dev
), "--> %s\n", __func__
);
1230 handle
= pci_get_drvdata(pcidev
);
1233 mutex_lock(&pcr
->pcr_mutex
);
1235 pci_set_power_state(pcidev
, PCI_D0
);
1236 pci_restore_state(pcidev
);
1237 ret
= pci_enable_device(pcidev
);
1240 pci_set_master(pcidev
);
1242 ret
= rtsx_pci_write_register(pcr
, HOST_SLEEP_STATE
, 0x03, 0x00);
1246 ret
= rtsx_pci_init_hw(pcr
);
1250 schedule_delayed_work(&pcr
->idle_work
, msecs_to_jiffies(200));
1253 mutex_unlock(&pcr
->pcr_mutex
);
1257 #else /* CONFIG_PM */
1259 #define rtsx_pci_suspend NULL
1260 #define rtsx_pci_resume NULL
1262 #endif /* CONFIG_PM */
1264 static struct pci_driver rtsx_pci_driver
= {
1265 .name
= DRV_NAME_RTSX_PCI
,
1266 .id_table
= rtsx_pci_ids
,
1267 .probe
= rtsx_pci_probe
,
1268 .remove
= rtsx_pci_remove
,
1269 .suspend
= rtsx_pci_suspend
,
1270 .resume
= rtsx_pci_resume
,
1272 module_pci_driver(rtsx_pci_driver
);
1274 MODULE_LICENSE("GPL");
1275 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1276 MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");