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25 * DOC: atomic modeset support
27 * The functions here implement the state management and hardware programming
28 * dispatch required by the atomic modeset infrastructure.
29 * See intel_atomic_plane.c for the plane-specific atomic functionality.
33 #include <drm/drm_atomic.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_plane_helper.h>
36 #include "intel_drv.h"
39 * intel_connector_atomic_get_property - fetch connector property value
40 * @connector: connector to fetch property for
41 * @state: state containing the property value
42 * @property: property to look up
43 * @val: pointer to write property value into
45 * The DRM core does not store shadow copies of properties for
46 * atomic-capable drivers. This entrypoint is used to fetch
47 * the current value of a driver-specific connector property.
50 intel_connector_atomic_get_property(struct drm_connector
*connector
,
51 const struct drm_connector_state
*state
,
52 struct drm_property
*property
,
58 * TODO: We only have atomic modeset for planes at the moment, so the
59 * crtc/connector code isn't quite ready yet. Until it's ready,
60 * continue to look up all property values in the DRM's shadow copy
61 * in obj->properties->values[].
63 * When the crtc/connector state work matures, this function should
64 * be updated to read the values out of the state structure instead.
66 for (i
= 0; i
< connector
->base
.properties
->count
; i
++) {
67 if (connector
->base
.properties
->properties
[i
] == property
) {
68 *val
= connector
->base
.properties
->values
[i
];
77 * intel_crtc_duplicate_state - duplicate crtc state
80 * Allocates and returns a copy of the crtc state (both common and
81 * Intel-specific) for the specified crtc.
83 * Returns: The newly allocated crtc state, or NULL on failure.
85 struct drm_crtc_state
*
86 intel_crtc_duplicate_state(struct drm_crtc
*crtc
)
88 struct intel_crtc_state
*crtc_state
;
90 crtc_state
= kmemdup(crtc
->state
, sizeof(*crtc_state
), GFP_KERNEL
);
94 __drm_atomic_helper_crtc_duplicate_state(crtc
, &crtc_state
->base
);
96 crtc_state
->update_pipe
= false;
97 crtc_state
->disable_lp_wm
= false;
99 return &crtc_state
->base
;
103 * intel_crtc_destroy_state - destroy crtc state
106 * Destroys the crtc state (both common and Intel-specific) for the
110 intel_crtc_destroy_state(struct drm_crtc
*crtc
,
111 struct drm_crtc_state
*state
)
113 drm_atomic_helper_crtc_destroy_state(crtc
, state
);
117 * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests
120 * @crtc_state: incoming crtc_state to validate and setup scalers
122 * This function sets up scalers based on staged scaling requests for
123 * a @crtc and its planes. It is called from crtc level check path. If request
124 * is a supportable request, it attaches scalers to requested planes and crtc.
126 * This function takes into account the current scaler(s) in use by any planes
127 * not being part of this atomic state
130 * 0 - scalers were setup succesfully
131 * error code - otherwise
133 int intel_atomic_setup_scalers(struct drm_device
*dev
,
134 struct intel_crtc
*intel_crtc
,
135 struct intel_crtc_state
*crtc_state
)
137 struct drm_plane
*plane
= NULL
;
138 struct intel_plane
*intel_plane
;
139 struct intel_plane_state
*plane_state
= NULL
;
140 struct intel_crtc_scaler_state
*scaler_state
=
141 &crtc_state
->scaler_state
;
142 struct drm_atomic_state
*drm_state
= crtc_state
->base
.state
;
143 int num_scalers_need
;
146 num_scalers_need
= hweight32(scaler_state
->scaler_users
);
150 * - staged scaler requests are already in scaler_state->scaler_users
151 * - check whether staged scaling requests can be supported
152 * - add planes using scalers that aren't in current transaction
153 * - assign scalers to requested users
154 * - as part of plane commit, scalers will be committed
155 * (i.e., either attached or detached) to respective planes in hw
156 * - as part of crtc_commit, scaler will be either attached or detached
160 /* fail if required scalers > available scalers */
161 if (num_scalers_need
> intel_crtc
->num_scalers
){
162 DRM_DEBUG_KMS("Too many scaling requests %d > %d\n",
163 num_scalers_need
, intel_crtc
->num_scalers
);
167 /* walkthrough scaler_users bits and start assigning scalers */
168 for (i
= 0; i
< sizeof(scaler_state
->scaler_users
) * 8; i
++) {
173 /* skip if scaler not required */
174 if (!(scaler_state
->scaler_users
& (1 << i
)))
177 if (i
== SKL_CRTC_INDEX
) {
179 idx
= intel_crtc
->base
.base
.id
;
181 /* panel fitter case: assign as a crtc scaler */
182 scaler_id
= &scaler_state
->scaler_id
;
186 /* plane scaler case: assign as a plane scaler */
187 /* find the plane that set the bit as scaler_user */
188 plane
= drm_state
->planes
[i
];
191 * to enable/disable hq mode, add planes that are using scaler
192 * into this transaction
195 struct drm_plane_state
*state
;
196 plane
= drm_plane_from_index(dev
, i
);
197 state
= drm_atomic_get_plane_state(drm_state
, plane
);
199 DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state\n",
201 return PTR_ERR(state
);
205 * the plane is added after plane checks are run,
206 * but since this plane is unchanged just do the
207 * minimum required validation.
209 crtc_state
->base
.planes_changed
= true;
212 intel_plane
= to_intel_plane(plane
);
213 idx
= plane
->base
.id
;
215 /* plane on different crtc cannot be a scaler user of this crtc */
216 if (WARN_ON(intel_plane
->pipe
!= intel_crtc
->pipe
)) {
220 plane_state
= to_intel_plane_state(drm_state
->plane_states
[i
]);
221 scaler_id
= &plane_state
->scaler_id
;
224 if (*scaler_id
< 0) {
225 /* find a free scaler */
226 for (j
= 0; j
< intel_crtc
->num_scalers
; j
++) {
227 if (!scaler_state
->scalers
[j
].in_use
) {
228 scaler_state
->scalers
[j
].in_use
= 1;
230 DRM_DEBUG_KMS("Attached scaler id %u.%u to %s:%d\n",
231 intel_crtc
->pipe
, *scaler_id
, name
, idx
);
237 if (WARN_ON(*scaler_id
< 0)) {
238 DRM_DEBUG_KMS("Cannot find scaler for %s:%d\n", name
, idx
);
242 /* set scaler mode */
243 if (num_scalers_need
== 1 && intel_crtc
->pipe
!= PIPE_C
) {
245 * when only 1 scaler is in use on either pipe A or B,
246 * scaler 0 operates in high quality (HQ) mode.
247 * In this case use scaler 0 to take advantage of HQ mode
250 scaler_state
->scalers
[0].in_use
= 1;
251 scaler_state
->scalers
[0].mode
= PS_SCALER_MODE_HQ
;
252 scaler_state
->scalers
[1].in_use
= 0;
254 scaler_state
->scalers
[*scaler_id
].mode
= PS_SCALER_MODE_DYN
;
262 intel_atomic_duplicate_dpll_state(struct drm_i915_private
*dev_priv
,
263 struct intel_shared_dpll_config
*shared_dpll
)
265 enum intel_dpll_id i
;
267 /* Copy shared dpll state */
268 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
269 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
271 shared_dpll
[i
] = pll
->config
;
275 struct intel_shared_dpll_config
*
276 intel_atomic_get_shared_dpll_state(struct drm_atomic_state
*s
)
278 struct intel_atomic_state
*state
= to_intel_atomic_state(s
);
280 WARN_ON(!drm_modeset_is_locked(&s
->dev
->mode_config
.connection_mutex
));
282 if (!state
->dpll_set
) {
283 state
->dpll_set
= true;
285 intel_atomic_duplicate_dpll_state(to_i915(s
->dev
),
289 return state
->shared_dpll
;
292 struct drm_atomic_state
*
293 intel_atomic_state_alloc(struct drm_device
*dev
)
295 struct intel_atomic_state
*state
= kzalloc(sizeof(*state
), GFP_KERNEL
);
297 if (!state
|| drm_atomic_state_init(dev
, &state
->base
) < 0) {
305 void intel_atomic_state_clear(struct drm_atomic_state
*s
)
307 struct intel_atomic_state
*state
= to_intel_atomic_state(s
);
308 drm_atomic_state_default_clear(&state
->base
);
309 state
->dpll_set
= false;