1 /* SuperH Ethernet device driver
3 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
4 * Copyright (C) 2008-2014 Renesas Solutions Corp.
5 * Copyright (C) 2013-2014 Cogent Embedded, Inc.
6 * Copyright (C) 2014 Codethink Limited
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * The full GNU General Public License is included in this distribution in
18 * the file called "COPYING".
21 #include <linux/module.h>
22 #include <linux/kernel.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/etherdevice.h>
27 #include <linux/delay.h>
28 #include <linux/platform_device.h>
29 #include <linux/mdio-bitbang.h>
30 #include <linux/netdevice.h>
32 #include <linux/of_device.h>
33 #include <linux/of_irq.h>
34 #include <linux/of_net.h>
35 #include <linux/phy.h>
36 #include <linux/cache.h>
38 #include <linux/pm_runtime.h>
39 #include <linux/slab.h>
40 #include <linux/ethtool.h>
41 #include <linux/if_vlan.h>
42 #include <linux/clk.h>
43 #include <linux/sh_eth.h>
44 #include <linux/of_mdio.h>
48 #define SH_ETH_DEF_MSG_ENABLE \
54 static const u16 sh_eth_offset_gigabit
[SH_ETH_MAX_REGISTER_OFFSET
] = {
108 [TSU_CTRST
] = 0x0004,
109 [TSU_FWEN0
] = 0x0010,
110 [TSU_FWEN1
] = 0x0014,
112 [TSU_BSYSL0
] = 0x0020,
113 [TSU_BSYSL1
] = 0x0024,
114 [TSU_PRISL0
] = 0x0028,
115 [TSU_PRISL1
] = 0x002c,
116 [TSU_FWSL0
] = 0x0030,
117 [TSU_FWSL1
] = 0x0034,
118 [TSU_FWSLC
] = 0x0038,
119 [TSU_QTAG0
] = 0x0040,
120 [TSU_QTAG1
] = 0x0044,
122 [TSU_FWINMK
] = 0x0054,
123 [TSU_ADQT0
] = 0x0048,
124 [TSU_ADQT1
] = 0x004c,
125 [TSU_VTAG0
] = 0x0058,
126 [TSU_VTAG1
] = 0x005c,
127 [TSU_ADSBSY
] = 0x0060,
129 [TSU_POST1
] = 0x0070,
130 [TSU_POST2
] = 0x0074,
131 [TSU_POST3
] = 0x0078,
132 [TSU_POST4
] = 0x007c,
133 [TSU_ADRH0
] = 0x0100,
134 [TSU_ADRL0
] = 0x0104,
135 [TSU_ADRH31
] = 0x01f8,
136 [TSU_ADRL31
] = 0x01fc,
152 static const u16 sh_eth_offset_fast_rz
[SH_ETH_MAX_REGISTER_OFFSET
] = {
196 [TSU_CTRST
] = 0x0004,
197 [TSU_VTAG0
] = 0x0058,
198 [TSU_ADSBSY
] = 0x0060,
200 [TSU_ADRH0
] = 0x0100,
201 [TSU_ADRL0
] = 0x0104,
202 [TSU_ADRH31
] = 0x01f8,
203 [TSU_ADRL31
] = 0x01fc,
211 static const u16 sh_eth_offset_fast_rcar
[SH_ETH_MAX_REGISTER_OFFSET
] = {
257 static const u16 sh_eth_offset_fast_sh4
[SH_ETH_MAX_REGISTER_OFFSET
] = {
309 static const u16 sh_eth_offset_fast_sh3_sh2
[SH_ETH_MAX_REGISTER_OFFSET
] = {
356 [TSU_CTRST
] = 0x0004,
357 [TSU_FWEN0
] = 0x0010,
358 [TSU_FWEN1
] = 0x0014,
360 [TSU_BSYSL0
] = 0x0020,
361 [TSU_BSYSL1
] = 0x0024,
362 [TSU_PRISL0
] = 0x0028,
363 [TSU_PRISL1
] = 0x002c,
364 [TSU_FWSL0
] = 0x0030,
365 [TSU_FWSL1
] = 0x0034,
366 [TSU_FWSLC
] = 0x0038,
367 [TSU_QTAGM0
] = 0x0040,
368 [TSU_QTAGM1
] = 0x0044,
369 [TSU_ADQT0
] = 0x0048,
370 [TSU_ADQT1
] = 0x004c,
372 [TSU_FWINMK
] = 0x0054,
373 [TSU_ADSBSY
] = 0x0060,
375 [TSU_POST1
] = 0x0070,
376 [TSU_POST2
] = 0x0074,
377 [TSU_POST3
] = 0x0078,
378 [TSU_POST4
] = 0x007c,
393 [TSU_ADRH0
] = 0x0100,
394 [TSU_ADRL0
] = 0x0104,
395 [TSU_ADRL31
] = 0x01fc,
398 static bool sh_eth_is_gether(struct sh_eth_private
*mdp
)
400 return mdp
->reg_offset
== sh_eth_offset_gigabit
;
403 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private
*mdp
)
405 return mdp
->reg_offset
== sh_eth_offset_fast_rz
;
408 static void sh_eth_select_mii(struct net_device
*ndev
)
411 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
413 switch (mdp
->phy_interface
) {
414 case PHY_INTERFACE_MODE_GMII
:
417 case PHY_INTERFACE_MODE_MII
:
420 case PHY_INTERFACE_MODE_RMII
:
425 "PHY interface mode was not setup. Set to MII.\n");
430 sh_eth_write(ndev
, value
, RMII_MII
);
433 static void sh_eth_set_duplex(struct net_device
*ndev
)
435 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
437 if (mdp
->duplex
) /* Full */
438 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
440 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
443 /* There is CPU dependent code */
444 static void sh_eth_set_rate_r8a777x(struct net_device
*ndev
)
446 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
448 switch (mdp
->speed
) {
449 case 10: /* 10BASE */
450 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_ELB
, ECMR
);
452 case 100:/* 100BASE */
453 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_ELB
, ECMR
);
461 static struct sh_eth_cpu_data r8a777x_data
= {
462 .set_duplex
= sh_eth_set_duplex
,
463 .set_rate
= sh_eth_set_rate_r8a777x
,
465 .register_type
= SH_ETH_REG_FAST_RCAR
,
467 .ecsr_value
= ECSR_PSRTO
| ECSR_LCHNG
| ECSR_ICD
,
468 .ecsipr_value
= ECSIPR_PSRTOIP
| ECSIPR_LCHNGIP
| ECSIPR_ICDIP
,
469 .eesipr_value
= 0x01ff009f,
471 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
472 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RFE
|
473 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
|
483 static struct sh_eth_cpu_data r8a779x_data
= {
484 .set_duplex
= sh_eth_set_duplex
,
485 .set_rate
= sh_eth_set_rate_r8a777x
,
487 .register_type
= SH_ETH_REG_FAST_RCAR
,
489 .ecsr_value
= ECSR_PSRTO
| ECSR_LCHNG
| ECSR_ICD
,
490 .ecsipr_value
= ECSIPR_PSRTOIP
| ECSIPR_LCHNGIP
| ECSIPR_ICDIP
,
491 .eesipr_value
= 0x01ff009f,
493 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
494 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RFE
|
495 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
|
506 static void sh_eth_set_rate_sh7724(struct net_device
*ndev
)
508 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
510 switch (mdp
->speed
) {
511 case 10: /* 10BASE */
512 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_RTM
, ECMR
);
514 case 100:/* 100BASE */
515 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_RTM
, ECMR
);
523 static struct sh_eth_cpu_data sh7724_data
= {
524 .set_duplex
= sh_eth_set_duplex
,
525 .set_rate
= sh_eth_set_rate_sh7724
,
527 .register_type
= SH_ETH_REG_FAST_SH4
,
529 .ecsr_value
= ECSR_PSRTO
| ECSR_LCHNG
| ECSR_ICD
,
530 .ecsipr_value
= ECSIPR_PSRTOIP
| ECSIPR_LCHNGIP
| ECSIPR_ICDIP
,
531 .eesipr_value
= 0x01ff009f,
533 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
534 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RFE
|
535 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
|
543 .rpadir_value
= 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
546 static void sh_eth_set_rate_sh7757(struct net_device
*ndev
)
548 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
550 switch (mdp
->speed
) {
551 case 10: /* 10BASE */
552 sh_eth_write(ndev
, 0, RTRATE
);
554 case 100:/* 100BASE */
555 sh_eth_write(ndev
, 1, RTRATE
);
563 static struct sh_eth_cpu_data sh7757_data
= {
564 .set_duplex
= sh_eth_set_duplex
,
565 .set_rate
= sh_eth_set_rate_sh7757
,
567 .register_type
= SH_ETH_REG_FAST_SH4
,
569 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
571 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
572 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RFE
|
573 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
|
576 .irq_flags
= IRQF_SHARED
,
583 .rpadir_value
= 2 << 16,
586 #define SH_GIGA_ETH_BASE 0xfee00000UL
587 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
588 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
589 static void sh_eth_chip_reset_giga(struct net_device
*ndev
)
592 unsigned long mahr
[2], malr
[2];
594 /* save MAHR and MALR */
595 for (i
= 0; i
< 2; i
++) {
596 malr
[i
] = ioread32((void *)GIGA_MALR(i
));
597 mahr
[i
] = ioread32((void *)GIGA_MAHR(i
));
601 iowrite32(ARSTR_ARSTR
, (void *)(SH_GIGA_ETH_BASE
+ 0x1800));
604 /* restore MAHR and MALR */
605 for (i
= 0; i
< 2; i
++) {
606 iowrite32(malr
[i
], (void *)GIGA_MALR(i
));
607 iowrite32(mahr
[i
], (void *)GIGA_MAHR(i
));
611 static void sh_eth_set_rate_giga(struct net_device
*ndev
)
613 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
615 switch (mdp
->speed
) {
616 case 10: /* 10BASE */
617 sh_eth_write(ndev
, 0x00000000, GECMR
);
619 case 100:/* 100BASE */
620 sh_eth_write(ndev
, 0x00000010, GECMR
);
622 case 1000: /* 1000BASE */
623 sh_eth_write(ndev
, 0x00000020, GECMR
);
630 /* SH7757(GETHERC) */
631 static struct sh_eth_cpu_data sh7757_data_giga
= {
632 .chip_reset
= sh_eth_chip_reset_giga
,
633 .set_duplex
= sh_eth_set_duplex
,
634 .set_rate
= sh_eth_set_rate_giga
,
636 .register_type
= SH_ETH_REG_GIGABIT
,
638 .ecsr_value
= ECSR_ICD
| ECSR_MPD
,
639 .ecsipr_value
= ECSIPR_LCHNGIP
| ECSIPR_ICDIP
| ECSIPR_MPDIP
,
640 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
642 .tx_check
= EESR_TC1
| EESR_FTC
,
643 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
|
644 EESR_RFE
| EESR_RDE
| EESR_RFRMER
| EESR_TFE
|
646 .fdr_value
= 0x0000072f,
648 .irq_flags
= IRQF_SHARED
,
655 .rpadir_value
= 2 << 16,
661 static void sh_eth_chip_reset(struct net_device
*ndev
)
663 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
666 sh_eth_tsu_write(mdp
, ARSTR_ARSTR
, ARSTR
);
670 static void sh_eth_set_rate_gether(struct net_device
*ndev
)
672 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
674 switch (mdp
->speed
) {
675 case 10: /* 10BASE */
676 sh_eth_write(ndev
, GECMR_10
, GECMR
);
678 case 100:/* 100BASE */
679 sh_eth_write(ndev
, GECMR_100
, GECMR
);
681 case 1000: /* 1000BASE */
682 sh_eth_write(ndev
, GECMR_1000
, GECMR
);
690 static struct sh_eth_cpu_data sh7734_data
= {
691 .chip_reset
= sh_eth_chip_reset
,
692 .set_duplex
= sh_eth_set_duplex
,
693 .set_rate
= sh_eth_set_rate_gether
,
695 .register_type
= SH_ETH_REG_GIGABIT
,
697 .ecsr_value
= ECSR_ICD
| ECSR_MPD
,
698 .ecsipr_value
= ECSIPR_LCHNGIP
| ECSIPR_ICDIP
| ECSIPR_MPDIP
,
699 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
701 .tx_check
= EESR_TC1
| EESR_FTC
,
702 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
|
703 EESR_RFE
| EESR_RDE
| EESR_RFRMER
| EESR_TFE
|
719 static struct sh_eth_cpu_data sh7763_data
= {
720 .chip_reset
= sh_eth_chip_reset
,
721 .set_duplex
= sh_eth_set_duplex
,
722 .set_rate
= sh_eth_set_rate_gether
,
724 .register_type
= SH_ETH_REG_GIGABIT
,
726 .ecsr_value
= ECSR_ICD
| ECSR_MPD
,
727 .ecsipr_value
= ECSIPR_LCHNGIP
| ECSIPR_ICDIP
| ECSIPR_MPDIP
,
728 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
730 .tx_check
= EESR_TC1
| EESR_FTC
,
731 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
|
732 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
|
743 .irq_flags
= IRQF_SHARED
,
746 static void sh_eth_chip_reset_r8a7740(struct net_device
*ndev
)
748 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
751 sh_eth_tsu_write(mdp
, ARSTR_ARSTR
, ARSTR
);
754 sh_eth_select_mii(ndev
);
758 static struct sh_eth_cpu_data r8a7740_data
= {
759 .chip_reset
= sh_eth_chip_reset_r8a7740
,
760 .set_duplex
= sh_eth_set_duplex
,
761 .set_rate
= sh_eth_set_rate_gether
,
763 .register_type
= SH_ETH_REG_GIGABIT
,
765 .ecsr_value
= ECSR_ICD
| ECSR_MPD
,
766 .ecsipr_value
= ECSIPR_LCHNGIP
| ECSIPR_ICDIP
| ECSIPR_MPDIP
,
767 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
769 .tx_check
= EESR_TC1
| EESR_FTC
,
770 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
|
771 EESR_RFE
| EESR_RDE
| EESR_RFRMER
| EESR_TFE
|
773 .fdr_value
= 0x0000070f,
781 .rpadir_value
= 2 << 16,
790 static struct sh_eth_cpu_data r7s72100_data
= {
791 .chip_reset
= sh_eth_chip_reset
,
792 .set_duplex
= sh_eth_set_duplex
,
794 .register_type
= SH_ETH_REG_FAST_RZ
,
796 .ecsr_value
= ECSR_ICD
,
797 .ecsipr_value
= ECSIPR_ICDIP
,
798 .eesipr_value
= 0xff7f009f,
800 .tx_check
= EESR_TC1
| EESR_FTC
,
801 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
|
802 EESR_RFE
| EESR_RDE
| EESR_RFRMER
| EESR_TFE
|
804 .fdr_value
= 0x0000070f,
812 .rpadir_value
= 2 << 16,
820 static struct sh_eth_cpu_data sh7619_data
= {
821 .register_type
= SH_ETH_REG_FAST_SH3_SH2
,
823 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
831 static struct sh_eth_cpu_data sh771x_data
= {
832 .register_type
= SH_ETH_REG_FAST_SH3_SH2
,
834 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
838 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data
*cd
)
841 cd
->ecsr_value
= DEFAULT_ECSR_INIT
;
843 if (!cd
->ecsipr_value
)
844 cd
->ecsipr_value
= DEFAULT_ECSIPR_INIT
;
846 if (!cd
->fcftr_value
)
847 cd
->fcftr_value
= DEFAULT_FIFO_F_D_RFF
|
848 DEFAULT_FIFO_F_D_RFD
;
851 cd
->fdr_value
= DEFAULT_FDR_INIT
;
854 cd
->tx_check
= DEFAULT_TX_CHECK
;
856 if (!cd
->eesr_err_check
)
857 cd
->eesr_err_check
= DEFAULT_EESR_ERR_CHECK
;
860 static int sh_eth_check_reset(struct net_device
*ndev
)
866 if (!(sh_eth_read(ndev
, EDMR
) & 0x3))
872 netdev_err(ndev
, "Device reset failed\n");
878 static int sh_eth_reset(struct net_device
*ndev
)
880 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
883 if (sh_eth_is_gether(mdp
) || sh_eth_is_rz_fast_ether(mdp
)) {
884 sh_eth_write(ndev
, EDSR_ENALL
, EDSR
);
885 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) | EDMR_SRST_GETHER
,
888 ret
= sh_eth_check_reset(ndev
);
893 sh_eth_write(ndev
, 0x0, TDLAR
);
894 sh_eth_write(ndev
, 0x0, TDFAR
);
895 sh_eth_write(ndev
, 0x0, TDFXR
);
896 sh_eth_write(ndev
, 0x0, TDFFR
);
897 sh_eth_write(ndev
, 0x0, RDLAR
);
898 sh_eth_write(ndev
, 0x0, RDFAR
);
899 sh_eth_write(ndev
, 0x0, RDFXR
);
900 sh_eth_write(ndev
, 0x0, RDFFR
);
902 /* Reset HW CRC register */
904 sh_eth_write(ndev
, 0x0, CSMR
);
906 /* Select MII mode */
907 if (mdp
->cd
->select_mii
)
908 sh_eth_select_mii(ndev
);
910 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) | EDMR_SRST_ETHER
,
913 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) & ~EDMR_SRST_ETHER
,
920 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
921 static void sh_eth_set_receive_align(struct sk_buff
*skb
)
925 reserve
= SH4_SKB_RX_ALIGN
- ((u32
)skb
->data
& (SH4_SKB_RX_ALIGN
- 1));
927 skb_reserve(skb
, reserve
);
930 static void sh_eth_set_receive_align(struct sk_buff
*skb
)
932 skb_reserve(skb
, SH2_SH3_SKB_RX_ALIGN
);
937 /* CPU <-> EDMAC endian convert */
938 static inline __u32
cpu_to_edmac(struct sh_eth_private
*mdp
, u32 x
)
940 switch (mdp
->edmac_endian
) {
941 case EDMAC_LITTLE_ENDIAN
:
942 return cpu_to_le32(x
);
943 case EDMAC_BIG_ENDIAN
:
944 return cpu_to_be32(x
);
949 static inline __u32
edmac_to_cpu(struct sh_eth_private
*mdp
, u32 x
)
951 switch (mdp
->edmac_endian
) {
952 case EDMAC_LITTLE_ENDIAN
:
953 return le32_to_cpu(x
);
954 case EDMAC_BIG_ENDIAN
:
955 return be32_to_cpu(x
);
960 /* Program the hardware MAC address from dev->dev_addr. */
961 static void update_mac_address(struct net_device
*ndev
)
964 (ndev
->dev_addr
[0] << 24) | (ndev
->dev_addr
[1] << 16) |
965 (ndev
->dev_addr
[2] << 8) | (ndev
->dev_addr
[3]), MAHR
);
967 (ndev
->dev_addr
[4] << 8) | (ndev
->dev_addr
[5]), MALR
);
970 /* Get MAC address from SuperH MAC address register
972 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
973 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
974 * When you want use this device, you must set MAC address in bootloader.
977 static void read_mac_address(struct net_device
*ndev
, unsigned char *mac
)
979 if (mac
[0] || mac
[1] || mac
[2] || mac
[3] || mac
[4] || mac
[5]) {
980 memcpy(ndev
->dev_addr
, mac
, ETH_ALEN
);
982 ndev
->dev_addr
[0] = (sh_eth_read(ndev
, MAHR
) >> 24);
983 ndev
->dev_addr
[1] = (sh_eth_read(ndev
, MAHR
) >> 16) & 0xFF;
984 ndev
->dev_addr
[2] = (sh_eth_read(ndev
, MAHR
) >> 8) & 0xFF;
985 ndev
->dev_addr
[3] = (sh_eth_read(ndev
, MAHR
) & 0xFF);
986 ndev
->dev_addr
[4] = (sh_eth_read(ndev
, MALR
) >> 8) & 0xFF;
987 ndev
->dev_addr
[5] = (sh_eth_read(ndev
, MALR
) & 0xFF);
991 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private
*mdp
)
993 if (sh_eth_is_gether(mdp
) || sh_eth_is_rz_fast_ether(mdp
))
994 return EDTRR_TRNS_GETHER
;
996 return EDTRR_TRNS_ETHER
;
1000 void (*set_gate
)(void *addr
);
1001 struct mdiobb_ctrl ctrl
;
1003 u32 mmd_msk
;/* MMD */
1010 static void bb_set(void *addr
, u32 msk
)
1012 iowrite32(ioread32(addr
) | msk
, addr
);
1016 static void bb_clr(void *addr
, u32 msk
)
1018 iowrite32((ioread32(addr
) & ~msk
), addr
);
1022 static int bb_read(void *addr
, u32 msk
)
1024 return (ioread32(addr
) & msk
) != 0;
1027 /* Data I/O pin control */
1028 static void sh_mmd_ctrl(struct mdiobb_ctrl
*ctrl
, int bit
)
1030 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
1032 if (bitbang
->set_gate
)
1033 bitbang
->set_gate(bitbang
->addr
);
1036 bb_set(bitbang
->addr
, bitbang
->mmd_msk
);
1038 bb_clr(bitbang
->addr
, bitbang
->mmd_msk
);
1042 static void sh_set_mdio(struct mdiobb_ctrl
*ctrl
, int bit
)
1044 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
1046 if (bitbang
->set_gate
)
1047 bitbang
->set_gate(bitbang
->addr
);
1050 bb_set(bitbang
->addr
, bitbang
->mdo_msk
);
1052 bb_clr(bitbang
->addr
, bitbang
->mdo_msk
);
1056 static int sh_get_mdio(struct mdiobb_ctrl
*ctrl
)
1058 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
1060 if (bitbang
->set_gate
)
1061 bitbang
->set_gate(bitbang
->addr
);
1063 return bb_read(bitbang
->addr
, bitbang
->mdi_msk
);
1066 /* MDC pin control */
1067 static void sh_mdc_ctrl(struct mdiobb_ctrl
*ctrl
, int bit
)
1069 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
1071 if (bitbang
->set_gate
)
1072 bitbang
->set_gate(bitbang
->addr
);
1075 bb_set(bitbang
->addr
, bitbang
->mdc_msk
);
1077 bb_clr(bitbang
->addr
, bitbang
->mdc_msk
);
1080 /* mdio bus control struct */
1081 static struct mdiobb_ops bb_ops
= {
1082 .owner
= THIS_MODULE
,
1083 .set_mdc
= sh_mdc_ctrl
,
1084 .set_mdio_dir
= sh_mmd_ctrl
,
1085 .set_mdio_data
= sh_set_mdio
,
1086 .get_mdio_data
= sh_get_mdio
,
1089 /* free skb and descriptor buffer */
1090 static void sh_eth_ring_free(struct net_device
*ndev
)
1092 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1095 /* Free Rx skb ringbuffer */
1096 if (mdp
->rx_skbuff
) {
1097 for (i
= 0; i
< mdp
->num_rx_ring
; i
++) {
1098 if (mdp
->rx_skbuff
[i
])
1099 dev_kfree_skb(mdp
->rx_skbuff
[i
]);
1102 kfree(mdp
->rx_skbuff
);
1103 mdp
->rx_skbuff
= NULL
;
1105 /* Free Tx skb ringbuffer */
1106 if (mdp
->tx_skbuff
) {
1107 for (i
= 0; i
< mdp
->num_tx_ring
; i
++) {
1108 if (mdp
->tx_skbuff
[i
])
1109 dev_kfree_skb(mdp
->tx_skbuff
[i
]);
1112 kfree(mdp
->tx_skbuff
);
1113 mdp
->tx_skbuff
= NULL
;
1116 /* format skb and descriptor buffer */
1117 static void sh_eth_ring_format(struct net_device
*ndev
)
1119 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1121 struct sk_buff
*skb
;
1122 struct sh_eth_rxdesc
*rxdesc
= NULL
;
1123 struct sh_eth_txdesc
*txdesc
= NULL
;
1124 int rx_ringsize
= sizeof(*rxdesc
) * mdp
->num_rx_ring
;
1125 int tx_ringsize
= sizeof(*txdesc
) * mdp
->num_tx_ring
;
1132 memset(mdp
->rx_ring
, 0, rx_ringsize
);
1134 /* build Rx ring buffer */
1135 for (i
= 0; i
< mdp
->num_rx_ring
; i
++) {
1137 mdp
->rx_skbuff
[i
] = NULL
;
1138 skb
= netdev_alloc_skb(ndev
, mdp
->rx_buf_sz
);
1139 mdp
->rx_skbuff
[i
] = skb
;
1142 dma_map_single(&ndev
->dev
, skb
->data
, mdp
->rx_buf_sz
,
1144 sh_eth_set_receive_align(skb
);
1147 rxdesc
= &mdp
->rx_ring
[i
];
1148 rxdesc
->addr
= virt_to_phys(PTR_ALIGN(skb
->data
, 4));
1149 rxdesc
->status
= cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
);
1151 /* The size of the buffer is 16 byte boundary. */
1152 rxdesc
->buffer_length
= ALIGN(mdp
->rx_buf_sz
, 16);
1153 /* Rx descriptor address set */
1155 sh_eth_write(ndev
, mdp
->rx_desc_dma
, RDLAR
);
1156 if (sh_eth_is_gether(mdp
) ||
1157 sh_eth_is_rz_fast_ether(mdp
))
1158 sh_eth_write(ndev
, mdp
->rx_desc_dma
, RDFAR
);
1162 mdp
->dirty_rx
= (u32
) (i
- mdp
->num_rx_ring
);
1164 /* Mark the last entry as wrapping the ring. */
1165 rxdesc
->status
|= cpu_to_edmac(mdp
, RD_RDEL
);
1167 memset(mdp
->tx_ring
, 0, tx_ringsize
);
1169 /* build Tx ring buffer */
1170 for (i
= 0; i
< mdp
->num_tx_ring
; i
++) {
1171 mdp
->tx_skbuff
[i
] = NULL
;
1172 txdesc
= &mdp
->tx_ring
[i
];
1173 txdesc
->status
= cpu_to_edmac(mdp
, TD_TFP
);
1174 txdesc
->buffer_length
= 0;
1176 /* Tx descriptor address set */
1177 sh_eth_write(ndev
, mdp
->tx_desc_dma
, TDLAR
);
1178 if (sh_eth_is_gether(mdp
) ||
1179 sh_eth_is_rz_fast_ether(mdp
))
1180 sh_eth_write(ndev
, mdp
->tx_desc_dma
, TDFAR
);
1184 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TDLE
);
1187 /* Get skb and descriptor buffer */
1188 static int sh_eth_ring_init(struct net_device
*ndev
)
1190 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1191 int rx_ringsize
, tx_ringsize
, ret
= 0;
1193 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1194 * card needs room to do 8 byte alignment, +2 so we can reserve
1195 * the first 2 bytes, and +16 gets room for the status word from the
1198 mdp
->rx_buf_sz
= (ndev
->mtu
<= 1492 ? PKT_BUF_SZ
:
1199 (((ndev
->mtu
+ 26 + 7) & ~7) + 2 + 16));
1200 if (mdp
->cd
->rpadir
)
1201 mdp
->rx_buf_sz
+= NET_IP_ALIGN
;
1203 /* Allocate RX and TX skb rings */
1204 mdp
->rx_skbuff
= kmalloc_array(mdp
->num_rx_ring
,
1205 sizeof(*mdp
->rx_skbuff
), GFP_KERNEL
);
1206 if (!mdp
->rx_skbuff
) {
1211 mdp
->tx_skbuff
= kmalloc_array(mdp
->num_tx_ring
,
1212 sizeof(*mdp
->tx_skbuff
), GFP_KERNEL
);
1213 if (!mdp
->tx_skbuff
) {
1218 /* Allocate all Rx descriptors. */
1219 rx_ringsize
= sizeof(struct sh_eth_rxdesc
) * mdp
->num_rx_ring
;
1220 mdp
->rx_ring
= dma_alloc_coherent(NULL
, rx_ringsize
, &mdp
->rx_desc_dma
,
1222 if (!mdp
->rx_ring
) {
1224 goto desc_ring_free
;
1229 /* Allocate all Tx descriptors. */
1230 tx_ringsize
= sizeof(struct sh_eth_txdesc
) * mdp
->num_tx_ring
;
1231 mdp
->tx_ring
= dma_alloc_coherent(NULL
, tx_ringsize
, &mdp
->tx_desc_dma
,
1233 if (!mdp
->tx_ring
) {
1235 goto desc_ring_free
;
1240 /* free DMA buffer */
1241 dma_free_coherent(NULL
, rx_ringsize
, mdp
->rx_ring
, mdp
->rx_desc_dma
);
1244 /* Free Rx and Tx skb ring buffer */
1245 sh_eth_ring_free(ndev
);
1246 mdp
->tx_ring
= NULL
;
1247 mdp
->rx_ring
= NULL
;
1252 static void sh_eth_free_dma_buffer(struct sh_eth_private
*mdp
)
1257 ringsize
= sizeof(struct sh_eth_rxdesc
) * mdp
->num_rx_ring
;
1258 dma_free_coherent(NULL
, ringsize
, mdp
->rx_ring
,
1260 mdp
->rx_ring
= NULL
;
1264 ringsize
= sizeof(struct sh_eth_txdesc
) * mdp
->num_tx_ring
;
1265 dma_free_coherent(NULL
, ringsize
, mdp
->tx_ring
,
1267 mdp
->tx_ring
= NULL
;
1271 static int sh_eth_dev_init(struct net_device
*ndev
, bool start
)
1274 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1278 ret
= sh_eth_reset(ndev
);
1282 if (mdp
->cd
->rmiimode
)
1283 sh_eth_write(ndev
, 0x1, RMIIMODE
);
1285 /* Descriptor format */
1286 sh_eth_ring_format(ndev
);
1287 if (mdp
->cd
->rpadir
)
1288 sh_eth_write(ndev
, mdp
->cd
->rpadir_value
, RPADIR
);
1290 /* all sh_eth int mask */
1291 sh_eth_write(ndev
, 0, EESIPR
);
1293 #if defined(__LITTLE_ENDIAN)
1294 if (mdp
->cd
->hw_swap
)
1295 sh_eth_write(ndev
, EDMR_EL
, EDMR
);
1298 sh_eth_write(ndev
, 0, EDMR
);
1301 sh_eth_write(ndev
, mdp
->cd
->fdr_value
, FDR
);
1302 sh_eth_write(ndev
, 0, TFTR
);
1304 /* Frame recv control (enable multiple-packets per rx irq) */
1305 sh_eth_write(ndev
, RMCR_RNC
, RMCR
);
1307 sh_eth_write(ndev
, DESC_I_RINT8
| DESC_I_RINT5
| DESC_I_TINT2
, TRSCER
);
1310 sh_eth_write(ndev
, 0x800, BCULR
); /* Burst sycle set */
1312 sh_eth_write(ndev
, mdp
->cd
->fcftr_value
, FCFTR
);
1314 if (!mdp
->cd
->no_trimd
)
1315 sh_eth_write(ndev
, 0, TRIMD
);
1317 /* Recv frame limit set register */
1318 sh_eth_write(ndev
, ndev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
+ ETH_FCS_LEN
,
1321 sh_eth_write(ndev
, sh_eth_read(ndev
, EESR
), EESR
);
1323 sh_eth_write(ndev
, mdp
->cd
->eesipr_value
, EESIPR
);
1325 /* PAUSE Prohibition */
1326 val
= (sh_eth_read(ndev
, ECMR
) & ECMR_DM
) |
1327 ECMR_ZPF
| (mdp
->duplex
? ECMR_DM
: 0) | ECMR_TE
| ECMR_RE
;
1329 sh_eth_write(ndev
, val
, ECMR
);
1331 if (mdp
->cd
->set_rate
)
1332 mdp
->cd
->set_rate(ndev
);
1334 /* E-MAC Status Register clear */
1335 sh_eth_write(ndev
, mdp
->cd
->ecsr_value
, ECSR
);
1337 /* E-MAC Interrupt Enable register */
1339 sh_eth_write(ndev
, mdp
->cd
->ecsipr_value
, ECSIPR
);
1341 /* Set MAC address */
1342 update_mac_address(ndev
);
1346 sh_eth_write(ndev
, APR_AP
, APR
);
1348 sh_eth_write(ndev
, MPR_MP
, MPR
);
1349 if (mdp
->cd
->tpauser
)
1350 sh_eth_write(ndev
, TPAUSER_UNLIMITED
, TPAUSER
);
1353 /* Setting the Rx mode will start the Rx process. */
1354 sh_eth_write(ndev
, EDRRR_R
, EDRRR
);
1356 netif_start_queue(ndev
);
1362 /* free Tx skb function */
1363 static int sh_eth_txfree(struct net_device
*ndev
)
1365 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1366 struct sh_eth_txdesc
*txdesc
;
1370 for (; mdp
->cur_tx
- mdp
->dirty_tx
> 0; mdp
->dirty_tx
++) {
1371 entry
= mdp
->dirty_tx
% mdp
->num_tx_ring
;
1372 txdesc
= &mdp
->tx_ring
[entry
];
1373 if (txdesc
->status
& cpu_to_edmac(mdp
, TD_TACT
))
1375 /* Free the original skb. */
1376 if (mdp
->tx_skbuff
[entry
]) {
1377 dma_unmap_single(&ndev
->dev
, txdesc
->addr
,
1378 txdesc
->buffer_length
, DMA_TO_DEVICE
);
1379 dev_kfree_skb_irq(mdp
->tx_skbuff
[entry
]);
1380 mdp
->tx_skbuff
[entry
] = NULL
;
1383 txdesc
->status
= cpu_to_edmac(mdp
, TD_TFP
);
1384 if (entry
>= mdp
->num_tx_ring
- 1)
1385 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TDLE
);
1387 ndev
->stats
.tx_packets
++;
1388 ndev
->stats
.tx_bytes
+= txdesc
->buffer_length
;
1393 /* Packet receive function */
1394 static int sh_eth_rx(struct net_device
*ndev
, u32 intr_status
, int *quota
)
1396 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1397 struct sh_eth_rxdesc
*rxdesc
;
1399 int entry
= mdp
->cur_rx
% mdp
->num_rx_ring
;
1400 int boguscnt
= (mdp
->dirty_rx
+ mdp
->num_rx_ring
) - mdp
->cur_rx
;
1401 struct sk_buff
*skb
;
1405 rxdesc
= &mdp
->rx_ring
[entry
];
1406 while (!(rxdesc
->status
& cpu_to_edmac(mdp
, RD_RACT
))) {
1407 desc_status
= edmac_to_cpu(mdp
, rxdesc
->status
);
1408 pkt_len
= rxdesc
->frame_length
;
1418 if (!(desc_status
& RDFEND
))
1419 ndev
->stats
.rx_length_errors
++;
1421 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1422 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1423 * bit 0. However, in case of the R8A7740, R8A779x, and
1424 * R7S72100 the RFS bits are from bit 25 to bit 16. So, the
1425 * driver needs right shifting by 16.
1427 if (mdp
->cd
->shift_rd0
)
1430 if (desc_status
& (RD_RFS1
| RD_RFS2
| RD_RFS3
| RD_RFS4
|
1431 RD_RFS5
| RD_RFS6
| RD_RFS10
)) {
1432 ndev
->stats
.rx_errors
++;
1433 if (desc_status
& RD_RFS1
)
1434 ndev
->stats
.rx_crc_errors
++;
1435 if (desc_status
& RD_RFS2
)
1436 ndev
->stats
.rx_frame_errors
++;
1437 if (desc_status
& RD_RFS3
)
1438 ndev
->stats
.rx_length_errors
++;
1439 if (desc_status
& RD_RFS4
)
1440 ndev
->stats
.rx_length_errors
++;
1441 if (desc_status
& RD_RFS6
)
1442 ndev
->stats
.rx_missed_errors
++;
1443 if (desc_status
& RD_RFS10
)
1444 ndev
->stats
.rx_over_errors
++;
1446 if (!mdp
->cd
->hw_swap
)
1448 phys_to_virt(ALIGN(rxdesc
->addr
, 4)),
1450 skb
= mdp
->rx_skbuff
[entry
];
1451 mdp
->rx_skbuff
[entry
] = NULL
;
1452 if (mdp
->cd
->rpadir
)
1453 skb_reserve(skb
, NET_IP_ALIGN
);
1454 dma_sync_single_for_cpu(&ndev
->dev
, rxdesc
->addr
,
1457 skb_put(skb
, pkt_len
);
1458 skb
->protocol
= eth_type_trans(skb
, ndev
);
1459 netif_receive_skb(skb
);
1460 ndev
->stats
.rx_packets
++;
1461 ndev
->stats
.rx_bytes
+= pkt_len
;
1463 rxdesc
->status
|= cpu_to_edmac(mdp
, RD_RACT
);
1464 entry
= (++mdp
->cur_rx
) % mdp
->num_rx_ring
;
1465 rxdesc
= &mdp
->rx_ring
[entry
];
1468 /* Refill the Rx ring buffers. */
1469 for (; mdp
->cur_rx
- mdp
->dirty_rx
> 0; mdp
->dirty_rx
++) {
1470 entry
= mdp
->dirty_rx
% mdp
->num_rx_ring
;
1471 rxdesc
= &mdp
->rx_ring
[entry
];
1472 /* The size of the buffer is 16 byte boundary. */
1473 rxdesc
->buffer_length
= ALIGN(mdp
->rx_buf_sz
, 16);
1475 if (mdp
->rx_skbuff
[entry
] == NULL
) {
1476 skb
= netdev_alloc_skb(ndev
, mdp
->rx_buf_sz
);
1477 mdp
->rx_skbuff
[entry
] = skb
;
1479 break; /* Better luck next round. */
1480 dma_map_single(&ndev
->dev
, skb
->data
, mdp
->rx_buf_sz
,
1482 sh_eth_set_receive_align(skb
);
1484 skb_checksum_none_assert(skb
);
1485 rxdesc
->addr
= virt_to_phys(PTR_ALIGN(skb
->data
, 4));
1487 if (entry
>= mdp
->num_rx_ring
- 1)
1489 cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
| RD_RDEL
);
1492 cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
);
1495 /* Restart Rx engine if stopped. */
1496 /* If we don't need to check status, don't. -KDU */
1497 if (!(sh_eth_read(ndev
, EDRRR
) & EDRRR_R
)) {
1498 /* fix the values for the next receiving if RDE is set */
1499 if (intr_status
& EESR_RDE
) {
1500 u32 count
= (sh_eth_read(ndev
, RDFAR
) -
1501 sh_eth_read(ndev
, RDLAR
)) >> 4;
1503 mdp
->cur_rx
= count
;
1504 mdp
->dirty_rx
= count
;
1506 sh_eth_write(ndev
, EDRRR_R
, EDRRR
);
1512 static void sh_eth_rcv_snd_disable(struct net_device
*ndev
)
1514 /* disable tx and rx */
1515 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) &
1516 ~(ECMR_RE
| ECMR_TE
), ECMR
);
1519 static void sh_eth_rcv_snd_enable(struct net_device
*ndev
)
1521 /* enable tx and rx */
1522 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) |
1523 (ECMR_RE
| ECMR_TE
), ECMR
);
1526 /* error control function */
1527 static void sh_eth_error(struct net_device
*ndev
, int intr_status
)
1529 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1534 if (intr_status
& EESR_ECI
) {
1535 felic_stat
= sh_eth_read(ndev
, ECSR
);
1536 sh_eth_write(ndev
, felic_stat
, ECSR
); /* clear int */
1537 if (felic_stat
& ECSR_ICD
)
1538 ndev
->stats
.tx_carrier_errors
++;
1539 if (felic_stat
& ECSR_LCHNG
) {
1541 if (mdp
->cd
->no_psr
|| mdp
->no_ether_link
) {
1544 link_stat
= (sh_eth_read(ndev
, PSR
));
1545 if (mdp
->ether_link_active_low
)
1546 link_stat
= ~link_stat
;
1548 if (!(link_stat
& PHY_ST_LINK
)) {
1549 sh_eth_rcv_snd_disable(ndev
);
1552 sh_eth_write(ndev
, sh_eth_read(ndev
, EESIPR
) &
1553 ~DMAC_M_ECI
, EESIPR
);
1555 sh_eth_write(ndev
, sh_eth_read(ndev
, ECSR
),
1557 sh_eth_write(ndev
, sh_eth_read(ndev
, EESIPR
) |
1558 DMAC_M_ECI
, EESIPR
);
1559 /* enable tx and rx */
1560 sh_eth_rcv_snd_enable(ndev
);
1566 if (intr_status
& EESR_TWB
) {
1567 /* Unused write back interrupt */
1568 if (intr_status
& EESR_TABT
) { /* Transmit Abort int */
1569 ndev
->stats
.tx_aborted_errors
++;
1570 netif_err(mdp
, tx_err
, ndev
, "Transmit Abort\n");
1574 if (intr_status
& EESR_RABT
) {
1575 /* Receive Abort int */
1576 if (intr_status
& EESR_RFRMER
) {
1577 /* Receive Frame Overflow int */
1578 ndev
->stats
.rx_frame_errors
++;
1579 netif_err(mdp
, rx_err
, ndev
, "Receive Abort\n");
1583 if (intr_status
& EESR_TDE
) {
1584 /* Transmit Descriptor Empty int */
1585 ndev
->stats
.tx_fifo_errors
++;
1586 netif_err(mdp
, tx_err
, ndev
, "Transmit Descriptor Empty\n");
1589 if (intr_status
& EESR_TFE
) {
1590 /* FIFO under flow */
1591 ndev
->stats
.tx_fifo_errors
++;
1592 netif_err(mdp
, tx_err
, ndev
, "Transmit FIFO Under flow\n");
1595 if (intr_status
& EESR_RDE
) {
1596 /* Receive Descriptor Empty int */
1597 ndev
->stats
.rx_over_errors
++;
1598 netif_err(mdp
, rx_err
, ndev
, "Receive Descriptor Empty\n");
1601 if (intr_status
& EESR_RFE
) {
1602 /* Receive FIFO Overflow int */
1603 ndev
->stats
.rx_fifo_errors
++;
1604 netif_err(mdp
, rx_err
, ndev
, "Receive FIFO Overflow\n");
1607 if (!mdp
->cd
->no_ade
&& (intr_status
& EESR_ADE
)) {
1609 ndev
->stats
.tx_fifo_errors
++;
1610 netif_err(mdp
, tx_err
, ndev
, "Address Error\n");
1613 mask
= EESR_TWB
| EESR_TABT
| EESR_ADE
| EESR_TDE
| EESR_TFE
;
1614 if (mdp
->cd
->no_ade
)
1616 if (intr_status
& mask
) {
1618 u32 edtrr
= sh_eth_read(ndev
, EDTRR
);
1621 netdev_err(ndev
, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1622 intr_status
, mdp
->cur_tx
, mdp
->dirty_tx
,
1623 (u32
)ndev
->state
, edtrr
);
1624 /* dirty buffer free */
1625 sh_eth_txfree(ndev
);
1628 if (edtrr
^ sh_eth_get_edtrr_trns(mdp
)) {
1630 sh_eth_write(ndev
, sh_eth_get_edtrr_trns(mdp
), EDTRR
);
1633 netif_wake_queue(ndev
);
1637 static irqreturn_t
sh_eth_interrupt(int irq
, void *netdev
)
1639 struct net_device
*ndev
= netdev
;
1640 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1641 struct sh_eth_cpu_data
*cd
= mdp
->cd
;
1642 irqreturn_t ret
= IRQ_NONE
;
1643 unsigned long intr_status
, intr_enable
;
1645 spin_lock(&mdp
->lock
);
1647 /* Get interrupt status */
1648 intr_status
= sh_eth_read(ndev
, EESR
);
1649 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1650 * enabled since it's the one that comes thru regardless of the mask,
1651 * and we need to fully handle it in sh_eth_error() in order to quench
1652 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1654 intr_enable
= sh_eth_read(ndev
, EESIPR
);
1655 intr_status
&= intr_enable
| DMAC_M_ECI
;
1656 if (intr_status
& (EESR_RX_CHECK
| cd
->tx_check
| cd
->eesr_err_check
))
1661 if (intr_status
& EESR_RX_CHECK
) {
1662 if (napi_schedule_prep(&mdp
->napi
)) {
1663 /* Mask Rx interrupts */
1664 sh_eth_write(ndev
, intr_enable
& ~EESR_RX_CHECK
,
1666 __napi_schedule(&mdp
->napi
);
1669 "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n",
1670 intr_status
, intr_enable
);
1675 if (intr_status
& cd
->tx_check
) {
1676 /* Clear Tx interrupts */
1677 sh_eth_write(ndev
, intr_status
& cd
->tx_check
, EESR
);
1679 sh_eth_txfree(ndev
);
1680 netif_wake_queue(ndev
);
1683 if (intr_status
& cd
->eesr_err_check
) {
1684 /* Clear error interrupts */
1685 sh_eth_write(ndev
, intr_status
& cd
->eesr_err_check
, EESR
);
1687 sh_eth_error(ndev
, intr_status
);
1691 spin_unlock(&mdp
->lock
);
1696 static int sh_eth_poll(struct napi_struct
*napi
, int budget
)
1698 struct sh_eth_private
*mdp
= container_of(napi
, struct sh_eth_private
,
1700 struct net_device
*ndev
= napi
->dev
;
1702 unsigned long intr_status
;
1705 intr_status
= sh_eth_read(ndev
, EESR
);
1706 if (!(intr_status
& EESR_RX_CHECK
))
1708 /* Clear Rx interrupts */
1709 sh_eth_write(ndev
, intr_status
& EESR_RX_CHECK
, EESR
);
1711 if (sh_eth_rx(ndev
, intr_status
, "a
))
1715 napi_complete(napi
);
1717 /* Reenable Rx interrupts */
1718 sh_eth_write(ndev
, mdp
->cd
->eesipr_value
, EESIPR
);
1720 return budget
- quota
;
1723 /* PHY state control function */
1724 static void sh_eth_adjust_link(struct net_device
*ndev
)
1726 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1727 struct phy_device
*phydev
= mdp
->phydev
;
1731 if (phydev
->duplex
!= mdp
->duplex
) {
1733 mdp
->duplex
= phydev
->duplex
;
1734 if (mdp
->cd
->set_duplex
)
1735 mdp
->cd
->set_duplex(ndev
);
1738 if (phydev
->speed
!= mdp
->speed
) {
1740 mdp
->speed
= phydev
->speed
;
1741 if (mdp
->cd
->set_rate
)
1742 mdp
->cd
->set_rate(ndev
);
1746 sh_eth_read(ndev
, ECMR
) & ~ECMR_TXF
,
1749 mdp
->link
= phydev
->link
;
1750 if (mdp
->cd
->no_psr
|| mdp
->no_ether_link
)
1751 sh_eth_rcv_snd_enable(ndev
);
1753 } else if (mdp
->link
) {
1758 if (mdp
->cd
->no_psr
|| mdp
->no_ether_link
)
1759 sh_eth_rcv_snd_disable(ndev
);
1762 if (new_state
&& netif_msg_link(mdp
))
1763 phy_print_status(phydev
);
1766 /* PHY init function */
1767 static int sh_eth_phy_init(struct net_device
*ndev
)
1769 struct device_node
*np
= ndev
->dev
.parent
->of_node
;
1770 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1771 struct phy_device
*phydev
= NULL
;
1777 /* Try connect to PHY */
1779 struct device_node
*pn
;
1781 pn
= of_parse_phandle(np
, "phy-handle", 0);
1782 phydev
= of_phy_connect(ndev
, pn
,
1783 sh_eth_adjust_link
, 0,
1784 mdp
->phy_interface
);
1787 phydev
= ERR_PTR(-ENOENT
);
1789 char phy_id
[MII_BUS_ID_SIZE
+ 3];
1791 snprintf(phy_id
, sizeof(phy_id
), PHY_ID_FMT
,
1792 mdp
->mii_bus
->id
, mdp
->phy_id
);
1794 phydev
= phy_connect(ndev
, phy_id
, sh_eth_adjust_link
,
1795 mdp
->phy_interface
);
1798 if (IS_ERR(phydev
)) {
1799 netdev_err(ndev
, "failed to connect PHY\n");
1800 return PTR_ERR(phydev
);
1803 netdev_info(ndev
, "attached PHY %d (IRQ %d) to driver %s\n",
1804 phydev
->addr
, phydev
->irq
, phydev
->drv
->name
);
1806 mdp
->phydev
= phydev
;
1811 /* PHY control start function */
1812 static int sh_eth_phy_start(struct net_device
*ndev
)
1814 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1817 ret
= sh_eth_phy_init(ndev
);
1821 phy_start(mdp
->phydev
);
1826 static int sh_eth_get_settings(struct net_device
*ndev
,
1827 struct ethtool_cmd
*ecmd
)
1829 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1830 unsigned long flags
;
1833 spin_lock_irqsave(&mdp
->lock
, flags
);
1834 ret
= phy_ethtool_gset(mdp
->phydev
, ecmd
);
1835 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1840 static int sh_eth_set_settings(struct net_device
*ndev
,
1841 struct ethtool_cmd
*ecmd
)
1843 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1844 unsigned long flags
;
1847 spin_lock_irqsave(&mdp
->lock
, flags
);
1849 /* disable tx and rx */
1850 sh_eth_rcv_snd_disable(ndev
);
1852 ret
= phy_ethtool_sset(mdp
->phydev
, ecmd
);
1856 if (ecmd
->duplex
== DUPLEX_FULL
)
1861 if (mdp
->cd
->set_duplex
)
1862 mdp
->cd
->set_duplex(ndev
);
1867 /* enable tx and rx */
1868 sh_eth_rcv_snd_enable(ndev
);
1870 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1875 static int sh_eth_nway_reset(struct net_device
*ndev
)
1877 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1878 unsigned long flags
;
1881 spin_lock_irqsave(&mdp
->lock
, flags
);
1882 ret
= phy_start_aneg(mdp
->phydev
);
1883 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1888 static u32
sh_eth_get_msglevel(struct net_device
*ndev
)
1890 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1891 return mdp
->msg_enable
;
1894 static void sh_eth_set_msglevel(struct net_device
*ndev
, u32 value
)
1896 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1897 mdp
->msg_enable
= value
;
1900 static const char sh_eth_gstrings_stats
[][ETH_GSTRING_LEN
] = {
1901 "rx_current", "tx_current",
1902 "rx_dirty", "tx_dirty",
1904 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1906 static int sh_eth_get_sset_count(struct net_device
*netdev
, int sset
)
1910 return SH_ETH_STATS_LEN
;
1916 static void sh_eth_get_ethtool_stats(struct net_device
*ndev
,
1917 struct ethtool_stats
*stats
, u64
*data
)
1919 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1922 /* device-specific stats */
1923 data
[i
++] = mdp
->cur_rx
;
1924 data
[i
++] = mdp
->cur_tx
;
1925 data
[i
++] = mdp
->dirty_rx
;
1926 data
[i
++] = mdp
->dirty_tx
;
1929 static void sh_eth_get_strings(struct net_device
*ndev
, u32 stringset
, u8
*data
)
1931 switch (stringset
) {
1933 memcpy(data
, *sh_eth_gstrings_stats
,
1934 sizeof(sh_eth_gstrings_stats
));
1939 static void sh_eth_get_ringparam(struct net_device
*ndev
,
1940 struct ethtool_ringparam
*ring
)
1942 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1944 ring
->rx_max_pending
= RX_RING_MAX
;
1945 ring
->tx_max_pending
= TX_RING_MAX
;
1946 ring
->rx_pending
= mdp
->num_rx_ring
;
1947 ring
->tx_pending
= mdp
->num_tx_ring
;
1950 static int sh_eth_set_ringparam(struct net_device
*ndev
,
1951 struct ethtool_ringparam
*ring
)
1953 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1956 if (ring
->tx_pending
> TX_RING_MAX
||
1957 ring
->rx_pending
> RX_RING_MAX
||
1958 ring
->tx_pending
< TX_RING_MIN
||
1959 ring
->rx_pending
< RX_RING_MIN
)
1961 if (ring
->rx_mini_pending
|| ring
->rx_jumbo_pending
)
1964 if (netif_running(ndev
)) {
1965 netif_tx_disable(ndev
);
1966 /* Disable interrupts by clearing the interrupt mask. */
1967 sh_eth_write(ndev
, 0x0000, EESIPR
);
1968 /* Stop the chip's Tx and Rx processes. */
1969 sh_eth_write(ndev
, 0, EDTRR
);
1970 sh_eth_write(ndev
, 0, EDRRR
);
1971 synchronize_irq(ndev
->irq
);
1974 /* Free all the skbuffs in the Rx queue. */
1975 sh_eth_ring_free(ndev
);
1976 /* Free DMA buffer */
1977 sh_eth_free_dma_buffer(mdp
);
1979 /* Set new parameters */
1980 mdp
->num_rx_ring
= ring
->rx_pending
;
1981 mdp
->num_tx_ring
= ring
->tx_pending
;
1983 ret
= sh_eth_ring_init(ndev
);
1985 netdev_err(ndev
, "%s: sh_eth_ring_init failed.\n", __func__
);
1988 ret
= sh_eth_dev_init(ndev
, false);
1990 netdev_err(ndev
, "%s: sh_eth_dev_init failed.\n", __func__
);
1994 if (netif_running(ndev
)) {
1995 sh_eth_write(ndev
, mdp
->cd
->eesipr_value
, EESIPR
);
1996 /* Setting the Rx mode will start the Rx process. */
1997 sh_eth_write(ndev
, EDRRR_R
, EDRRR
);
1998 netif_wake_queue(ndev
);
2004 static const struct ethtool_ops sh_eth_ethtool_ops
= {
2005 .get_settings
= sh_eth_get_settings
,
2006 .set_settings
= sh_eth_set_settings
,
2007 .nway_reset
= sh_eth_nway_reset
,
2008 .get_msglevel
= sh_eth_get_msglevel
,
2009 .set_msglevel
= sh_eth_set_msglevel
,
2010 .get_link
= ethtool_op_get_link
,
2011 .get_strings
= sh_eth_get_strings
,
2012 .get_ethtool_stats
= sh_eth_get_ethtool_stats
,
2013 .get_sset_count
= sh_eth_get_sset_count
,
2014 .get_ringparam
= sh_eth_get_ringparam
,
2015 .set_ringparam
= sh_eth_set_ringparam
,
2018 /* network device open function */
2019 static int sh_eth_open(struct net_device
*ndev
)
2022 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2024 pm_runtime_get_sync(&mdp
->pdev
->dev
);
2026 napi_enable(&mdp
->napi
);
2028 ret
= request_irq(ndev
->irq
, sh_eth_interrupt
,
2029 mdp
->cd
->irq_flags
, ndev
->name
, ndev
);
2031 netdev_err(ndev
, "Can not assign IRQ number\n");
2035 /* Descriptor set */
2036 ret
= sh_eth_ring_init(ndev
);
2041 ret
= sh_eth_dev_init(ndev
, true);
2045 /* PHY control start*/
2046 ret
= sh_eth_phy_start(ndev
);
2053 free_irq(ndev
->irq
, ndev
);
2055 napi_disable(&mdp
->napi
);
2056 pm_runtime_put_sync(&mdp
->pdev
->dev
);
2060 /* Timeout function */
2061 static void sh_eth_tx_timeout(struct net_device
*ndev
)
2063 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2064 struct sh_eth_rxdesc
*rxdesc
;
2067 netif_stop_queue(ndev
);
2069 netif_err(mdp
, timer
, ndev
,
2070 "transmit timed out, status %8.8x, resetting...\n",
2071 (int)sh_eth_read(ndev
, EESR
));
2073 /* tx_errors count up */
2074 ndev
->stats
.tx_errors
++;
2076 /* Free all the skbuffs in the Rx queue. */
2077 for (i
= 0; i
< mdp
->num_rx_ring
; i
++) {
2078 rxdesc
= &mdp
->rx_ring
[i
];
2080 rxdesc
->addr
= 0xBADF00D0;
2081 if (mdp
->rx_skbuff
[i
])
2082 dev_kfree_skb(mdp
->rx_skbuff
[i
]);
2083 mdp
->rx_skbuff
[i
] = NULL
;
2085 for (i
= 0; i
< mdp
->num_tx_ring
; i
++) {
2086 if (mdp
->tx_skbuff
[i
])
2087 dev_kfree_skb(mdp
->tx_skbuff
[i
]);
2088 mdp
->tx_skbuff
[i
] = NULL
;
2092 sh_eth_dev_init(ndev
, true);
2095 /* Packet transmit function */
2096 static int sh_eth_start_xmit(struct sk_buff
*skb
, struct net_device
*ndev
)
2098 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2099 struct sh_eth_txdesc
*txdesc
;
2101 unsigned long flags
;
2103 spin_lock_irqsave(&mdp
->lock
, flags
);
2104 if ((mdp
->cur_tx
- mdp
->dirty_tx
) >= (mdp
->num_tx_ring
- 4)) {
2105 if (!sh_eth_txfree(ndev
)) {
2106 netif_warn(mdp
, tx_queued
, ndev
, "TxFD exhausted.\n");
2107 netif_stop_queue(ndev
);
2108 spin_unlock_irqrestore(&mdp
->lock
, flags
);
2109 return NETDEV_TX_BUSY
;
2112 spin_unlock_irqrestore(&mdp
->lock
, flags
);
2114 entry
= mdp
->cur_tx
% mdp
->num_tx_ring
;
2115 mdp
->tx_skbuff
[entry
] = skb
;
2116 txdesc
= &mdp
->tx_ring
[entry
];
2118 if (!mdp
->cd
->hw_swap
)
2119 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc
->addr
, 4)),
2121 txdesc
->addr
= dma_map_single(&ndev
->dev
, skb
->data
, skb
->len
,
2123 if (skb
->len
< ETH_ZLEN
)
2124 txdesc
->buffer_length
= ETH_ZLEN
;
2126 txdesc
->buffer_length
= skb
->len
;
2128 if (entry
>= mdp
->num_tx_ring
- 1)
2129 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TACT
| TD_TDLE
);
2131 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TACT
);
2135 if (!(sh_eth_read(ndev
, EDTRR
) & sh_eth_get_edtrr_trns(mdp
)))
2136 sh_eth_write(ndev
, sh_eth_get_edtrr_trns(mdp
), EDTRR
);
2138 return NETDEV_TX_OK
;
2141 /* device close function */
2142 static int sh_eth_close(struct net_device
*ndev
)
2144 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2146 netif_stop_queue(ndev
);
2148 /* Disable interrupts by clearing the interrupt mask. */
2149 sh_eth_write(ndev
, 0x0000, EESIPR
);
2151 /* Stop the chip's Tx and Rx processes. */
2152 sh_eth_write(ndev
, 0, EDTRR
);
2153 sh_eth_write(ndev
, 0, EDRRR
);
2155 /* PHY Disconnect */
2157 phy_stop(mdp
->phydev
);
2158 phy_disconnect(mdp
->phydev
);
2161 free_irq(ndev
->irq
, ndev
);
2163 napi_disable(&mdp
->napi
);
2165 /* Free all the skbuffs in the Rx queue. */
2166 sh_eth_ring_free(ndev
);
2168 /* free DMA buffer */
2169 sh_eth_free_dma_buffer(mdp
);
2171 pm_runtime_put_sync(&mdp
->pdev
->dev
);
2176 static struct net_device_stats
*sh_eth_get_stats(struct net_device
*ndev
)
2178 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2180 if (sh_eth_is_rz_fast_ether(mdp
))
2181 return &ndev
->stats
;
2183 pm_runtime_get_sync(&mdp
->pdev
->dev
);
2185 ndev
->stats
.tx_dropped
+= sh_eth_read(ndev
, TROCR
);
2186 sh_eth_write(ndev
, 0, TROCR
); /* (write clear) */
2187 ndev
->stats
.collisions
+= sh_eth_read(ndev
, CDCR
);
2188 sh_eth_write(ndev
, 0, CDCR
); /* (write clear) */
2189 ndev
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, LCCR
);
2190 sh_eth_write(ndev
, 0, LCCR
); /* (write clear) */
2191 if (sh_eth_is_gether(mdp
)) {
2192 ndev
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, CERCR
);
2193 sh_eth_write(ndev
, 0, CERCR
); /* (write clear) */
2194 ndev
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, CEECR
);
2195 sh_eth_write(ndev
, 0, CEECR
); /* (write clear) */
2197 ndev
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, CNDCR
);
2198 sh_eth_write(ndev
, 0, CNDCR
); /* (write clear) */
2200 pm_runtime_put_sync(&mdp
->pdev
->dev
);
2202 return &ndev
->stats
;
2205 /* ioctl to device function */
2206 static int sh_eth_do_ioctl(struct net_device
*ndev
, struct ifreq
*rq
, int cmd
)
2208 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2209 struct phy_device
*phydev
= mdp
->phydev
;
2211 if (!netif_running(ndev
))
2217 return phy_mii_ioctl(phydev
, rq
, cmd
);
2220 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2221 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private
*mdp
,
2224 return sh_eth_tsu_get_offset(mdp
, TSU_POST1
) + (entry
/ 8 * 4);
2227 static u32
sh_eth_tsu_get_post_mask(int entry
)
2229 return 0x0f << (28 - ((entry
% 8) * 4));
2232 static u32
sh_eth_tsu_get_post_bit(struct sh_eth_private
*mdp
, int entry
)
2234 return (0x08 >> (mdp
->port
<< 1)) << (28 - ((entry
% 8) * 4));
2237 static void sh_eth_tsu_enable_cam_entry_post(struct net_device
*ndev
,
2240 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2244 reg_offset
= sh_eth_tsu_get_post_reg_offset(mdp
, entry
);
2245 tmp
= ioread32(reg_offset
);
2246 iowrite32(tmp
| sh_eth_tsu_get_post_bit(mdp
, entry
), reg_offset
);
2249 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device
*ndev
,
2252 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2253 u32 post_mask
, ref_mask
, tmp
;
2256 reg_offset
= sh_eth_tsu_get_post_reg_offset(mdp
, entry
);
2257 post_mask
= sh_eth_tsu_get_post_mask(entry
);
2258 ref_mask
= sh_eth_tsu_get_post_bit(mdp
, entry
) & ~post_mask
;
2260 tmp
= ioread32(reg_offset
);
2261 iowrite32(tmp
& ~post_mask
, reg_offset
);
2263 /* If other port enables, the function returns "true" */
2264 return tmp
& ref_mask
;
2267 static int sh_eth_tsu_busy(struct net_device
*ndev
)
2269 int timeout
= SH_ETH_TSU_TIMEOUT_MS
* 100;
2270 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2272 while ((sh_eth_tsu_read(mdp
, TSU_ADSBSY
) & TSU_ADSBSY_0
)) {
2276 netdev_err(ndev
, "%s: timeout\n", __func__
);
2284 static int sh_eth_tsu_write_entry(struct net_device
*ndev
, void *reg
,
2289 val
= addr
[0] << 24 | addr
[1] << 16 | addr
[2] << 8 | addr
[3];
2290 iowrite32(val
, reg
);
2291 if (sh_eth_tsu_busy(ndev
) < 0)
2294 val
= addr
[4] << 8 | addr
[5];
2295 iowrite32(val
, reg
+ 4);
2296 if (sh_eth_tsu_busy(ndev
) < 0)
2302 static void sh_eth_tsu_read_entry(void *reg
, u8
*addr
)
2306 val
= ioread32(reg
);
2307 addr
[0] = (val
>> 24) & 0xff;
2308 addr
[1] = (val
>> 16) & 0xff;
2309 addr
[2] = (val
>> 8) & 0xff;
2310 addr
[3] = val
& 0xff;
2311 val
= ioread32(reg
+ 4);
2312 addr
[4] = (val
>> 8) & 0xff;
2313 addr
[5] = val
& 0xff;
2317 static int sh_eth_tsu_find_entry(struct net_device
*ndev
, const u8
*addr
)
2319 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2320 void *reg_offset
= sh_eth_tsu_get_offset(mdp
, TSU_ADRH0
);
2322 u8 c_addr
[ETH_ALEN
];
2324 for (i
= 0; i
< SH_ETH_TSU_CAM_ENTRIES
; i
++, reg_offset
+= 8) {
2325 sh_eth_tsu_read_entry(reg_offset
, c_addr
);
2326 if (ether_addr_equal(addr
, c_addr
))
2333 static int sh_eth_tsu_find_empty(struct net_device
*ndev
)
2338 memset(blank
, 0, sizeof(blank
));
2339 entry
= sh_eth_tsu_find_entry(ndev
, blank
);
2340 return (entry
< 0) ? -ENOMEM
: entry
;
2343 static int sh_eth_tsu_disable_cam_entry_table(struct net_device
*ndev
,
2346 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2347 void *reg_offset
= sh_eth_tsu_get_offset(mdp
, TSU_ADRH0
);
2351 sh_eth_tsu_write(mdp
, sh_eth_tsu_read(mdp
, TSU_TEN
) &
2352 ~(1 << (31 - entry
)), TSU_TEN
);
2354 memset(blank
, 0, sizeof(blank
));
2355 ret
= sh_eth_tsu_write_entry(ndev
, reg_offset
+ entry
* 8, blank
);
2361 static int sh_eth_tsu_add_entry(struct net_device
*ndev
, const u8
*addr
)
2363 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2364 void *reg_offset
= sh_eth_tsu_get_offset(mdp
, TSU_ADRH0
);
2370 i
= sh_eth_tsu_find_entry(ndev
, addr
);
2372 /* No entry found, create one */
2373 i
= sh_eth_tsu_find_empty(ndev
);
2376 ret
= sh_eth_tsu_write_entry(ndev
, reg_offset
+ i
* 8, addr
);
2380 /* Enable the entry */
2381 sh_eth_tsu_write(mdp
, sh_eth_tsu_read(mdp
, TSU_TEN
) |
2382 (1 << (31 - i
)), TSU_TEN
);
2385 /* Entry found or created, enable POST */
2386 sh_eth_tsu_enable_cam_entry_post(ndev
, i
);
2391 static int sh_eth_tsu_del_entry(struct net_device
*ndev
, const u8
*addr
)
2393 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2399 i
= sh_eth_tsu_find_entry(ndev
, addr
);
2402 if (sh_eth_tsu_disable_cam_entry_post(ndev
, i
))
2405 /* Disable the entry if both ports was disabled */
2406 ret
= sh_eth_tsu_disable_cam_entry_table(ndev
, i
);
2414 static int sh_eth_tsu_purge_all(struct net_device
*ndev
)
2416 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2419 if (unlikely(!mdp
->cd
->tsu
))
2422 for (i
= 0; i
< SH_ETH_TSU_CAM_ENTRIES
; i
++) {
2423 if (sh_eth_tsu_disable_cam_entry_post(ndev
, i
))
2426 /* Disable the entry if both ports was disabled */
2427 ret
= sh_eth_tsu_disable_cam_entry_table(ndev
, i
);
2435 static void sh_eth_tsu_purge_mcast(struct net_device
*ndev
)
2437 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2439 void *reg_offset
= sh_eth_tsu_get_offset(mdp
, TSU_ADRH0
);
2442 if (unlikely(!mdp
->cd
->tsu
))
2445 for (i
= 0; i
< SH_ETH_TSU_CAM_ENTRIES
; i
++, reg_offset
+= 8) {
2446 sh_eth_tsu_read_entry(reg_offset
, addr
);
2447 if (is_multicast_ether_addr(addr
))
2448 sh_eth_tsu_del_entry(ndev
, addr
);
2452 /* Multicast reception directions set */
2453 static void sh_eth_set_multicast_list(struct net_device
*ndev
)
2455 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2458 unsigned long flags
;
2460 spin_lock_irqsave(&mdp
->lock
, flags
);
2461 /* Initial condition is MCT = 1, PRM = 0.
2462 * Depending on ndev->flags, set PRM or clear MCT
2464 ecmr_bits
= (sh_eth_read(ndev
, ECMR
) & ~ECMR_PRM
) | ECMR_MCT
;
2466 if (!(ndev
->flags
& IFF_MULTICAST
)) {
2467 sh_eth_tsu_purge_mcast(ndev
);
2470 if (ndev
->flags
& IFF_ALLMULTI
) {
2471 sh_eth_tsu_purge_mcast(ndev
);
2472 ecmr_bits
&= ~ECMR_MCT
;
2476 if (ndev
->flags
& IFF_PROMISC
) {
2477 sh_eth_tsu_purge_all(ndev
);
2478 ecmr_bits
= (ecmr_bits
& ~ECMR_MCT
) | ECMR_PRM
;
2479 } else if (mdp
->cd
->tsu
) {
2480 struct netdev_hw_addr
*ha
;
2481 netdev_for_each_mc_addr(ha
, ndev
) {
2482 if (mcast_all
&& is_multicast_ether_addr(ha
->addr
))
2485 if (sh_eth_tsu_add_entry(ndev
, ha
->addr
) < 0) {
2487 sh_eth_tsu_purge_mcast(ndev
);
2488 ecmr_bits
&= ~ECMR_MCT
;
2494 /* Normal, unicast/broadcast-only mode. */
2495 ecmr_bits
= (ecmr_bits
& ~ECMR_PRM
) | ECMR_MCT
;
2498 /* update the ethernet mode */
2499 sh_eth_write(ndev
, ecmr_bits
, ECMR
);
2501 spin_unlock_irqrestore(&mdp
->lock
, flags
);
2504 static int sh_eth_get_vtag_index(struct sh_eth_private
*mdp
)
2512 static int sh_eth_vlan_rx_add_vid(struct net_device
*ndev
,
2513 __be16 proto
, u16 vid
)
2515 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2516 int vtag_reg_index
= sh_eth_get_vtag_index(mdp
);
2518 if (unlikely(!mdp
->cd
->tsu
))
2521 /* No filtering if vid = 0 */
2525 mdp
->vlan_num_ids
++;
2527 /* The controller has one VLAN tag HW filter. So, if the filter is
2528 * already enabled, the driver disables it and the filte
2530 if (mdp
->vlan_num_ids
> 1) {
2531 /* disable VLAN filter */
2532 sh_eth_tsu_write(mdp
, 0, vtag_reg_index
);
2536 sh_eth_tsu_write(mdp
, TSU_VTAG_ENABLE
| (vid
& TSU_VTAG_VID_MASK
),
2542 static int sh_eth_vlan_rx_kill_vid(struct net_device
*ndev
,
2543 __be16 proto
, u16 vid
)
2545 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2546 int vtag_reg_index
= sh_eth_get_vtag_index(mdp
);
2548 if (unlikely(!mdp
->cd
->tsu
))
2551 /* No filtering if vid = 0 */
2555 mdp
->vlan_num_ids
--;
2556 sh_eth_tsu_write(mdp
, 0, vtag_reg_index
);
2561 /* SuperH's TSU register init function */
2562 static void sh_eth_tsu_init(struct sh_eth_private
*mdp
)
2564 if (sh_eth_is_rz_fast_ether(mdp
)) {
2565 sh_eth_tsu_write(mdp
, 0, TSU_TEN
); /* Disable all CAM entry */
2569 sh_eth_tsu_write(mdp
, 0, TSU_FWEN0
); /* Disable forward(0->1) */
2570 sh_eth_tsu_write(mdp
, 0, TSU_FWEN1
); /* Disable forward(1->0) */
2571 sh_eth_tsu_write(mdp
, 0, TSU_FCM
); /* forward fifo 3k-3k */
2572 sh_eth_tsu_write(mdp
, 0xc, TSU_BSYSL0
);
2573 sh_eth_tsu_write(mdp
, 0xc, TSU_BSYSL1
);
2574 sh_eth_tsu_write(mdp
, 0, TSU_PRISL0
);
2575 sh_eth_tsu_write(mdp
, 0, TSU_PRISL1
);
2576 sh_eth_tsu_write(mdp
, 0, TSU_FWSL0
);
2577 sh_eth_tsu_write(mdp
, 0, TSU_FWSL1
);
2578 sh_eth_tsu_write(mdp
, TSU_FWSLC_POSTENU
| TSU_FWSLC_POSTENL
, TSU_FWSLC
);
2579 if (sh_eth_is_gether(mdp
)) {
2580 sh_eth_tsu_write(mdp
, 0, TSU_QTAG0
); /* Disable QTAG(0->1) */
2581 sh_eth_tsu_write(mdp
, 0, TSU_QTAG1
); /* Disable QTAG(1->0) */
2583 sh_eth_tsu_write(mdp
, 0, TSU_QTAGM0
); /* Disable QTAG(0->1) */
2584 sh_eth_tsu_write(mdp
, 0, TSU_QTAGM1
); /* Disable QTAG(1->0) */
2586 sh_eth_tsu_write(mdp
, 0, TSU_FWSR
); /* all interrupt status clear */
2587 sh_eth_tsu_write(mdp
, 0, TSU_FWINMK
); /* Disable all interrupt */
2588 sh_eth_tsu_write(mdp
, 0, TSU_TEN
); /* Disable all CAM entry */
2589 sh_eth_tsu_write(mdp
, 0, TSU_POST1
); /* Disable CAM entry [ 0- 7] */
2590 sh_eth_tsu_write(mdp
, 0, TSU_POST2
); /* Disable CAM entry [ 8-15] */
2591 sh_eth_tsu_write(mdp
, 0, TSU_POST3
); /* Disable CAM entry [16-23] */
2592 sh_eth_tsu_write(mdp
, 0, TSU_POST4
); /* Disable CAM entry [24-31] */
2595 /* MDIO bus release function */
2596 static int sh_mdio_release(struct sh_eth_private
*mdp
)
2598 /* unregister mdio bus */
2599 mdiobus_unregister(mdp
->mii_bus
);
2601 /* free bitbang info */
2602 free_mdio_bitbang(mdp
->mii_bus
);
2607 /* MDIO bus init function */
2608 static int sh_mdio_init(struct sh_eth_private
*mdp
,
2609 struct sh_eth_plat_data
*pd
)
2612 struct bb_info
*bitbang
;
2613 struct platform_device
*pdev
= mdp
->pdev
;
2614 struct device
*dev
= &mdp
->pdev
->dev
;
2616 /* create bit control struct for PHY */
2617 bitbang
= devm_kzalloc(dev
, sizeof(struct bb_info
), GFP_KERNEL
);
2622 bitbang
->addr
= mdp
->addr
+ mdp
->reg_offset
[PIR
];
2623 bitbang
->set_gate
= pd
->set_mdio_gate
;
2624 bitbang
->mdi_msk
= PIR_MDI
;
2625 bitbang
->mdo_msk
= PIR_MDO
;
2626 bitbang
->mmd_msk
= PIR_MMD
;
2627 bitbang
->mdc_msk
= PIR_MDC
;
2628 bitbang
->ctrl
.ops
= &bb_ops
;
2630 /* MII controller setting */
2631 mdp
->mii_bus
= alloc_mdio_bitbang(&bitbang
->ctrl
);
2635 /* Hook up MII support for ethtool */
2636 mdp
->mii_bus
->name
= "sh_mii";
2637 mdp
->mii_bus
->parent
= dev
;
2638 snprintf(mdp
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%s-%x",
2639 pdev
->name
, pdev
->id
);
2642 mdp
->mii_bus
->irq
= devm_kmalloc_array(dev
, PHY_MAX_ADDR
, sizeof(int),
2644 if (!mdp
->mii_bus
->irq
) {
2649 /* register MDIO bus */
2651 ret
= of_mdiobus_register(mdp
->mii_bus
, dev
->of_node
);
2653 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
2654 mdp
->mii_bus
->irq
[i
] = PHY_POLL
;
2655 if (pd
->phy_irq
> 0)
2656 mdp
->mii_bus
->irq
[pd
->phy
] = pd
->phy_irq
;
2658 ret
= mdiobus_register(mdp
->mii_bus
);
2667 free_mdio_bitbang(mdp
->mii_bus
);
2671 static const u16
*sh_eth_get_register_offset(int register_type
)
2673 const u16
*reg_offset
= NULL
;
2675 switch (register_type
) {
2676 case SH_ETH_REG_GIGABIT
:
2677 reg_offset
= sh_eth_offset_gigabit
;
2679 case SH_ETH_REG_FAST_RZ
:
2680 reg_offset
= sh_eth_offset_fast_rz
;
2682 case SH_ETH_REG_FAST_RCAR
:
2683 reg_offset
= sh_eth_offset_fast_rcar
;
2685 case SH_ETH_REG_FAST_SH4
:
2686 reg_offset
= sh_eth_offset_fast_sh4
;
2688 case SH_ETH_REG_FAST_SH3_SH2
:
2689 reg_offset
= sh_eth_offset_fast_sh3_sh2
;
2698 static const struct net_device_ops sh_eth_netdev_ops
= {
2699 .ndo_open
= sh_eth_open
,
2700 .ndo_stop
= sh_eth_close
,
2701 .ndo_start_xmit
= sh_eth_start_xmit
,
2702 .ndo_get_stats
= sh_eth_get_stats
,
2703 .ndo_tx_timeout
= sh_eth_tx_timeout
,
2704 .ndo_do_ioctl
= sh_eth_do_ioctl
,
2705 .ndo_validate_addr
= eth_validate_addr
,
2706 .ndo_set_mac_address
= eth_mac_addr
,
2707 .ndo_change_mtu
= eth_change_mtu
,
2710 static const struct net_device_ops sh_eth_netdev_ops_tsu
= {
2711 .ndo_open
= sh_eth_open
,
2712 .ndo_stop
= sh_eth_close
,
2713 .ndo_start_xmit
= sh_eth_start_xmit
,
2714 .ndo_get_stats
= sh_eth_get_stats
,
2715 .ndo_set_rx_mode
= sh_eth_set_multicast_list
,
2716 .ndo_vlan_rx_add_vid
= sh_eth_vlan_rx_add_vid
,
2717 .ndo_vlan_rx_kill_vid
= sh_eth_vlan_rx_kill_vid
,
2718 .ndo_tx_timeout
= sh_eth_tx_timeout
,
2719 .ndo_do_ioctl
= sh_eth_do_ioctl
,
2720 .ndo_validate_addr
= eth_validate_addr
,
2721 .ndo_set_mac_address
= eth_mac_addr
,
2722 .ndo_change_mtu
= eth_change_mtu
,
2726 static struct sh_eth_plat_data
*sh_eth_parse_dt(struct device
*dev
)
2728 struct device_node
*np
= dev
->of_node
;
2729 struct sh_eth_plat_data
*pdata
;
2730 const char *mac_addr
;
2732 pdata
= devm_kzalloc(dev
, sizeof(*pdata
), GFP_KERNEL
);
2736 pdata
->phy_interface
= of_get_phy_mode(np
);
2738 mac_addr
= of_get_mac_address(np
);
2740 memcpy(pdata
->mac_addr
, mac_addr
, ETH_ALEN
);
2742 pdata
->no_ether_link
=
2743 of_property_read_bool(np
, "renesas,no-ether-link");
2744 pdata
->ether_link_active_low
=
2745 of_property_read_bool(np
, "renesas,ether-link-active-low");
2750 static const struct of_device_id sh_eth_match_table
[] = {
2751 { .compatible
= "renesas,gether-r8a7740", .data
= &r8a7740_data
},
2752 { .compatible
= "renesas,ether-r8a7778", .data
= &r8a777x_data
},
2753 { .compatible
= "renesas,ether-r8a7779", .data
= &r8a777x_data
},
2754 { .compatible
= "renesas,ether-r8a7790", .data
= &r8a779x_data
},
2755 { .compatible
= "renesas,ether-r8a7791", .data
= &r8a779x_data
},
2756 { .compatible
= "renesas,ether-r7s72100", .data
= &r7s72100_data
},
2759 MODULE_DEVICE_TABLE(of
, sh_eth_match_table
);
2761 static inline struct sh_eth_plat_data
*sh_eth_parse_dt(struct device
*dev
)
2767 static int sh_eth_drv_probe(struct platform_device
*pdev
)
2770 struct resource
*res
;
2771 struct net_device
*ndev
= NULL
;
2772 struct sh_eth_private
*mdp
= NULL
;
2773 struct sh_eth_plat_data
*pd
= dev_get_platdata(&pdev
->dev
);
2774 const struct platform_device_id
*id
= platform_get_device_id(pdev
);
2777 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2778 if (unlikely(res
== NULL
)) {
2779 dev_err(&pdev
->dev
, "invalid resource\n");
2783 ndev
= alloc_etherdev(sizeof(struct sh_eth_private
));
2787 pm_runtime_enable(&pdev
->dev
);
2788 pm_runtime_get_sync(&pdev
->dev
);
2790 /* The sh Ether-specific entries in the device structure. */
2791 ndev
->base_addr
= res
->start
;
2797 ret
= platform_get_irq(pdev
, 0);
2804 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
2806 mdp
= netdev_priv(ndev
);
2807 mdp
->num_tx_ring
= TX_RING_SIZE
;
2808 mdp
->num_rx_ring
= RX_RING_SIZE
;
2809 mdp
->addr
= devm_ioremap_resource(&pdev
->dev
, res
);
2810 if (IS_ERR(mdp
->addr
)) {
2811 ret
= PTR_ERR(mdp
->addr
);
2815 spin_lock_init(&mdp
->lock
);
2818 if (pdev
->dev
.of_node
)
2819 pd
= sh_eth_parse_dt(&pdev
->dev
);
2821 dev_err(&pdev
->dev
, "no platform data\n");
2827 mdp
->phy_id
= pd
->phy
;
2828 mdp
->phy_interface
= pd
->phy_interface
;
2830 mdp
->edmac_endian
= pd
->edmac_endian
;
2831 mdp
->no_ether_link
= pd
->no_ether_link
;
2832 mdp
->ether_link_active_low
= pd
->ether_link_active_low
;
2836 mdp
->cd
= (struct sh_eth_cpu_data
*)id
->driver_data
;
2838 const struct of_device_id
*match
;
2840 match
= of_match_device(of_match_ptr(sh_eth_match_table
),
2842 mdp
->cd
= (struct sh_eth_cpu_data
*)match
->data
;
2844 mdp
->reg_offset
= sh_eth_get_register_offset(mdp
->cd
->register_type
);
2845 if (!mdp
->reg_offset
) {
2846 dev_err(&pdev
->dev
, "Unknown register type (%d)\n",
2847 mdp
->cd
->register_type
);
2851 sh_eth_set_default_cpu_data(mdp
->cd
);
2855 ndev
->netdev_ops
= &sh_eth_netdev_ops_tsu
;
2857 ndev
->netdev_ops
= &sh_eth_netdev_ops
;
2858 ndev
->ethtool_ops
= &sh_eth_ethtool_ops
;
2859 ndev
->watchdog_timeo
= TX_TIMEOUT
;
2861 /* debug message level */
2862 mdp
->msg_enable
= SH_ETH_DEF_MSG_ENABLE
;
2864 /* read and set MAC address */
2865 read_mac_address(ndev
, pd
->mac_addr
);
2866 if (!is_valid_ether_addr(ndev
->dev_addr
)) {
2867 dev_warn(&pdev
->dev
,
2868 "no valid MAC address supplied, using a random one.\n");
2869 eth_hw_addr_random(ndev
);
2872 /* ioremap the TSU registers */
2874 struct resource
*rtsu
;
2875 rtsu
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
2876 mdp
->tsu_addr
= devm_ioremap_resource(&pdev
->dev
, rtsu
);
2877 if (IS_ERR(mdp
->tsu_addr
)) {
2878 ret
= PTR_ERR(mdp
->tsu_addr
);
2881 mdp
->port
= devno
% 2;
2882 ndev
->features
= NETIF_F_HW_VLAN_CTAG_FILTER
;
2885 /* initialize first or needed device */
2886 if (!devno
|| pd
->needs_init
) {
2887 if (mdp
->cd
->chip_reset
)
2888 mdp
->cd
->chip_reset(ndev
);
2891 /* TSU init (Init only)*/
2892 sh_eth_tsu_init(mdp
);
2897 ret
= sh_mdio_init(mdp
, pd
);
2899 dev_err(&ndev
->dev
, "failed to initialise MDIO\n");
2903 netif_napi_add(ndev
, &mdp
->napi
, sh_eth_poll
, 64);
2905 /* network device register */
2906 ret
= register_netdev(ndev
);
2910 /* print device information */
2911 netdev_info(ndev
, "Base address at 0x%x, %pM, IRQ %d.\n",
2912 (u32
)ndev
->base_addr
, ndev
->dev_addr
, ndev
->irq
);
2914 pm_runtime_put(&pdev
->dev
);
2915 platform_set_drvdata(pdev
, ndev
);
2920 netif_napi_del(&mdp
->napi
);
2921 sh_mdio_release(mdp
);
2928 pm_runtime_put(&pdev
->dev
);
2929 pm_runtime_disable(&pdev
->dev
);
2933 static int sh_eth_drv_remove(struct platform_device
*pdev
)
2935 struct net_device
*ndev
= platform_get_drvdata(pdev
);
2936 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2938 unregister_netdev(ndev
);
2939 netif_napi_del(&mdp
->napi
);
2940 sh_mdio_release(mdp
);
2941 pm_runtime_disable(&pdev
->dev
);
2948 static int sh_eth_runtime_nop(struct device
*dev
)
2950 /* Runtime PM callback shared between ->runtime_suspend()
2951 * and ->runtime_resume(). Simply returns success.
2953 * This driver re-initializes all registers after
2954 * pm_runtime_get_sync() anyway so there is no need
2955 * to save and restore registers here.
2960 static const struct dev_pm_ops sh_eth_dev_pm_ops
= {
2961 .runtime_suspend
= sh_eth_runtime_nop
,
2962 .runtime_resume
= sh_eth_runtime_nop
,
2964 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
2966 #define SH_ETH_PM_OPS NULL
2969 static struct platform_device_id sh_eth_id_table
[] = {
2970 { "sh7619-ether", (kernel_ulong_t
)&sh7619_data
},
2971 { "sh771x-ether", (kernel_ulong_t
)&sh771x_data
},
2972 { "sh7724-ether", (kernel_ulong_t
)&sh7724_data
},
2973 { "sh7734-gether", (kernel_ulong_t
)&sh7734_data
},
2974 { "sh7757-ether", (kernel_ulong_t
)&sh7757_data
},
2975 { "sh7757-gether", (kernel_ulong_t
)&sh7757_data_giga
},
2976 { "sh7763-gether", (kernel_ulong_t
)&sh7763_data
},
2977 { "r7s72100-ether", (kernel_ulong_t
)&r7s72100_data
},
2978 { "r8a7740-gether", (kernel_ulong_t
)&r8a7740_data
},
2979 { "r8a777x-ether", (kernel_ulong_t
)&r8a777x_data
},
2980 { "r8a7790-ether", (kernel_ulong_t
)&r8a779x_data
},
2981 { "r8a7791-ether", (kernel_ulong_t
)&r8a779x_data
},
2984 MODULE_DEVICE_TABLE(platform
, sh_eth_id_table
);
2986 static struct platform_driver sh_eth_driver
= {
2987 .probe
= sh_eth_drv_probe
,
2988 .remove
= sh_eth_drv_remove
,
2989 .id_table
= sh_eth_id_table
,
2992 .pm
= SH_ETH_PM_OPS
,
2993 .of_match_table
= of_match_ptr(sh_eth_match_table
),
2997 module_platform_driver(sh_eth_driver
);
2999 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3000 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3001 MODULE_LICENSE("GPL v2");