1 #include <linux/errno.h>
2 #include <linux/kernel.h>
5 #include <linux/prctl.h>
6 #include <linux/slab.h>
7 #include <linux/sched.h>
8 #include <linux/module.h>
10 #include <linux/clockchips.h>
11 #include <linux/random.h>
12 #include <linux/user-return-notifier.h>
13 #include <linux/dmi.h>
14 #include <linux/utsname.h>
15 #include <trace/events/power.h>
16 #include <linux/hw_breakpoint.h>
17 #include <asm/system.h>
19 #include <asm/syscalls.h>
21 #include <asm/uaccess.h>
23 #include <asm/debugreg.h>
25 unsigned long idle_halt
;
26 EXPORT_SYMBOL(idle_halt
);
27 unsigned long idle_nomwait
;
28 EXPORT_SYMBOL(idle_nomwait
);
30 struct kmem_cache
*task_xstate_cachep
;
31 EXPORT_SYMBOL_GPL(task_xstate_cachep
);
33 int arch_dup_task_struct(struct task_struct
*dst
, struct task_struct
*src
)
38 if (fpu_allocated(&src
->thread
.fpu
)) {
39 memset(&dst
->thread
.fpu
, 0, sizeof(dst
->thread
.fpu
));
40 ret
= fpu_alloc(&dst
->thread
.fpu
);
43 fpu_copy(&dst
->thread
.fpu
, &src
->thread
.fpu
);
48 void free_thread_xstate(struct task_struct
*tsk
)
50 fpu_free(&tsk
->thread
.fpu
);
53 void free_thread_info(struct thread_info
*ti
)
55 free_thread_xstate(ti
->task
);
56 free_pages((unsigned long)ti
, get_order(THREAD_SIZE
));
59 void arch_task_cache_init(void)
62 kmem_cache_create("task_xstate", xstate_size
,
63 __alignof__(union thread_xstate
),
64 SLAB_PANIC
| SLAB_NOTRACK
, NULL
);
68 * Free current thread data structures etc..
70 void exit_thread(void)
72 struct task_struct
*me
= current
;
73 struct thread_struct
*t
= &me
->thread
;
74 unsigned long *bp
= t
->io_bitmap_ptr
;
77 struct tss_struct
*tss
= &per_cpu(init_tss
, get_cpu());
79 t
->io_bitmap_ptr
= NULL
;
80 clear_thread_flag(TIF_IO_BITMAP
);
82 * Careful, clear this in the TSS too:
84 memset(tss
->io_bitmap
, 0xff, t
->io_bitmap_max
);
91 void show_regs(struct pt_regs
*regs
)
94 show_trace(NULL
, regs
, (unsigned long *)kernel_stack_pointer(regs
),
98 void show_regs_common(void)
100 const char *board
, *product
;
102 board
= dmi_get_system_info(DMI_BOARD_NAME
);
105 product
= dmi_get_system_info(DMI_PRODUCT_NAME
);
109 printk(KERN_CONT
"\n");
110 printk(KERN_DEFAULT
"Pid: %d, comm: %.20s %s %s %.*s %s/%s\n",
111 current
->pid
, current
->comm
, print_tainted(),
112 init_utsname()->release
,
113 (int)strcspn(init_utsname()->version
, " "),
114 init_utsname()->version
, board
, product
);
117 void flush_thread(void)
119 struct task_struct
*tsk
= current
;
121 flush_ptrace_hw_breakpoint(tsk
);
122 memset(tsk
->thread
.tls_array
, 0, sizeof(tsk
->thread
.tls_array
));
124 * Forget coprocessor state..
126 tsk
->fpu_counter
= 0;
131 static void hard_disable_TSC(void)
133 write_cr4(read_cr4() | X86_CR4_TSD
);
136 void disable_TSC(void)
139 if (!test_and_set_thread_flag(TIF_NOTSC
))
141 * Must flip the CPU state synchronously with
142 * TIF_NOTSC in the current running context.
148 static void hard_enable_TSC(void)
150 write_cr4(read_cr4() & ~X86_CR4_TSD
);
153 static void enable_TSC(void)
156 if (test_and_clear_thread_flag(TIF_NOTSC
))
158 * Must flip the CPU state synchronously with
159 * TIF_NOTSC in the current running context.
165 int get_tsc_mode(unsigned long adr
)
169 if (test_thread_flag(TIF_NOTSC
))
170 val
= PR_TSC_SIGSEGV
;
174 return put_user(val
, (unsigned int __user
*)adr
);
177 int set_tsc_mode(unsigned int val
)
179 if (val
== PR_TSC_SIGSEGV
)
181 else if (val
== PR_TSC_ENABLE
)
189 void __switch_to_xtra(struct task_struct
*prev_p
, struct task_struct
*next_p
,
190 struct tss_struct
*tss
)
192 struct thread_struct
*prev
, *next
;
194 prev
= &prev_p
->thread
;
195 next
= &next_p
->thread
;
197 if (test_tsk_thread_flag(prev_p
, TIF_BLOCKSTEP
) ^
198 test_tsk_thread_flag(next_p
, TIF_BLOCKSTEP
)) {
199 unsigned long debugctl
= get_debugctlmsr();
201 debugctl
&= ~DEBUGCTLMSR_BTF
;
202 if (test_tsk_thread_flag(next_p
, TIF_BLOCKSTEP
))
203 debugctl
|= DEBUGCTLMSR_BTF
;
205 update_debugctlmsr(debugctl
);
208 if (test_tsk_thread_flag(prev_p
, TIF_NOTSC
) ^
209 test_tsk_thread_flag(next_p
, TIF_NOTSC
)) {
210 /* prev and next are different */
211 if (test_tsk_thread_flag(next_p
, TIF_NOTSC
))
217 if (test_tsk_thread_flag(next_p
, TIF_IO_BITMAP
)) {
219 * Copy the relevant range of the IO bitmap.
220 * Normally this is 128 bytes or less:
222 memcpy(tss
->io_bitmap
, next
->io_bitmap_ptr
,
223 max(prev
->io_bitmap_max
, next
->io_bitmap_max
));
224 } else if (test_tsk_thread_flag(prev_p
, TIF_IO_BITMAP
)) {
226 * Clear any possible leftover bits:
228 memset(tss
->io_bitmap
, 0xff, prev
->io_bitmap_max
);
230 propagate_user_return_notify(prev_p
, next_p
);
233 int sys_fork(struct pt_regs
*regs
)
235 return do_fork(SIGCHLD
, regs
->sp
, regs
, 0, NULL
, NULL
);
239 * This is trivial, and on the face of it looks like it
240 * could equally well be done in user mode.
242 * Not so, for quite unobvious reasons - register pressure.
243 * In user mode vfork() cannot have a stack frame, and if
244 * done by calling the "clone()" system call directly, you
245 * do not have enough call-clobbered registers to hold all
246 * the information you need.
248 int sys_vfork(struct pt_regs
*regs
)
250 return do_fork(CLONE_VFORK
| CLONE_VM
| SIGCHLD
, regs
->sp
, regs
, 0,
255 sys_clone(unsigned long clone_flags
, unsigned long newsp
,
256 void __user
*parent_tid
, void __user
*child_tid
, struct pt_regs
*regs
)
260 return do_fork(clone_flags
, newsp
, regs
, 0, parent_tid
, child_tid
);
264 * This gets run with %si containing the
265 * function to call, and %di containing
268 extern void kernel_thread_helper(void);
271 * Create a kernel thread
273 int kernel_thread(int (*fn
)(void *), void *arg
, unsigned long flags
)
277 memset(®s
, 0, sizeof(regs
));
279 regs
.si
= (unsigned long) fn
;
280 regs
.di
= (unsigned long) arg
;
285 regs
.fs
= __KERNEL_PERCPU
;
286 regs
.gs
= __KERNEL_STACK_CANARY
;
288 regs
.ss
= __KERNEL_DS
;
292 regs
.ip
= (unsigned long) kernel_thread_helper
;
293 regs
.cs
= __KERNEL_CS
| get_kernel_rpl();
294 regs
.flags
= X86_EFLAGS_IF
| 0x2;
296 /* Ok, create the new process.. */
297 return do_fork(flags
| CLONE_VM
| CLONE_UNTRACED
, 0, ®s
, 0, NULL
, NULL
);
299 EXPORT_SYMBOL(kernel_thread
);
302 * sys_execve() executes a new program.
304 long sys_execve(const char __user
*name
, char __user
* __user
*argv
,
305 char __user
* __user
*envp
, struct pt_regs
*regs
)
310 filename
= getname(name
);
311 error
= PTR_ERR(filename
);
312 if (IS_ERR(filename
))
314 error
= do_execve(filename
, argv
, envp
, regs
);
318 /* Make sure we don't return using sysenter.. */
319 set_thread_flag(TIF_IRET
);
328 * Idle related variables and functions
330 unsigned long boot_option_idle_override
= 0;
331 EXPORT_SYMBOL(boot_option_idle_override
);
334 * Powermanagement idle function, if any..
336 void (*pm_idle
)(void);
337 EXPORT_SYMBOL(pm_idle
);
341 * This halt magic was a workaround for ancient floppy DMA
342 * wreckage. It should be safe to remove.
344 static int hlt_counter
;
345 void disable_hlt(void)
349 EXPORT_SYMBOL(disable_hlt
);
351 void enable_hlt(void)
355 EXPORT_SYMBOL(enable_hlt
);
357 static inline int hlt_use_halt(void)
359 return (!hlt_counter
&& boot_cpu_data
.hlt_works_ok
);
362 static inline int hlt_use_halt(void)
369 * We use this if we don't have any better
372 void default_idle(void)
374 if (hlt_use_halt()) {
375 trace_power_start(POWER_CSTATE
, 1, smp_processor_id());
376 current_thread_info()->status
&= ~TS_POLLING
;
378 * TS_POLLING-cleared state must be visible before we
384 safe_halt(); /* enables interrupts racelessly */
387 current_thread_info()->status
|= TS_POLLING
;
390 /* loop is done by the caller */
394 #ifdef CONFIG_APM_MODULE
395 EXPORT_SYMBOL(default_idle
);
398 void stop_this_cpu(void *dummy
)
404 set_cpu_online(smp_processor_id(), false);
405 disable_local_APIC();
408 if (hlt_works(smp_processor_id()))
413 static void do_nothing(void *unused
)
418 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
419 * pm_idle and update to new pm_idle value. Required while changing pm_idle
420 * handler on SMP systems.
422 * Caller must have changed pm_idle to the new value before the call. Old
423 * pm_idle value will not be used by any CPU after the return of this function.
425 void cpu_idle_wait(void)
428 /* kick all the CPUs so that they exit out of pm_idle */
429 smp_call_function(do_nothing
, NULL
, 1);
431 EXPORT_SYMBOL_GPL(cpu_idle_wait
);
434 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
435 * which can obviate IPI to trigger checking of need_resched.
436 * We execute MONITOR against need_resched and enter optimized wait state
437 * through MWAIT. Whenever someone changes need_resched, we would be woken
438 * up from MWAIT (without an IPI).
440 * New with Core Duo processors, MWAIT can take some hints based on CPU
443 void mwait_idle_with_hints(unsigned long ax
, unsigned long cx
)
445 trace_power_start(POWER_CSTATE
, (ax
>>4)+1, smp_processor_id());
446 if (!need_resched()) {
447 if (cpu_has(¤t_cpu_data
, X86_FEATURE_CLFLUSH_MONITOR
))
448 clflush((void *)¤t_thread_info()->flags
);
450 __monitor((void *)¤t_thread_info()->flags
, 0, 0);
457 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
458 static void mwait_idle(void)
460 if (!need_resched()) {
461 trace_power_start(POWER_CSTATE
, 1, smp_processor_id());
462 if (cpu_has(¤t_cpu_data
, X86_FEATURE_CLFLUSH_MONITOR
))
463 clflush((void *)¤t_thread_info()->flags
);
465 __monitor((void *)¤t_thread_info()->flags
, 0, 0);
476 * On SMP it's slightly faster (but much more power-consuming!)
477 * to poll the ->work.need_resched flag instead of waiting for the
478 * cross-CPU IPI to arrive. Use this option with caution.
480 static void poll_idle(void)
482 trace_power_start(POWER_CSTATE
, 0, smp_processor_id());
484 while (!need_resched())
490 * mwait selection logic:
492 * It depends on the CPU. For AMD CPUs that support MWAIT this is
493 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
494 * then depend on a clock divisor and current Pstate of the core. If
495 * all cores of a processor are in halt state (C1) the processor can
496 * enter the C1E (C1 enhanced) state. If mwait is used this will never
499 * idle=mwait overrides this decision and forces the usage of mwait.
501 static int __cpuinitdata force_mwait
;
503 #define MWAIT_INFO 0x05
504 #define MWAIT_ECX_EXTENDED_INFO 0x01
505 #define MWAIT_EDX_C1 0xf0
507 static int __cpuinit
mwait_usable(const struct cpuinfo_x86
*c
)
509 u32 eax
, ebx
, ecx
, edx
;
514 if (c
->cpuid_level
< MWAIT_INFO
)
517 cpuid(MWAIT_INFO
, &eax
, &ebx
, &ecx
, &edx
);
518 /* Check, whether EDX has extended info about MWAIT */
519 if (!(ecx
& MWAIT_ECX_EXTENDED_INFO
))
523 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
526 return (edx
& MWAIT_EDX_C1
);
530 EXPORT_SYMBOL(c1e_detected
);
532 static cpumask_var_t c1e_mask
;
534 void c1e_remove_cpu(int cpu
)
536 if (c1e_mask
!= NULL
)
537 cpumask_clear_cpu(cpu
, c1e_mask
);
541 * C1E aware idle routine. We check for C1E active in the interrupt
542 * pending message MSR. If we detect C1E, then we handle it the same
543 * way as C3 power states (local apic timer and TSC stop)
545 static void c1e_idle(void)
553 rdmsr(MSR_K8_INT_PENDING_MSG
, lo
, hi
);
555 if (lo
& K8_INTP_C1E_ACTIVE_MASK
) {
557 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC
))
558 mark_tsc_unstable("TSC halt in AMD C1E");
559 printk(KERN_INFO
"System has AMD C1E enabled\n");
564 int cpu
= smp_processor_id();
566 if (!cpumask_test_cpu(cpu
, c1e_mask
)) {
567 cpumask_set_cpu(cpu
, c1e_mask
);
569 * Force broadcast so ACPI can not interfere.
571 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE
,
573 printk(KERN_INFO
"Switch to broadcast mode on CPU%d\n",
576 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER
, &cpu
);
581 * The switch back from broadcast mode needs to be
582 * called with interrupts disabled.
585 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT
, &cpu
);
591 void __cpuinit
select_idle_routine(const struct cpuinfo_x86
*c
)
594 if (pm_idle
== poll_idle
&& smp_num_siblings
> 1) {
595 printk_once(KERN_WARNING
"WARNING: polling idle and HT enabled,"
596 " performance may degrade.\n");
602 if (cpu_has(c
, X86_FEATURE_MWAIT
) && mwait_usable(c
)) {
604 * One CPU supports mwait => All CPUs supports mwait
606 printk(KERN_INFO
"using mwait in idle threads.\n");
607 pm_idle
= mwait_idle
;
608 } else if (cpu_has_amd_erratum(amd_erratum_400
)) {
609 /* E400: APIC timer interrupt does not wake up CPU from C1e */
610 printk(KERN_INFO
"using C1E aware idle routine\n");
613 pm_idle
= default_idle
;
616 void __init
init_c1e_mask(void)
618 /* If we're using c1e_idle, we need to allocate c1e_mask. */
619 if (pm_idle
== c1e_idle
)
620 zalloc_cpumask_var(&c1e_mask
, GFP_KERNEL
);
623 static int __init
idle_setup(char *str
)
628 if (!strcmp(str
, "poll")) {
629 printk("using polling idle threads.\n");
631 } else if (!strcmp(str
, "mwait"))
633 else if (!strcmp(str
, "halt")) {
635 * When the boot option of idle=halt is added, halt is
636 * forced to be used for CPU idle. In such case CPU C2/C3
637 * won't be used again.
638 * To continue to load the CPU idle driver, don't touch
639 * the boot_option_idle_override.
641 pm_idle
= default_idle
;
644 } else if (!strcmp(str
, "nomwait")) {
646 * If the boot option of "idle=nomwait" is added,
647 * it means that mwait will be disabled for CPU C2/C3
648 * states. In such case it won't touch the variable
649 * of boot_option_idle_override.
656 boot_option_idle_override
= 1;
659 early_param("idle", idle_setup
);
661 unsigned long arch_align_stack(unsigned long sp
)
663 if (!(current
->personality
& ADDR_NO_RANDOMIZE
) && randomize_va_space
)
664 sp
-= get_random_int() % 8192;
668 unsigned long arch_randomize_brk(struct mm_struct
*mm
)
670 unsigned long range_end
= mm
->brk
+ 0x02000000;
671 return randomize_range(mm
->brk
, range_end
, 0) ? : mm
->brk
;