drivers/gpu/drm/exynos/exynos5433_drm_decon.c

   1 /* drivers/gpu/drm/exynos5433_drm_decon.c
   2  *
   3  * Copyright (C) 2015 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Hyungwon Hwang <human.hwang@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundationr
  11  */
  12
  13 #include <linux/platform_device.h>
  14 #include <linux/clk.h>
  15 #include <linux/component.h>
  16 #include <linux/of_gpio.h>
  17 #include <linux/pm_runtime.h>
  18
  19 #include <video/exynos5433_decon.h>
  20
  21 #include "exynos_drm_drv.h"
  22 #include "exynos_drm_crtc.h"
  23 #include "exynos_drm_plane.h"
  24 #include "exynos_drm_iommu.h"
  25
  26 #define WINDOWS_NR      3
  27 #define CURSOR_WIN      2
  28 #define MIN_FB_WIDTH_FOR_16WORD_BURST   128
  29
  30 static const char * const decon_clks_name[] = {
  31         "pclk",
  32         "aclk_decon",
  33         "aclk_smmu_decon0x",
  34         "aclk_xiu_decon0x",
  35         "pclk_smmu_decon0x",
  36         "sclk_decon_vclk",
  37         "sclk_decon_eclk",
  38 };
  39
  40 struct decon_context {
  41         struct device                   *dev;
  42         struct drm_device               *drm_dev;
  43         struct exynos_drm_crtc          *crtc;
  44         struct exynos_drm_plane         planes[WINDOWS_NR];
  45         void __iomem                    *addr;
  46         struct clk                      *clks[ARRAY_SIZE(decon_clks_name)];
  47         unsigned long                   irq_flags;
  48         int                             pipe;
  49         bool                            suspended;
  50
  51 #define BIT_CLKS_ENABLED                0
  52 #define BIT_IRQS_ENABLED                1
  53         unsigned long                   enabled;
  54         bool                            i80_if;
  55         atomic_t                        win_updated;
  56 };
  57
  58 static const uint32_t decon_formats[] = {
  59         DRM_FORMAT_XRGB1555,
  60         DRM_FORMAT_RGB565,
  61         DRM_FORMAT_XRGB8888,
  62         DRM_FORMAT_ARGB8888,
  63 };
  64
  65 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
  66 {
  67         struct decon_context *ctx = crtc->ctx;
  68         u32 val;
  69
  70         if (ctx->suspended)
  71                 return -EPERM;
  72
  73         if (test_and_set_bit(0, &ctx->irq_flags)) {
  74                 val = VIDINTCON0_INTEN;
  75                 if (ctx->i80_if)
  76                         val |= VIDINTCON0_FRAMEDONE;
  77                 else
  78                         val |= VIDINTCON0_INTFRMEN;
  79
  80                 writel(val, ctx->addr + DECON_VIDINTCON0);
  81         }
  82
  83         return 0;
  84 }
  85
  86 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
  87 {
  88         struct decon_context *ctx = crtc->ctx;
  89
  90         if (ctx->suspended)
  91                 return;
  92
  93         if (test_and_clear_bit(0, &ctx->irq_flags))
  94                 writel(0, ctx->addr + DECON_VIDINTCON0);
  95 }
  96
  97 static void decon_setup_trigger(struct decon_context *ctx)
  98 {
  99         u32 val = TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
 100                         TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN;
 101         writel(val, ctx->addr + DECON_TRIGCON);
 102 }
 103
 104 static void decon_commit(struct exynos_drm_crtc *crtc)
 105 {
 106         struct decon_context *ctx = crtc->ctx;
 107         struct drm_display_mode *mode = &crtc->base.mode;
 108         u32 val;
 109
 110         if (ctx->suspended)
 111                 return;
 112
 113         /* enable clock gate */
 114         val = CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F;
 115         writel(val, ctx->addr + DECON_CMU);
 116
 117         /* lcd on and use command if */
 118         val = VIDOUT_LCD_ON;
 119         if (ctx->i80_if)
 120                 val |= VIDOUT_COMMAND_IF;
 121         else
 122                 val |= VIDOUT_RGB_IF;
 123         writel(val, ctx->addr + DECON_VIDOUTCON0);
 124
 125         val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
 126                 VIDTCON2_HOZVAL(mode->hdisplay - 1);
 127         writel(val, ctx->addr + DECON_VIDTCON2);
 128
 129         if (!ctx->i80_if) {
 130                 val = VIDTCON00_VBPD_F(
 131                                 mode->crtc_vtotal - mode->crtc_vsync_end) |
 132                         VIDTCON00_VFPD_F(
 133                                 mode->crtc_vsync_start - mode->crtc_vdisplay);
 134                 writel(val, ctx->addr + DECON_VIDTCON00);
 135
 136                 val = VIDTCON01_VSPW_F(
 137                                 mode->crtc_vsync_end - mode->crtc_vsync_start);
 138                 writel(val, ctx->addr + DECON_VIDTCON01);
 139
 140                 val = VIDTCON10_HBPD_F(
 141                                 mode->crtc_htotal - mode->crtc_hsync_end) |
 142                         VIDTCON10_HFPD_F(
 143                                 mode->crtc_hsync_start - mode->crtc_hdisplay);
 144                 writel(val, ctx->addr + DECON_VIDTCON10);
 145
 146                 val = VIDTCON11_HSPW_F(
 147                                 mode->crtc_hsync_end - mode->crtc_hsync_start);
 148                 writel(val, ctx->addr + DECON_VIDTCON11);
 149         }
 150
 151         decon_setup_trigger(ctx);
 152
 153         /* enable output and display signal */
 154         val = VIDCON0_ENVID | VIDCON0_ENVID_F;
 155         writel(val, ctx->addr + DECON_VIDCON0);
 156 }
 157
 158 #define COORDINATE_X(x)         (((x) & 0xfff) << 12)
 159 #define COORDINATE_Y(x)         ((x) & 0xfff)
 160 #define OFFSIZE(x)              (((x) & 0x3fff) << 14)
 161 #define PAGEWIDTH(x)            ((x) & 0x3fff)
 162
 163 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
 164                                  struct drm_framebuffer *fb)
 165 {
 166         unsigned long val;
 167
 168         val = readl(ctx->addr + DECON_WINCONx(win));
 169         val &= ~WINCONx_BPPMODE_MASK;
 170
 171         switch (fb->pixel_format) {
 172         case DRM_FORMAT_XRGB1555:
 173                 val |= WINCONx_BPPMODE_16BPP_I1555;
 174                 val |= WINCONx_HAWSWP_F;
 175                 val |= WINCONx_BURSTLEN_16WORD;
 176                 break;
 177         case DRM_FORMAT_RGB565:
 178                 val |= WINCONx_BPPMODE_16BPP_565;
 179                 val |= WINCONx_HAWSWP_F;
 180                 val |= WINCONx_BURSTLEN_16WORD;
 181                 break;
 182         case DRM_FORMAT_XRGB8888:
 183                 val |= WINCONx_BPPMODE_24BPP_888;
 184                 val |= WINCONx_WSWP_F;
 185                 val |= WINCONx_BURSTLEN_16WORD;
 186                 break;
 187         case DRM_FORMAT_ARGB8888:
 188                 val |= WINCONx_BPPMODE_32BPP_A8888;
 189                 val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F;
 190                 val |= WINCONx_BURSTLEN_16WORD;
 191                 break;
 192         default:
 193                 DRM_ERROR("Proper pixel format is not set\n");
 194                 return;
 195         }
 196
 197         DRM_DEBUG_KMS("bpp = %u\n", fb->bits_per_pixel);
 198
 199         /*
 200          * In case of exynos, setting dma-burst to 16Word causes permanent
 201          * tearing for very small buffers, e.g. cursor buffer. Burst Mode
 202          * switching which is based on plane size is not recommended as
 203          * plane size varies a lot towards the end of the screen and rapid
 204          * movement causes unstable DMA which results into iommu crash/tear.
 205          */
 206
 207         if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 208                 val &= ~WINCONx_BURSTLEN_MASK;
 209                 val |= WINCONx_BURSTLEN_8WORD;
 210         }
 211
 212         writel(val, ctx->addr + DECON_WINCONx(win));
 213 }
 214
 215 static void decon_shadow_protect_win(struct decon_context *ctx, int win,
 216                                         bool protect)
 217 {
 218         u32 val;
 219
 220         val = readl(ctx->addr + DECON_SHADOWCON);
 221
 222         if (protect)
 223                 val |= SHADOWCON_Wx_PROTECT(win);
 224         else
 225                 val &= ~SHADOWCON_Wx_PROTECT(win);
 226
 227         writel(val, ctx->addr + DECON_SHADOWCON);
 228 }
 229
 230 static void decon_atomic_begin(struct exynos_drm_crtc *crtc,
 231                                         struct exynos_drm_plane *plane)
 232 {
 233         struct decon_context *ctx = crtc->ctx;
 234
 235         if (ctx->suspended)
 236                 return;
 237
 238         decon_shadow_protect_win(ctx, plane->zpos, true);
 239 }
 240
 241 static void decon_update_plane(struct exynos_drm_crtc *crtc,
 242                                struct exynos_drm_plane *plane)
 243 {
 244         struct decon_context *ctx = crtc->ctx;
 245         struct drm_plane_state *state = plane->base.state;
 246         unsigned int win = plane->zpos;
 247         unsigned int bpp = state->fb->bits_per_pixel >> 3;
 248         unsigned int pitch = state->fb->pitches[0];
 249         u32 val;
 250
 251         if (ctx->suspended)
 252                 return;
 253
 254         val = COORDINATE_X(plane->crtc_x) | COORDINATE_Y(plane->crtc_y);
 255         writel(val, ctx->addr + DECON_VIDOSDxA(win));
 256
 257         val = COORDINATE_X(plane->crtc_x + plane->crtc_w - 1) |
 258                 COORDINATE_Y(plane->crtc_y + plane->crtc_h - 1);
 259         writel(val, ctx->addr + DECON_VIDOSDxB(win));
 260
 261         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 262                 VIDOSD_Wx_ALPHA_B_F(0x0);
 263         writel(val, ctx->addr + DECON_VIDOSDxC(win));
 264
 265         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 266                 VIDOSD_Wx_ALPHA_B_F(0x0);
 267         writel(val, ctx->addr + DECON_VIDOSDxD(win));
 268
 269         writel(plane->dma_addr[0], ctx->addr + DECON_VIDW0xADD0B0(win));
 270
 271         val = plane->dma_addr[0] + pitch * plane->crtc_h;
 272         writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
 273
 274         val = OFFSIZE(pitch - plane->crtc_w * bpp)
 275                 | PAGEWIDTH(plane->crtc_w * bpp);
 276         writel(val, ctx->addr + DECON_VIDW0xADD2(win));
 277
 278         decon_win_set_pixfmt(ctx, win, state->fb);
 279
 280         /* window enable */
 281         val = readl(ctx->addr + DECON_WINCONx(win));
 282         val |= WINCONx_ENWIN_F;
 283         writel(val, ctx->addr + DECON_WINCONx(win));
 284
 285         /* standalone update */
 286         val = readl(ctx->addr + DECON_UPDATE);
 287         val |= STANDALONE_UPDATE_F;
 288         writel(val, ctx->addr + DECON_UPDATE);
 289 }
 290
 291 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
 292                                 struct exynos_drm_plane *plane)
 293 {
 294         struct decon_context *ctx = crtc->ctx;
 295         unsigned int win = plane->zpos;
 296         u32 val;
 297
 298         if (ctx->suspended)
 299                 return;
 300
 301         decon_shadow_protect_win(ctx, win, true);
 302
 303         /* window disable */
 304         val = readl(ctx->addr + DECON_WINCONx(win));
 305         val &= ~WINCONx_ENWIN_F;
 306         writel(val, ctx->addr + DECON_WINCONx(win));
 307
 308         decon_shadow_protect_win(ctx, win, false);
 309
 310         /* standalone update */
 311         val = readl(ctx->addr + DECON_UPDATE);
 312         val |= STANDALONE_UPDATE_F;
 313         writel(val, ctx->addr + DECON_UPDATE);
 314 }
 315
 316 static void decon_atomic_flush(struct exynos_drm_crtc *crtc,
 317                                 struct exynos_drm_plane *plane)
 318 {
 319         struct decon_context *ctx = crtc->ctx;
 320
 321         if (ctx->suspended)
 322                 return;
 323
 324         decon_shadow_protect_win(ctx, plane->zpos, false);
 325
 326         if (ctx->i80_if)
 327                 atomic_set(&ctx->win_updated, 1);
 328 }
 329
 330 static void decon_swreset(struct decon_context *ctx)
 331 {
 332         unsigned int tries;
 333
 334         writel(0, ctx->addr + DECON_VIDCON0);
 335         for (tries = 2000; tries; --tries) {
 336                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_STOP_STATUS)
 337                         break;
 338                 udelay(10);
 339         }
 340
 341         WARN(tries == 0, "failed to disable DECON\n");
 342
 343         writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
 344         for (tries = 2000; tries; --tries) {
 345                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET)
 346                         break;
 347                 udelay(10);
 348         }
 349
 350         WARN(tries == 0, "failed to software reset DECON\n");
 351 }
 352
 353 static void decon_enable(struct exynos_drm_crtc *crtc)
 354 {
 355         struct decon_context *ctx = crtc->ctx;
 356         int ret;
 357         int i;
 358
 359         if (!ctx->suspended)
 360                 return;
 361
 362         ctx->suspended = false;
 363
 364         pm_runtime_get_sync(ctx->dev);
 365
 366         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 367                 ret = clk_prepare_enable(ctx->clks[i]);
 368                 if (ret < 0)
 369                         goto err;
 370         }
 371
 372         set_bit(BIT_CLKS_ENABLED, &ctx->enabled);
 373
 374         /* if vblank was enabled status, enable it again. */
 375         if (test_and_clear_bit(0, &ctx->irq_flags))
 376                 decon_enable_vblank(ctx->crtc);
 377
 378         decon_commit(ctx->crtc);
 379
 380         return;
 381 err:
 382         while (--i >= 0)
 383                 clk_disable_unprepare(ctx->clks[i]);
 384
 385         ctx->suspended = true;
 386 }
 387
 388 static void decon_disable(struct exynos_drm_crtc *crtc)
 389 {
 390         struct decon_context *ctx = crtc->ctx;
 391         int i;
 392
 393         if (ctx->suspended)
 394                 return;
 395
 396         /*
 397          * We need to make sure that all windows are disabled before we
 398          * suspend that connector. Otherwise we might try to scan from
 399          * a destroyed buffer later.
 400          */
 401         for (i = 0; i < WINDOWS_NR; i++)
 402                 decon_disable_plane(crtc, &ctx->planes[i]);
 403
 404         decon_swreset(ctx);
 405
 406         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++)
 407                 clk_disable_unprepare(ctx->clks[i]);
 408
 409         clear_bit(BIT_CLKS_ENABLED, &ctx->enabled);
 410
 411         pm_runtime_put_sync(ctx->dev);
 412
 413         ctx->suspended = true;
 414 }
 415
 416 void decon_te_irq_handler(struct exynos_drm_crtc *crtc)
 417 {
 418         struct decon_context *ctx = crtc->ctx;
 419         u32 val;
 420
 421         if (!test_bit(BIT_CLKS_ENABLED, &ctx->enabled))
 422                 return;
 423
 424         if (atomic_add_unless(&ctx->win_updated, -1, 0)) {
 425                 /* trigger */
 426                 val = readl(ctx->addr + DECON_TRIGCON);
 427                 val |= TRIGCON_SWTRIGCMD;
 428                 writel(val, ctx->addr + DECON_TRIGCON);
 429         }
 430
 431         drm_crtc_handle_vblank(&ctx->crtc->base);
 432 }
 433
 434 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
 435 {
 436         struct decon_context *ctx = crtc->ctx;
 437         int win, i, ret;
 438         u32 val;
 439
 440         DRM_DEBUG_KMS("%s\n", __FILE__);
 441
 442         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 443                 ret = clk_prepare_enable(ctx->clks[i]);
 444                 if (ret < 0)
 445                         goto err;
 446         }
 447
 448         for (win = 0; win < WINDOWS_NR; win++) {
 449                 /* shadow update disable */
 450                 val = readl(ctx->addr + DECON_SHADOWCON);
 451                 val |= SHADOWCON_Wx_PROTECT(win);
 452                 writel(val, ctx->addr + DECON_SHADOWCON);
 453
 454                 /* window disable */
 455                 val = readl(ctx->addr + DECON_WINCONx(win));
 456                 val &= ~WINCONx_ENWIN_F;
 457                 writel(val, ctx->addr + DECON_WINCONx(win));
 458
 459                 /* shadow update enable */
 460                 val = readl(ctx->addr + DECON_SHADOWCON);
 461                 val &= ~SHADOWCON_Wx_PROTECT(win);
 462                 writel(val, ctx->addr + DECON_SHADOWCON);
 463
 464                 /* standalone update */
 465                 val = readl(ctx->addr + DECON_UPDATE);
 466                 val |= STANDALONE_UPDATE_F;
 467                 writel(val, ctx->addr + DECON_UPDATE);
 468         }
 469         /* TODO: wait for possible vsync */
 470         msleep(50);
 471
 472 err:
 473         while (--i >= 0)
 474                 clk_disable_unprepare(ctx->clks[i]);
 475 }
 476
 477 static struct exynos_drm_crtc_ops decon_crtc_ops = {
 478         .enable                 = decon_enable,
 479         .disable                = decon_disable,
 480         .commit                 = decon_commit,
 481         .enable_vblank          = decon_enable_vblank,
 482         .disable_vblank         = decon_disable_vblank,
 483         .commit                 = decon_commit,
 484         .atomic_begin           = decon_atomic_begin,
 485         .update_plane           = decon_update_plane,
 486         .disable_plane          = decon_disable_plane,
 487         .atomic_flush           = decon_atomic_flush,
 488         .te_handler             = decon_te_irq_handler,
 489 };
 490
 491 static int decon_bind(struct device *dev, struct device *master, void *data)
 492 {
 493         struct decon_context *ctx = dev_get_drvdata(dev);
 494         struct drm_device *drm_dev = data;
 495         struct exynos_drm_private *priv = drm_dev->dev_private;
 496         struct exynos_drm_plane *exynos_plane;
 497         enum drm_plane_type type;
 498         unsigned int zpos;
 499         int ret;
 500
 501         ctx->drm_dev = drm_dev;
 502         ctx->pipe = priv->pipe++;
 503
 504         for (zpos = 0; zpos < WINDOWS_NR; zpos++) {
 505                 type = exynos_plane_get_type(zpos, CURSOR_WIN);
 506                 ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
 507                                 1 << ctx->pipe, type, decon_formats,
 508                                 ARRAY_SIZE(decon_formats), zpos);
 509                 if (ret)
 510                         return ret;
 511         }
 512
 513         exynos_plane = &ctx->planes[DEFAULT_WIN];
 514         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
 515                                         ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
 516                                         &decon_crtc_ops, ctx);
 517         if (IS_ERR(ctx->crtc)) {
 518                 ret = PTR_ERR(ctx->crtc);
 519                 goto err;
 520         }
 521
 522         decon_clear_channels(ctx->crtc);
 523
 524         ret = drm_iommu_attach_device(drm_dev, dev);
 525         if (ret)
 526                 goto err;
 527
 528         return ret;
 529 err:
 530         priv->pipe--;
 531         return ret;
 532 }
 533
 534 static void decon_unbind(struct device *dev, struct device *master, void *data)
 535 {
 536         struct decon_context *ctx = dev_get_drvdata(dev);
 537
 538         decon_disable(ctx->crtc);
 539
 540         /* detach this sub driver from iommu mapping if supported. */
 541         drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
 542 }
 543
 544 static const struct component_ops decon_component_ops = {
 545         .bind   = decon_bind,
 546         .unbind = decon_unbind,
 547 };
 548
 549 static irqreturn_t decon_vsync_irq_handler(int irq, void *dev_id)
 550 {
 551         struct decon_context *ctx = dev_id;
 552         u32 val;
 553
 554         if (!test_bit(BIT_CLKS_ENABLED, &ctx->enabled))
 555                 goto out;
 556
 557         val = readl(ctx->addr + DECON_VIDINTCON1);
 558         if (val & VIDINTCON1_INTFRMPEND) {
 559                 drm_crtc_handle_vblank(&ctx->crtc->base);
 560
 561                 /* clear */
 562                 writel(VIDINTCON1_INTFRMPEND, ctx->addr + DECON_VIDINTCON1);
 563         }
 564
 565 out:
 566         return IRQ_HANDLED;
 567 }
 568
 569 static irqreturn_t decon_lcd_sys_irq_handler(int irq, void *dev_id)
 570 {
 571         struct decon_context *ctx = dev_id;
 572         u32 val;
 573         int win;
 574
 575         if (!test_bit(BIT_CLKS_ENABLED, &ctx->enabled))
 576                 goto out;
 577
 578         val = readl(ctx->addr + DECON_VIDINTCON1);
 579         if (val & VIDINTCON1_INTFRMDONEPEND) {
 580                 for (win = 0 ; win < WINDOWS_NR ; win++) {
 581                         struct exynos_drm_plane *plane = &ctx->planes[win];
 582
 583                         if (!plane->pending_fb)
 584                                 continue;
 585
 586                         exynos_drm_crtc_finish_update(ctx->crtc, plane);
 587                 }
 588
 589                 /* clear */
 590                 writel(VIDINTCON1_INTFRMDONEPEND,
 591                                 ctx->addr + DECON_VIDINTCON1);
 592         }
 593
 594 out:
 595         return IRQ_HANDLED;
 596 }
 597
 598 static int exynos5433_decon_probe(struct platform_device *pdev)
 599 {
 600         struct device *dev = &pdev->dev;
 601         struct decon_context *ctx;
 602         struct resource *res;
 603         int ret;
 604         int i;
 605
 606         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 607         if (!ctx)
 608                 return -ENOMEM;
 609
 610         ctx->suspended = true;
 611         ctx->dev = dev;
 612         if (of_get_child_by_name(dev->of_node, "i80-if-timings"))
 613                 ctx->i80_if = true;
 614
 615         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 616                 struct clk *clk;
 617
 618                 clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
 619                 if (IS_ERR(clk))
 620                         return PTR_ERR(clk);
 621
 622                 ctx->clks[i] = clk;
 623         }
 624
 625         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 626         if (!res) {
 627                 dev_err(dev, "cannot find IO resource\n");
 628                 return -ENXIO;
 629         }
 630
 631         ctx->addr = devm_ioremap_resource(dev, res);
 632         if (IS_ERR(ctx->addr)) {
 633                 dev_err(dev, "ioremap failed\n");
 634                 return PTR_ERR(ctx->addr);
 635         }
 636
 637         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
 638                         ctx->i80_if ? "lcd_sys" : "vsync");
 639         if (!res) {
 640                 dev_err(dev, "cannot find IRQ resource\n");
 641                 return -ENXIO;
 642         }
 643
 644         ret = devm_request_irq(dev, res->start, ctx->i80_if ?
 645                         decon_lcd_sys_irq_handler : decon_vsync_irq_handler, 0,
 646                         "drm_decon", ctx);
 647         if (ret < 0) {
 648                 dev_err(dev, "lcd_sys irq request failed\n");
 649                 return ret;
 650         }
 651
 652         platform_set_drvdata(pdev, ctx);
 653
 654         pm_runtime_enable(dev);
 655
 656         ret = component_add(dev, &decon_component_ops);
 657         if (ret)
 658                 goto err_disable_pm_runtime;
 659
 660         return 0;
 661
 662 err_disable_pm_runtime:
 663         pm_runtime_disable(dev);
 664
 665         return ret;
 666 }
 667
 668 static int exynos5433_decon_remove(struct platform_device *pdev)
 669 {
 670         pm_runtime_disable(&pdev->dev);
 671
 672         component_del(&pdev->dev, &decon_component_ops);
 673
 674         return 0;
 675 }
 676
 677 static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
 678         { .compatible = "samsung,exynos5433-decon" },
 679         {},
 680 };
 681 MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
 682
 683 struct platform_driver exynos5433_decon_driver = {
 684         .probe          = exynos5433_decon_probe,
 685         .remove         = exynos5433_decon_remove,
 686         .driver         = {
 687                 .name   = "exynos5433-decon",
 688                 .of_match_table = exynos5433_decon_driver_dt_match,
 689         },
 690 };