1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 82562G 10/100 Network Connection
31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
44 * 82567V Gigabit Network Connection
45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
50 * 82567LM-4 Gigabit Network Connection
51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
59 #define ICH_FLASH_GFPREG 0x0000
60 #define ICH_FLASH_HSFSTS 0x0004
61 #define ICH_FLASH_HSFCTL 0x0006
62 #define ICH_FLASH_FADDR 0x0008
63 #define ICH_FLASH_FDATA0 0x0010
64 #define ICH_FLASH_PR0 0x0074
66 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
67 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
68 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
69 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
70 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
72 #define ICH_CYCLE_READ 0
73 #define ICH_CYCLE_WRITE 2
74 #define ICH_CYCLE_ERASE 3
76 #define FLASH_GFPREG_BASE_MASK 0x1FFF
77 #define FLASH_SECTOR_ADDR_SHIFT 12
79 #define ICH_FLASH_SEG_SIZE_256 256
80 #define ICH_FLASH_SEG_SIZE_4K 4096
81 #define ICH_FLASH_SEG_SIZE_8K 8192
82 #define ICH_FLASH_SEG_SIZE_64K 65536
85 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
87 #define E1000_ICH_MNG_IAMT_MODE 0x2
89 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
90 (ID_LED_DEF1_OFF2 << 8) | \
91 (ID_LED_DEF1_ON2 << 4) | \
94 #define E1000_ICH_NVM_SIG_WORD 0x13
95 #define E1000_ICH_NVM_SIG_MASK 0xC000
96 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
97 #define E1000_ICH_NVM_SIG_VALUE 0x80
99 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
101 #define E1000_FEXTNVM_SW_CONFIG 1
102 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
104 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
106 #define E1000_ICH_RAR_ENTRIES 7
108 #define PHY_PAGE_SHIFT 5
109 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
110 ((reg) & MAX_PHY_REG_ADDRESS))
111 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
112 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
114 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
115 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
116 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
118 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
120 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
122 /* SMBus Address Phy Register */
123 #define HV_SMB_ADDR PHY_REG(768, 26)
124 #define HV_SMB_ADDR_PEC_EN 0x0200
125 #define HV_SMB_ADDR_VALID 0x0080
127 /* Strapping Option Register - RO */
128 #define E1000_STRAP 0x0000C
129 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
130 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
132 /* OEM Bits Phy Register */
133 #define HV_OEM_BITS PHY_REG(768, 25)
134 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
135 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
136 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
138 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
139 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
141 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
142 /* Offset 04h HSFSTS */
143 union ich8_hws_flash_status
{
145 u16 flcdone
:1; /* bit 0 Flash Cycle Done */
146 u16 flcerr
:1; /* bit 1 Flash Cycle Error */
147 u16 dael
:1; /* bit 2 Direct Access error Log */
148 u16 berasesz
:2; /* bit 4:3 Sector Erase Size */
149 u16 flcinprog
:1; /* bit 5 flash cycle in Progress */
150 u16 reserved1
:2; /* bit 13:6 Reserved */
151 u16 reserved2
:6; /* bit 13:6 Reserved */
152 u16 fldesvalid
:1; /* bit 14 Flash Descriptor Valid */
153 u16 flockdn
:1; /* bit 15 Flash Config Lock-Down */
158 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
159 /* Offset 06h FLCTL */
160 union ich8_hws_flash_ctrl
{
161 struct ich8_hsflctl
{
162 u16 flcgo
:1; /* 0 Flash Cycle Go */
163 u16 flcycle
:2; /* 2:1 Flash Cycle */
164 u16 reserved
:5; /* 7:3 Reserved */
165 u16 fldbcount
:2; /* 9:8 Flash Data Byte Count */
166 u16 flockdn
:6; /* 15:10 Reserved */
171 /* ICH Flash Region Access Permissions */
172 union ich8_hws_flash_regacc
{
174 u32 grra
:8; /* 0:7 GbE region Read Access */
175 u32 grwa
:8; /* 8:15 GbE region Write Access */
176 u32 gmrag
:8; /* 23:16 GbE Master Read Access Grant */
177 u32 gmwag
:8; /* 31:24 GbE Master Write Access Grant */
182 /* ICH Flash Protected Region */
183 union ich8_flash_protected_range
{
185 u32 base
:13; /* 0:12 Protected Range Base */
186 u32 reserved1
:2; /* 13:14 Reserved */
187 u32 rpe
:1; /* 15 Read Protection Enable */
188 u32 limit
:13; /* 16:28 Protected Range Limit */
189 u32 reserved2
:2; /* 29:30 Reserved */
190 u32 wpe
:1; /* 31 Write Protection Enable */
195 static s32
e1000_setup_link_ich8lan(struct e1000_hw
*hw
);
196 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw
*hw
);
197 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw
*hw
);
198 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw
*hw
, u32 bank
);
199 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw
*hw
,
200 u32 offset
, u8 byte
);
201 static s32
e1000_read_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
203 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw
*hw
, u32 offset
,
205 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
207 static s32
e1000_setup_copper_link_ich8lan(struct e1000_hw
*hw
);
208 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
);
209 static s32
e1000_get_cfg_done_ich8lan(struct e1000_hw
*hw
);
210 static s32
e1000_cleanup_led_ich8lan(struct e1000_hw
*hw
);
211 static s32
e1000_led_on_ich8lan(struct e1000_hw
*hw
);
212 static s32
e1000_led_off_ich8lan(struct e1000_hw
*hw
);
213 static s32
e1000_id_led_init_pchlan(struct e1000_hw
*hw
);
214 static s32
e1000_setup_led_pchlan(struct e1000_hw
*hw
);
215 static s32
e1000_cleanup_led_pchlan(struct e1000_hw
*hw
);
216 static s32
e1000_led_on_pchlan(struct e1000_hw
*hw
);
217 static s32
e1000_led_off_pchlan(struct e1000_hw
*hw
);
218 static s32
e1000_set_lplu_state_pchlan(struct e1000_hw
*hw
, bool active
);
219 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw
*hw
);
220 static void e1000_lan_init_done_ich8lan(struct e1000_hw
*hw
);
221 static s32
e1000_k1_gig_workaround_hv(struct e1000_hw
*hw
, bool link
);
223 static inline u16
__er16flash(struct e1000_hw
*hw
, unsigned long reg
)
225 return readw(hw
->flash_address
+ reg
);
228 static inline u32
__er32flash(struct e1000_hw
*hw
, unsigned long reg
)
230 return readl(hw
->flash_address
+ reg
);
233 static inline void __ew16flash(struct e1000_hw
*hw
, unsigned long reg
, u16 val
)
235 writew(val
, hw
->flash_address
+ reg
);
238 static inline void __ew32flash(struct e1000_hw
*hw
, unsigned long reg
, u32 val
)
240 writel(val
, hw
->flash_address
+ reg
);
243 #define er16flash(reg) __er16flash(hw, (reg))
244 #define er32flash(reg) __er32flash(hw, (reg))
245 #define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
246 #define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
249 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
250 * @hw: pointer to the HW structure
252 * Initialize family-specific PHY parameters and function pointers.
254 static s32
e1000_init_phy_params_pchlan(struct e1000_hw
*hw
)
256 struct e1000_phy_info
*phy
= &hw
->phy
;
260 phy
->reset_delay_us
= 100;
262 phy
->ops
.read_reg
= e1000_read_phy_reg_hv
;
263 phy
->ops
.read_reg_locked
= e1000_read_phy_reg_hv_locked
;
264 phy
->ops
.set_d0_lplu_state
= e1000_set_lplu_state_pchlan
;
265 phy
->ops
.set_d3_lplu_state
= e1000_set_lplu_state_pchlan
;
266 phy
->ops
.write_reg
= e1000_write_phy_reg_hv
;
267 phy
->ops
.write_reg_locked
= e1000_write_phy_reg_hv_locked
;
268 phy
->ops
.power_up
= e1000_power_up_phy_copper
;
269 phy
->ops
.power_down
= e1000_power_down_phy_copper_ich8lan
;
270 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
272 phy
->id
= e1000_phy_unknown
;
273 e1000e_get_phy_id(hw
);
274 phy
->type
= e1000e_get_phy_type_from_id(phy
->id
);
277 case e1000_phy_82577
:
278 phy
->ops
.check_polarity
= e1000_check_polarity_82577
;
279 phy
->ops
.force_speed_duplex
=
280 e1000_phy_force_speed_duplex_82577
;
281 phy
->ops
.get_cable_length
= e1000_get_cable_length_82577
;
282 phy
->ops
.get_info
= e1000_get_phy_info_82577
;
283 phy
->ops
.commit
= e1000e_phy_sw_reset
;
284 case e1000_phy_82578
:
285 phy
->ops
.check_polarity
= e1000_check_polarity_m88
;
286 phy
->ops
.force_speed_duplex
= e1000e_phy_force_speed_duplex_m88
;
287 phy
->ops
.get_cable_length
= e1000e_get_cable_length_m88
;
288 phy
->ops
.get_info
= e1000e_get_phy_info_m88
;
291 ret_val
= -E1000_ERR_PHY
;
299 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
300 * @hw: pointer to the HW structure
302 * Initialize family-specific PHY parameters and function pointers.
304 static s32
e1000_init_phy_params_ich8lan(struct e1000_hw
*hw
)
306 struct e1000_phy_info
*phy
= &hw
->phy
;
311 phy
->reset_delay_us
= 100;
313 phy
->ops
.power_up
= e1000_power_up_phy_copper
;
314 phy
->ops
.power_down
= e1000_power_down_phy_copper_ich8lan
;
317 * We may need to do this twice - once for IGP and if that fails,
318 * we'll set BM func pointers and try again
320 ret_val
= e1000e_determine_phy_address(hw
);
322 phy
->ops
.write_reg
= e1000e_write_phy_reg_bm
;
323 phy
->ops
.read_reg
= e1000e_read_phy_reg_bm
;
324 ret_val
= e1000e_determine_phy_address(hw
);
326 e_dbg("Cannot determine PHY addr. Erroring out\n");
332 while ((e1000_phy_unknown
== e1000e_get_phy_type_from_id(phy
->id
)) &&
335 ret_val
= e1000e_get_phy_id(hw
);
342 case IGP03E1000_E_PHY_ID
:
343 phy
->type
= e1000_phy_igp_3
;
344 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
345 phy
->ops
.read_reg_locked
= e1000e_read_phy_reg_igp_locked
;
346 phy
->ops
.write_reg_locked
= e1000e_write_phy_reg_igp_locked
;
347 phy
->ops
.get_info
= e1000e_get_phy_info_igp
;
348 phy
->ops
.check_polarity
= e1000_check_polarity_igp
;
349 phy
->ops
.force_speed_duplex
= e1000e_phy_force_speed_duplex_igp
;
352 case IFE_PLUS_E_PHY_ID
:
354 phy
->type
= e1000_phy_ife
;
355 phy
->autoneg_mask
= E1000_ALL_NOT_GIG
;
356 phy
->ops
.get_info
= e1000_get_phy_info_ife
;
357 phy
->ops
.check_polarity
= e1000_check_polarity_ife
;
358 phy
->ops
.force_speed_duplex
= e1000_phy_force_speed_duplex_ife
;
360 case BME1000_E_PHY_ID
:
361 phy
->type
= e1000_phy_bm
;
362 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
363 phy
->ops
.read_reg
= e1000e_read_phy_reg_bm
;
364 phy
->ops
.write_reg
= e1000e_write_phy_reg_bm
;
365 phy
->ops
.commit
= e1000e_phy_sw_reset
;
366 phy
->ops
.get_info
= e1000e_get_phy_info_m88
;
367 phy
->ops
.check_polarity
= e1000_check_polarity_m88
;
368 phy
->ops
.force_speed_duplex
= e1000e_phy_force_speed_duplex_m88
;
371 return -E1000_ERR_PHY
;
379 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
380 * @hw: pointer to the HW structure
382 * Initialize family-specific NVM parameters and function
385 static s32
e1000_init_nvm_params_ich8lan(struct e1000_hw
*hw
)
387 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
388 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
389 u32 gfpreg
, sector_base_addr
, sector_end_addr
;
392 /* Can't read flash registers if the register set isn't mapped. */
393 if (!hw
->flash_address
) {
394 e_dbg("ERROR: Flash registers not mapped\n");
395 return -E1000_ERR_CONFIG
;
398 nvm
->type
= e1000_nvm_flash_sw
;
400 gfpreg
= er32flash(ICH_FLASH_GFPREG
);
403 * sector_X_addr is a "sector"-aligned address (4096 bytes)
404 * Add 1 to sector_end_addr since this sector is included in
407 sector_base_addr
= gfpreg
& FLASH_GFPREG_BASE_MASK
;
408 sector_end_addr
= ((gfpreg
>> 16) & FLASH_GFPREG_BASE_MASK
) + 1;
410 /* flash_base_addr is byte-aligned */
411 nvm
->flash_base_addr
= sector_base_addr
<< FLASH_SECTOR_ADDR_SHIFT
;
414 * find total size of the NVM, then cut in half since the total
415 * size represents two separate NVM banks.
417 nvm
->flash_bank_size
= (sector_end_addr
- sector_base_addr
)
418 << FLASH_SECTOR_ADDR_SHIFT
;
419 nvm
->flash_bank_size
/= 2;
420 /* Adjust to word count */
421 nvm
->flash_bank_size
/= sizeof(u16
);
423 nvm
->word_size
= E1000_ICH8_SHADOW_RAM_WORDS
;
425 /* Clear shadow ram */
426 for (i
= 0; i
< nvm
->word_size
; i
++) {
427 dev_spec
->shadow_ram
[i
].modified
= false;
428 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
435 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
436 * @hw: pointer to the HW structure
438 * Initialize family-specific MAC parameters and function
441 static s32
e1000_init_mac_params_ich8lan(struct e1000_adapter
*adapter
)
443 struct e1000_hw
*hw
= &adapter
->hw
;
444 struct e1000_mac_info
*mac
= &hw
->mac
;
446 /* Set media type function pointer */
447 hw
->phy
.media_type
= e1000_media_type_copper
;
449 /* Set mta register count */
450 mac
->mta_reg_count
= 32;
451 /* Set rar entry count */
452 mac
->rar_entry_count
= E1000_ICH_RAR_ENTRIES
;
453 if (mac
->type
== e1000_ich8lan
)
454 mac
->rar_entry_count
--;
455 /* Set if manageability features are enabled. */
456 mac
->arc_subsystem_valid
= true;
464 mac
->ops
.id_led_init
= e1000e_id_led_init
;
466 mac
->ops
.setup_led
= e1000e_setup_led_generic
;
468 mac
->ops
.cleanup_led
= e1000_cleanup_led_ich8lan
;
469 /* turn on/off LED */
470 mac
->ops
.led_on
= e1000_led_on_ich8lan
;
471 mac
->ops
.led_off
= e1000_led_off_ich8lan
;
475 mac
->ops
.id_led_init
= e1000_id_led_init_pchlan
;
477 mac
->ops
.setup_led
= e1000_setup_led_pchlan
;
479 mac
->ops
.cleanup_led
= e1000_cleanup_led_pchlan
;
480 /* turn on/off LED */
481 mac
->ops
.led_on
= e1000_led_on_pchlan
;
482 mac
->ops
.led_off
= e1000_led_off_pchlan
;
488 /* Enable PCS Lock-loss workaround for ICH8 */
489 if (mac
->type
== e1000_ich8lan
)
490 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw
, true);
496 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
497 * @hw: pointer to the HW structure
499 * Checks to see of the link status of the hardware has changed. If a
500 * change in link status has been detected, then we read the PHY registers
501 * to get the current speed/duplex if link exists.
503 static s32
e1000_check_for_copper_link_ich8lan(struct e1000_hw
*hw
)
505 struct e1000_mac_info
*mac
= &hw
->mac
;
510 * We only want to go out to the PHY registers to see if Auto-Neg
511 * has completed and/or if our link status has changed. The
512 * get_link_status flag is set upon receiving a Link Status
513 * Change or Rx Sequence Error interrupt.
515 if (!mac
->get_link_status
) {
521 * First we want to see if the MII Status Register reports
522 * link. If so, then we want to get the current speed/duplex
525 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
529 if (hw
->mac
.type
== e1000_pchlan
) {
530 ret_val
= e1000_k1_gig_workaround_hv(hw
, link
);
536 goto out
; /* No link detected */
538 mac
->get_link_status
= false;
540 if (hw
->phy
.type
== e1000_phy_82578
) {
541 ret_val
= e1000_link_stall_workaround_hv(hw
);
547 * Check if there was DownShift, must be checked
548 * immediately after link-up
550 e1000e_check_downshift(hw
);
553 * If we are forcing speed/duplex, then we simply return since
554 * we have already determined whether we have link or not.
557 ret_val
= -E1000_ERR_CONFIG
;
562 * Auto-Neg is enabled. Auto Speed Detection takes care
563 * of MAC speed/duplex configuration. So we only need to
564 * configure Collision Distance in the MAC.
566 e1000e_config_collision_dist(hw
);
569 * Configure Flow Control now that Auto-Neg has completed.
570 * First, we need to restore the desired flow control
571 * settings because we may have had to re-autoneg with a
572 * different link partner.
574 ret_val
= e1000e_config_fc_after_link_up(hw
);
576 e_dbg("Error configuring flow control\n");
582 static s32
e1000_get_variants_ich8lan(struct e1000_adapter
*adapter
)
584 struct e1000_hw
*hw
= &adapter
->hw
;
587 rc
= e1000_init_mac_params_ich8lan(adapter
);
591 rc
= e1000_init_nvm_params_ich8lan(hw
);
595 if (hw
->mac
.type
== e1000_pchlan
)
596 rc
= e1000_init_phy_params_pchlan(hw
);
598 rc
= e1000_init_phy_params_ich8lan(hw
);
602 if (adapter
->hw
.phy
.type
== e1000_phy_ife
) {
603 adapter
->flags
&= ~FLAG_HAS_JUMBO_FRAMES
;
604 adapter
->max_hw_frame_size
= ETH_FRAME_LEN
+ ETH_FCS_LEN
;
607 if ((adapter
->hw
.mac
.type
== e1000_ich8lan
) &&
608 (adapter
->hw
.phy
.type
== e1000_phy_igp_3
))
609 adapter
->flags
|= FLAG_LSC_GIG_SPEED_DROP
;
614 static DEFINE_MUTEX(nvm_mutex
);
617 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
618 * @hw: pointer to the HW structure
620 * Acquires the mutex for performing NVM operations.
622 static s32
e1000_acquire_nvm_ich8lan(struct e1000_hw
*hw
)
624 mutex_lock(&nvm_mutex
);
630 * e1000_release_nvm_ich8lan - Release NVM mutex
631 * @hw: pointer to the HW structure
633 * Releases the mutex used while performing NVM operations.
635 static void e1000_release_nvm_ich8lan(struct e1000_hw
*hw
)
637 mutex_unlock(&nvm_mutex
);
642 static DEFINE_MUTEX(swflag_mutex
);
645 * e1000_acquire_swflag_ich8lan - Acquire software control flag
646 * @hw: pointer to the HW structure
648 * Acquires the software control flag for performing PHY and select
651 static s32
e1000_acquire_swflag_ich8lan(struct e1000_hw
*hw
)
653 u32 extcnf_ctrl
, timeout
= PHY_CFG_TIMEOUT
;
656 mutex_lock(&swflag_mutex
);
659 extcnf_ctrl
= er32(EXTCNF_CTRL
);
660 if (!(extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
))
668 e_dbg("SW/FW/HW has locked the resource for too long.\n");
669 ret_val
= -E1000_ERR_CONFIG
;
673 timeout
= SW_FLAG_TIMEOUT
;
675 extcnf_ctrl
|= E1000_EXTCNF_CTRL_SWFLAG
;
676 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
679 extcnf_ctrl
= er32(EXTCNF_CTRL
);
680 if (extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
)
688 e_dbg("Failed to acquire the semaphore.\n");
689 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_SWFLAG
;
690 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
691 ret_val
= -E1000_ERR_CONFIG
;
697 mutex_unlock(&swflag_mutex
);
703 * e1000_release_swflag_ich8lan - Release software control flag
704 * @hw: pointer to the HW structure
706 * Releases the software control flag for performing PHY and select
709 static void e1000_release_swflag_ich8lan(struct e1000_hw
*hw
)
713 extcnf_ctrl
= er32(EXTCNF_CTRL
);
714 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_SWFLAG
;
715 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
717 mutex_unlock(&swflag_mutex
);
723 * e1000_check_mng_mode_ich8lan - Checks management mode
724 * @hw: pointer to the HW structure
726 * This checks if the adapter has manageability enabled.
727 * This is a function pointer entry point only called by read/write
728 * routines for the PHY and NVM parts.
730 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw
*hw
)
736 return (fwsm
& E1000_FWSM_MODE_MASK
) ==
737 (E1000_ICH_MNG_IAMT_MODE
<< E1000_FWSM_MODE_SHIFT
);
741 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
742 * @hw: pointer to the HW structure
744 * Checks if firmware is blocking the reset of the PHY.
745 * This is a function pointer entry point only called by
748 static s32
e1000_check_reset_block_ich8lan(struct e1000_hw
*hw
)
754 return (fwsm
& E1000_ICH_FWSM_RSPCIPHY
) ? 0 : E1000_BLK_PHY_RESET
;
758 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
759 * @hw: pointer to the HW structure
761 * SW should configure the LCD from the NVM extended configuration region
762 * as a workaround for certain parts.
764 static s32
e1000_sw_lcd_config_ich8lan(struct e1000_hw
*hw
)
766 struct e1000_phy_info
*phy
= &hw
->phy
;
767 u32 i
, data
, cnf_size
, cnf_base_addr
, sw_cfg_mask
;
769 u16 word_addr
, reg_data
, reg_addr
, phy_page
= 0;
771 ret_val
= hw
->phy
.ops
.acquire(hw
);
776 * Initialize the PHY from the NVM on ICH platforms. This
777 * is needed due to an issue where the NVM configuration is
778 * not properly autoloaded after power transitions.
779 * Therefore, after each PHY reset, we will load the
780 * configuration data out of the NVM manually.
782 if ((hw
->mac
.type
== e1000_ich8lan
&& phy
->type
== e1000_phy_igp_3
) ||
783 (hw
->mac
.type
== e1000_pchlan
)) {
784 struct e1000_adapter
*adapter
= hw
->adapter
;
786 /* Check if SW needs to configure the PHY */
787 if ((adapter
->pdev
->device
== E1000_DEV_ID_ICH8_IGP_M_AMT
) ||
788 (adapter
->pdev
->device
== E1000_DEV_ID_ICH8_IGP_M
) ||
789 (hw
->mac
.type
== e1000_pchlan
))
790 sw_cfg_mask
= E1000_FEXTNVM_SW_CONFIG_ICH8M
;
792 sw_cfg_mask
= E1000_FEXTNVM_SW_CONFIG
;
794 data
= er32(FEXTNVM
);
795 if (!(data
& sw_cfg_mask
))
798 /* Wait for basic configuration completes before proceeding */
799 e1000_lan_init_done_ich8lan(hw
);
802 * Make sure HW does not configure LCD from PHY
803 * extended configuration before SW configuration
805 data
= er32(EXTCNF_CTRL
);
806 if (data
& E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE
)
809 cnf_size
= er32(EXTCNF_SIZE
);
810 cnf_size
&= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK
;
811 cnf_size
>>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT
;
815 cnf_base_addr
= data
& E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK
;
816 cnf_base_addr
>>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT
;
818 if (!(data
& E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE
) &&
819 (hw
->mac
.type
== e1000_pchlan
)) {
821 * HW configures the SMBus address and LEDs when the
822 * OEM and LCD Write Enable bits are set in the NVM.
823 * When both NVM bits are cleared, SW will configure
827 data
&= E1000_STRAP_SMBUS_ADDRESS_MASK
;
828 reg_data
= data
>> E1000_STRAP_SMBUS_ADDRESS_SHIFT
;
829 reg_data
|= HV_SMB_ADDR_PEC_EN
| HV_SMB_ADDR_VALID
;
830 ret_val
= e1000_write_phy_reg_hv_locked(hw
, HV_SMB_ADDR
,
836 ret_val
= e1000_write_phy_reg_hv_locked(hw
,
842 /* Configure LCD from extended configuration region. */
844 /* cnf_base_addr is in DWORD */
845 word_addr
= (u16
)(cnf_base_addr
<< 1);
847 for (i
= 0; i
< cnf_size
; i
++) {
848 ret_val
= e1000_read_nvm(hw
, (word_addr
+ i
* 2), 1,
853 ret_val
= e1000_read_nvm(hw
, (word_addr
+ i
* 2 + 1),
858 /* Save off the PHY page for future writes. */
859 if (reg_addr
== IGP01E1000_PHY_PAGE_SELECT
) {
864 reg_addr
&= PHY_REG_MASK
;
865 reg_addr
|= phy_page
;
867 ret_val
= phy
->ops
.write_reg_locked(hw
,
876 hw
->phy
.ops
.release(hw
);
881 * e1000_k1_gig_workaround_hv - K1 Si workaround
882 * @hw: pointer to the HW structure
883 * @link: link up bool flag
885 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
886 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
887 * If link is down, the function will restore the default K1 setting located
890 static s32
e1000_k1_gig_workaround_hv(struct e1000_hw
*hw
, bool link
)
894 bool k1_enable
= hw
->dev_spec
.ich8lan
.nvm_k1_enabled
;
896 if (hw
->mac
.type
!= e1000_pchlan
)
899 /* Wrap the whole flow with the sw flag */
900 ret_val
= hw
->phy
.ops
.acquire(hw
);
904 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
906 if (hw
->phy
.type
== e1000_phy_82578
) {
907 ret_val
= hw
->phy
.ops
.read_reg_locked(hw
, BM_CS_STATUS
,
912 status_reg
&= BM_CS_STATUS_LINK_UP
|
913 BM_CS_STATUS_RESOLVED
|
914 BM_CS_STATUS_SPEED_MASK
;
916 if (status_reg
== (BM_CS_STATUS_LINK_UP
|
917 BM_CS_STATUS_RESOLVED
|
918 BM_CS_STATUS_SPEED_1000
))
922 if (hw
->phy
.type
== e1000_phy_82577
) {
923 ret_val
= hw
->phy
.ops
.read_reg_locked(hw
, HV_M_STATUS
,
928 status_reg
&= HV_M_STATUS_LINK_UP
|
929 HV_M_STATUS_AUTONEG_COMPLETE
|
930 HV_M_STATUS_SPEED_MASK
;
932 if (status_reg
== (HV_M_STATUS_LINK_UP
|
933 HV_M_STATUS_AUTONEG_COMPLETE
|
934 HV_M_STATUS_SPEED_1000
))
938 /* Link stall fix for link up */
939 ret_val
= hw
->phy
.ops
.write_reg_locked(hw
, PHY_REG(770, 19),
945 /* Link stall fix for link down */
946 ret_val
= hw
->phy
.ops
.write_reg_locked(hw
, PHY_REG(770, 19),
952 ret_val
= e1000_configure_k1_ich8lan(hw
, k1_enable
);
955 hw
->phy
.ops
.release(hw
);
961 * e1000_configure_k1_ich8lan - Configure K1 power state
962 * @hw: pointer to the HW structure
963 * @enable: K1 state to configure
965 * Configure the K1 power state based on the provided parameter.
966 * Assumes semaphore already acquired.
968 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
970 s32
e1000_configure_k1_ich8lan(struct e1000_hw
*hw
, bool k1_enable
)
978 ret_val
= e1000e_read_kmrn_reg_locked(hw
,
979 E1000_KMRNCTRLSTA_K1_CONFIG
,
985 kmrn_reg
|= E1000_KMRNCTRLSTA_K1_ENABLE
;
987 kmrn_reg
&= ~E1000_KMRNCTRLSTA_K1_ENABLE
;
989 ret_val
= e1000e_write_kmrn_reg_locked(hw
,
990 E1000_KMRNCTRLSTA_K1_CONFIG
,
996 ctrl_ext
= er32(CTRL_EXT
);
997 ctrl_reg
= er32(CTRL
);
999 reg
= ctrl_reg
& ~(E1000_CTRL_SPD_1000
| E1000_CTRL_SPD_100
);
1000 reg
|= E1000_CTRL_FRCSPD
;
1003 ew32(CTRL_EXT
, ctrl_ext
| E1000_CTRL_EXT_SPD_BYPS
);
1005 ew32(CTRL
, ctrl_reg
);
1006 ew32(CTRL_EXT
, ctrl_ext
);
1014 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1015 * @hw: pointer to the HW structure
1016 * @d0_state: boolean if entering d0 or d3 device state
1018 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1019 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1020 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1022 static s32
e1000_oem_bits_config_ich8lan(struct e1000_hw
*hw
, bool d0_state
)
1028 if (hw
->mac
.type
!= e1000_pchlan
)
1031 ret_val
= hw
->phy
.ops
.acquire(hw
);
1035 mac_reg
= er32(EXTCNF_CTRL
);
1036 if (mac_reg
& E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE
)
1039 mac_reg
= er32(FEXTNVM
);
1040 if (!(mac_reg
& E1000_FEXTNVM_SW_CONFIG_ICH8M
))
1043 mac_reg
= er32(PHY_CTRL
);
1045 ret_val
= hw
->phy
.ops
.read_reg_locked(hw
, HV_OEM_BITS
, &oem_reg
);
1049 oem_reg
&= ~(HV_OEM_BITS_GBE_DIS
| HV_OEM_BITS_LPLU
);
1052 if (mac_reg
& E1000_PHY_CTRL_GBE_DISABLE
)
1053 oem_reg
|= HV_OEM_BITS_GBE_DIS
;
1055 if (mac_reg
& E1000_PHY_CTRL_D0A_LPLU
)
1056 oem_reg
|= HV_OEM_BITS_LPLU
;
1058 if (mac_reg
& E1000_PHY_CTRL_NOND0A_GBE_DISABLE
)
1059 oem_reg
|= HV_OEM_BITS_GBE_DIS
;
1061 if (mac_reg
& E1000_PHY_CTRL_NOND0A_LPLU
)
1062 oem_reg
|= HV_OEM_BITS_LPLU
;
1064 /* Restart auto-neg to activate the bits */
1065 if (!e1000_check_reset_block(hw
))
1066 oem_reg
|= HV_OEM_BITS_RESTART_AN
;
1067 ret_val
= hw
->phy
.ops
.write_reg_locked(hw
, HV_OEM_BITS
, oem_reg
);
1070 hw
->phy
.ops
.release(hw
);
1077 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1078 * done after every PHY reset.
1080 static s32
e1000_hv_phy_workarounds_ich8lan(struct e1000_hw
*hw
)
1084 if (hw
->mac
.type
!= e1000_pchlan
)
1087 if (((hw
->phy
.type
== e1000_phy_82577
) &&
1088 ((hw
->phy
.revision
== 1) || (hw
->phy
.revision
== 2))) ||
1089 ((hw
->phy
.type
== e1000_phy_82578
) && (hw
->phy
.revision
== 1))) {
1090 /* Disable generation of early preamble */
1091 ret_val
= e1e_wphy(hw
, PHY_REG(769, 25), 0x4431);
1095 /* Preamble tuning for SSC */
1096 ret_val
= e1e_wphy(hw
, PHY_REG(770, 16), 0xA204);
1101 if (hw
->phy
.type
== e1000_phy_82578
) {
1103 * Return registers to default by doing a soft reset then
1104 * writing 0x3140 to the control register.
1106 if (hw
->phy
.revision
< 2) {
1107 e1000e_phy_sw_reset(hw
);
1108 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, 0x3140);
1113 ret_val
= hw
->phy
.ops
.acquire(hw
);
1118 ret_val
= e1000e_write_phy_reg_mdic(hw
, IGP01E1000_PHY_PAGE_SELECT
, 0);
1121 hw
->phy
.ops
.release(hw
);
1124 * Configure the K1 Si workaround during phy reset assuming there is
1125 * link so that it disables K1 if link is in 1Gbps.
1127 ret_val
= e1000_k1_gig_workaround_hv(hw
, true);
1134 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1135 * @hw: pointer to the HW structure
1137 * Check the appropriate indication the MAC has finished configuring the
1138 * PHY after a software reset.
1140 static void e1000_lan_init_done_ich8lan(struct e1000_hw
*hw
)
1142 u32 data
, loop
= E1000_ICH8_LAN_INIT_TIMEOUT
;
1144 /* Wait for basic configuration completes before proceeding */
1146 data
= er32(STATUS
);
1147 data
&= E1000_STATUS_LAN_INIT_DONE
;
1149 } while ((!data
) && --loop
);
1152 * If basic configuration is incomplete before the above loop
1153 * count reaches 0, loading the configuration from NVM will
1154 * leave the PHY in a bad state possibly resulting in no link.
1157 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1159 /* Clear the Init Done bit for the next init event */
1160 data
= er32(STATUS
);
1161 data
&= ~E1000_STATUS_LAN_INIT_DONE
;
1166 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1167 * @hw: pointer to the HW structure
1170 * This is a function pointer entry point called by drivers
1171 * or other shared routines.
1173 static s32
e1000_phy_hw_reset_ich8lan(struct e1000_hw
*hw
)
1178 ret_val
= e1000e_phy_hw_reset_generic(hw
);
1182 /* Allow time for h/w to get to a quiescent state after reset */
1185 if (hw
->mac
.type
== e1000_pchlan
) {
1186 ret_val
= e1000_hv_phy_workarounds_ich8lan(hw
);
1191 /* Dummy read to clear the phy wakeup bit after lcd reset */
1192 if (hw
->mac
.type
== e1000_pchlan
)
1193 e1e_rphy(hw
, BM_WUC
, ®
);
1195 /* Configure the LCD with the extended configuration region in NVM */
1196 ret_val
= e1000_sw_lcd_config_ich8lan(hw
);
1200 /* Configure the LCD with the OEM bits in NVM */
1201 if (hw
->mac
.type
== e1000_pchlan
)
1202 ret_val
= e1000_oem_bits_config_ich8lan(hw
, true);
1209 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1210 * @hw: pointer to the HW structure
1211 * @active: true to enable LPLU, false to disable
1213 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1214 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1215 * the phy speed. This function will manually set the LPLU bit and restart
1216 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1217 * since it configures the same bit.
1219 static s32
e1000_set_lplu_state_pchlan(struct e1000_hw
*hw
, bool active
)
1224 ret_val
= e1e_rphy(hw
, HV_OEM_BITS
, &oem_reg
);
1229 oem_reg
|= HV_OEM_BITS_LPLU
;
1231 oem_reg
&= ~HV_OEM_BITS_LPLU
;
1233 oem_reg
|= HV_OEM_BITS_RESTART_AN
;
1234 ret_val
= e1e_wphy(hw
, HV_OEM_BITS
, oem_reg
);
1241 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1242 * @hw: pointer to the HW structure
1243 * @active: true to enable LPLU, false to disable
1245 * Sets the LPLU D0 state according to the active flag. When
1246 * activating LPLU this function also disables smart speed
1247 * and vice versa. LPLU will not be activated unless the
1248 * device autonegotiation advertisement meets standards of
1249 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1250 * This is a function pointer entry point only called by
1251 * PHY setup routines.
1253 static s32
e1000_set_d0_lplu_state_ich8lan(struct e1000_hw
*hw
, bool active
)
1255 struct e1000_phy_info
*phy
= &hw
->phy
;
1260 if (phy
->type
== e1000_phy_ife
)
1263 phy_ctrl
= er32(PHY_CTRL
);
1266 phy_ctrl
|= E1000_PHY_CTRL_D0A_LPLU
;
1267 ew32(PHY_CTRL
, phy_ctrl
);
1269 if (phy
->type
!= e1000_phy_igp_3
)
1273 * Call gig speed drop workaround on LPLU before accessing
1276 if (hw
->mac
.type
== e1000_ich8lan
)
1277 e1000e_gig_downshift_workaround_ich8lan(hw
);
1279 /* When LPLU is enabled, we should disable SmartSpeed */
1280 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
1281 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1282 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
1286 phy_ctrl
&= ~E1000_PHY_CTRL_D0A_LPLU
;
1287 ew32(PHY_CTRL
, phy_ctrl
);
1289 if (phy
->type
!= e1000_phy_igp_3
)
1293 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1294 * during Dx states where the power conservation is most
1295 * important. During driver activity we should enable
1296 * SmartSpeed, so performance is maintained.
1298 if (phy
->smart_speed
== e1000_smart_speed_on
) {
1299 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1304 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
1305 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1309 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
1310 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1315 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1316 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1327 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1328 * @hw: pointer to the HW structure
1329 * @active: true to enable LPLU, false to disable
1331 * Sets the LPLU D3 state according to the active flag. When
1332 * activating LPLU this function also disables smart speed
1333 * and vice versa. LPLU will not be activated unless the
1334 * device autonegotiation advertisement meets standards of
1335 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1336 * This is a function pointer entry point only called by
1337 * PHY setup routines.
1339 static s32
e1000_set_d3_lplu_state_ich8lan(struct e1000_hw
*hw
, bool active
)
1341 struct e1000_phy_info
*phy
= &hw
->phy
;
1346 phy_ctrl
= er32(PHY_CTRL
);
1349 phy_ctrl
&= ~E1000_PHY_CTRL_NOND0A_LPLU
;
1350 ew32(PHY_CTRL
, phy_ctrl
);
1352 if (phy
->type
!= e1000_phy_igp_3
)
1356 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1357 * during Dx states where the power conservation is most
1358 * important. During driver activity we should enable
1359 * SmartSpeed, so performance is maintained.
1361 if (phy
->smart_speed
== e1000_smart_speed_on
) {
1362 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1367 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
1368 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1372 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
1373 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1378 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1379 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1384 } else if ((phy
->autoneg_advertised
== E1000_ALL_SPEED_DUPLEX
) ||
1385 (phy
->autoneg_advertised
== E1000_ALL_NOT_GIG
) ||
1386 (phy
->autoneg_advertised
== E1000_ALL_10_SPEED
)) {
1387 phy_ctrl
|= E1000_PHY_CTRL_NOND0A_LPLU
;
1388 ew32(PHY_CTRL
, phy_ctrl
);
1390 if (phy
->type
!= e1000_phy_igp_3
)
1394 * Call gig speed drop workaround on LPLU before accessing
1397 if (hw
->mac
.type
== e1000_ich8lan
)
1398 e1000e_gig_downshift_workaround_ich8lan(hw
);
1400 /* When LPLU is enabled, we should disable SmartSpeed */
1401 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
1405 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1406 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
1413 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1414 * @hw: pointer to the HW structure
1415 * @bank: pointer to the variable that returns the active bank
1417 * Reads signature byte from the NVM using the flash access registers.
1418 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1420 static s32
e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw
*hw
, u32
*bank
)
1423 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1424 u32 bank1_offset
= nvm
->flash_bank_size
* sizeof(u16
);
1425 u32 act_offset
= E1000_ICH_NVM_SIG_WORD
* 2 + 1;
1429 switch (hw
->mac
.type
) {
1433 if ((eecd
& E1000_EECD_SEC1VAL_VALID_MASK
) ==
1434 E1000_EECD_SEC1VAL_VALID_MASK
) {
1435 if (eecd
& E1000_EECD_SEC1VAL
)
1442 e_dbg("Unable to determine valid NVM bank via EEC - "
1443 "reading flash signature\n");
1446 /* set bank to 0 in case flash read fails */
1450 ret_val
= e1000_read_flash_byte_ich8lan(hw
, act_offset
,
1454 if ((sig_byte
& E1000_ICH_NVM_VALID_SIG_MASK
) ==
1455 E1000_ICH_NVM_SIG_VALUE
) {
1461 ret_val
= e1000_read_flash_byte_ich8lan(hw
, act_offset
+
1466 if ((sig_byte
& E1000_ICH_NVM_VALID_SIG_MASK
) ==
1467 E1000_ICH_NVM_SIG_VALUE
) {
1472 e_dbg("ERROR: No valid NVM bank present\n");
1473 return -E1000_ERR_NVM
;
1480 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1481 * @hw: pointer to the HW structure
1482 * @offset: The offset (in bytes) of the word(s) to read.
1483 * @words: Size of data to read in words
1484 * @data: Pointer to the word(s) to read at offset.
1486 * Reads a word(s) from the NVM using the flash access registers.
1488 static s32
e1000_read_nvm_ich8lan(struct e1000_hw
*hw
, u16 offset
, u16 words
,
1491 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1492 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
1498 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
1500 e_dbg("nvm parameter(s) out of bounds\n");
1501 ret_val
= -E1000_ERR_NVM
;
1505 nvm
->ops
.acquire(hw
);
1507 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
1509 e_dbg("Could not detect valid bank, assuming bank 0\n");
1513 act_offset
= (bank
) ? nvm
->flash_bank_size
: 0;
1514 act_offset
+= offset
;
1517 for (i
= 0; i
< words
; i
++) {
1518 if ((dev_spec
->shadow_ram
) &&
1519 (dev_spec
->shadow_ram
[offset
+i
].modified
)) {
1520 data
[i
] = dev_spec
->shadow_ram
[offset
+i
].value
;
1522 ret_val
= e1000_read_flash_word_ich8lan(hw
,
1531 nvm
->ops
.release(hw
);
1535 e_dbg("NVM read error: %d\n", ret_val
);
1541 * e1000_flash_cycle_init_ich8lan - Initialize flash
1542 * @hw: pointer to the HW structure
1544 * This function does initial flash setup so that a new read/write/erase cycle
1547 static s32
e1000_flash_cycle_init_ich8lan(struct e1000_hw
*hw
)
1549 union ich8_hws_flash_status hsfsts
;
1550 s32 ret_val
= -E1000_ERR_NVM
;
1553 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1555 /* Check if the flash descriptor is valid */
1556 if (hsfsts
.hsf_status
.fldesvalid
== 0) {
1557 e_dbg("Flash descriptor invalid. "
1558 "SW Sequencing must be used.");
1559 return -E1000_ERR_NVM
;
1562 /* Clear FCERR and DAEL in hw status by writing 1 */
1563 hsfsts
.hsf_status
.flcerr
= 1;
1564 hsfsts
.hsf_status
.dael
= 1;
1566 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
1569 * Either we should have a hardware SPI cycle in progress
1570 * bit to check against, in order to start a new cycle or
1571 * FDONE bit should be changed in the hardware so that it
1572 * is 1 after hardware reset, which can then be used as an
1573 * indication whether a cycle is in progress or has been
1577 if (hsfsts
.hsf_status
.flcinprog
== 0) {
1579 * There is no cycle running at present,
1580 * so we can start a cycle.
1581 * Begin by setting Flash Cycle Done.
1583 hsfsts
.hsf_status
.flcdone
= 1;
1584 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
1588 * Otherwise poll for sometime so the current
1589 * cycle has a chance to end before giving up.
1591 for (i
= 0; i
< ICH_FLASH_READ_COMMAND_TIMEOUT
; i
++) {
1592 hsfsts
.regval
= __er16flash(hw
, ICH_FLASH_HSFSTS
);
1593 if (hsfsts
.hsf_status
.flcinprog
== 0) {
1601 * Successful in waiting for previous cycle to timeout,
1602 * now set the Flash Cycle Done.
1604 hsfsts
.hsf_status
.flcdone
= 1;
1605 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
1607 e_dbg("Flash controller busy, cannot get access");
1615 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1616 * @hw: pointer to the HW structure
1617 * @timeout: maximum time to wait for completion
1619 * This function starts a flash cycle and waits for its completion.
1621 static s32
e1000_flash_cycle_ich8lan(struct e1000_hw
*hw
, u32 timeout
)
1623 union ich8_hws_flash_ctrl hsflctl
;
1624 union ich8_hws_flash_status hsfsts
;
1625 s32 ret_val
= -E1000_ERR_NVM
;
1628 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1629 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
1630 hsflctl
.hsf_ctrl
.flcgo
= 1;
1631 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
1633 /* wait till FDONE bit is set to 1 */
1635 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1636 if (hsfsts
.hsf_status
.flcdone
== 1)
1639 } while (i
++ < timeout
);
1641 if (hsfsts
.hsf_status
.flcdone
== 1 && hsfsts
.hsf_status
.flcerr
== 0)
1648 * e1000_read_flash_word_ich8lan - Read word from flash
1649 * @hw: pointer to the HW structure
1650 * @offset: offset to data location
1651 * @data: pointer to the location for storing the data
1653 * Reads the flash word at offset into data. Offset is converted
1654 * to bytes before read.
1656 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1659 /* Must convert offset into bytes. */
1662 return e1000_read_flash_data_ich8lan(hw
, offset
, 2, data
);
1666 * e1000_read_flash_byte_ich8lan - Read byte from flash
1667 * @hw: pointer to the HW structure
1668 * @offset: The offset of the byte to read.
1669 * @data: Pointer to a byte to store the value read.
1671 * Reads a single byte from the NVM using the flash access registers.
1673 static s32
e1000_read_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1679 ret_val
= e1000_read_flash_data_ich8lan(hw
, offset
, 1, &word
);
1689 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1690 * @hw: pointer to the HW structure
1691 * @offset: The offset (in bytes) of the byte or word to read.
1692 * @size: Size of data to read, 1=byte 2=word
1693 * @data: Pointer to the word to store the value read.
1695 * Reads a byte or word from the NVM using the flash access registers.
1697 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1700 union ich8_hws_flash_status hsfsts
;
1701 union ich8_hws_flash_ctrl hsflctl
;
1702 u32 flash_linear_addr
;
1704 s32 ret_val
= -E1000_ERR_NVM
;
1707 if (size
< 1 || size
> 2 || offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
1708 return -E1000_ERR_NVM
;
1710 flash_linear_addr
= (ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
1711 hw
->nvm
.flash_base_addr
;
1716 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
1720 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
1721 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1722 hsflctl
.hsf_ctrl
.fldbcount
= size
- 1;
1723 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_READ
;
1724 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
1726 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
1728 ret_val
= e1000_flash_cycle_ich8lan(hw
,
1729 ICH_FLASH_READ_COMMAND_TIMEOUT
);
1732 * Check if FCERR is set to 1, if set to 1, clear it
1733 * and try the whole sequence a few more times, else
1734 * read in (shift in) the Flash Data0, the order is
1735 * least significant byte first msb to lsb
1738 flash_data
= er32flash(ICH_FLASH_FDATA0
);
1740 *data
= (u8
)(flash_data
& 0x000000FF);
1741 } else if (size
== 2) {
1742 *data
= (u16
)(flash_data
& 0x0000FFFF);
1747 * If we've gotten here, then things are probably
1748 * completely hosed, but if the error condition is
1749 * detected, it won't hurt to give it another try...
1750 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1752 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1753 if (hsfsts
.hsf_status
.flcerr
== 1) {
1754 /* Repeat for some time before giving up. */
1756 } else if (hsfsts
.hsf_status
.flcdone
== 0) {
1757 e_dbg("Timeout error - flash cycle "
1758 "did not complete.");
1762 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
1768 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1769 * @hw: pointer to the HW structure
1770 * @offset: The offset (in bytes) of the word(s) to write.
1771 * @words: Size of data to write in words
1772 * @data: Pointer to the word(s) to write at offset.
1774 * Writes a byte or word to the NVM using the flash access registers.
1776 static s32
e1000_write_nvm_ich8lan(struct e1000_hw
*hw
, u16 offset
, u16 words
,
1779 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1780 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
1783 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
1785 e_dbg("nvm parameter(s) out of bounds\n");
1786 return -E1000_ERR_NVM
;
1789 nvm
->ops
.acquire(hw
);
1791 for (i
= 0; i
< words
; i
++) {
1792 dev_spec
->shadow_ram
[offset
+i
].modified
= true;
1793 dev_spec
->shadow_ram
[offset
+i
].value
= data
[i
];
1796 nvm
->ops
.release(hw
);
1802 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1803 * @hw: pointer to the HW structure
1805 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1806 * which writes the checksum to the shadow ram. The changes in the shadow
1807 * ram are then committed to the EEPROM by processing each bank at a time
1808 * checking for the modified bit and writing only the pending changes.
1809 * After a successful commit, the shadow ram is cleared and is ready for
1812 static s32
e1000_update_nvm_checksum_ich8lan(struct e1000_hw
*hw
)
1814 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1815 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
1816 u32 i
, act_offset
, new_bank_offset
, old_bank_offset
, bank
;
1820 ret_val
= e1000e_update_nvm_checksum_generic(hw
);
1824 if (nvm
->type
!= e1000_nvm_flash_sw
)
1827 nvm
->ops
.acquire(hw
);
1830 * We're writing to the opposite bank so if we're on bank 1,
1831 * write to bank 0 etc. We also need to erase the segment that
1832 * is going to be written
1834 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
1836 e_dbg("Could not detect valid bank, assuming bank 0\n");
1841 new_bank_offset
= nvm
->flash_bank_size
;
1842 old_bank_offset
= 0;
1843 ret_val
= e1000_erase_flash_bank_ich8lan(hw
, 1);
1845 nvm
->ops
.release(hw
);
1849 old_bank_offset
= nvm
->flash_bank_size
;
1850 new_bank_offset
= 0;
1851 ret_val
= e1000_erase_flash_bank_ich8lan(hw
, 0);
1853 nvm
->ops
.release(hw
);
1858 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
1860 * Determine whether to write the value stored
1861 * in the other NVM bank or a modified value stored
1864 if (dev_spec
->shadow_ram
[i
].modified
) {
1865 data
= dev_spec
->shadow_ram
[i
].value
;
1867 ret_val
= e1000_read_flash_word_ich8lan(hw
, i
+
1875 * If the word is 0x13, then make sure the signature bits
1876 * (15:14) are 11b until the commit has completed.
1877 * This will allow us to write 10b which indicates the
1878 * signature is valid. We want to do this after the write
1879 * has completed so that we don't mark the segment valid
1880 * while the write is still in progress
1882 if (i
== E1000_ICH_NVM_SIG_WORD
)
1883 data
|= E1000_ICH_NVM_SIG_MASK
;
1885 /* Convert offset to bytes. */
1886 act_offset
= (i
+ new_bank_offset
) << 1;
1889 /* Write the bytes to the new bank. */
1890 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
1897 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
1905 * Don't bother writing the segment valid bits if sector
1906 * programming failed.
1909 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
1910 e_dbg("Flash commit failed.\n");
1911 nvm
->ops
.release(hw
);
1916 * Finally validate the new segment by setting bit 15:14
1917 * to 10b in word 0x13 , this can be done without an
1918 * erase as well since these bits are 11 to start with
1919 * and we need to change bit 14 to 0b
1921 act_offset
= new_bank_offset
+ E1000_ICH_NVM_SIG_WORD
;
1922 ret_val
= e1000_read_flash_word_ich8lan(hw
, act_offset
, &data
);
1924 nvm
->ops
.release(hw
);
1928 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
1932 nvm
->ops
.release(hw
);
1937 * And invalidate the previously valid segment by setting
1938 * its signature word (0x13) high_byte to 0b. This can be
1939 * done without an erase because flash erase sets all bits
1940 * to 1's. We can write 1's to 0's without an erase
1942 act_offset
= (old_bank_offset
+ E1000_ICH_NVM_SIG_WORD
) * 2 + 1;
1943 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
, act_offset
, 0);
1945 nvm
->ops
.release(hw
);
1949 /* Great! Everything worked, we can now clear the cached entries. */
1950 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
1951 dev_spec
->shadow_ram
[i
].modified
= false;
1952 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
1955 nvm
->ops
.release(hw
);
1958 * Reload the EEPROM, or else modifications will not appear
1959 * until after the next adapter reset.
1961 e1000e_reload_nvm(hw
);
1966 e_dbg("NVM update error: %d\n", ret_val
);
1972 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1973 * @hw: pointer to the HW structure
1975 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1976 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
1977 * calculated, in which case we need to calculate the checksum and set bit 6.
1979 static s32
e1000_validate_nvm_checksum_ich8lan(struct e1000_hw
*hw
)
1985 * Read 0x19 and check bit 6. If this bit is 0, the checksum
1986 * needs to be fixed. This bit is an indication that the NVM
1987 * was prepared by OEM software and did not calculate the
1988 * checksum...a likely scenario.
1990 ret_val
= e1000_read_nvm(hw
, 0x19, 1, &data
);
1994 if ((data
& 0x40) == 0) {
1996 ret_val
= e1000_write_nvm(hw
, 0x19, 1, &data
);
1999 ret_val
= e1000e_update_nvm_checksum(hw
);
2004 return e1000e_validate_nvm_checksum_generic(hw
);
2008 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2009 * @hw: pointer to the HW structure
2011 * To prevent malicious write/erase of the NVM, set it to be read-only
2012 * so that the hardware ignores all write/erase cycles of the NVM via
2013 * the flash control registers. The shadow-ram copy of the NVM will
2014 * still be updated, however any updates to this copy will not stick
2015 * across driver reloads.
2017 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw
*hw
)
2019 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
2020 union ich8_flash_protected_range pr0
;
2021 union ich8_hws_flash_status hsfsts
;
2024 nvm
->ops
.acquire(hw
);
2026 gfpreg
= er32flash(ICH_FLASH_GFPREG
);
2028 /* Write-protect GbE Sector of NVM */
2029 pr0
.regval
= er32flash(ICH_FLASH_PR0
);
2030 pr0
.range
.base
= gfpreg
& FLASH_GFPREG_BASE_MASK
;
2031 pr0
.range
.limit
= ((gfpreg
>> 16) & FLASH_GFPREG_BASE_MASK
);
2032 pr0
.range
.wpe
= true;
2033 ew32flash(ICH_FLASH_PR0
, pr0
.regval
);
2036 * Lock down a subset of GbE Flash Control Registers, e.g.
2037 * PR0 to prevent the write-protection from being lifted.
2038 * Once FLOCKDN is set, the registers protected by it cannot
2039 * be written until FLOCKDN is cleared by a hardware reset.
2041 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2042 hsfsts
.hsf_status
.flockdn
= true;
2043 ew32flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
2045 nvm
->ops
.release(hw
);
2049 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2050 * @hw: pointer to the HW structure
2051 * @offset: The offset (in bytes) of the byte/word to read.
2052 * @size: Size of data to read, 1=byte 2=word
2053 * @data: The byte(s) to write to the NVM.
2055 * Writes one/two bytes to the NVM using the flash access registers.
2057 static s32
e1000_write_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
2060 union ich8_hws_flash_status hsfsts
;
2061 union ich8_hws_flash_ctrl hsflctl
;
2062 u32 flash_linear_addr
;
2067 if (size
< 1 || size
> 2 || data
> size
* 0xff ||
2068 offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
2069 return -E1000_ERR_NVM
;
2071 flash_linear_addr
= (ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
2072 hw
->nvm
.flash_base_addr
;
2077 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
2081 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
2082 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2083 hsflctl
.hsf_ctrl
.fldbcount
= size
-1;
2084 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_WRITE
;
2085 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
2087 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
2090 flash_data
= (u32
)data
& 0x00FF;
2092 flash_data
= (u32
)data
;
2094 ew32flash(ICH_FLASH_FDATA0
, flash_data
);
2097 * check if FCERR is set to 1 , if set to 1, clear it
2098 * and try the whole sequence a few more times else done
2100 ret_val
= e1000_flash_cycle_ich8lan(hw
,
2101 ICH_FLASH_WRITE_COMMAND_TIMEOUT
);
2106 * If we're here, then things are most likely
2107 * completely hosed, but if the error condition
2108 * is detected, it won't hurt to give it another
2109 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2111 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2112 if (hsfsts
.hsf_status
.flcerr
== 1)
2113 /* Repeat for some time before giving up. */
2115 if (hsfsts
.hsf_status
.flcdone
== 0) {
2116 e_dbg("Timeout error - flash cycle "
2117 "did not complete.");
2120 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
2126 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2127 * @hw: pointer to the HW structure
2128 * @offset: The index of the byte to read.
2129 * @data: The byte to write to the NVM.
2131 * Writes a single byte to the NVM using the flash access registers.
2133 static s32
e1000_write_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
2136 u16 word
= (u16
)data
;
2138 return e1000_write_flash_data_ich8lan(hw
, offset
, 1, word
);
2142 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2143 * @hw: pointer to the HW structure
2144 * @offset: The offset of the byte to write.
2145 * @byte: The byte to write to the NVM.
2147 * Writes a single byte to the NVM using the flash access registers.
2148 * Goes through a retry algorithm before giving up.
2150 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw
*hw
,
2151 u32 offset
, u8 byte
)
2154 u16 program_retries
;
2156 ret_val
= e1000_write_flash_byte_ich8lan(hw
, offset
, byte
);
2160 for (program_retries
= 0; program_retries
< 100; program_retries
++) {
2161 e_dbg("Retrying Byte %2.2X at offset %u\n", byte
, offset
);
2163 ret_val
= e1000_write_flash_byte_ich8lan(hw
, offset
, byte
);
2167 if (program_retries
== 100)
2168 return -E1000_ERR_NVM
;
2174 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2175 * @hw: pointer to the HW structure
2176 * @bank: 0 for first bank, 1 for second bank, etc.
2178 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2179 * bank N is 4096 * N + flash_reg_addr.
2181 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw
*hw
, u32 bank
)
2183 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
2184 union ich8_hws_flash_status hsfsts
;
2185 union ich8_hws_flash_ctrl hsflctl
;
2186 u32 flash_linear_addr
;
2187 /* bank size is in 16bit words - adjust to bytes */
2188 u32 flash_bank_size
= nvm
->flash_bank_size
* 2;
2191 s32 j
, iteration
, sector_size
;
2193 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2196 * Determine HW Sector size: Read BERASE bits of hw flash status
2198 * 00: The Hw sector is 256 bytes, hence we need to erase 16
2199 * consecutive sectors. The start index for the nth Hw sector
2200 * can be calculated as = bank * 4096 + n * 256
2201 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2202 * The start index for the nth Hw sector can be calculated
2204 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2205 * (ich9 only, otherwise error condition)
2206 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2208 switch (hsfsts
.hsf_status
.berasesz
) {
2210 /* Hw sector size 256 */
2211 sector_size
= ICH_FLASH_SEG_SIZE_256
;
2212 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_256
;
2215 sector_size
= ICH_FLASH_SEG_SIZE_4K
;
2219 sector_size
= ICH_FLASH_SEG_SIZE_8K
;
2223 sector_size
= ICH_FLASH_SEG_SIZE_64K
;
2227 return -E1000_ERR_NVM
;
2230 /* Start with the base address, then add the sector offset. */
2231 flash_linear_addr
= hw
->nvm
.flash_base_addr
;
2232 flash_linear_addr
+= (bank
) ? flash_bank_size
: 0;
2234 for (j
= 0; j
< iteration
; j
++) {
2237 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
2242 * Write a value 11 (block Erase) in Flash
2243 * Cycle field in hw flash control
2245 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
2246 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_ERASE
;
2247 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
2250 * Write the last 24 bits of an index within the
2251 * block into Flash Linear address field in Flash
2254 flash_linear_addr
+= (j
* sector_size
);
2255 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
2257 ret_val
= e1000_flash_cycle_ich8lan(hw
,
2258 ICH_FLASH_ERASE_COMMAND_TIMEOUT
);
2263 * Check if FCERR is set to 1. If 1,
2264 * clear it and try the whole sequence
2265 * a few more times else Done
2267 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2268 if (hsfsts
.hsf_status
.flcerr
== 1)
2269 /* repeat for some time before giving up */
2271 else if (hsfsts
.hsf_status
.flcdone
== 0)
2273 } while (++count
< ICH_FLASH_CYCLE_REPEAT_COUNT
);
2280 * e1000_valid_led_default_ich8lan - Set the default LED settings
2281 * @hw: pointer to the HW structure
2282 * @data: Pointer to the LED settings
2284 * Reads the LED default settings from the NVM to data. If the NVM LED
2285 * settings is all 0's or F's, set the LED default to a valid LED default
2288 static s32
e1000_valid_led_default_ich8lan(struct e1000_hw
*hw
, u16
*data
)
2292 ret_val
= e1000_read_nvm(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
2294 e_dbg("NVM Read Error\n");
2298 if (*data
== ID_LED_RESERVED_0000
||
2299 *data
== ID_LED_RESERVED_FFFF
)
2300 *data
= ID_LED_DEFAULT_ICH8LAN
;
2306 * e1000_id_led_init_pchlan - store LED configurations
2307 * @hw: pointer to the HW structure
2309 * PCH does not control LEDs via the LEDCTL register, rather it uses
2310 * the PHY LED configuration register.
2312 * PCH also does not have an "always on" or "always off" mode which
2313 * complicates the ID feature. Instead of using the "on" mode to indicate
2314 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2315 * use "link_up" mode. The LEDs will still ID on request if there is no
2316 * link based on logic in e1000_led_[on|off]_pchlan().
2318 static s32
e1000_id_led_init_pchlan(struct e1000_hw
*hw
)
2320 struct e1000_mac_info
*mac
= &hw
->mac
;
2322 const u32 ledctl_on
= E1000_LEDCTL_MODE_LINK_UP
;
2323 const u32 ledctl_off
= E1000_LEDCTL_MODE_LINK_UP
| E1000_PHY_LED0_IVRT
;
2324 u16 data
, i
, temp
, shift
;
2326 /* Get default ID LED modes */
2327 ret_val
= hw
->nvm
.ops
.valid_led_default(hw
, &data
);
2331 mac
->ledctl_default
= er32(LEDCTL
);
2332 mac
->ledctl_mode1
= mac
->ledctl_default
;
2333 mac
->ledctl_mode2
= mac
->ledctl_default
;
2335 for (i
= 0; i
< 4; i
++) {
2336 temp
= (data
>> (i
<< 2)) & E1000_LEDCTL_LED0_MODE_MASK
;
2339 case ID_LED_ON1_DEF2
:
2340 case ID_LED_ON1_ON2
:
2341 case ID_LED_ON1_OFF2
:
2342 mac
->ledctl_mode1
&= ~(E1000_PHY_LED0_MASK
<< shift
);
2343 mac
->ledctl_mode1
|= (ledctl_on
<< shift
);
2345 case ID_LED_OFF1_DEF2
:
2346 case ID_LED_OFF1_ON2
:
2347 case ID_LED_OFF1_OFF2
:
2348 mac
->ledctl_mode1
&= ~(E1000_PHY_LED0_MASK
<< shift
);
2349 mac
->ledctl_mode1
|= (ledctl_off
<< shift
);
2356 case ID_LED_DEF1_ON2
:
2357 case ID_LED_ON1_ON2
:
2358 case ID_LED_OFF1_ON2
:
2359 mac
->ledctl_mode2
&= ~(E1000_PHY_LED0_MASK
<< shift
);
2360 mac
->ledctl_mode2
|= (ledctl_on
<< shift
);
2362 case ID_LED_DEF1_OFF2
:
2363 case ID_LED_ON1_OFF2
:
2364 case ID_LED_OFF1_OFF2
:
2365 mac
->ledctl_mode2
&= ~(E1000_PHY_LED0_MASK
<< shift
);
2366 mac
->ledctl_mode2
|= (ledctl_off
<< shift
);
2379 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2380 * @hw: pointer to the HW structure
2382 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2383 * register, so the the bus width is hard coded.
2385 static s32
e1000_get_bus_info_ich8lan(struct e1000_hw
*hw
)
2387 struct e1000_bus_info
*bus
= &hw
->bus
;
2390 ret_val
= e1000e_get_bus_info_pcie(hw
);
2393 * ICH devices are "PCI Express"-ish. They have
2394 * a configuration space, but do not contain
2395 * PCI Express Capability registers, so bus width
2396 * must be hardcoded.
2398 if (bus
->width
== e1000_bus_width_unknown
)
2399 bus
->width
= e1000_bus_width_pcie_x1
;
2405 * e1000_reset_hw_ich8lan - Reset the hardware
2406 * @hw: pointer to the HW structure
2408 * Does a full reset of the hardware which includes a reset of the PHY and
2411 static s32
e1000_reset_hw_ich8lan(struct e1000_hw
*hw
)
2413 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2419 * Prevent the PCI-E bus from sticking if there is no TLP connection
2420 * on the last TLP read/write transaction when MAC is reset.
2422 ret_val
= e1000e_disable_pcie_master(hw
);
2424 e_dbg("PCI-E Master disable polling has failed.\n");
2427 e_dbg("Masking off all interrupts\n");
2428 ew32(IMC
, 0xffffffff);
2431 * Disable the Transmit and Receive units. Then delay to allow
2432 * any pending transactions to complete before we hit the MAC
2433 * with the global reset.
2436 ew32(TCTL
, E1000_TCTL_PSP
);
2441 /* Workaround for ICH8 bit corruption issue in FIFO memory */
2442 if (hw
->mac
.type
== e1000_ich8lan
) {
2443 /* Set Tx and Rx buffer allocation to 8k apiece. */
2444 ew32(PBA
, E1000_PBA_8K
);
2445 /* Set Packet Buffer Size to 16k. */
2446 ew32(PBS
, E1000_PBS_16K
);
2449 if (hw
->mac
.type
== e1000_pchlan
) {
2450 /* Save the NVM K1 bit setting*/
2451 ret_val
= e1000_read_nvm(hw
, E1000_NVM_K1_CONFIG
, 1, ®
);
2455 if (reg
& E1000_NVM_K1_ENABLE
)
2456 dev_spec
->nvm_k1_enabled
= true;
2458 dev_spec
->nvm_k1_enabled
= false;
2463 if (!e1000_check_reset_block(hw
)) {
2464 /* Clear PHY Reset Asserted bit */
2465 if (hw
->mac
.type
>= e1000_pchlan
) {
2466 u32 status
= er32(STATUS
);
2467 ew32(STATUS
, status
& ~E1000_STATUS_PHYRA
);
2471 * PHY HW reset requires MAC CORE reset at the same
2472 * time to make sure the interface between MAC and the
2473 * external PHY is reset.
2475 ctrl
|= E1000_CTRL_PHY_RST
;
2477 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
2478 e_dbg("Issuing a global reset to ich8lan\n");
2479 ew32(CTRL
, (ctrl
| E1000_CTRL_RST
));
2483 e1000_release_swflag_ich8lan(hw
);
2485 if (ctrl
& E1000_CTRL_PHY_RST
)
2486 ret_val
= hw
->phy
.ops
.get_cfg_done(hw
);
2488 if (hw
->mac
.type
>= e1000_ich10lan
) {
2489 e1000_lan_init_done_ich8lan(hw
);
2491 ret_val
= e1000e_get_auto_rd_done(hw
);
2494 * When auto config read does not complete, do not
2495 * return with an error. This can happen in situations
2496 * where there is no eeprom and prevents getting link.
2498 e_dbg("Auto Read Done did not complete\n");
2501 /* Dummy read to clear the phy wakeup bit after lcd reset */
2502 if (hw
->mac
.type
== e1000_pchlan
)
2503 e1e_rphy(hw
, BM_WUC
, ®
);
2505 ret_val
= e1000_sw_lcd_config_ich8lan(hw
);
2509 if (hw
->mac
.type
== e1000_pchlan
) {
2510 ret_val
= e1000_oem_bits_config_ich8lan(hw
, true);
2515 * For PCH, this write will make sure that any noise
2516 * will be detected as a CRC error and be dropped rather than show up
2517 * as a bad packet to the DMA engine.
2519 if (hw
->mac
.type
== e1000_pchlan
)
2520 ew32(CRC_OFFSET
, 0x65656565);
2522 ew32(IMC
, 0xffffffff);
2525 kab
= er32(KABGTXD
);
2526 kab
|= E1000_KABGTXD_BGSQLBIAS
;
2529 if (hw
->mac
.type
== e1000_pchlan
)
2530 ret_val
= e1000_hv_phy_workarounds_ich8lan(hw
);
2537 * e1000_init_hw_ich8lan - Initialize the hardware
2538 * @hw: pointer to the HW structure
2540 * Prepares the hardware for transmit and receive by doing the following:
2541 * - initialize hardware bits
2542 * - initialize LED identification
2543 * - setup receive address registers
2544 * - setup flow control
2545 * - setup transmit descriptors
2546 * - clear statistics
2548 static s32
e1000_init_hw_ich8lan(struct e1000_hw
*hw
)
2550 struct e1000_mac_info
*mac
= &hw
->mac
;
2551 u32 ctrl_ext
, txdctl
, snoop
;
2555 e1000_initialize_hw_bits_ich8lan(hw
);
2557 /* Initialize identification LED */
2558 ret_val
= mac
->ops
.id_led_init(hw
);
2560 e_dbg("Error initializing identification LED\n");
2561 /* This is not fatal and we should not stop init due to this */
2563 /* Setup the receive address. */
2564 e1000e_init_rx_addrs(hw
, mac
->rar_entry_count
);
2566 /* Zero out the Multicast HASH table */
2567 e_dbg("Zeroing the MTA\n");
2568 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
2569 E1000_WRITE_REG_ARRAY(hw
, E1000_MTA
, i
, 0);
2572 * The 82578 Rx buffer will stall if wakeup is enabled in host and
2573 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
2574 * Reset the phy after disabling host wakeup to reset the Rx buffer.
2576 if (hw
->phy
.type
== e1000_phy_82578
) {
2577 hw
->phy
.ops
.read_reg(hw
, BM_WUC
, &i
);
2578 ret_val
= e1000_phy_hw_reset_ich8lan(hw
);
2583 /* Setup link and flow control */
2584 ret_val
= e1000_setup_link_ich8lan(hw
);
2586 /* Set the transmit descriptor write-back policy for both queues */
2587 txdctl
= er32(TXDCTL(0));
2588 txdctl
= (txdctl
& ~E1000_TXDCTL_WTHRESH
) |
2589 E1000_TXDCTL_FULL_TX_DESC_WB
;
2590 txdctl
= (txdctl
& ~E1000_TXDCTL_PTHRESH
) |
2591 E1000_TXDCTL_MAX_TX_DESC_PREFETCH
;
2592 ew32(TXDCTL(0), txdctl
);
2593 txdctl
= er32(TXDCTL(1));
2594 txdctl
= (txdctl
& ~E1000_TXDCTL_WTHRESH
) |
2595 E1000_TXDCTL_FULL_TX_DESC_WB
;
2596 txdctl
= (txdctl
& ~E1000_TXDCTL_PTHRESH
) |
2597 E1000_TXDCTL_MAX_TX_DESC_PREFETCH
;
2598 ew32(TXDCTL(1), txdctl
);
2601 * ICH8 has opposite polarity of no_snoop bits.
2602 * By default, we should use snoop behavior.
2604 if (mac
->type
== e1000_ich8lan
)
2605 snoop
= PCIE_ICH8_SNOOP_ALL
;
2607 snoop
= (u32
) ~(PCIE_NO_SNOOP_ALL
);
2608 e1000e_set_pcie_no_snoop(hw
, snoop
);
2610 ctrl_ext
= er32(CTRL_EXT
);
2611 ctrl_ext
|= E1000_CTRL_EXT_RO_DIS
;
2612 ew32(CTRL_EXT
, ctrl_ext
);
2615 * Clear all of the statistics registers (clear on read). It is
2616 * important that we do this after we have tried to establish link
2617 * because the symbol error count will increment wildly if there
2620 e1000_clear_hw_cntrs_ich8lan(hw
);
2625 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2626 * @hw: pointer to the HW structure
2628 * Sets/Clears required hardware bits necessary for correctly setting up the
2629 * hardware for transmit and receive.
2631 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw
*hw
)
2635 /* Extended Device Control */
2636 reg
= er32(CTRL_EXT
);
2638 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2639 if (hw
->mac
.type
>= e1000_pchlan
)
2640 reg
|= E1000_CTRL_EXT_PHYPDEN
;
2641 ew32(CTRL_EXT
, reg
);
2643 /* Transmit Descriptor Control 0 */
2644 reg
= er32(TXDCTL(0));
2646 ew32(TXDCTL(0), reg
);
2648 /* Transmit Descriptor Control 1 */
2649 reg
= er32(TXDCTL(1));
2651 ew32(TXDCTL(1), reg
);
2653 /* Transmit Arbitration Control 0 */
2654 reg
= er32(TARC(0));
2655 if (hw
->mac
.type
== e1000_ich8lan
)
2656 reg
|= (1 << 28) | (1 << 29);
2657 reg
|= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2660 /* Transmit Arbitration Control 1 */
2661 reg
= er32(TARC(1));
2662 if (er32(TCTL
) & E1000_TCTL_MULR
)
2666 reg
|= (1 << 24) | (1 << 26) | (1 << 30);
2670 if (hw
->mac
.type
== e1000_ich8lan
) {
2678 * e1000_setup_link_ich8lan - Setup flow control and link settings
2679 * @hw: pointer to the HW structure
2681 * Determines which flow control settings to use, then configures flow
2682 * control. Calls the appropriate media-specific link configuration
2683 * function. Assuming the adapter has a valid link partner, a valid link
2684 * should be established. Assumes the hardware has previously been reset
2685 * and the transmitter and receiver are not enabled.
2687 static s32
e1000_setup_link_ich8lan(struct e1000_hw
*hw
)
2691 if (e1000_check_reset_block(hw
))
2695 * ICH parts do not have a word in the NVM to determine
2696 * the default flow control setting, so we explicitly
2699 if (hw
->fc
.requested_mode
== e1000_fc_default
) {
2700 /* Workaround h/w hang when Tx flow control enabled */
2701 if (hw
->mac
.type
== e1000_pchlan
)
2702 hw
->fc
.requested_mode
= e1000_fc_rx_pause
;
2704 hw
->fc
.requested_mode
= e1000_fc_full
;
2708 * Save off the requested flow control mode for use later. Depending
2709 * on the link partner's capabilities, we may or may not use this mode.
2711 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
2713 e_dbg("After fix-ups FlowControl is now = %x\n",
2714 hw
->fc
.current_mode
);
2716 /* Continue to configure the copper link. */
2717 ret_val
= e1000_setup_copper_link_ich8lan(hw
);
2721 ew32(FCTTV
, hw
->fc
.pause_time
);
2722 if ((hw
->phy
.type
== e1000_phy_82578
) ||
2723 (hw
->phy
.type
== e1000_phy_82577
)) {
2724 ret_val
= hw
->phy
.ops
.write_reg(hw
,
2725 PHY_REG(BM_PORT_CTRL_PAGE
, 27),
2731 return e1000e_set_fc_watermarks(hw
);
2735 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2736 * @hw: pointer to the HW structure
2738 * Configures the kumeran interface to the PHY to wait the appropriate time
2739 * when polling the PHY, then call the generic setup_copper_link to finish
2740 * configuring the copper link.
2742 static s32
e1000_setup_copper_link_ich8lan(struct e1000_hw
*hw
)
2749 ctrl
|= E1000_CTRL_SLU
;
2750 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
2754 * Set the mac to wait the maximum time between each iteration
2755 * and increase the max iterations when polling the phy;
2756 * this fixes erroneous timeouts at 10Mbps.
2758 ret_val
= e1000e_write_kmrn_reg(hw
, GG82563_REG(0x34, 4), 0xFFFF);
2761 ret_val
= e1000e_read_kmrn_reg(hw
, GG82563_REG(0x34, 9), ®_data
);
2765 ret_val
= e1000e_write_kmrn_reg(hw
, GG82563_REG(0x34, 9), reg_data
);
2769 switch (hw
->phy
.type
) {
2770 case e1000_phy_igp_3
:
2771 ret_val
= e1000e_copper_link_setup_igp(hw
);
2776 case e1000_phy_82578
:
2777 ret_val
= e1000e_copper_link_setup_m88(hw
);
2781 case e1000_phy_82577
:
2782 ret_val
= e1000_copper_link_setup_82577(hw
);
2787 ret_val
= hw
->phy
.ops
.read_reg(hw
, IFE_PHY_MDIX_CONTROL
,
2792 reg_data
&= ~IFE_PMC_AUTO_MDIX
;
2794 switch (hw
->phy
.mdix
) {
2796 reg_data
&= ~IFE_PMC_FORCE_MDIX
;
2799 reg_data
|= IFE_PMC_FORCE_MDIX
;
2803 reg_data
|= IFE_PMC_AUTO_MDIX
;
2806 ret_val
= hw
->phy
.ops
.write_reg(hw
, IFE_PHY_MDIX_CONTROL
,
2814 return e1000e_setup_copper_link(hw
);
2818 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2819 * @hw: pointer to the HW structure
2820 * @speed: pointer to store current link speed
2821 * @duplex: pointer to store the current link duplex
2823 * Calls the generic get_speed_and_duplex to retrieve the current link
2824 * information and then calls the Kumeran lock loss workaround for links at
2827 static s32
e1000_get_link_up_info_ich8lan(struct e1000_hw
*hw
, u16
*speed
,
2832 ret_val
= e1000e_get_speed_and_duplex_copper(hw
, speed
, duplex
);
2836 if ((hw
->mac
.type
== e1000_ich8lan
) &&
2837 (hw
->phy
.type
== e1000_phy_igp_3
) &&
2838 (*speed
== SPEED_1000
)) {
2839 ret_val
= e1000_kmrn_lock_loss_workaround_ich8lan(hw
);
2846 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2847 * @hw: pointer to the HW structure
2849 * Work-around for 82566 Kumeran PCS lock loss:
2850 * On link status change (i.e. PCI reset, speed change) and link is up and
2852 * 0) if workaround is optionally disabled do nothing
2853 * 1) wait 1ms for Kumeran link to come up
2854 * 2) check Kumeran Diagnostic register PCS lock loss bit
2855 * 3) if not set the link is locked (all is good), otherwise...
2857 * 5) repeat up to 10 times
2858 * Note: this is only called for IGP3 copper when speed is 1gb.
2860 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
)
2862 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2868 if (!dev_spec
->kmrn_lock_loss_workaround_enabled
)
2872 * Make sure link is up before proceeding. If not just return.
2873 * Attempting this while link is negotiating fouled up link
2876 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
2880 for (i
= 0; i
< 10; i
++) {
2881 /* read once to clear */
2882 ret_val
= e1e_rphy(hw
, IGP3_KMRN_DIAG
, &data
);
2885 /* and again to get new status */
2886 ret_val
= e1e_rphy(hw
, IGP3_KMRN_DIAG
, &data
);
2890 /* check for PCS lock */
2891 if (!(data
& IGP3_KMRN_DIAG_PCS_LOCK_LOSS
))
2894 /* Issue PHY reset */
2895 e1000_phy_hw_reset(hw
);
2898 /* Disable GigE link negotiation */
2899 phy_ctrl
= er32(PHY_CTRL
);
2900 phy_ctrl
|= (E1000_PHY_CTRL_GBE_DISABLE
|
2901 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
);
2902 ew32(PHY_CTRL
, phy_ctrl
);
2905 * Call gig speed drop workaround on Gig disable before accessing
2908 e1000e_gig_downshift_workaround_ich8lan(hw
);
2910 /* unable to acquire PCS lock */
2911 return -E1000_ERR_PHY
;
2915 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2916 * @hw: pointer to the HW structure
2917 * @state: boolean value used to set the current Kumeran workaround state
2919 * If ICH8, set the current Kumeran workaround state (enabled - true
2920 * /disabled - false).
2922 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
,
2925 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2927 if (hw
->mac
.type
!= e1000_ich8lan
) {
2928 e_dbg("Workaround applies to ICH8 only.\n");
2932 dev_spec
->kmrn_lock_loss_workaround_enabled
= state
;
2936 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2937 * @hw: pointer to the HW structure
2939 * Workaround for 82566 power-down on D3 entry:
2940 * 1) disable gigabit link
2941 * 2) write VR power-down enable
2943 * Continue if successful, else issue LCD reset and repeat
2945 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw
*hw
)
2951 if (hw
->phy
.type
!= e1000_phy_igp_3
)
2954 /* Try the workaround twice (if needed) */
2957 reg
= er32(PHY_CTRL
);
2958 reg
|= (E1000_PHY_CTRL_GBE_DISABLE
|
2959 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
);
2960 ew32(PHY_CTRL
, reg
);
2963 * Call gig speed drop workaround on Gig disable before
2964 * accessing any PHY registers
2966 if (hw
->mac
.type
== e1000_ich8lan
)
2967 e1000e_gig_downshift_workaround_ich8lan(hw
);
2969 /* Write VR power-down enable */
2970 e1e_rphy(hw
, IGP3_VR_CTRL
, &data
);
2971 data
&= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
;
2972 e1e_wphy(hw
, IGP3_VR_CTRL
, data
| IGP3_VR_CTRL_MODE_SHUTDOWN
);
2974 /* Read it back and test */
2975 e1e_rphy(hw
, IGP3_VR_CTRL
, &data
);
2976 data
&= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
;
2977 if ((data
== IGP3_VR_CTRL_MODE_SHUTDOWN
) || retry
)
2980 /* Issue PHY reset and repeat at most one more time */
2982 ew32(CTRL
, reg
| E1000_CTRL_PHY_RST
);
2988 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2989 * @hw: pointer to the HW structure
2991 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2992 * LPLU, Gig disable, MDIC PHY reset):
2993 * 1) Set Kumeran Near-end loopback
2994 * 2) Clear Kumeran Near-end loopback
2995 * Should only be called for ICH8[m] devices with IGP_3 Phy.
2997 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw
*hw
)
3002 if ((hw
->mac
.type
!= e1000_ich8lan
) ||
3003 (hw
->phy
.type
!= e1000_phy_igp_3
))
3006 ret_val
= e1000e_read_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
3010 reg_data
|= E1000_KMRNCTRLSTA_DIAG_NELPBK
;
3011 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
3015 reg_data
&= ~E1000_KMRNCTRLSTA_DIAG_NELPBK
;
3016 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
3021 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3022 * @hw: pointer to the HW structure
3024 * During S0 to Sx transition, it is possible the link remains at gig
3025 * instead of negotiating to a lower speed. Before going to Sx, set
3026 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3029 * Should only be called for applicable parts.
3031 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw
*hw
)
3035 switch (hw
->mac
.type
) {
3038 case e1000_ich10lan
:
3040 phy_ctrl
= er32(PHY_CTRL
);
3041 phy_ctrl
|= E1000_PHY_CTRL_D0A_LPLU
|
3042 E1000_PHY_CTRL_GBE_DISABLE
;
3043 ew32(PHY_CTRL
, phy_ctrl
);
3045 if (hw
->mac
.type
== e1000_pchlan
)
3046 e1000_phy_hw_reset_ich8lan(hw
);
3055 * e1000_cleanup_led_ich8lan - Restore the default LED operation
3056 * @hw: pointer to the HW structure
3058 * Return the LED back to the default configuration.
3060 static s32
e1000_cleanup_led_ich8lan(struct e1000_hw
*hw
)
3062 if (hw
->phy
.type
== e1000_phy_ife
)
3063 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
, 0);
3065 ew32(LEDCTL
, hw
->mac
.ledctl_default
);
3070 * e1000_led_on_ich8lan - Turn LEDs on
3071 * @hw: pointer to the HW structure
3075 static s32
e1000_led_on_ich8lan(struct e1000_hw
*hw
)
3077 if (hw
->phy
.type
== e1000_phy_ife
)
3078 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
,
3079 (IFE_PSCL_PROBE_MODE
| IFE_PSCL_PROBE_LEDS_ON
));
3081 ew32(LEDCTL
, hw
->mac
.ledctl_mode2
);
3086 * e1000_led_off_ich8lan - Turn LEDs off
3087 * @hw: pointer to the HW structure
3089 * Turn off the LEDs.
3091 static s32
e1000_led_off_ich8lan(struct e1000_hw
*hw
)
3093 if (hw
->phy
.type
== e1000_phy_ife
)
3094 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
,
3095 (IFE_PSCL_PROBE_MODE
| IFE_PSCL_PROBE_LEDS_OFF
));
3097 ew32(LEDCTL
, hw
->mac
.ledctl_mode1
);
3102 * e1000_setup_led_pchlan - Configures SW controllable LED
3103 * @hw: pointer to the HW structure
3105 * This prepares the SW controllable LED for use.
3107 static s32
e1000_setup_led_pchlan(struct e1000_hw
*hw
)
3109 return hw
->phy
.ops
.write_reg(hw
, HV_LED_CONFIG
,
3110 (u16
)hw
->mac
.ledctl_mode1
);
3114 * e1000_cleanup_led_pchlan - Restore the default LED operation
3115 * @hw: pointer to the HW structure
3117 * Return the LED back to the default configuration.
3119 static s32
e1000_cleanup_led_pchlan(struct e1000_hw
*hw
)
3121 return hw
->phy
.ops
.write_reg(hw
, HV_LED_CONFIG
,
3122 (u16
)hw
->mac
.ledctl_default
);
3126 * e1000_led_on_pchlan - Turn LEDs on
3127 * @hw: pointer to the HW structure
3131 static s32
e1000_led_on_pchlan(struct e1000_hw
*hw
)
3133 u16 data
= (u16
)hw
->mac
.ledctl_mode2
;
3137 * If no link, then turn LED on by setting the invert bit
3138 * for each LED that's mode is "link_up" in ledctl_mode2.
3140 if (!(er32(STATUS
) & E1000_STATUS_LU
)) {
3141 for (i
= 0; i
< 3; i
++) {
3142 led
= (data
>> (i
* 5)) & E1000_PHY_LED0_MASK
;
3143 if ((led
& E1000_PHY_LED0_MODE_MASK
) !=
3144 E1000_LEDCTL_MODE_LINK_UP
)
3146 if (led
& E1000_PHY_LED0_IVRT
)
3147 data
&= ~(E1000_PHY_LED0_IVRT
<< (i
* 5));
3149 data
|= (E1000_PHY_LED0_IVRT
<< (i
* 5));
3153 return hw
->phy
.ops
.write_reg(hw
, HV_LED_CONFIG
, data
);
3157 * e1000_led_off_pchlan - Turn LEDs off
3158 * @hw: pointer to the HW structure
3160 * Turn off the LEDs.
3162 static s32
e1000_led_off_pchlan(struct e1000_hw
*hw
)
3164 u16 data
= (u16
)hw
->mac
.ledctl_mode1
;
3168 * If no link, then turn LED off by clearing the invert bit
3169 * for each LED that's mode is "link_up" in ledctl_mode1.
3171 if (!(er32(STATUS
) & E1000_STATUS_LU
)) {
3172 for (i
= 0; i
< 3; i
++) {
3173 led
= (data
>> (i
* 5)) & E1000_PHY_LED0_MASK
;
3174 if ((led
& E1000_PHY_LED0_MODE_MASK
) !=
3175 E1000_LEDCTL_MODE_LINK_UP
)
3177 if (led
& E1000_PHY_LED0_IVRT
)
3178 data
&= ~(E1000_PHY_LED0_IVRT
<< (i
* 5));
3180 data
|= (E1000_PHY_LED0_IVRT
<< (i
* 5));
3184 return hw
->phy
.ops
.write_reg(hw
, HV_LED_CONFIG
, data
);
3188 * e1000_get_cfg_done_ich8lan - Read config done bit
3189 * @hw: pointer to the HW structure
3191 * Read the management control register for the config done bit for
3192 * completion status. NOTE: silicon which is EEPROM-less will fail trying
3193 * to read the config done bit, so an error is *ONLY* logged and returns
3194 * 0. If we were to return with error, EEPROM-less silicon
3195 * would not be able to be reset or change link.
3197 static s32
e1000_get_cfg_done_ich8lan(struct e1000_hw
*hw
)
3201 if (hw
->mac
.type
>= e1000_pchlan
) {
3202 u32 status
= er32(STATUS
);
3204 if (status
& E1000_STATUS_PHYRA
)
3205 ew32(STATUS
, status
& ~E1000_STATUS_PHYRA
);
3207 e_dbg("PHY Reset Asserted not set - needs delay\n");
3210 e1000e_get_cfg_done(hw
);
3212 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3213 if ((hw
->mac
.type
!= e1000_ich10lan
) &&
3214 (hw
->mac
.type
!= e1000_pchlan
)) {
3215 if (((er32(EECD
) & E1000_EECD_PRES
) == 0) &&
3216 (hw
->phy
.type
== e1000_phy_igp_3
)) {
3217 e1000e_phy_init_script_igp3(hw
);
3220 if (e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
)) {
3221 /* Maybe we should do a basic PHY config */
3222 e_dbg("EEPROM not present\n");
3223 return -E1000_ERR_CONFIG
;
3231 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3232 * @hw: pointer to the HW structure
3234 * In the case of a PHY power down to save power, or to turn off link during a
3235 * driver unload, or wake on lan is not enabled, remove the link.
3237 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw
*hw
)
3239 /* If the management interface is not enabled, then power down */
3240 if (!(hw
->mac
.ops
.check_mng_mode(hw
) ||
3241 hw
->phy
.ops
.check_reset_block(hw
)))
3242 e1000_power_down_phy_copper(hw
);
3248 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3249 * @hw: pointer to the HW structure
3251 * Clears hardware counters specific to the silicon family and calls
3252 * clear_hw_cntrs_generic to clear all general purpose counters.
3254 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw
*hw
)
3258 e1000e_clear_hw_cntrs_base(hw
);
3274 /* Clear PHY statistics registers */
3275 if ((hw
->phy
.type
== e1000_phy_82578
) ||
3276 (hw
->phy
.type
== e1000_phy_82577
)) {
3277 hw
->phy
.ops
.read_reg(hw
, HV_SCC_UPPER
, &phy_data
);
3278 hw
->phy
.ops
.read_reg(hw
, HV_SCC_LOWER
, &phy_data
);
3279 hw
->phy
.ops
.read_reg(hw
, HV_ECOL_UPPER
, &phy_data
);
3280 hw
->phy
.ops
.read_reg(hw
, HV_ECOL_LOWER
, &phy_data
);
3281 hw
->phy
.ops
.read_reg(hw
, HV_MCC_UPPER
, &phy_data
);
3282 hw
->phy
.ops
.read_reg(hw
, HV_MCC_LOWER
, &phy_data
);
3283 hw
->phy
.ops
.read_reg(hw
, HV_LATECOL_UPPER
, &phy_data
);
3284 hw
->phy
.ops
.read_reg(hw
, HV_LATECOL_LOWER
, &phy_data
);
3285 hw
->phy
.ops
.read_reg(hw
, HV_COLC_UPPER
, &phy_data
);
3286 hw
->phy
.ops
.read_reg(hw
, HV_COLC_LOWER
, &phy_data
);
3287 hw
->phy
.ops
.read_reg(hw
, HV_DC_UPPER
, &phy_data
);
3288 hw
->phy
.ops
.read_reg(hw
, HV_DC_LOWER
, &phy_data
);
3289 hw
->phy
.ops
.read_reg(hw
, HV_TNCRS_UPPER
, &phy_data
);
3290 hw
->phy
.ops
.read_reg(hw
, HV_TNCRS_LOWER
, &phy_data
);
3294 static struct e1000_mac_operations ich8_mac_ops
= {
3295 .id_led_init
= e1000e_id_led_init
,
3296 .check_mng_mode
= e1000_check_mng_mode_ich8lan
,
3297 .check_for_link
= e1000_check_for_copper_link_ich8lan
,
3298 /* cleanup_led dependent on mac type */
3299 .clear_hw_cntrs
= e1000_clear_hw_cntrs_ich8lan
,
3300 .get_bus_info
= e1000_get_bus_info_ich8lan
,
3301 .get_link_up_info
= e1000_get_link_up_info_ich8lan
,
3302 /* led_on dependent on mac type */
3303 /* led_off dependent on mac type */
3304 .update_mc_addr_list
= e1000e_update_mc_addr_list_generic
,
3305 .reset_hw
= e1000_reset_hw_ich8lan
,
3306 .init_hw
= e1000_init_hw_ich8lan
,
3307 .setup_link
= e1000_setup_link_ich8lan
,
3308 .setup_physical_interface
= e1000_setup_copper_link_ich8lan
,
3309 /* id_led_init dependent on mac type */
3312 static struct e1000_phy_operations ich8_phy_ops
= {
3313 .acquire
= e1000_acquire_swflag_ich8lan
,
3314 .check_reset_block
= e1000_check_reset_block_ich8lan
,
3316 .get_cfg_done
= e1000_get_cfg_done_ich8lan
,
3317 .get_cable_length
= e1000e_get_cable_length_igp_2
,
3318 .read_reg
= e1000e_read_phy_reg_igp
,
3319 .release
= e1000_release_swflag_ich8lan
,
3320 .reset
= e1000_phy_hw_reset_ich8lan
,
3321 .set_d0_lplu_state
= e1000_set_d0_lplu_state_ich8lan
,
3322 .set_d3_lplu_state
= e1000_set_d3_lplu_state_ich8lan
,
3323 .write_reg
= e1000e_write_phy_reg_igp
,
3326 static struct e1000_nvm_operations ich8_nvm_ops
= {
3327 .acquire
= e1000_acquire_nvm_ich8lan
,
3328 .read
= e1000_read_nvm_ich8lan
,
3329 .release
= e1000_release_nvm_ich8lan
,
3330 .update
= e1000_update_nvm_checksum_ich8lan
,
3331 .valid_led_default
= e1000_valid_led_default_ich8lan
,
3332 .validate
= e1000_validate_nvm_checksum_ich8lan
,
3333 .write
= e1000_write_nvm_ich8lan
,
3336 struct e1000_info e1000_ich8_info
= {
3337 .mac
= e1000_ich8lan
,
3338 .flags
= FLAG_HAS_WOL
3340 | FLAG_RX_CSUM_ENABLED
3341 | FLAG_HAS_CTRLEXT_ON_LOAD
3346 .max_hw_frame_size
= ETH_FRAME_LEN
+ ETH_FCS_LEN
,
3347 .get_variants
= e1000_get_variants_ich8lan
,
3348 .mac_ops
= &ich8_mac_ops
,
3349 .phy_ops
= &ich8_phy_ops
,
3350 .nvm_ops
= &ich8_nvm_ops
,
3353 struct e1000_info e1000_ich9_info
= {
3354 .mac
= e1000_ich9lan
,
3355 .flags
= FLAG_HAS_JUMBO_FRAMES
3358 | FLAG_RX_CSUM_ENABLED
3359 | FLAG_HAS_CTRLEXT_ON_LOAD
3365 .max_hw_frame_size
= DEFAULT_JUMBO
,
3366 .get_variants
= e1000_get_variants_ich8lan
,
3367 .mac_ops
= &ich8_mac_ops
,
3368 .phy_ops
= &ich8_phy_ops
,
3369 .nvm_ops
= &ich8_nvm_ops
,
3372 struct e1000_info e1000_ich10_info
= {
3373 .mac
= e1000_ich10lan
,
3374 .flags
= FLAG_HAS_JUMBO_FRAMES
3377 | FLAG_RX_CSUM_ENABLED
3378 | FLAG_HAS_CTRLEXT_ON_LOAD
3384 .max_hw_frame_size
= DEFAULT_JUMBO
,
3385 .get_variants
= e1000_get_variants_ich8lan
,
3386 .mac_ops
= &ich8_mac_ops
,
3387 .phy_ops
= &ich8_phy_ops
,
3388 .nvm_ops
= &ich8_nvm_ops
,
3391 struct e1000_info e1000_pch_info
= {
3392 .mac
= e1000_pchlan
,
3393 .flags
= FLAG_IS_ICH
3395 | FLAG_RX_CSUM_ENABLED
3396 | FLAG_HAS_CTRLEXT_ON_LOAD
3399 | FLAG_HAS_JUMBO_FRAMES
3400 | FLAG_DISABLE_FC_PAUSE_TIME
/* errata */
3403 .max_hw_frame_size
= 4096,
3404 .get_variants
= e1000_get_variants_ich8lan
,
3405 .mac_ops
= &ich8_mac_ops
,
3406 .phy_ops
= &ich8_phy_ops
,
3407 .nvm_ops
= &ich8_nvm_ops
,