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ASoC: McASP: add support for clock dividers
[linux-2.6/btrfs-unstable.git] / sound / soc / davinci / davinci-mcasp.c
blob9b1920e255649b9c3cf66b4d1b1f7b59ffe00a46
1 /*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/io.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/of.h>
26 #include <linux/of_platform.h>
27 #include <linux/of_device.h>
28
29 #include <sound/core.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/initval.h>
33 #include <sound/soc.h>
34
35 #include "davinci-pcm.h"
36 #include "davinci-mcasp.h"
37
38 /*
39 * McASP register definitions
40 */
41 #define DAVINCI_MCASP_PID_REG 0x00
42 #define DAVINCI_MCASP_PWREMUMGT_REG 0x04
43
44 #define DAVINCI_MCASP_PFUNC_REG 0x10
45 #define DAVINCI_MCASP_PDIR_REG 0x14
46 #define DAVINCI_MCASP_PDOUT_REG 0x18
47 #define DAVINCI_MCASP_PDSET_REG 0x1c
48
49 #define DAVINCI_MCASP_PDCLR_REG 0x20
50
51 #define DAVINCI_MCASP_TLGC_REG 0x30
52 #define DAVINCI_MCASP_TLMR_REG 0x34
53
54 #define DAVINCI_MCASP_GBLCTL_REG 0x44
55 #define DAVINCI_MCASP_AMUTE_REG 0x48
56 #define DAVINCI_MCASP_LBCTL_REG 0x4c
57
58 #define DAVINCI_MCASP_TXDITCTL_REG 0x50
59
60 #define DAVINCI_MCASP_GBLCTLR_REG 0x60
61 #define DAVINCI_MCASP_RXMASK_REG 0x64
62 #define DAVINCI_MCASP_RXFMT_REG 0x68
63 #define DAVINCI_MCASP_RXFMCTL_REG 0x6c
64
65 #define DAVINCI_MCASP_ACLKRCTL_REG 0x70
66 #define DAVINCI_MCASP_AHCLKRCTL_REG 0x74
67 #define DAVINCI_MCASP_RXTDM_REG 0x78
68 #define DAVINCI_MCASP_EVTCTLR_REG 0x7c
69
70 #define DAVINCI_MCASP_RXSTAT_REG 0x80
71 #define DAVINCI_MCASP_RXTDMSLOT_REG 0x84
72 #define DAVINCI_MCASP_RXCLKCHK_REG 0x88
73 #define DAVINCI_MCASP_REVTCTL_REG 0x8c
74
75 #define DAVINCI_MCASP_GBLCTLX_REG 0xa0
76 #define DAVINCI_MCASP_TXMASK_REG 0xa4
77 #define DAVINCI_MCASP_TXFMT_REG 0xa8
78 #define DAVINCI_MCASP_TXFMCTL_REG 0xac
79
80 #define DAVINCI_MCASP_ACLKXCTL_REG 0xb0
81 #define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4
82 #define DAVINCI_MCASP_TXTDM_REG 0xb8
83 #define DAVINCI_MCASP_EVTCTLX_REG 0xbc
84
85 #define DAVINCI_MCASP_TXSTAT_REG 0xc0
86 #define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4
87 #define DAVINCI_MCASP_TXCLKCHK_REG 0xc8
88 #define DAVINCI_MCASP_XEVTCTL_REG 0xcc
89
90 /* Left(even TDM Slot) Channel Status Register File */
91 #define DAVINCI_MCASP_DITCSRA_REG 0x100
92 /* Right(odd TDM slot) Channel Status Register File */
93 #define DAVINCI_MCASP_DITCSRB_REG 0x118
94 /* Left(even TDM slot) User Data Register File */
95 #define DAVINCI_MCASP_DITUDRA_REG 0x130
96 /* Right(odd TDM Slot) User Data Register File */
97 #define DAVINCI_MCASP_DITUDRB_REG 0x148
98
99 /* Serializer n Control Register */
100 #define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180
101 #define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
102 (n << 2))
103
104 /* Transmit Buffer for Serializer n */
105 #define DAVINCI_MCASP_TXBUF_REG 0x200
106 /* Receive Buffer for Serializer n */
107 #define DAVINCI_MCASP_RXBUF_REG 0x280
108
109 /* McASP FIFO Registers */
110 #define DAVINCI_MCASP_WFIFOCTL (0x1010)
111 #define DAVINCI_MCASP_WFIFOSTS (0x1014)
112 #define DAVINCI_MCASP_RFIFOCTL (0x1018)
113 #define DAVINCI_MCASP_RFIFOSTS (0x101C)
114 #define MCASP_VER3_WFIFOCTL (0x1000)
115 #define MCASP_VER3_WFIFOSTS (0x1004)
116 #define MCASP_VER3_RFIFOCTL (0x1008)
117 #define MCASP_VER3_RFIFOSTS (0x100C)
118
119 /*
120 * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
121 * Register Bits
122 */
123 #define MCASP_FREE BIT(0)
124 #define MCASP_SOFT BIT(1)
125
126 /*
127 * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
128 */
129 #define AXR(n) (1<<n)
130 #define PFUNC_AMUTE BIT(25)
131 #define ACLKX BIT(26)
132 #define AHCLKX BIT(27)
133 #define AFSX BIT(28)
134 #define ACLKR BIT(29)
135 #define AHCLKR BIT(30)
136 #define AFSR BIT(31)
137
138 /*
139 * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
140 */
141 #define AXR(n) (1<<n)
142 #define PDIR_AMUTE BIT(25)
143 #define ACLKX BIT(26)
144 #define AHCLKX BIT(27)
145 #define AFSX BIT(28)
146 #define ACLKR BIT(29)
147 #define AHCLKR BIT(30)
148 #define AFSR BIT(31)
149
150 /*
151 * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
152 */
153 #define DITEN BIT(0) /* Transmit DIT mode enable/disable */
154 #define VA BIT(2)
155 #define VB BIT(3)
156
157 /*
158 * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
159 */
160 #define TXROT(val) (val)
161 #define TXSEL BIT(3)
162 #define TXSSZ(val) (val<<4)
163 #define TXPBIT(val) (val<<8)
164 #define TXPAD(val) (val<<13)
165 #define TXORD BIT(15)
166 #define FSXDLY(val) (val<<16)
167
168 /*
169 * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
170 */
171 #define RXROT(val) (val)
172 #define RXSEL BIT(3)
173 #define RXSSZ(val) (val<<4)
174 #define RXPBIT(val) (val<<8)
175 #define RXPAD(val) (val<<13)
176 #define RXORD BIT(15)
177 #define FSRDLY(val) (val<<16)
178
179 /*
180 * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
181 */
182 #define FSXPOL BIT(0)
183 #define AFSXE BIT(1)
184 #define FSXDUR BIT(4)
185 #define FSXMOD(val) (val<<7)
186
187 /*
188 * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
189 */
190 #define FSRPOL BIT(0)
191 #define AFSRE BIT(1)
192 #define FSRDUR BIT(4)
193 #define FSRMOD(val) (val<<7)
194
195 /*
196 * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
197 */
198 #define ACLKXDIV(val) (val)
199 #define ACLKXE BIT(5)
200 #define TX_ASYNC BIT(6)
201 #define ACLKXPOL BIT(7)
202 #define ACLKXDIV_MASK 0x1f
203
204 /*
205 * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
206 */
207 #define ACLKRDIV(val) (val)
208 #define ACLKRE BIT(5)
209 #define RX_ASYNC BIT(6)
210 #define ACLKRPOL BIT(7)
211 #define ACLKRDIV_MASK 0x1f
212
213 /*
214 * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
215 * Register Bits
216 */
217 #define AHCLKXDIV(val) (val)
218 #define AHCLKXPOL BIT(14)
219 #define AHCLKXE BIT(15)
220 #define AHCLKXDIV_MASK 0xfff
221
222 /*
223 * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
224 * Register Bits
225 */
226 #define AHCLKRDIV(val) (val)
227 #define AHCLKRPOL BIT(14)
228 #define AHCLKRE BIT(15)
229 #define AHCLKRDIV_MASK 0xfff
230
231 /*
232 * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
233 */
234 #define MODE(val) (val)
235 #define DISMOD (val)(val<<2)
236 #define TXSTATE BIT(4)
237 #define RXSTATE BIT(5)
238
239 /*
240 * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
241 */
242 #define LBEN BIT(0)
243 #define LBORD BIT(1)
244 #define LBGENMODE(val) (val<<2)
245
246 /*
247 * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
248 */
249 #define TXTDMS(n) (1<<n)
250
251 /*
252 * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
253 */
254 #define RXTDMS(n) (1<<n)
255
256 /*
257 * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits
258 */
259 #define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
260 #define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
261 #define RXSERCLR BIT(2) /* Receiver Serializer Clear */
262 #define RXSMRST BIT(3) /* Receiver State Machine Reset */
263 #define RXFSRST BIT(4) /* Frame Sync Generator Reset */
264 #define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
265 #define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
266 #define TXSERCLR BIT(10) /* Transmit Serializer Clear */
267 #define TXSMRST BIT(11) /* Transmitter State Machine Reset */
268 #define TXFSRST BIT(12) /* Frame Sync Generator Reset */
269
270 /*
271 * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
272 */
273 #define MUTENA(val) (val)
274 #define MUTEINPOL BIT(2)
275 #define MUTEINENA BIT(3)
276 #define MUTEIN BIT(4)
277 #define MUTER BIT(5)
278 #define MUTEX BIT(6)
279 #define MUTEFSR BIT(7)
280 #define MUTEFSX BIT(8)
281 #define MUTEBADCLKR BIT(9)
282 #define MUTEBADCLKX BIT(10)
283 #define MUTERXDMAERR BIT(11)
284 #define MUTETXDMAERR BIT(12)
285
286 /*
287 * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
288 */
289 #define RXDATADMADIS BIT(0)
290
291 /*
292 * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
293 */
294 #define TXDATADMADIS BIT(0)
295
296 /*
297 * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
298 */
299 #define FIFO_ENABLE BIT(16)
300 #define NUMEVT_MASK (0xFF << 8)
301 #define NUMDMA_MASK (0xFF)
302
303 #define DAVINCI_MCASP_NUM_SERIALIZER 16
304
305 static inline void mcasp_set_bits(void __iomem *reg, u32 val)
306 {
307 __raw_writel(__raw_readl(reg) | val, reg);
308 }
309
310 static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
311 {
312 __raw_writel((__raw_readl(reg) & ~(val)), reg);
313 }
314
315 static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
316 {
317 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
318 }
319
320 static inline void mcasp_set_reg(void __iomem *reg, u32 val)
321 {
322 __raw_writel(val, reg);
323 }
324
325 static inline u32 mcasp_get_reg(void __iomem *reg)
326 {
327 return (unsigned int)__raw_readl(reg);
328 }
329
330 static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
331 {
332 int i = 0;
333
334 mcasp_set_bits(regs, val);
335
336 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
337 /* loop count is to avoid the lock-up */
338 for (i = 0; i < 1000; i++) {
339 if ((mcasp_get_reg(regs) & val) == val)
340 break;
341 }
342
343 if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
344 printk(KERN_ERR "GBLCTL write error\n");
345 }
346
347 static void mcasp_start_rx(struct davinci_audio_dev *dev)
348 {
349 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
350 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
351 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
352 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
353
354 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
355 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
356 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
357
358 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
359 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
360 }
361
362 static void mcasp_start_tx(struct davinci_audio_dev *dev)
363 {
364 u8 offset = 0, i;
365 u32 cnt;
366
367 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
368 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
369 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
370 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
371
372 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
373 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
374 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
375 for (i = 0; i < dev->num_serializer; i++) {
376 if (dev->serial_dir[i] == TX_MODE) {
377 offset = i;
378 break;
379 }
380 }
381
382 /* wait for TX ready */
383 cnt = 0;
384 while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
385 TXSTATE) && (cnt < 100000))
386 cnt++;
387
388 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
389 }
390
391 static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
392 {
393 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
394 if (dev->txnumevt) { /* enable FIFO */
395 switch (dev->version) {
396 case MCASP_VERSION_3:
397 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
398 FIFO_ENABLE);
399 mcasp_set_bits(dev->base + MCASP_VER3_WFIFOCTL,
400 FIFO_ENABLE);
401 break;
402 default:
403 mcasp_clr_bits(dev->base +
404 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
405 mcasp_set_bits(dev->base +
406 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
407 }
408 }
409 mcasp_start_tx(dev);
410 } else {
411 if (dev->rxnumevt) { /* enable FIFO */
412 switch (dev->version) {
413 case MCASP_VERSION_3:
414 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
415 FIFO_ENABLE);
416 mcasp_set_bits(dev->base + MCASP_VER3_RFIFOCTL,
417 FIFO_ENABLE);
418 break;
419 default:
420 mcasp_clr_bits(dev->base +
421 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
422 mcasp_set_bits(dev->base +
423 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
424 }
425 }
426 mcasp_start_rx(dev);
427 }
428 }
429
430 static void mcasp_stop_rx(struct davinci_audio_dev *dev)
431 {
432 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
433 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
434 }
435
436 static void mcasp_stop_tx(struct davinci_audio_dev *dev)
437 {
438 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
439 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
440 }
441
442 static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
443 {
444 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
445 if (dev->txnumevt) { /* disable FIFO */
446 switch (dev->version) {
447 case MCASP_VERSION_3:
448 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
449 FIFO_ENABLE);
450 break;
451 default:
452 mcasp_clr_bits(dev->base +
453 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
454 }
455 }
456 mcasp_stop_tx(dev);
457 } else {
458 if (dev->rxnumevt) { /* disable FIFO */
459 switch (dev->version) {
460 case MCASP_VERSION_3:
461 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
462 FIFO_ENABLE);
463 break;
464
465 default:
466 mcasp_clr_bits(dev->base +
467 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
468 }
469 }
470 mcasp_stop_rx(dev);
471 }
472 }
473
474 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
475 unsigned int fmt)
476 {
477 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
478 void __iomem *base = dev->base;
479
480 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
481 case SND_SOC_DAIFMT_CBS_CFS:
482 /* codec is clock and frame slave */
483 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
484 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
485
486 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
487 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
488
489 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
490 ACLKX | AHCLKX | AFSX);
491 break;
492 case SND_SOC_DAIFMT_CBM_CFS:
493 /* codec is clock master and frame slave */
494 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
495 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
496
497 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
498 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
499
500 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
501 ACLKX | ACLKR);
502 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
503 AFSX | AFSR);
504 break;
505 case SND_SOC_DAIFMT_CBM_CFM:
506 /* codec is clock and frame master */
507 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
508 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
509
510 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
511 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
512
513 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
514 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
515 break;
516
517 default:
518 return -EINVAL;
519 }
520
521 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
522 case SND_SOC_DAIFMT_IB_NF:
523 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
524 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
525
526 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
527 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
528 break;
529
530 case SND_SOC_DAIFMT_NB_IF:
531 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
532 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
533
534 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
535 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
536 break;
537
538 case SND_SOC_DAIFMT_IB_IF:
539 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
540 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
541
542 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
543 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
544 break;
545
546 case SND_SOC_DAIFMT_NB_NF:
547 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
548 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
549
550 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
551 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
552 break;
553
554 default:
555 return -EINVAL;
556 }
557
558 return 0;
559 }
560
561 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
562 {
563 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
564
565 switch (div_id) {
566 case 0: /* MCLK divider */
567 mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
568 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
569 mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
570 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
571 break;
572
573 case 1: /* BCLK divider */
574 mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
575 ACLKXDIV(div - 1), ACLKXDIV_MASK);
576 mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKRCTL_REG,
577 ACLKRDIV(div - 1), ACLKRDIV_MASK);
578 break;
579
580 default:
581 return -EINVAL;
582 }
583
584 return 0;
585 }
586
587 static int davinci_config_channel_size(struct davinci_audio_dev *dev,
588 int channel_size)
589 {
590 u32 fmt = 0;
591 u32 mask, rotate;
592
593 switch (channel_size) {
594 case DAVINCI_AUDIO_WORD_8:
595 fmt = 0x03;
596 rotate = 6;
597 mask = 0x000000ff;
598 break;
599
600 case DAVINCI_AUDIO_WORD_12:
601 fmt = 0x05;
602 rotate = 5;
603 mask = 0x00000fff;
604 break;
605
606 case DAVINCI_AUDIO_WORD_16:
607 fmt = 0x07;
608 rotate = 4;
609 mask = 0x0000ffff;
610 break;
611
612 case DAVINCI_AUDIO_WORD_20:
613 fmt = 0x09;
614 rotate = 3;
615 mask = 0x000fffff;
616 break;
617
618 case DAVINCI_AUDIO_WORD_24:
619 fmt = 0x0B;
620 rotate = 2;
621 mask = 0x00ffffff;
622 break;
623
624 case DAVINCI_AUDIO_WORD_28:
625 fmt = 0x0D;
626 rotate = 1;
627 mask = 0x0fffffff;
628 break;
629
630 case DAVINCI_AUDIO_WORD_32:
631 fmt = 0x0F;
632 rotate = 0;
633 mask = 0xffffffff;
634 break;
635
636 default:
637 return -EINVAL;
638 }
639
640 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
641 RXSSZ(fmt), RXSSZ(0x0F));
642 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
643 TXSSZ(fmt), TXSSZ(0x0F));
644 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXROT(rotate),
645 TXROT(7));
646 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXROT(rotate),
647 RXROT(7));
648 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask);
649 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, mask);
650
651 return 0;
652 }
653
654 static void davinci_hw_common_param(struct davinci_audio_dev *dev, int stream)
655 {
656 int i;
657 u8 tx_ser = 0;
658 u8 rx_ser = 0;
659
660 /* Default configuration */
661 mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
662
663 /* All PINS as McASP */
664 mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
665
666 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
667 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
668 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG,
669 TXDATADMADIS);
670 } else {
671 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
672 mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG,
673 RXDATADMADIS);
674 }
675
676 for (i = 0; i < dev->num_serializer; i++) {
677 mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
678 dev->serial_dir[i]);
679 if (dev->serial_dir[i] == TX_MODE) {
680 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
681 AXR(i));
682 tx_ser++;
683 } else if (dev->serial_dir[i] == RX_MODE) {
684 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
685 AXR(i));
686 rx_ser++;
687 }
688 }
689
690 if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
691 if (dev->txnumevt * tx_ser > 64)
692 dev->txnumevt = 1;
693
694 switch (dev->version) {
695 case MCASP_VERSION_3:
696 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL, tx_ser,
697 NUMDMA_MASK);
698 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL,
699 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
700 break;
701 default:
702 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
703 tx_ser, NUMDMA_MASK);
704 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
705 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
706 }
707 }
708
709 if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
710 if (dev->rxnumevt * rx_ser > 64)
711 dev->rxnumevt = 1;
712 switch (dev->version) {
713 case MCASP_VERSION_3:
714 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL, rx_ser,
715 NUMDMA_MASK);
716 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL,
717 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
718 break;
719 default:
720 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
721 rx_ser, NUMDMA_MASK);
722 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
723 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
724 }
725 }
726 }
727
728 static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
729 {
730 int i, active_slots;
731 u32 mask = 0;
732
733 active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
734 for (i = 0; i < active_slots; i++)
735 mask |= (1 << i);
736
737 mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
738
739 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
740 /* bit stream is MSB first with no delay */
741 /* DSP_B mode */
742 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
743 AHCLKXE);
744 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
745 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
746
747 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
748 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
749 FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
750 else
751 printk(KERN_ERR "playback tdm slot %d not supported\n",
752 dev->tdm_slots);
753
754 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
755 } else {
756 /* bit stream is MSB first with no delay */
757 /* DSP_B mode */
758 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
759 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
760 AHCLKRE);
761 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
762
763 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
764 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
765 FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
766 else
767 printk(KERN_ERR "capture tdm slot %d not supported\n",
768 dev->tdm_slots);
769
770 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
771 }
772 }
773
774 /* S/PDIF */
775 static void davinci_hw_dit_param(struct davinci_audio_dev *dev)
776 {
777 /* Set the PDIR for Serialiser as output */
778 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AFSX);
779
780 /* TXMASK for 24 bits */
781 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0x00FFFFFF);
782
783 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
784 and LSB first */
785 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
786 TXROT(6) | TXSSZ(15));
787
788 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
789 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
790 AFSXE | FSXMOD(0x180));
791
792 /* Set the TX tdm : for all the slots */
793 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
794
795 /* Set the TX clock controls : div = 1 and internal */
796 mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
797 ACLKXE | TX_ASYNC);
798
799 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
800
801 /* Only 44100 and 48000 are valid, both have the same setting */
802 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
803
804 /* Enable the DIT */
805 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
806 }
807
808 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
809 struct snd_pcm_hw_params *params,
810 struct snd_soc_dai *cpu_dai)
811 {
812 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
813 struct davinci_pcm_dma_params *dma_params =
814 &dev->dma_params[substream->stream];
815 int word_length;
816 u8 fifo_level;
817
818 davinci_hw_common_param(dev, substream->stream);
819 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
820 fifo_level = dev->txnumevt;
821 else
822 fifo_level = dev->rxnumevt;
823
824 if (dev->op_mode == DAVINCI_MCASP_DIT_MODE)
825 davinci_hw_dit_param(dev);
826 else
827 davinci_hw_param(dev, substream->stream);
828
829 switch (params_format(params)) {
830 case SNDRV_PCM_FORMAT_U8:
831 case SNDRV_PCM_FORMAT_S8:
832 dma_params->data_type = 1;
833 word_length = DAVINCI_AUDIO_WORD_8;
834 break;
835
836 case SNDRV_PCM_FORMAT_U16_LE:
837 case SNDRV_PCM_FORMAT_S16_LE:
838 dma_params->data_type = 2;
839 word_length = DAVINCI_AUDIO_WORD_16;
840 break;
841
842 case SNDRV_PCM_FORMAT_U32_LE:
843 case SNDRV_PCM_FORMAT_S32_LE:
844 dma_params->data_type = 4;
845 word_length = DAVINCI_AUDIO_WORD_32;
846 break;
847
848 default:
849 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
850 return -EINVAL;
851 }
852
853 if (dev->version == MCASP_VERSION_2 && !fifo_level)
854 dma_params->acnt = 4;
855 else
856 dma_params->acnt = dma_params->data_type;
857
858 dma_params->fifo_level = fifo_level;
859 davinci_config_channel_size(dev, word_length);
860
861 return 0;
862 }
863
864 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
865 int cmd, struct snd_soc_dai *cpu_dai)
866 {
867 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
868 int ret = 0;
869
870 switch (cmd) {
871 case SNDRV_PCM_TRIGGER_RESUME:
872 case SNDRV_PCM_TRIGGER_START:
873 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
874 ret = pm_runtime_get_sync(dev->dev);
875 if (IS_ERR_VALUE(ret))
876 dev_err(dev->dev, "pm_runtime_get_sync() failed\n");
877 davinci_mcasp_start(dev, substream->stream);
878 break;
879
880 case SNDRV_PCM_TRIGGER_SUSPEND:
881 davinci_mcasp_stop(dev, substream->stream);
882 ret = pm_runtime_put_sync(dev->dev);
883 if (IS_ERR_VALUE(ret))
884 dev_err(dev->dev, "pm_runtime_put_sync() failed\n");
885 break;
886
887 case SNDRV_PCM_TRIGGER_STOP:
888 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
889 davinci_mcasp_stop(dev, substream->stream);
890 break;
891
892 default:
893 ret = -EINVAL;
894 }
895
896 return ret;
897 }
898
899 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
900 struct snd_soc_dai *dai)
901 {
902 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
903
904 snd_soc_dai_set_dma_data(dai, substream, dev->dma_params);
905 return 0;
906 }
907
908 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
909 .startup = davinci_mcasp_startup,
910 .trigger = davinci_mcasp_trigger,
911 .hw_params = davinci_mcasp_hw_params,
912 .set_fmt = davinci_mcasp_set_dai_fmt,
913 .set_clkdiv = davinci_mcasp_set_clkdiv,
914 };
915
916 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
917 SNDRV_PCM_FMTBIT_U8 | \
918 SNDRV_PCM_FMTBIT_S16_LE | \
919 SNDRV_PCM_FMTBIT_U16_LE | \
920 SNDRV_PCM_FMTBIT_S32_LE | \
921 SNDRV_PCM_FMTBIT_U32_LE)
922
923 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
924 {
925 .name = "davinci-mcasp.0",
926 .playback = {
927 .channels_min = 2,
928 .channels_max = 2,
929 .rates = DAVINCI_MCASP_RATES,
930 .formats = DAVINCI_MCASP_PCM_FMTS,
931 },
932 .capture = {
933 .channels_min = 2,
934 .channels_max = 2,
935 .rates = DAVINCI_MCASP_RATES,
936 .formats = DAVINCI_MCASP_PCM_FMTS,
937 },
938 .ops = &davinci_mcasp_dai_ops,
939
940 },
941 {
942 "davinci-mcasp.1",
943 .playback = {
944 .channels_min = 1,
945 .channels_max = 384,
946 .rates = DAVINCI_MCASP_RATES,
947 .formats = DAVINCI_MCASP_PCM_FMTS,
948 },
949 .ops = &davinci_mcasp_dai_ops,
950 },
951
952 };
953
954 static const struct of_device_id mcasp_dt_ids[] = {
955 {
956 .compatible = "ti,dm646x-mcasp-audio",
957 .data = (void *)MCASP_VERSION_1,
958 },
959 {
960 .compatible = "ti,da830-mcasp-audio",
961 .data = (void *)MCASP_VERSION_2,
962 },
963 {
964 .compatible = "ti,omap2-mcasp-audio",
965 .data = (void *)MCASP_VERSION_3,
966 },
967 { /* sentinel */ }
968 };
969 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
970
971 static struct snd_platform_data *davinci_mcasp_set_pdata_from_of(
972 struct platform_device *pdev)
973 {
974 struct device_node *np = pdev->dev.of_node;
975 struct snd_platform_data *pdata = NULL;
976 const struct of_device_id *match =
977 of_match_device(of_match_ptr(mcasp_dt_ids), &pdev->dev);
978
979 const u32 *of_serial_dir32;
980 u8 *of_serial_dir;
981 u32 val;
982 int i, ret = 0;
983
984 if (pdev->dev.platform_data) {
985 pdata = pdev->dev.platform_data;
986 return pdata;
987 } else if (match) {
988 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
989 if (!pdata) {
990 ret = -ENOMEM;
991 goto nodata;
992 }
993 } else {
994 /* control shouldn't reach here. something is wrong */
995 ret = -EINVAL;
996 goto nodata;
997 }
998
999 if (match->data)
1000 pdata->version = (u8)((int)match->data);
1001
1002 ret = of_property_read_u32(np, "op-mode", &val);
1003 if (ret >= 0)
1004 pdata->op_mode = val;
1005
1006 ret = of_property_read_u32(np, "tdm-slots", &val);
1007 if (ret >= 0)
1008 pdata->tdm_slots = val;
1009
1010 ret = of_property_read_u32(np, "num-serializer", &val);
1011 if (ret >= 0)
1012 pdata->num_serializer = val;
1013
1014 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1015 val /= sizeof(u32);
1016 if (val != pdata->num_serializer) {
1017 dev_err(&pdev->dev,
1018 "num-serializer(%d) != serial-dir size(%d)\n",
1019 pdata->num_serializer, val);
1020 ret = -EINVAL;
1021 goto nodata;
1022 }
1023
1024 if (of_serial_dir32) {
1025 of_serial_dir = devm_kzalloc(&pdev->dev,
1026 (sizeof(*of_serial_dir) * val),
1027 GFP_KERNEL);
1028 if (!of_serial_dir) {
1029 ret = -ENOMEM;
1030 goto nodata;
1031 }
1032
1033 for (i = 0; i < pdata->num_serializer; i++)
1034 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1035
1036 pdata->serial_dir = of_serial_dir;
1037 }
1038
1039 ret = of_property_read_u32(np, "tx-num-evt", &val);
1040 if (ret >= 0)
1041 pdata->txnumevt = val;
1042
1043 ret = of_property_read_u32(np, "rx-num-evt", &val);
1044 if (ret >= 0)
1045 pdata->rxnumevt = val;
1046
1047 ret = of_property_read_u32(np, "sram-size-playback", &val);
1048 if (ret >= 0)
1049 pdata->sram_size_playback = val;
1050
1051 ret = of_property_read_u32(np, "sram-size-capture", &val);
1052 if (ret >= 0)
1053 pdata->sram_size_capture = val;
1054
1055 return pdata;
1056
1057 nodata:
1058 if (ret < 0) {
1059 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1060 ret);
1061 pdata = NULL;
1062 }
1063 return pdata;
1064 }
1065
1066 static int davinci_mcasp_probe(struct platform_device *pdev)
1067 {
1068 struct davinci_pcm_dma_params *dma_data;
1069 struct resource *mem, *ioarea, *res;
1070 struct snd_platform_data *pdata;
1071 struct davinci_audio_dev *dev;
1072 int ret;
1073
1074 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1075 dev_err(&pdev->dev, "No platform data supplied\n");
1076 return -EINVAL;
1077 }
1078
1079 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_audio_dev),
1080 GFP_KERNEL);
1081 if (!dev)
1082 return -ENOMEM;
1083
1084 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1085 if (!pdata) {
1086 dev_err(&pdev->dev, "no platform data\n");
1087 return -EINVAL;
1088 }
1089
1090 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1091 if (!mem) {
1092 dev_err(&pdev->dev, "no mem resource?\n");
1093 return -ENODEV;
1094 }
1095
1096 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
1097 resource_size(mem), pdev->name);
1098 if (!ioarea) {
1099 dev_err(&pdev->dev, "Audio region already claimed\n");
1100 return -EBUSY;
1101 }
1102
1103 pm_runtime_enable(&pdev->dev);
1104
1105 ret = pm_runtime_get_sync(&pdev->dev);
1106 if (IS_ERR_VALUE(ret)) {
1107 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
1108 return ret;
1109 }
1110
1111 dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
1112 if (!dev->base) {
1113 dev_err(&pdev->dev, "ioremap failed\n");
1114 ret = -ENOMEM;
1115 goto err_release_clk;
1116 }
1117
1118 dev->op_mode = pdata->op_mode;
1119 dev->tdm_slots = pdata->tdm_slots;
1120 dev->num_serializer = pdata->num_serializer;
1121 dev->serial_dir = pdata->serial_dir;
1122 dev->codec_fmt = pdata->codec_fmt;
1123 dev->version = pdata->version;
1124 dev->txnumevt = pdata->txnumevt;
1125 dev->rxnumevt = pdata->rxnumevt;
1126 dev->dev = &pdev->dev;
1127
1128 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
1129 dma_data->asp_chan_q = pdata->asp_chan_q;
1130 dma_data->ram_chan_q = pdata->ram_chan_q;
1131 dma_data->sram_size = pdata->sram_size_playback;
1132 dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset +
1133 mem->start);
1134
1135 /* first TX, then RX */
1136 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1137 if (!res) {
1138 dev_err(&pdev->dev, "no DMA resource\n");
1139 ret = -ENODEV;
1140 goto err_release_clk;
1141 }
1142
1143 dma_data->channel = res->start;
1144
1145 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE];
1146 dma_data->asp_chan_q = pdata->asp_chan_q;
1147 dma_data->ram_chan_q = pdata->ram_chan_q;
1148 dma_data->sram_size = pdata->sram_size_capture;
1149 dma_data->dma_addr = (dma_addr_t)(pdata->rx_dma_offset +
1150 mem->start);
1151
1152 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1153 if (!res) {
1154 dev_err(&pdev->dev, "no DMA resource\n");
1155 ret = -ENODEV;
1156 goto err_release_clk;
1157 }
1158
1159 dma_data->channel = res->start;
1160 dev_set_drvdata(&pdev->dev, dev);
1161 ret = snd_soc_register_dai(&pdev->dev, &davinci_mcasp_dai[pdata->op_mode]);
1162
1163 if (ret != 0)
1164 goto err_release_clk;
1165
1166 ret = davinci_soc_platform_register(&pdev->dev);
1167 if (ret) {
1168 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1169 goto err_unregister_dai;
1170 }
1171
1172 return 0;
1173
1174 err_unregister_dai:
1175 snd_soc_unregister_dai(&pdev->dev);
1176 err_release_clk:
1177 pm_runtime_put_sync(&pdev->dev);
1178 pm_runtime_disable(&pdev->dev);
1179 return ret;
1180 }
1181
1182 static int davinci_mcasp_remove(struct platform_device *pdev)
1183 {
1184
1185 snd_soc_unregister_dai(&pdev->dev);
1186 davinci_soc_platform_unregister(&pdev->dev);
1187
1188 pm_runtime_put_sync(&pdev->dev);
1189 pm_runtime_disable(&pdev->dev);
1190
1191 return 0;
1192 }
1193
1194 static struct platform_driver davinci_mcasp_driver = {
1195 .probe = davinci_mcasp_probe,
1196 .remove = davinci_mcasp_remove,
1197 .driver = {
1198 .name = "davinci-mcasp",
1199 .owner = THIS_MODULE,
1200 .of_match_table = of_match_ptr(mcasp_dt_ids),
1201 },
1202 };
1203
1204 module_platform_driver(davinci_mcasp_driver);
1205
1206 MODULE_AUTHOR("Steve Chen");
1207 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1208 MODULE_LICENSE("GPL");
1209
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