| blob | a32af6e4d94cd0f68bd90467ffd7236c3c70e936 |
1 /*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
9 /*
10 * Carveout for multimedia usecases
11 * It should be the last 48MB of the first 512MB memory part
12 * In theory, it should not even exist. That zone should be reserved
13 * dynamically during the .reserve callback.
14 */
15 /memreserve/ 0x9d000000 0x03000000;
17 /include/ "skeleton.dtsi"
19 / {
20 compatible = "ti,omap4430", "ti,omap4";
21 interrupt-parent = <&gic>;
23 aliases {
24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 serial3 = &uart4;
28 };
30 cpus {
31 cpu@0 {
32 compatible = "arm,cortex-a9";
33 next-level-cache = <&L2>;
34 };
35 cpu@1 {
36 compatible = "arm,cortex-a9";
37 next-level-cache = <&L2>;
38 };
39 };
41 gic: interrupt-controller@48241000 {
42 compatible = "arm,cortex-a9-gic";
43 interrupt-controller;
44 #interrupt-cells = <3>;
45 reg = <0x48241000 0x1000>,
46 <0x48240100 0x0100>;
47 };
49 L2: l2-cache-controller@48242000 {
50 compatible = "arm,pl310-cache";
51 reg = <0x48242000 0x1000>;
52 cache-unified;
53 cache-level = <2>;
54 };
56 local-timer@0x48240600 {
57 compatible = "arm,cortex-a9-twd-timer";
58 reg = <0x48240600 0x20>;
59 interrupts = <1 13 0x304>;
60 };
62 /*
63 * The soc node represents the soc top level view. It is uses for IPs
64 * that are not memory mapped in the MPU view or for the MPU itself.
65 */
66 soc {
67 compatible = "ti,omap-infra";
68 mpu {
69 compatible = "ti,omap4-mpu";
70 ti,hwmods = "mpu";
71 };
73 dsp {
74 compatible = "ti,omap3-c64";
75 ti,hwmods = "dsp";
76 };
78 iva {
79 compatible = "ti,ivahd";
80 ti,hwmods = "iva";
81 };
82 };
84 /*
85 * XXX: Use a flat representation of the OMAP4 interconnect.
86 * The real OMAP interconnect network is quite complex.
87 * Since that will not bring real advantage to represent that in DT for
88 * the moment, just use a fake OCP bus entry to represent the whole bus
89 * hierarchy.
90 */
91 ocp {
92 compatible = "ti,omap4-l3-noc", "simple-bus";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges;
96 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
98 counter32k: counter@4a304000 {
99 compatible = "ti,omap-counter32k";
100 reg = <0x4a304000 0x20>;
101 ti,hwmods = "counter_32k";
102 };
104 omap4_pmx_core: pinmux@4a100040 {
105 compatible = "ti,omap4-padconf", "pinctrl-single";
106 reg = <0x4a100040 0x0196>;
107 #address-cells = <1>;
108 #size-cells = <0>;
109 pinctrl-single,register-width = <16>;
110 pinctrl-single,function-mask = <0x7fff>;
111 };
112 omap4_pmx_wkup: pinmux@4a31e040 {
113 compatible = "ti,omap4-padconf", "pinctrl-single";
114 reg = <0x4a31e040 0x0038>;
115 #address-cells = <1>;
116 #size-cells = <0>;
117 pinctrl-single,register-width = <16>;
118 pinctrl-single,function-mask = <0x7fff>;
119 };
121 sdma: dma-controller@4a056000 {
122 compatible = "ti,omap4430-sdma";
123 reg = <0x4a056000 0x1000>;
124 interrupts = <0 12 0x4>,
125 <0 13 0x4>,
126 <0 14 0x4>,
127 <0 15 0x4>;
128 #dma-cells = <1>;
129 #dma-channels = <32>;
130 #dma-requests = <127>;
131 };
133 gpio1: gpio@4a310000 {
134 compatible = "ti,omap4-gpio";
135 reg = <0x4a310000 0x200>;
136 interrupts = <0 29 0x4>;
137 ti,hwmods = "gpio1";
138 gpio-controller;
139 #gpio-cells = <2>;
140 interrupt-controller;
141 #interrupt-cells = <2>;
142 };
144 gpio2: gpio@48055000 {
145 compatible = "ti,omap4-gpio";
146 reg = <0x48055000 0x200>;
147 interrupts = <0 30 0x4>;
148 ti,hwmods = "gpio2";
149 gpio-controller;
150 #gpio-cells = <2>;
151 interrupt-controller;
152 #interrupt-cells = <2>;
153 };
155 gpio3: gpio@48057000 {
156 compatible = "ti,omap4-gpio";
157 reg = <0x48057000 0x200>;
158 interrupts = <0 31 0x4>;
159 ti,hwmods = "gpio3";
160 gpio-controller;
161 #gpio-cells = <2>;
162 interrupt-controller;
163 #interrupt-cells = <2>;
164 };
166 gpio4: gpio@48059000 {
167 compatible = "ti,omap4-gpio";
168 reg = <0x48059000 0x200>;
169 interrupts = <0 32 0x4>;
170 ti,hwmods = "gpio4";
171 gpio-controller;
172 #gpio-cells = <2>;
173 interrupt-controller;
174 #interrupt-cells = <2>;
175 };
177 gpio5: gpio@4805b000 {
178 compatible = "ti,omap4-gpio";
179 reg = <0x4805b000 0x200>;
180 interrupts = <0 33 0x4>;
181 ti,hwmods = "gpio5";
182 gpio-controller;
183 #gpio-cells = <2>;
184 interrupt-controller;
185 #interrupt-cells = <2>;
186 };
188 gpio6: gpio@4805d000 {
189 compatible = "ti,omap4-gpio";
190 reg = <0x4805d000 0x200>;
191 interrupts = <0 34 0x4>;
192 ti,hwmods = "gpio6";
193 gpio-controller;
194 #gpio-cells = <2>;
195 interrupt-controller;
196 #interrupt-cells = <2>;
197 };
199 gpmc: gpmc@50000000 {
200 compatible = "ti,omap4430-gpmc";
201 reg = <0x50000000 0x1000>;
202 #address-cells = <2>;
203 #size-cells = <1>;
204 interrupts = <0 20 0x4>;
205 gpmc,num-cs = <8>;
206 gpmc,num-waitpins = <4>;
207 ti,hwmods = "gpmc";
208 };
210 uart1: serial@4806a000 {
211 compatible = "ti,omap4-uart";
212 reg = <0x4806a000 0x100>;
213 interrupts = <0 72 0x4>;
214 ti,hwmods = "uart1";
215 clock-frequency = <48000000>;
216 };
218 uart2: serial@4806c000 {
219 compatible = "ti,omap4-uart";
220 reg = <0x4806c000 0x100>;
221 interrupts = <0 73 0x4>;
222 ti,hwmods = "uart2";
223 clock-frequency = <48000000>;
224 };
226 uart3: serial@48020000 {
227 compatible = "ti,omap4-uart";
228 reg = <0x48020000 0x100>;
229 interrupts = <0 74 0x4>;
230 ti,hwmods = "uart3";
231 clock-frequency = <48000000>;
232 };
234 uart4: serial@4806e000 {
235 compatible = "ti,omap4-uart";
236 reg = <0x4806e000 0x100>;
237 interrupts = <0 70 0x4>;
238 ti,hwmods = "uart4";
239 clock-frequency = <48000000>;
240 };
242 i2c1: i2c@48070000 {
243 compatible = "ti,omap4-i2c";
244 reg = <0x48070000 0x100>;
245 interrupts = <0 56 0x4>;
246 #address-cells = <1>;
247 #size-cells = <0>;
248 ti,hwmods = "i2c1";
249 };
251 i2c2: i2c@48072000 {
252 compatible = "ti,omap4-i2c";
253 reg = <0x48072000 0x100>;
254 interrupts = <0 57 0x4>;
255 #address-cells = <1>;
256 #size-cells = <0>;
257 ti,hwmods = "i2c2";
258 };
260 i2c3: i2c@48060000 {
261 compatible = "ti,omap4-i2c";
262 reg = <0x48060000 0x100>;
263 interrupts = <0 61 0x4>;
264 #address-cells = <1>;
265 #size-cells = <0>;
266 ti,hwmods = "i2c3";
267 };
269 i2c4: i2c@48350000 {
270 compatible = "ti,omap4-i2c";
271 reg = <0x48350000 0x100>;
272 interrupts = <0 62 0x4>;
273 #address-cells = <1>;
274 #size-cells = <0>;
275 ti,hwmods = "i2c4";
276 };
278 mcspi1: spi@48098000 {
279 compatible = "ti,omap4-mcspi";
280 reg = <0x48098000 0x200>;
281 interrupts = <0 65 0x4>;
282 #address-cells = <1>;
283 #size-cells = <0>;
284 ti,hwmods = "mcspi1";
285 ti,spi-num-cs = <4>;
286 dmas = <&sdma 35>,
287 <&sdma 36>,
288 <&sdma 37>,
289 <&sdma 38>,
290 <&sdma 39>,
291 <&sdma 40>,
292 <&sdma 41>,
293 <&sdma 42>;
294 dma-names = "tx0", "rx0", "tx1", "rx1",
295 "tx2", "rx2", "tx3", "rx3";
296 };
298 mcspi2: spi@4809a000 {
299 compatible = "ti,omap4-mcspi";
300 reg = <0x4809a000 0x200>;
301 interrupts = <0 66 0x4>;
302 #address-cells = <1>;
303 #size-cells = <0>;
304 ti,hwmods = "mcspi2";
305 ti,spi-num-cs = <2>;
306 dmas = <&sdma 43>,
307 <&sdma 44>,
308 <&sdma 45>,
309 <&sdma 46>;
310 dma-names = "tx0", "rx0", "tx1", "rx1";
311 };
313 mcspi3: spi@480b8000 {
314 compatible = "ti,omap4-mcspi";
315 reg = <0x480b8000 0x200>;
316 interrupts = <0 91 0x4>;
317 #address-cells = <1>;
318 #size-cells = <0>;
319 ti,hwmods = "mcspi3";
320 ti,spi-num-cs = <2>;
321 dmas = <&sdma 15>, <&sdma 16>;
322 dma-names = "tx0", "rx0";
323 };
325 mcspi4: spi@480ba000 {
326 compatible = "ti,omap4-mcspi";
327 reg = <0x480ba000 0x200>;
328 interrupts = <0 48 0x4>;
329 #address-cells = <1>;
330 #size-cells = <0>;
331 ti,hwmods = "mcspi4";
332 ti,spi-num-cs = <1>;
333 dmas = <&sdma 70>, <&sdma 71>;
334 dma-names = "tx0", "rx0";
335 };
337 mmc1: mmc@4809c000 {
338 compatible = "ti,omap4-hsmmc";
339 reg = <0x4809c000 0x400>;
340 interrupts = <0 83 0x4>;
341 ti,hwmods = "mmc1";
342 ti,dual-volt;
343 ti,needs-special-reset;
344 dmas = <&sdma 61>, <&sdma 62>;
345 dma-names = "tx", "rx";
346 };
348 mmc2: mmc@480b4000 {
349 compatible = "ti,omap4-hsmmc";
350 reg = <0x480b4000 0x400>;
351 interrupts = <0 86 0x4>;
352 ti,hwmods = "mmc2";
353 ti,needs-special-reset;
354 dmas = <&sdma 47>, <&sdma 48>;
355 dma-names = "tx", "rx";
356 };
358 mmc3: mmc@480ad000 {
359 compatible = "ti,omap4-hsmmc";
360 reg = <0x480ad000 0x400>;
361 interrupts = <0 94 0x4>;
362 ti,hwmods = "mmc3";
363 ti,needs-special-reset;
364 dmas = <&sdma 77>, <&sdma 78>;
365 dma-names = "tx", "rx";
366 };
368 mmc4: mmc@480d1000 {
369 compatible = "ti,omap4-hsmmc";
370 reg = <0x480d1000 0x400>;
371 interrupts = <0 96 0x4>;
372 ti,hwmods = "mmc4";
373 ti,needs-special-reset;
374 dmas = <&sdma 57>, <&sdma 58>;
375 dma-names = "tx", "rx";
376 };
378 mmc5: mmc@480d5000 {
379 compatible = "ti,omap4-hsmmc";
380 reg = <0x480d5000 0x400>;
381 interrupts = <0 59 0x4>;
382 ti,hwmods = "mmc5";
383 ti,needs-special-reset;
384 dmas = <&sdma 59>, <&sdma 60>;
385 dma-names = "tx", "rx";
386 };
388 wdt2: wdt@4a314000 {
389 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
390 reg = <0x4a314000 0x80>;
391 interrupts = <0 80 0x4>;
392 ti,hwmods = "wd_timer2";
393 };
395 mcpdm: mcpdm@40132000 {
396 compatible = "ti,omap4-mcpdm";
397 reg = <0x40132000 0x7f>, /* MPU private access */
398 <0x49032000 0x7f>; /* L3 Interconnect */
399 reg-names = "mpu", "dma";
400 interrupts = <0 112 0x4>;
401 ti,hwmods = "mcpdm";
402 dmas = <&sdma 65>,
403 <&sdma 66>;
404 dma-names = "up_link", "dn_link";
405 };
407 dmic: dmic@4012e000 {
408 compatible = "ti,omap4-dmic";
409 reg = <0x4012e000 0x7f>, /* MPU private access */
410 <0x4902e000 0x7f>; /* L3 Interconnect */
411 reg-names = "mpu", "dma";
412 interrupts = <0 114 0x4>;
413 ti,hwmods = "dmic";
414 dmas = <&sdma 67>;
415 dma-names = "up_link";
416 };
418 mcbsp1: mcbsp@40122000 {
419 compatible = "ti,omap4-mcbsp";
420 reg = <0x40122000 0xff>, /* MPU private access */
421 <0x49022000 0xff>; /* L3 Interconnect */
422 reg-names = "mpu", "dma";
423 interrupts = <0 17 0x4>;
424 interrupt-names = "common";
425 ti,buffer-size = <128>;
426 ti,hwmods = "mcbsp1";
427 dmas = <&sdma 33>,
428 <&sdma 34>;
429 dma-names = "tx", "rx";
430 };
432 mcbsp2: mcbsp@40124000 {
433 compatible = "ti,omap4-mcbsp";
434 reg = <0x40124000 0xff>, /* MPU private access */
435 <0x49024000 0xff>; /* L3 Interconnect */
436 reg-names = "mpu", "dma";
437 interrupts = <0 22 0x4>;
438 interrupt-names = "common";
439 ti,buffer-size = <128>;
440 ti,hwmods = "mcbsp2";
441 dmas = <&sdma 17>,
442 <&sdma 18>;
443 dma-names = "tx", "rx";
444 };
446 mcbsp3: mcbsp@40126000 {
447 compatible = "ti,omap4-mcbsp";
448 reg = <0x40126000 0xff>, /* MPU private access */
449 <0x49026000 0xff>; /* L3 Interconnect */
450 reg-names = "mpu", "dma";
451 interrupts = <0 23 0x4>;
452 interrupt-names = "common";
453 ti,buffer-size = <128>;
454 ti,hwmods = "mcbsp3";
455 dmas = <&sdma 19>,
456 <&sdma 20>;
457 dma-names = "tx", "rx";
458 };
460 mcbsp4: mcbsp@48096000 {
461 compatible = "ti,omap4-mcbsp";
462 reg = <0x48096000 0xff>; /* L4 Interconnect */
463 reg-names = "mpu";
464 interrupts = <0 16 0x4>;
465 interrupt-names = "common";
466 ti,buffer-size = <128>;
467 ti,hwmods = "mcbsp4";
468 dmas = <&sdma 31>,
469 <&sdma 32>;
470 dma-names = "tx", "rx";
471 };
473 keypad: keypad@4a31c000 {
474 compatible = "ti,omap4-keypad";
475 reg = <0x4a31c000 0x80>;
476 interrupts = <0 120 0x4>;
477 reg-names = "mpu";
478 ti,hwmods = "kbd";
479 };
481 emif1: emif@4c000000 {
482 compatible = "ti,emif-4d";
483 reg = <0x4c000000 0x100>;
484 interrupts = <0 110 0x4>;
485 ti,hwmods = "emif1";
486 phy-type = <1>;
487 hw-caps-read-idle-ctrl;
488 hw-caps-ll-interface;
489 hw-caps-temp-alert;
490 };
492 emif2: emif@4d000000 {
493 compatible = "ti,emif-4d";
494 reg = <0x4d000000 0x100>;
495 interrupts = <0 111 0x4>;
496 ti,hwmods = "emif2";
497 phy-type = <1>;
498 hw-caps-read-idle-ctrl;
499 hw-caps-ll-interface;
500 hw-caps-temp-alert;
501 };
503 ocp2scp@4a0ad000 {
504 compatible = "ti,omap-ocp2scp";
505 reg = <0x4a0ad000 0x1f>;
506 #address-cells = <1>;
507 #size-cells = <1>;
508 ranges;
509 ti,hwmods = "ocp2scp_usb_phy";
510 usb2_phy: usb2phy@4a0ad080 {
511 compatible = "ti,omap-usb2";
512 reg = <0x4a0ad080 0x58>;
513 ctrl-module = <&omap_control_usb>;
514 };
515 };
517 timer1: timer@4a318000 {
518 compatible = "ti,omap2-timer";
519 reg = <0x4a318000 0x80>;
520 interrupts = <0 37 0x4>;
521 ti,hwmods = "timer1";
522 ti,timer-alwon;
523 };
525 timer2: timer@48032000 {
526 compatible = "ti,omap2-timer";
527 reg = <0x48032000 0x80>;
528 interrupts = <0 38 0x4>;
529 ti,hwmods = "timer2";
530 };
532 timer3: timer@48034000 {
533 compatible = "ti,omap2-timer";
534 reg = <0x48034000 0x80>;
535 interrupts = <0 39 0x4>;
536 ti,hwmods = "timer3";
537 };
539 timer4: timer@48036000 {
540 compatible = "ti,omap2-timer";
541 reg = <0x48036000 0x80>;
542 interrupts = <0 40 0x4>;
543 ti,hwmods = "timer4";
544 };
546 timer5: timer@40138000 {
547 compatible = "ti,omap2-timer";
548 reg = <0x40138000 0x80>,
549 <0x49038000 0x80>;
550 interrupts = <0 41 0x4>;
551 ti,hwmods = "timer5";
552 ti,timer-dsp;
553 };
555 timer6: timer@4013a000 {
556 compatible = "ti,omap2-timer";
557 reg = <0x4013a000 0x80>,
558 <0x4903a000 0x80>;
559 interrupts = <0 42 0x4>;
560 ti,hwmods = "timer6";
561 ti,timer-dsp;
562 };
564 timer7: timer@4013c000 {
565 compatible = "ti,omap2-timer";
566 reg = <0x4013c000 0x80>,
567 <0x4903c000 0x80>;
568 interrupts = <0 43 0x4>;
569 ti,hwmods = "timer7";
570 ti,timer-dsp;
571 };
573 timer8: timer@4013e000 {
574 compatible = "ti,omap2-timer";
575 reg = <0x4013e000 0x80>,
576 <0x4903e000 0x80>;
577 interrupts = <0 44 0x4>;
578 ti,hwmods = "timer8";
579 ti,timer-pwm;
580 ti,timer-dsp;
581 };
583 timer9: timer@4803e000 {
584 compatible = "ti,omap2-timer";
585 reg = <0x4803e000 0x80>;
586 interrupts = <0 45 0x4>;
587 ti,hwmods = "timer9";
588 ti,timer-pwm;
589 };
591 timer10: timer@48086000 {
592 compatible = "ti,omap2-timer";
593 reg = <0x48086000 0x80>;
594 interrupts = <0 46 0x4>;
595 ti,hwmods = "timer10";
596 ti,timer-pwm;
597 };
599 timer11: timer@48088000 {
600 compatible = "ti,omap2-timer";
601 reg = <0x48088000 0x80>;
602 interrupts = <0 47 0x4>;
603 ti,hwmods = "timer11";
604 ti,timer-pwm;
605 };
607 usbhstll: usbhstll@4a062000 {
608 compatible = "ti,usbhs-tll";
609 reg = <0x4a062000 0x1000>;
610 interrupts = <0 78 0x4>;
611 ti,hwmods = "usb_tll_hs";
612 };
614 usbhshost: usbhshost@4a064000 {
615 compatible = "ti,usbhs-host";
616 reg = <0x4a064000 0x800>;
617 ti,hwmods = "usb_host_hs";
618 #address-cells = <1>;
619 #size-cells = <1>;
620 ranges;
622 usbhsohci: ohci@4a064800 {
623 compatible = "ti,ohci-omap3", "usb-ohci";
624 reg = <0x4a064800 0x400>;
625 interrupt-parent = <&gic>;
626 interrupts = <0 76 0x4>;
627 };
629 usbhsehci: ehci@4a064c00 {
630 compatible = "ti,ehci-omap", "usb-ehci";
631 reg = <0x4a064c00 0x400>;
632 interrupt-parent = <&gic>;
633 interrupts = <0 77 0x4>;
634 };
635 };
637 omap_control_usb: omap-control-usb@4a002300 {
638 compatible = "ti,omap-control-usb";
639 reg = <0x4a002300 0x4>,
640 <0x4a00233c 0x4>;
641 reg-names = "control_dev_conf", "otghs_control";
642 ti,type = <1>;
643 };
645 usb_otg_hs: usb_otg_hs@4a0ab000 {
646 compatible = "ti,omap4-musb";
647 reg = <0x4a0ab000 0x7ff>;
648 interrupts = <0 92 0x4>, <0 93 0x4>;
649 interrupt-names = "mc", "dma";
650 ti,hwmods = "usb_otg_hs";
651 usb-phy = <&usb2_phy>;
652 multipoint = <1>;
653 num-eps = <16>;
654 ram-bits = <12>;
655 ti,has-mailbox;
656 };
657 };
658 };