| blob | 08cd592652fc41e952b1f577ac561c40341853d1 |
1 /*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
13 #include "skeleton.dtsi"
14 #include "imx53-pinfunc.h"
15 #include <dt-bindings/clock/imx5-clock.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
19 / {
20 aliases {
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 gpio4 = &gpio5;
26 gpio5 = &gpio6;
27 gpio6 = &gpio7;
28 i2c0 = &i2c1;
29 i2c1 = &i2c2;
30 i2c2 = &i2c3;
31 serial0 = &uart1;
32 serial1 = &uart2;
33 serial2 = &uart3;
34 serial3 = &uart4;
35 serial4 = &uart5;
36 spi0 = &ecspi1;
37 spi1 = &ecspi2;
38 spi2 = &cspi;
39 };
41 cpus {
42 #address-cells = <1>;
43 #size-cells = <0>;
44 cpu@0 {
45 device_type = "cpu";
46 compatible = "arm,cortex-a8";
47 reg = <0x0>;
48 };
49 };
51 tzic: tz-interrupt-controller@0fffc000 {
52 compatible = "fsl,imx53-tzic", "fsl,tzic";
53 interrupt-controller;
54 #interrupt-cells = <1>;
55 reg = <0x0fffc000 0x4000>;
56 };
58 clocks {
59 #address-cells = <1>;
60 #size-cells = <0>;
62 ckil {
63 compatible = "fsl,imx-ckil", "fixed-clock";
64 clock-frequency = <32768>;
65 };
67 ckih1 {
68 compatible = "fsl,imx-ckih1", "fixed-clock";
69 clock-frequency = <22579200>;
70 };
72 ckih2 {
73 compatible = "fsl,imx-ckih2", "fixed-clock";
74 clock-frequency = <0>;
75 };
77 osc {
78 compatible = "fsl,imx-osc", "fixed-clock";
79 clock-frequency = <24000000>;
80 };
81 };
83 soc {
84 #address-cells = <1>;
85 #size-cells = <1>;
86 compatible = "simple-bus";
87 interrupt-parent = <&tzic>;
88 ranges;
90 sata: sata@10000000 {
91 compatible = "fsl,imx53-ahci";
92 reg = <0x10000000 0x1000>;
93 interrupts = <28>;
94 clocks = <&clks IMX5_CLK_SATA_GATE>,
95 <&clks IMX5_CLK_SATA_REF>,
96 <&clks IMX5_CLK_AHB>;
97 clock-names = "sata_gate", "sata_ref", "ahb";
98 status = "disabled";
99 };
101 ipu: ipu@18000000 {
102 #crtc-cells = <1>;
103 compatible = "fsl,imx53-ipu";
104 reg = <0x18000000 0x080000000>;
105 interrupts = <11 10>;
106 clocks = <&clks IMX5_CLK_IPU_GATE>,
107 <&clks IMX5_CLK_IPU_DI0_GATE>,
108 <&clks IMX5_CLK_IPU_DI1_GATE>;
109 clock-names = "bus", "di0", "di1";
110 resets = <&src 2>;
111 };
113 aips@50000000 { /* AIPS1 */
114 compatible = "fsl,aips-bus", "simple-bus";
115 #address-cells = <1>;
116 #size-cells = <1>;
117 reg = <0x50000000 0x10000000>;
118 ranges;
120 spba@50000000 {
121 compatible = "fsl,spba-bus", "simple-bus";
122 #address-cells = <1>;
123 #size-cells = <1>;
124 reg = <0x50000000 0x40000>;
125 ranges;
127 esdhc1: esdhc@50004000 {
128 compatible = "fsl,imx53-esdhc";
129 reg = <0x50004000 0x4000>;
130 interrupts = <1>;
131 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
132 <&clks IMX5_CLK_DUMMY>,
133 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
134 clock-names = "ipg", "ahb", "per";
135 bus-width = <4>;
136 status = "disabled";
137 };
139 esdhc2: esdhc@50008000 {
140 compatible = "fsl,imx53-esdhc";
141 reg = <0x50008000 0x4000>;
142 interrupts = <2>;
143 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
144 <&clks IMX5_CLK_DUMMY>,
145 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
146 clock-names = "ipg", "ahb", "per";
147 bus-width = <4>;
148 status = "disabled";
149 };
151 uart3: serial@5000c000 {
152 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
153 reg = <0x5000c000 0x4000>;
154 interrupts = <33>;
155 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
156 <&clks IMX5_CLK_UART3_PER_GATE>;
157 clock-names = "ipg", "per";
158 status = "disabled";
159 };
161 ecspi1: ecspi@50010000 {
162 #address-cells = <1>;
163 #size-cells = <0>;
164 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
165 reg = <0x50010000 0x4000>;
166 interrupts = <36>;
167 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
168 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
169 clock-names = "ipg", "per";
170 status = "disabled";
171 };
173 ssi2: ssi@50014000 {
174 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
175 reg = <0x50014000 0x4000>;
176 interrupts = <30>;
177 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
178 dmas = <&sdma 24 1 0>,
179 <&sdma 25 1 0>;
180 dma-names = "rx", "tx";
181 fsl,fifo-depth = <15>;
182 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
183 status = "disabled";
184 };
186 esdhc3: esdhc@50020000 {
187 compatible = "fsl,imx53-esdhc";
188 reg = <0x50020000 0x4000>;
189 interrupts = <3>;
190 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
191 <&clks IMX5_CLK_DUMMY>,
192 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
193 clock-names = "ipg", "ahb", "per";
194 bus-width = <4>;
195 status = "disabled";
196 };
198 esdhc4: esdhc@50024000 {
199 compatible = "fsl,imx53-esdhc";
200 reg = <0x50024000 0x4000>;
201 interrupts = <4>;
202 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
203 <&clks IMX5_CLK_DUMMY>,
204 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
205 clock-names = "ipg", "ahb", "per";
206 bus-width = <4>;
207 status = "disabled";
208 };
209 };
211 usbphy0: usbphy@0 {
212 compatible = "usb-nop-xceiv";
213 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
214 clock-names = "main_clk";
215 status = "okay";
216 };
218 usbphy1: usbphy@1 {
219 compatible = "usb-nop-xceiv";
220 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
221 clock-names = "main_clk";
222 status = "okay";
223 };
225 usbotg: usb@53f80000 {
226 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
227 reg = <0x53f80000 0x0200>;
228 interrupts = <18>;
229 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
230 fsl,usbmisc = <&usbmisc 0>;
231 fsl,usbphy = <&usbphy0>;
232 status = "disabled";
233 };
235 usbh1: usb@53f80200 {
236 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
237 reg = <0x53f80200 0x0200>;
238 interrupts = <14>;
239 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
240 fsl,usbmisc = <&usbmisc 1>;
241 fsl,usbphy = <&usbphy1>;
242 status = "disabled";
243 };
245 usbh2: usb@53f80400 {
246 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
247 reg = <0x53f80400 0x0200>;
248 interrupts = <16>;
249 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
250 fsl,usbmisc = <&usbmisc 2>;
251 status = "disabled";
252 };
254 usbh3: usb@53f80600 {
255 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
256 reg = <0x53f80600 0x0200>;
257 interrupts = <17>;
258 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
259 fsl,usbmisc = <&usbmisc 3>;
260 status = "disabled";
261 };
263 usbmisc: usbmisc@53f80800 {
264 #index-cells = <1>;
265 compatible = "fsl,imx53-usbmisc";
266 reg = <0x53f80800 0x200>;
267 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
268 };
270 gpio1: gpio@53f84000 {
271 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
272 reg = <0x53f84000 0x4000>;
273 interrupts = <50 51>;
274 gpio-controller;
275 #gpio-cells = <2>;
276 interrupt-controller;
277 #interrupt-cells = <2>;
278 };
280 gpio2: gpio@53f88000 {
281 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
282 reg = <0x53f88000 0x4000>;
283 interrupts = <52 53>;
284 gpio-controller;
285 #gpio-cells = <2>;
286 interrupt-controller;
287 #interrupt-cells = <2>;
288 };
290 gpio3: gpio@53f8c000 {
291 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
292 reg = <0x53f8c000 0x4000>;
293 interrupts = <54 55>;
294 gpio-controller;
295 #gpio-cells = <2>;
296 interrupt-controller;
297 #interrupt-cells = <2>;
298 };
300 gpio4: gpio@53f90000 {
301 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
302 reg = <0x53f90000 0x4000>;
303 interrupts = <56 57>;
304 gpio-controller;
305 #gpio-cells = <2>;
306 interrupt-controller;
307 #interrupt-cells = <2>;
308 };
310 kpp: kpp@53f94000 {
311 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
312 reg = <0x53f94000 0x4000>;
313 interrupts = <60>;
314 clocks = <&clks IMX5_CLK_DUMMY>;
315 status = "disabled";
316 };
318 wdog1: wdog@53f98000 {
319 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
320 reg = <0x53f98000 0x4000>;
321 interrupts = <58>;
322 clocks = <&clks IMX5_CLK_DUMMY>;
323 };
325 wdog2: wdog@53f9c000 {
326 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
327 reg = <0x53f9c000 0x4000>;
328 interrupts = <59>;
329 clocks = <&clks IMX5_CLK_DUMMY>;
330 status = "disabled";
331 };
333 gpt: timer@53fa0000 {
334 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
335 reg = <0x53fa0000 0x4000>;
336 interrupts = <39>;
337 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
338 <&clks IMX5_CLK_GPT_HF_GATE>;
339 clock-names = "ipg", "per";
340 };
342 iomuxc: iomuxc@53fa8000 {
343 compatible = "fsl,imx53-iomuxc";
344 reg = <0x53fa8000 0x4000>;
345 };
347 gpr: iomuxc-gpr@53fa8000 {
348 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
349 reg = <0x53fa8000 0xc>;
350 };
352 ldb: ldb@53fa8008 {
353 #address-cells = <1>;
354 #size-cells = <0>;
355 compatible = "fsl,imx53-ldb";
356 reg = <0x53fa8008 0x4>;
357 gpr = <&gpr>;
358 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
359 <&clks IMX5_CLK_LDB_DI1_SEL>,
360 <&clks IMX5_CLK_IPU_DI0_SEL>,
361 <&clks IMX5_CLK_IPU_DI1_SEL>,
362 <&clks IMX5_CLK_LDB_DI0_GATE>,
363 <&clks IMX5_CLK_LDB_DI1_GATE>;
364 clock-names = "di0_pll", "di1_pll",
365 "di0_sel", "di1_sel",
366 "di0", "di1";
367 status = "disabled";
369 lvds-channel@0 {
370 reg = <0>;
371 crtcs = <&ipu 0>;
372 status = "disabled";
373 };
375 lvds-channel@1 {
376 reg = <1>;
377 crtcs = <&ipu 1>;
378 status = "disabled";
379 };
380 };
382 pwm1: pwm@53fb4000 {
383 #pwm-cells = <2>;
384 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
385 reg = <0x53fb4000 0x4000>;
386 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
387 <&clks IMX5_CLK_PWM1_HF_GATE>;
388 clock-names = "ipg", "per";
389 interrupts = <61>;
390 };
392 pwm2: pwm@53fb8000 {
393 #pwm-cells = <2>;
394 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
395 reg = <0x53fb8000 0x4000>;
396 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
397 <&clks IMX5_CLK_PWM2_HF_GATE>;
398 clock-names = "ipg", "per";
399 interrupts = <94>;
400 };
402 uart1: serial@53fbc000 {
403 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
404 reg = <0x53fbc000 0x4000>;
405 interrupts = <31>;
406 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
407 <&clks IMX5_CLK_UART1_PER_GATE>;
408 clock-names = "ipg", "per";
409 status = "disabled";
410 };
412 uart2: serial@53fc0000 {
413 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
414 reg = <0x53fc0000 0x4000>;
415 interrupts = <32>;
416 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
417 <&clks IMX5_CLK_UART2_PER_GATE>;
418 clock-names = "ipg", "per";
419 status = "disabled";
420 };
422 can1: can@53fc8000 {
423 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
424 reg = <0x53fc8000 0x4000>;
425 interrupts = <82>;
426 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
427 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
428 clock-names = "ipg", "per";
429 status = "disabled";
430 };
432 can2: can@53fcc000 {
433 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
434 reg = <0x53fcc000 0x4000>;
435 interrupts = <83>;
436 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
437 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
438 clock-names = "ipg", "per";
439 status = "disabled";
440 };
442 src: src@53fd0000 {
443 compatible = "fsl,imx53-src", "fsl,imx51-src";
444 reg = <0x53fd0000 0x4000>;
445 #reset-cells = <1>;
446 };
448 clks: ccm@53fd4000{
449 compatible = "fsl,imx53-ccm";
450 reg = <0x53fd4000 0x4000>;
451 interrupts = <0 71 0x04 0 72 0x04>;
452 #clock-cells = <1>;
453 };
455 gpio5: gpio@53fdc000 {
456 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
457 reg = <0x53fdc000 0x4000>;
458 interrupts = <103 104>;
459 gpio-controller;
460 #gpio-cells = <2>;
461 interrupt-controller;
462 #interrupt-cells = <2>;
463 };
465 gpio6: gpio@53fe0000 {
466 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
467 reg = <0x53fe0000 0x4000>;
468 interrupts = <105 106>;
469 gpio-controller;
470 #gpio-cells = <2>;
471 interrupt-controller;
472 #interrupt-cells = <2>;
473 };
475 gpio7: gpio@53fe4000 {
476 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
477 reg = <0x53fe4000 0x4000>;
478 interrupts = <107 108>;
479 gpio-controller;
480 #gpio-cells = <2>;
481 interrupt-controller;
482 #interrupt-cells = <2>;
483 };
485 i2c3: i2c@53fec000 {
486 #address-cells = <1>;
487 #size-cells = <0>;
488 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
489 reg = <0x53fec000 0x4000>;
490 interrupts = <64>;
491 clocks = <&clks IMX5_CLK_I2C3_GATE>;
492 status = "disabled";
493 };
495 uart4: serial@53ff0000 {
496 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
497 reg = <0x53ff0000 0x4000>;
498 interrupts = <13>;
499 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
500 <&clks IMX5_CLK_UART4_PER_GATE>;
501 clock-names = "ipg", "per";
502 status = "disabled";
503 };
504 };
506 aips@60000000 { /* AIPS2 */
507 compatible = "fsl,aips-bus", "simple-bus";
508 #address-cells = <1>;
509 #size-cells = <1>;
510 reg = <0x60000000 0x10000000>;
511 ranges;
513 iim: iim@63f98000 {
514 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
515 reg = <0x63f98000 0x4000>;
516 interrupts = <69>;
517 clocks = <&clks IMX5_CLK_IIM_GATE>;
518 };
520 uart5: serial@63f90000 {
521 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
522 reg = <0x63f90000 0x4000>;
523 interrupts = <86>;
524 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
525 <&clks IMX5_CLK_UART5_PER_GATE>;
526 clock-names = "ipg", "per";
527 status = "disabled";
528 };
530 owire: owire@63fa4000 {
531 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
532 reg = <0x63fa4000 0x4000>;
533 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
534 status = "disabled";
535 };
537 ecspi2: ecspi@63fac000 {
538 #address-cells = <1>;
539 #size-cells = <0>;
540 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
541 reg = <0x63fac000 0x4000>;
542 interrupts = <37>;
543 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
544 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
545 clock-names = "ipg", "per";
546 status = "disabled";
547 };
549 sdma: sdma@63fb0000 {
550 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
551 reg = <0x63fb0000 0x4000>;
552 interrupts = <6>;
553 clocks = <&clks IMX5_CLK_SDMA_GATE>,
554 <&clks IMX5_CLK_SDMA_GATE>;
555 clock-names = "ipg", "ahb";
556 #dma-cells = <3>;
557 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
558 };
560 cspi: cspi@63fc0000 {
561 #address-cells = <1>;
562 #size-cells = <0>;
563 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
564 reg = <0x63fc0000 0x4000>;
565 interrupts = <38>;
566 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
567 <&clks IMX5_CLK_CSPI_IPG_GATE>;
568 clock-names = "ipg", "per";
569 status = "disabled";
570 };
572 i2c2: i2c@63fc4000 {
573 #address-cells = <1>;
574 #size-cells = <0>;
575 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
576 reg = <0x63fc4000 0x4000>;
577 interrupts = <63>;
578 clocks = <&clks IMX5_CLK_I2C2_GATE>;
579 status = "disabled";
580 };
582 i2c1: i2c@63fc8000 {
583 #address-cells = <1>;
584 #size-cells = <0>;
585 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
586 reg = <0x63fc8000 0x4000>;
587 interrupts = <62>;
588 clocks = <&clks IMX5_CLK_I2C1_GATE>;
589 status = "disabled";
590 };
592 ssi1: ssi@63fcc000 {
593 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
594 reg = <0x63fcc000 0x4000>;
595 interrupts = <29>;
596 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
597 dmas = <&sdma 28 0 0>,
598 <&sdma 29 0 0>;
599 dma-names = "rx", "tx";
600 fsl,fifo-depth = <15>;
601 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
602 status = "disabled";
603 };
605 audmux: audmux@63fd0000 {
606 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
607 reg = <0x63fd0000 0x4000>;
608 status = "disabled";
609 };
611 nfc: nand@63fdb000 {
612 compatible = "fsl,imx53-nand";
613 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
614 interrupts = <8>;
615 clocks = <&clks IMX5_CLK_NFC_GATE>;
616 status = "disabled";
617 };
619 ssi3: ssi@63fe8000 {
620 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
621 reg = <0x63fe8000 0x4000>;
622 interrupts = <96>;
623 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
624 dmas = <&sdma 46 0 0>,
625 <&sdma 47 0 0>;
626 dma-names = "rx", "tx";
627 fsl,fifo-depth = <15>;
628 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
629 status = "disabled";
630 };
632 fec: ethernet@63fec000 {
633 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
634 reg = <0x63fec000 0x4000>;
635 interrupts = <87>;
636 clocks = <&clks IMX5_CLK_FEC_GATE>,
637 <&clks IMX5_CLK_FEC_GATE>,
638 <&clks IMX5_CLK_FEC_GATE>;
639 clock-names = "ipg", "ahb", "ptp";
640 status = "disabled";
641 };
643 tve: tve@63ff0000 {
644 compatible = "fsl,imx53-tve";
645 reg = <0x63ff0000 0x1000>;
646 interrupts = <92>;
647 clocks = <&clks IMX5_CLK_TVE_GATE>,
648 <&clks IMX5_CLK_IPU_DI1_SEL>;
649 clock-names = "tve", "di_sel";
650 crtcs = <&ipu 1>;
651 status = "disabled";
652 };
654 vpu: vpu@63ff4000 {
655 compatible = "fsl,imx53-vpu";
656 reg = <0x63ff4000 0x1000>;
657 interrupts = <9>;
658 clocks = <&clks IMX5_CLK_VPU_GATE>,
659 <&clks IMX5_CLK_VPU_GATE>;
660 clock-names = "per", "ahb";
661 iram = <&ocram>;
662 status = "disabled";
663 };
664 };
666 ocram: sram@f8000000 {
667 compatible = "mmio-sram";
668 reg = <0xf8000000 0x20000>;
669 clocks = <&clks IMX5_CLK_OCRAM>;
670 };
671 };
672 };