drivers/pinctrl/pinctrl-coh901.c

   1 /*
   2  * U300 GPIO module.
   3  *
   4  * Copyright (C) 2007-2011 ST-Ericsson AB
   5  * License terms: GNU General Public License (GPL) version 2
   6  * This can driver either of the two basic GPIO cores
   7  * available in the U300 platforms:
   8  * COH 901 335   - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0)
   9  * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
  10  * Author: Linus Walleij <linus.walleij@linaro.org>
  11  * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
  12  */
  13 #include <linux/module.h>
  14 #include <linux/irq.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/delay.h>
  17 #include <linux/errno.h>
  18 #include <linux/io.h>
  19 #include <linux/clk.h>
  20 #include <linux/err.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/gpio.h>
  23 #include <linux/list.h>
  24 #include <linux/slab.h>
  25 #include <linux/pinctrl/pinmux.h>
  26 #include <mach/gpio-u300.h>
  27
  28 /*
  29  * Bias modes for U300 GPIOs
  30  *
  31  * GPIO_U300_CONFIG_BIAS_UNKNOWN: this bias mode is not known to us
  32  * GPIO_U300_CONFIG_BIAS_FLOAT: no specific bias, the GPIO will float or state
  33  *      is not controlled by software
  34  * GPIO_U300_CONFIG_BIAS_PULL_UP: the GPIO will be pulled up (usually with high
  35  *      impedance to VDD)
  36  */
  37 #define GPIO_U300_CONFIG_BIAS_UNKNOWN   0x1000
  38 #define GPIO_U300_CONFIG_BIAS_FLOAT     0x1001
  39 #define GPIO_U300_CONFIG_BIAS_PULL_UP   0x1002
  40
  41 /*
  42  * Drive modes for U300 GPIOs (output)
  43  *
  44  * GPIO_U300_CONFIG_DRIVE_PUSH_PULL: the GPIO will be driven actively high and
  45  *      low, this is the most typical case and is typically achieved with two
  46  *      active transistors on the output
  47  * GPIO_U300_CONFIG_DRIVE_OPEN_DRAIN: the GPIO will be driven with open drain
  48  *      (open collector) which means it is usually wired with other output
  49  *      ports which are then pulled up with an external resistor
  50  * GPIO_U300_CONFIG_DRIVE_OPEN_SOURCE: the GPIO will be driven with open drain
  51  *      (open emitter) which is the same as open drain mutatis mutandis but
  52  *      pulled to ground
  53  */
  54 #define GPIO_U300_CONFIG_DRIVE_PUSH_PULL        0x2000
  55 #define GPIO_U300_CONFIG_DRIVE_OPEN_DRAIN       0x2001
  56 #define GPIO_U300_CONFIG_DRIVE_OPEN_SOURCE      0x2002
  57
  58 /*
  59  * Register definitions for COH 901 335 variant
  60  */
  61 #define U300_335_PORT_STRIDE                            (0x1C)
  62 /* Port X Pin Data Register 32bit, this is both input and output (R/W) */
  63 #define U300_335_PXPDIR                                 (0x00)
  64 #define U300_335_PXPDOR                                 (0x00)
  65 /* Port X Pin Config Register 32bit (R/W) */
  66 #define U300_335_PXPCR                                  (0x04)
  67 /* This register layout is the same in both blocks */
  68 #define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK              (0x0000FFFFUL)
  69 #define U300_GPIO_PXPCR_PIN_MODE_MASK                   (0x00000003UL)
  70 #define U300_GPIO_PXPCR_PIN_MODE_SHIFT                  (0x00000002UL)
  71 #define U300_GPIO_PXPCR_PIN_MODE_INPUT                  (0x00000000UL)
  72 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL       (0x00000001UL)
  73 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN      (0x00000002UL)
  74 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE     (0x00000003UL)
  75 /* Port X Interrupt Event Register 32bit (R/W) */
  76 #define U300_335_PXIEV                                  (0x08)
  77 /* Port X Interrupt Enable Register 32bit (R/W) */
  78 #define U300_335_PXIEN                                  (0x0C)
  79 /* Port X Interrupt Force Register 32bit (R/W) */
  80 #define U300_335_PXIFR                                  (0x10)
  81 /* Port X Interrupt Config Register 32bit (R/W) */
  82 #define U300_335_PXICR                                  (0x14)
  83 /* This register layout is the same in both blocks */
  84 #define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK             (0x000000FFUL)
  85 #define U300_GPIO_PXICR_IRQ_CONFIG_MASK                 (0x00000001UL)
  86 #define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE         (0x00000000UL)
  87 #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE          (0x00000001UL)
  88 /* Port X Pull-up Enable Register 32bit (R/W) */
  89 #define U300_335_PXPER                                  (0x18)
  90 /* This register layout is the same in both blocks */
  91 #define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK        (0x000000FFUL)
  92 #define U300_GPIO_PXPER_PULL_UP_DISABLE                 (0x00000001UL)
  93 /* Control Register 32bit (R/W) */
  94 #define U300_335_CR                                     (0x54)
  95 #define U300_335_CR_BLOCK_CLOCK_ENABLE                  (0x00000001UL)
  96
  97 /*
  98  * Register definitions for COH 901 571 / 3 variant
  99  */
 100 #define U300_571_PORT_STRIDE                            (0x30)
 101 /*
 102  * Control Register 32bit (R/W)
 103  * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
 104  * gives the number of GPIO pins.
 105  * bit 8-2  (mask 0x000001FC) contains the core version ID.
 106  */
 107 #define U300_571_CR                                     (0x00)
 108 #define U300_571_CR_SYNC_SEL_ENABLE                     (0x00000002UL)
 109 #define U300_571_CR_BLOCK_CLKRQ_ENABLE                  (0x00000001UL)
 110 /*
 111  * These registers have the same layout and function as the corresponding
 112  * COH 901 335 registers, just at different offset.
 113  */
 114 #define U300_571_PXPDIR                                 (0x04)
 115 #define U300_571_PXPDOR                                 (0x08)
 116 #define U300_571_PXPCR                                  (0x0C)
 117 #define U300_571_PXPER                                  (0x10)
 118 #define U300_571_PXIEV                                  (0x14)
 119 #define U300_571_PXIEN                                  (0x18)
 120 #define U300_571_PXIFR                                  (0x1C)
 121 #define U300_571_PXICR                                  (0x20)
 122
 123 /* 8 bits per port, no version has more than 7 ports */
 124 #define U300_GPIO_PINS_PER_PORT 8
 125 #define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * 7)
 126
 127 struct u300_gpio {
 128         struct gpio_chip chip;
 129         struct list_head port_list;
 130         struct clk *clk;
 131         struct resource *memres;
 132         void __iomem *base;
 133         struct device *dev;
 134         int irq_base;
 135         u32 stride;
 136         /* Register offsets */
 137         u32 pcr;
 138         u32 dor;
 139         u32 dir;
 140         u32 per;
 141         u32 icr;
 142         u32 ien;
 143         u32 iev;
 144 };
 145
 146 struct u300_gpio_port {
 147         struct list_head node;
 148         struct u300_gpio *gpio;
 149         char name[8];
 150         int irq;
 151         int number;
 152         u8 toggle_edge_mode;
 153 };
 154
 155 /*
 156  * Macro to expand to read a specific register found in the "gpio"
 157  * struct. It requires the struct u300_gpio *gpio variable to exist in
 158  * its context. It calculates the port offset from the given pin
 159  * offset, muliplies by the port stride and adds the register offset
 160  * so it provides a pointer to the desired register.
 161  */
 162 #define U300_PIN_REG(pin, reg) \
 163         (gpio->base + (pin >> 3) * gpio->stride + gpio->reg)
 164
 165 /*
 166  * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO
 167  * register.
 168  */
 169 #define U300_PIN_BIT(pin) \
 170         (1 << (pin & 0x07))
 171
 172 struct u300_gpio_confdata {
 173         u16 bias_mode;
 174         bool output;
 175         int outval;
 176 };
 177
 178 /* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */
 179 #define BS335_GPIO_NUM_PORTS 7
 180 /* BS365 has five ports of 8 bits each = GPIO pins 0..39 */
 181 #define BS365_GPIO_NUM_PORTS 5
 182
 183 #define U300_FLOATING_INPUT { \
 184         .bias_mode = GPIO_U300_CONFIG_BIAS_FLOAT, \
 185         .output = false, \
 186 }
 187
 188 #define U300_PULL_UP_INPUT { \
 189         .bias_mode = GPIO_U300_CONFIG_BIAS_PULL_UP, \
 190         .output = false, \
 191 }
 192
 193 #define U300_OUTPUT_LOW { \
 194         .output = true, \
 195         .outval = 0, \
 196 }
 197
 198 #define U300_OUTPUT_HIGH { \
 199         .output = true, \
 200         .outval = 1, \
 201 }
 202
 203
 204 /* Initial configuration */
 205 static const struct __initdata u300_gpio_confdata
 206 bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
 207         /* Port 0, pins 0-7 */
 208         {
 209                 U300_FLOATING_INPUT,
 210                 U300_OUTPUT_HIGH,
 211                 U300_FLOATING_INPUT,
 212                 U300_OUTPUT_LOW,
 213                 U300_OUTPUT_LOW,
 214                 U300_OUTPUT_LOW,
 215                 U300_OUTPUT_LOW,
 216                 U300_OUTPUT_LOW,
 217         },
 218         /* Port 1, pins 0-7 */
 219         {
 220                 U300_OUTPUT_LOW,
 221                 U300_OUTPUT_LOW,
 222                 U300_OUTPUT_LOW,
 223                 U300_PULL_UP_INPUT,
 224                 U300_FLOATING_INPUT,
 225                 U300_OUTPUT_HIGH,
 226                 U300_OUTPUT_LOW,
 227                 U300_OUTPUT_LOW,
 228         },
 229         /* Port 2, pins 0-7 */
 230         {
 231                 U300_FLOATING_INPUT,
 232                 U300_FLOATING_INPUT,
 233                 U300_FLOATING_INPUT,
 234                 U300_FLOATING_INPUT,
 235                 U300_OUTPUT_LOW,
 236                 U300_PULL_UP_INPUT,
 237                 U300_OUTPUT_LOW,
 238                 U300_PULL_UP_INPUT,
 239         },
 240         /* Port 3, pins 0-7 */
 241         {
 242                 U300_PULL_UP_INPUT,
 243                 U300_OUTPUT_LOW,
 244                 U300_FLOATING_INPUT,
 245                 U300_FLOATING_INPUT,
 246                 U300_FLOATING_INPUT,
 247                 U300_FLOATING_INPUT,
 248                 U300_FLOATING_INPUT,
 249                 U300_FLOATING_INPUT,
 250         },
 251         /* Port 4, pins 0-7 */
 252         {
 253                 U300_FLOATING_INPUT,
 254                 U300_FLOATING_INPUT,
 255                 U300_FLOATING_INPUT,
 256                 U300_FLOATING_INPUT,
 257                 U300_FLOATING_INPUT,
 258                 U300_FLOATING_INPUT,
 259                 U300_FLOATING_INPUT,
 260                 U300_FLOATING_INPUT,
 261         },
 262         /* Port 5, pins 0-7 */
 263         {
 264                 U300_FLOATING_INPUT,
 265                 U300_FLOATING_INPUT,
 266                 U300_FLOATING_INPUT,
 267                 U300_FLOATING_INPUT,
 268                 U300_FLOATING_INPUT,
 269                 U300_FLOATING_INPUT,
 270                 U300_FLOATING_INPUT,
 271                 U300_FLOATING_INPUT,
 272         },
 273         /* Port 6, pind 0-7 */
 274         {
 275                 U300_FLOATING_INPUT,
 276                 U300_FLOATING_INPUT,
 277                 U300_FLOATING_INPUT,
 278                 U300_FLOATING_INPUT,
 279                 U300_FLOATING_INPUT,
 280                 U300_FLOATING_INPUT,
 281                 U300_FLOATING_INPUT,
 282                 U300_FLOATING_INPUT,
 283         }
 284 };
 285
 286 static const struct __initdata u300_gpio_confdata
 287 bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
 288         /* Port 0, pins 0-7 */
 289         {
 290                 U300_FLOATING_INPUT,
 291                 U300_OUTPUT_LOW,
 292                 U300_FLOATING_INPUT,
 293                 U300_OUTPUT_LOW,
 294                 U300_OUTPUT_LOW,
 295                 U300_OUTPUT_LOW,
 296                 U300_PULL_UP_INPUT,
 297                 U300_FLOATING_INPUT,
 298         },
 299         /* Port 1, pins 0-7 */
 300         {
 301                 U300_OUTPUT_LOW,
 302                 U300_FLOATING_INPUT,
 303                 U300_OUTPUT_LOW,
 304                 U300_FLOATING_INPUT,
 305                 U300_FLOATING_INPUT,
 306                 U300_OUTPUT_HIGH,
 307                 U300_OUTPUT_LOW,
 308                 U300_OUTPUT_LOW,
 309         },
 310         /* Port 2, pins 0-7 */
 311         {
 312                 U300_FLOATING_INPUT,
 313                 U300_PULL_UP_INPUT,
 314                 U300_OUTPUT_LOW,
 315                 U300_OUTPUT_LOW,
 316                 U300_PULL_UP_INPUT,
 317                 U300_PULL_UP_INPUT,
 318                 U300_PULL_UP_INPUT,
 319                 U300_PULL_UP_INPUT,
 320         },
 321         /* Port 3, pins 0-7 */
 322         {
 323                 U300_PULL_UP_INPUT,
 324                 U300_PULL_UP_INPUT,
 325                 U300_PULL_UP_INPUT,
 326                 U300_PULL_UP_INPUT,
 327                 U300_PULL_UP_INPUT,
 328                 U300_PULL_UP_INPUT,
 329                 U300_PULL_UP_INPUT,
 330                 U300_PULL_UP_INPUT,
 331         },
 332         /* Port 4, pins 0-7 */
 333         {
 334                 U300_PULL_UP_INPUT,
 335                 U300_PULL_UP_INPUT,
 336                 U300_PULL_UP_INPUT,
 337                 U300_PULL_UP_INPUT,
 338                 /* These 4 pins doesn't exist on DB3210 */
 339                 U300_OUTPUT_LOW,
 340                 U300_OUTPUT_LOW,
 341                 U300_OUTPUT_LOW,
 342                 U300_OUTPUT_LOW,
 343         }
 344 };
 345
 346 /**
 347  * to_u300_gpio() - get the pointer to u300_gpio
 348  * @chip: the gpio chip member of the structure u300_gpio
 349  */
 350 static inline struct u300_gpio *to_u300_gpio(struct gpio_chip *chip)
 351 {
 352         return container_of(chip, struct u300_gpio, chip);
 353 }
 354
 355 static int u300_gpio_request(struct gpio_chip *chip, unsigned offset)
 356 {
 357         /*
 358          * Map back to global GPIO space and request muxing, the direction
 359          * parameter does not matter for this controller.
 360          */
 361         int gpio = chip->base + offset;
 362
 363         return pinmux_request_gpio(gpio);
 364 }
 365
 366 static void u300_gpio_free(struct gpio_chip *chip, unsigned offset)
 367 {
 368         int gpio = chip->base + offset;
 369
 370         pinmux_free_gpio(gpio);
 371 }
 372
 373 static int u300_gpio_get(struct gpio_chip *chip, unsigned offset)
 374 {
 375         struct u300_gpio *gpio = to_u300_gpio(chip);
 376
 377         return readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset);
 378 }
 379
 380 static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 381 {
 382         struct u300_gpio *gpio = to_u300_gpio(chip);
 383         unsigned long flags;
 384         u32 val;
 385
 386         local_irq_save(flags);
 387
 388         val = readl(U300_PIN_REG(offset, dor));
 389         if (value)
 390                 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
 391         else
 392                 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
 393
 394         local_irq_restore(flags);
 395 }
 396
 397 static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 398 {
 399         struct u300_gpio *gpio = to_u300_gpio(chip);
 400         unsigned long flags;
 401         u32 val;
 402
 403         local_irq_save(flags);
 404         val = readl(U300_PIN_REG(offset, pcr));
 405         /* Mask out this pin, note 2 bits per setting */
 406         val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
 407         writel(val, U300_PIN_REG(offset, pcr));
 408         local_irq_restore(flags);
 409         return 0;
 410 }
 411
 412 static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 413                                       int value)
 414 {
 415         struct u300_gpio *gpio = to_u300_gpio(chip);
 416         unsigned long flags;
 417         u32 oldmode;
 418         u32 val;
 419
 420         local_irq_save(flags);
 421         val = readl(U300_PIN_REG(offset, pcr));
 422         /*
 423          * Drive mode must be set by the special mode set function, set
 424          * push/pull mode by default if no mode has been selected.
 425          */
 426         oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK <<
 427                          ((offset & 0x07) << 1));
 428         /* mode = 0 means input, else some mode is already set */
 429         if (oldmode == 0) {
 430                 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK <<
 431                          ((offset & 0x07) << 1));
 432                 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
 433                         << ((offset & 0x07) << 1));
 434                 writel(val, U300_PIN_REG(offset, pcr));
 435         }
 436         u300_gpio_set(chip, offset, value);
 437         local_irq_restore(flags);
 438         return 0;
 439 }
 440
 441 static int u300_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 442 {
 443         struct u300_gpio *gpio = to_u300_gpio(chip);
 444         int retirq = gpio->irq_base + offset;
 445
 446         dev_dbg(gpio->dev, "request IRQ for GPIO %d, return %d\n", offset,
 447                 retirq);
 448         return retirq;
 449 }
 450
 451 static int u300_gpio_config(struct gpio_chip *chip, unsigned offset,
 452                      u16 param, unsigned long *data)
 453 {
 454         struct u300_gpio *gpio = to_u300_gpio(chip);
 455         unsigned long flags;
 456         u32 val;
 457
 458         local_irq_save(flags);
 459         switch (param) {
 460         case GPIO_U300_CONFIG_BIAS_UNKNOWN:
 461         case GPIO_U300_CONFIG_BIAS_FLOAT:
 462                 val = readl(U300_PIN_REG(offset, per));
 463                 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
 464                 break;
 465         case GPIO_U300_CONFIG_BIAS_PULL_UP:
 466                 val = readl(U300_PIN_REG(offset, per));
 467                 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
 468                 break;
 469         case GPIO_U300_CONFIG_DRIVE_PUSH_PULL:
 470                 val = readl(U300_PIN_REG(offset, pcr));
 471                 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
 472                          << ((offset & 0x07) << 1));
 473                 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
 474                         << ((offset & 0x07) << 1));
 475                 writel(val, U300_PIN_REG(offset, pcr));
 476                 break;
 477         case GPIO_U300_CONFIG_DRIVE_OPEN_DRAIN:
 478                 val = readl(U300_PIN_REG(offset, pcr));
 479                 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
 480                          << ((offset & 0x07) << 1));
 481                 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN
 482                         << ((offset & 0x07) << 1));
 483                 writel(val, U300_PIN_REG(offset, pcr));
 484                 break;
 485         case GPIO_U300_CONFIG_DRIVE_OPEN_SOURCE:
 486                 val = readl(U300_PIN_REG(offset, pcr));
 487                 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
 488                          << ((offset & 0x07) << 1));
 489                 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE
 490                         << ((offset & 0x07) << 1));
 491                 writel(val, U300_PIN_REG(offset, pcr));
 492                 break;
 493         default:
 494                 local_irq_restore(flags);
 495                 dev_err(gpio->dev, "illegal configuration requested\n");
 496                 return -EINVAL;
 497         }
 498         local_irq_restore(flags);
 499         return 0;
 500 }
 501
 502 static struct gpio_chip u300_gpio_chip = {
 503         .label                  = "u300-gpio-chip",
 504         .owner                  = THIS_MODULE,
 505         .request                = u300_gpio_request,
 506         .free                   = u300_gpio_free,
 507         .get                    = u300_gpio_get,
 508         .set                    = u300_gpio_set,
 509         .direction_input        = u300_gpio_direction_input,
 510         .direction_output       = u300_gpio_direction_output,
 511         .to_irq                 = u300_gpio_to_irq,
 512 };
 513
 514 static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset)
 515 {
 516         u32 val;
 517
 518         val = readl(U300_PIN_REG(offset, icr));
 519         /* Set mode depending on state */
 520         if (u300_gpio_get(&gpio->chip, offset)) {
 521                 /* High now, let's trigger on falling edge next then */
 522                 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
 523                 dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n",
 524                         offset);
 525         } else {
 526                 /* Low now, let's trigger on rising edge next then */
 527                 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
 528                 dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n",
 529                         offset);
 530         }
 531 }
 532
 533 static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger)
 534 {
 535         struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
 536         struct u300_gpio *gpio = port->gpio;
 537         int offset = d->irq - gpio->irq_base;
 538         u32 val;
 539
 540         if ((trigger & IRQF_TRIGGER_RISING) &&
 541             (trigger & IRQF_TRIGGER_FALLING)) {
 542                 /*
 543                  * The GPIO block can only trigger on falling OR rising edges,
 544                  * not both. So we need to toggle the mode whenever the pin
 545                  * goes from one state to the other with a special state flag
 546                  */
 547                 dev_dbg(gpio->dev,
 548                         "trigger on both rising and falling edge on pin %d\n",
 549                         offset);
 550                 port->toggle_edge_mode |= U300_PIN_BIT(offset);
 551                 u300_toggle_trigger(gpio, offset);
 552         } else if (trigger & IRQF_TRIGGER_RISING) {
 553                 dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n",
 554                         offset);
 555                 val = readl(U300_PIN_REG(offset, icr));
 556                 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
 557                 port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
 558         } else if (trigger & IRQF_TRIGGER_FALLING) {
 559                 dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n",
 560                         offset);
 561                 val = readl(U300_PIN_REG(offset, icr));
 562                 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
 563                 port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
 564         }
 565
 566         return 0;
 567 }
 568
 569 static void u300_gpio_irq_enable(struct irq_data *d)
 570 {
 571         struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
 572         struct u300_gpio *gpio = port->gpio;
 573         int offset = d->irq - gpio->irq_base;
 574         u32 val;
 575         unsigned long flags;
 576
 577         local_irq_save(flags);
 578         val = readl(U300_PIN_REG(offset, ien));
 579         writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
 580         local_irq_restore(flags);
 581 }
 582
 583 static void u300_gpio_irq_disable(struct irq_data *d)
 584 {
 585         struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
 586         struct u300_gpio *gpio = port->gpio;
 587         int offset = d->irq - gpio->irq_base;
 588         u32 val;
 589         unsigned long flags;
 590
 591         local_irq_save(flags);
 592         val = readl(U300_PIN_REG(offset, ien));
 593         writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
 594         local_irq_restore(flags);
 595 }
 596
 597 static struct irq_chip u300_gpio_irqchip = {
 598         .name                   = "u300-gpio-irqchip",
 599         .irq_enable             = u300_gpio_irq_enable,
 600         .irq_disable            = u300_gpio_irq_disable,
 601         .irq_set_type           = u300_gpio_irq_type,
 602
 603 };
 604
 605 static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 606 {
 607         struct u300_gpio_port *port = irq_get_handler_data(irq);
 608         struct u300_gpio *gpio = port->gpio;
 609         int pinoffset = port->number << 3; /* get the right stride */
 610         unsigned long val;
 611
 612         desc->irq_data.chip->irq_ack(&desc->irq_data);
 613         /* Read event register */
 614         val = readl(U300_PIN_REG(pinoffset, iev));
 615         /* Mask relevant bits */
 616         val &= 0xFFU; /* 8 bits per port */
 617         /* ACK IRQ (clear event) */
 618         writel(val, U300_PIN_REG(pinoffset, iev));
 619
 620         /* Call IRQ handler */
 621         if (val != 0) {
 622                 int irqoffset;
 623
 624                 for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) {
 625                         int pin_irq = gpio->irq_base + (port->number << 3)
 626                                 + irqoffset;
 627                         int offset = pinoffset + irqoffset;
 628
 629                         dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n",
 630                                 pin_irq, offset);
 631                         generic_handle_irq(pin_irq);
 632                         /*
 633                          * Triggering IRQ on both rising and falling edge
 634                          * needs mockery
 635                          */
 636                         if (port->toggle_edge_mode & U300_PIN_BIT(offset))
 637                                 u300_toggle_trigger(gpio, offset);
 638                 }
 639         }
 640
 641         desc->irq_data.chip->irq_unmask(&desc->irq_data);
 642 }
 643
 644 static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
 645                                       int offset,
 646                                       const struct u300_gpio_confdata *conf)
 647 {
 648         /* Set mode: input or output */
 649         if (conf->output) {
 650                 u300_gpio_direction_output(&gpio->chip, offset, conf->outval);
 651
 652                 /* Deactivate bias mode for output */
 653                 u300_gpio_config(&gpio->chip, offset,
 654                                  GPIO_U300_CONFIG_BIAS_FLOAT,
 655                                  NULL);
 656
 657                 /* Set drive mode for output */
 658                 u300_gpio_config(&gpio->chip, offset,
 659                                  GPIO_U300_CONFIG_DRIVE_PUSH_PULL, NULL);
 660
 661                 dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n",
 662                         offset, conf->outval);
 663         } else {
 664                 u300_gpio_direction_input(&gpio->chip, offset);
 665
 666                 /* Always set output low on input pins */
 667                 u300_gpio_set(&gpio->chip, offset, 0);
 668
 669                 /* Set bias mode for input */
 670                 u300_gpio_config(&gpio->chip, offset, conf->bias_mode, NULL);
 671
 672                 dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n",
 673                         offset, conf->bias_mode);
 674         }
 675 }
 676
 677 static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio,
 678                                      struct u300_gpio_platform *plat)
 679 {
 680         int i, j;
 681
 682         /* Write default config and values to all pins */
 683         for (i = 0; i < plat->ports; i++) {
 684                 for (j = 0; j < 8; j++) {
 685                         const struct u300_gpio_confdata *conf;
 686                         int offset = (i*8) + j;
 687
 688                         if (plat->variant == U300_GPIO_COH901571_3_BS335)
 689                                 conf = &bs335_gpio_config[i][j];
 690                         else if (plat->variant == U300_GPIO_COH901571_3_BS365)
 691                                 conf = &bs365_gpio_config[i][j];
 692                         else
 693                                 break;
 694
 695                         u300_gpio_init_pin(gpio, offset, conf);
 696                 }
 697         }
 698 }
 699
 700 static inline void u300_gpio_free_ports(struct u300_gpio *gpio)
 701 {
 702         struct u300_gpio_port *port;
 703         struct list_head *p, *n;
 704
 705         list_for_each_safe(p, n, &gpio->port_list) {
 706                 port = list_entry(p, struct u300_gpio_port, node);
 707                 list_del(&port->node);
 708                 free_irq(port->irq, port);
 709                 kfree(port);
 710         }
 711 }
 712
 713 static int __init u300_gpio_probe(struct platform_device *pdev)
 714 {
 715         struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
 716         struct u300_gpio *gpio;
 717         int err = 0;
 718         int portno;
 719         u32 val;
 720         u32 ifr;
 721         int i;
 722
 723         gpio = kzalloc(sizeof(struct u300_gpio), GFP_KERNEL);
 724         if (gpio == NULL) {
 725                 dev_err(&pdev->dev, "failed to allocate memory\n");
 726                 return -ENOMEM;
 727         }
 728
 729         gpio->chip = u300_gpio_chip;
 730         gpio->chip.ngpio = plat->ports * U300_GPIO_PINS_PER_PORT;
 731         gpio->irq_base = plat->gpio_irq_base;
 732         gpio->chip.dev = &pdev->dev;
 733         gpio->chip.base = plat->gpio_base;
 734         gpio->dev = &pdev->dev;
 735
 736         /* Get GPIO clock */
 737         gpio->clk = clk_get(gpio->dev, NULL);
 738         if (IS_ERR(gpio->clk)) {
 739                 err = PTR_ERR(gpio->clk);
 740                 dev_err(gpio->dev, "could not get GPIO clock\n");
 741                 goto err_no_clk;
 742         }
 743         err = clk_enable(gpio->clk);
 744         if (err) {
 745                 dev_err(gpio->dev, "could not enable GPIO clock\n");
 746                 goto err_no_clk_enable;
 747         }
 748
 749         gpio->memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 750         if (!gpio->memres) {
 751                 dev_err(gpio->dev, "could not get GPIO memory resource\n");
 752                 err = -ENODEV;
 753                 goto err_no_resource;
 754         }
 755
 756         if (!request_mem_region(gpio->memres->start,
 757                                 resource_size(gpio->memres),
 758                                 "GPIO Controller")) {
 759                 err = -ENODEV;
 760                 goto err_no_ioregion;
 761         }
 762
 763         gpio->base = ioremap(gpio->memres->start, resource_size(gpio->memres));
 764         if (!gpio->base) {
 765                 err = -ENOMEM;
 766                 goto err_no_ioremap;
 767         }
 768
 769         if (plat->variant == U300_GPIO_COH901335) {
 770                 dev_info(gpio->dev,
 771                          "initializing GPIO Controller COH 901 335\n");
 772                 gpio->stride = U300_335_PORT_STRIDE;
 773                 gpio->pcr = U300_335_PXPCR;
 774                 gpio->dor = U300_335_PXPDOR;
 775                 gpio->dir = U300_335_PXPDIR;
 776                 gpio->per = U300_335_PXPER;
 777                 gpio->icr = U300_335_PXICR;
 778                 gpio->ien = U300_335_PXIEN;
 779                 gpio->iev = U300_335_PXIEV;
 780                 ifr = U300_335_PXIFR;
 781
 782                 /* Turn on the GPIO block */
 783                 writel(U300_335_CR_BLOCK_CLOCK_ENABLE,
 784                        gpio->base + U300_335_CR);
 785         } else if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
 786                    plat->variant == U300_GPIO_COH901571_3_BS365) {
 787                 dev_info(gpio->dev,
 788                          "initializing GPIO Controller COH 901 571/3\n");
 789                 gpio->stride = U300_571_PORT_STRIDE;
 790                 gpio->pcr = U300_571_PXPCR;
 791                 gpio->dor = U300_571_PXPDOR;
 792                 gpio->dir = U300_571_PXPDIR;
 793                 gpio->per = U300_571_PXPER;
 794                 gpio->icr = U300_571_PXICR;
 795                 gpio->ien = U300_571_PXIEN;
 796                 gpio->iev = U300_571_PXIEV;
 797                 ifr = U300_571_PXIFR;
 798
 799                 val = readl(gpio->base + U300_571_CR);
 800                 dev_info(gpio->dev, "COH901571/3 block version: %d, " \
 801                          "number of cores: %d totalling %d pins\n",
 802                          ((val & 0x000001FC) >> 2),
 803                          ((val & 0x0000FE00) >> 9),
 804                          ((val & 0x0000FE00) >> 9) * 8);
 805                 writel(U300_571_CR_BLOCK_CLKRQ_ENABLE,
 806                        gpio->base + U300_571_CR);
 807                 u300_gpio_init_coh901571(gpio, plat);
 808         } else {
 809                 dev_err(gpio->dev, "unknown block variant\n");
 810                 err = -ENODEV;
 811                 goto err_unknown_variant;
 812         }
 813
 814         /* Add each port with its IRQ separately */
 815         INIT_LIST_HEAD(&gpio->port_list);
 816         for (portno = 0 ; portno < plat->ports; portno++) {
 817                 struct u300_gpio_port *port =
 818                         kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL);
 819
 820                 if (!port) {
 821                         dev_err(gpio->dev, "out of memory\n");
 822                         err = -ENOMEM;
 823                         goto err_no_port;
 824                 }
 825
 826                 snprintf(port->name, 8, "gpio%d", portno);
 827                 port->number = portno;
 828                 port->gpio = gpio;
 829
 830                 port->irq = platform_get_irq_byname(pdev,
 831                                                     port->name);
 832
 833                 dev_dbg(gpio->dev, "register IRQ %d for %s\n", port->irq,
 834                         port->name);
 835
 836                 irq_set_chained_handler(port->irq, u300_gpio_irq_handler);
 837                 irq_set_handler_data(port->irq, port);
 838
 839                 /* For each GPIO pin set the unique IRQ handler */
 840                 for (i = 0; i < U300_GPIO_PINS_PER_PORT; i++) {
 841                         int irqno = gpio->irq_base + (portno << 3) + i;
 842
 843                         dev_dbg(gpio->dev, "handler for IRQ %d on %s\n",
 844                                 irqno, port->name);
 845                         irq_set_chip_and_handler(irqno, &u300_gpio_irqchip,
 846                                                  handle_simple_irq);
 847                         set_irq_flags(irqno, IRQF_VALID);
 848                         irq_set_chip_data(irqno, port);
 849                 }
 850
 851                 /* Turns off irq force (test register) for this port */
 852                 writel(0x0, gpio->base + portno * gpio->stride + ifr);
 853
 854                 list_add_tail(&port->node, &gpio->port_list);
 855         }
 856         dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno);
 857
 858         err = gpiochip_add(&gpio->chip);
 859         if (err) {
 860                 dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
 861                 goto err_no_chip;
 862         }
 863
 864         platform_set_drvdata(pdev, gpio);
 865
 866         return 0;
 867
 868 err_no_chip:
 869 err_no_port:
 870         u300_gpio_free_ports(gpio);
 871 err_unknown_variant:
 872         iounmap(gpio->base);
 873 err_no_ioremap:
 874         release_mem_region(gpio->memres->start, resource_size(gpio->memres));
 875 err_no_ioregion:
 876 err_no_resource:
 877         clk_disable(gpio->clk);
 878 err_no_clk_enable:
 879         clk_put(gpio->clk);
 880 err_no_clk:
 881         kfree(gpio);
 882         dev_info(&pdev->dev, "module ERROR:%d\n", err);
 883         return err;
 884 }
 885
 886 static int __exit u300_gpio_remove(struct platform_device *pdev)
 887 {
 888         struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
 889         struct u300_gpio *gpio = platform_get_drvdata(pdev);
 890         int err;
 891
 892         /* Turn off the GPIO block */
 893         if (plat->variant == U300_GPIO_COH901335)
 894                 writel(0x00000000U, gpio->base + U300_335_CR);
 895         if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
 896             plat->variant == U300_GPIO_COH901571_3_BS365)
 897                 writel(0x00000000U, gpio->base + U300_571_CR);
 898
 899         err = gpiochip_remove(&gpio->chip);
 900         if (err < 0) {
 901                 dev_err(gpio->dev, "unable to remove gpiochip: %d\n", err);
 902                 return err;
 903         }
 904         u300_gpio_free_ports(gpio);
 905         iounmap(gpio->base);
 906         release_mem_region(gpio->memres->start,
 907                            resource_size(gpio->memres));
 908         clk_disable(gpio->clk);
 909         clk_put(gpio->clk);
 910         platform_set_drvdata(pdev, NULL);
 911         kfree(gpio);
 912         return 0;
 913 }
 914
 915 static struct platform_driver u300_gpio_driver = {
 916         .driver         = {
 917                 .name   = "u300-gpio",
 918         },
 919         .remove         = __exit_p(u300_gpio_remove),
 920 };
 921
 922
 923 static int __init u300_gpio_init(void)
 924 {
 925         return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe);
 926 }
 927
 928 static void __exit u300_gpio_exit(void)
 929 {
 930         platform_driver_unregister(&u300_gpio_driver);
 931 }
 932
 933 arch_initcall(u300_gpio_init);
 934 module_exit(u300_gpio_exit);
 935
 936 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
 937 MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver");
 938 MODULE_LICENSE("GPL");