2 * at91_can.c - CAN network driver for AT91 SoC CAN controller
4 * (C) 2007 by Hans J. Koch <hjk@linutronix.de>
5 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de>
7 * This software may be distributed under the terms of the GNU General
8 * Public License ("GPL") version 2 as distributed in the 'COPYING'
9 * file from the main directory of the linux kernel source.
11 * Send feedback to <socketcan-users@lists.berlios.de>
14 * Your platform definition file should specify something like:
16 * static struct at91_can_data ek_can_data = {
17 * transceiver_switch = sam9263ek_transceiver_switch,
20 * at91_add_device_can(&ek_can_data);
24 #include <linux/clk.h>
25 #include <linux/errno.h>
26 #include <linux/if_arp.h>
27 #include <linux/init.h>
28 #include <linux/interrupt.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/netdevice.h>
32 #include <linux/platform_device.h>
33 #include <linux/skbuff.h>
34 #include <linux/spinlock.h>
35 #include <linux/string.h>
36 #include <linux/types.h>
38 #include <linux/can.h>
39 #include <linux/can/dev.h>
40 #include <linux/can/error.h>
42 #include <mach/board.h>
44 #define DRV_NAME "at91_can"
45 #define AT91_NAPI_WEIGHT 12
51 #define AT91_MB_RX_NUM 12
52 #define AT91_MB_TX_SHIFT 2
54 #define AT91_MB_RX_FIRST 0
55 #define AT91_MB_RX_LAST (AT91_MB_RX_FIRST + AT91_MB_RX_NUM - 1)
57 #define AT91_MB_RX_MASK(i) ((1 << (i)) - 1)
58 #define AT91_MB_RX_SPLIT 8
59 #define AT91_MB_RX_LOW_LAST (AT91_MB_RX_SPLIT - 1)
60 #define AT91_MB_RX_LOW_MASK (AT91_MB_RX_MASK(AT91_MB_RX_SPLIT))
62 #define AT91_MB_TX_NUM (1 << AT91_MB_TX_SHIFT)
63 #define AT91_MB_TX_FIRST (AT91_MB_RX_LAST + 1)
64 #define AT91_MB_TX_LAST (AT91_MB_TX_FIRST + AT91_MB_TX_NUM - 1)
66 #define AT91_NEXT_PRIO_SHIFT (AT91_MB_TX_SHIFT)
67 #define AT91_NEXT_PRIO_MASK (0xf << AT91_MB_TX_SHIFT)
68 #define AT91_NEXT_MB_MASK (AT91_MB_TX_NUM - 1)
69 #define AT91_NEXT_MASK ((AT91_MB_TX_NUM - 1) | AT91_NEXT_PRIO_MASK)
71 /* Common registers */
86 /* Mailbox registers (0 <= i <= 15) */
87 #define AT91_MMR(i) (enum at91_reg)(0x200 + ((i) * 0x20))
88 #define AT91_MAM(i) (enum at91_reg)(0x204 + ((i) * 0x20))
89 #define AT91_MID(i) (enum at91_reg)(0x208 + ((i) * 0x20))
90 #define AT91_MFID(i) (enum at91_reg)(0x20C + ((i) * 0x20))
91 #define AT91_MSR(i) (enum at91_reg)(0x210 + ((i) * 0x20))
92 #define AT91_MDL(i) (enum at91_reg)(0x214 + ((i) * 0x20))
93 #define AT91_MDH(i) (enum at91_reg)(0x218 + ((i) * 0x20))
94 #define AT91_MCR(i) (enum at91_reg)(0x21C + ((i) * 0x20))
97 #define AT91_MR_CANEN BIT(0)
98 #define AT91_MR_LPM BIT(1)
99 #define AT91_MR_ABM BIT(2)
100 #define AT91_MR_OVL BIT(3)
101 #define AT91_MR_TEOF BIT(4)
102 #define AT91_MR_TTM BIT(5)
103 #define AT91_MR_TIMFRZ BIT(6)
104 #define AT91_MR_DRPT BIT(7)
106 #define AT91_SR_RBSY BIT(29)
108 #define AT91_MMR_PRIO_SHIFT (16)
110 #define AT91_MID_MIDE BIT(29)
112 #define AT91_MSR_MRTR BIT(20)
113 #define AT91_MSR_MABT BIT(22)
114 #define AT91_MSR_MRDY BIT(23)
115 #define AT91_MSR_MMI BIT(24)
117 #define AT91_MCR_MRTR BIT(20)
118 #define AT91_MCR_MTCR BIT(23)
122 AT91_MB_MODE_DISABLED
= 0,
124 AT91_MB_MODE_RX_OVRWR
= 2,
126 AT91_MB_MODE_CONSUMER
= 4,
127 AT91_MB_MODE_PRODUCER
= 5,
130 /* Interrupt mask bits */
131 #define AT91_IRQ_MB_RX ((1 << (AT91_MB_RX_LAST + 1)) \
132 - (1 << AT91_MB_RX_FIRST))
133 #define AT91_IRQ_MB_TX ((1 << (AT91_MB_TX_LAST + 1)) \
134 - (1 << AT91_MB_TX_FIRST))
135 #define AT91_IRQ_MB_ALL (AT91_IRQ_MB_RX | AT91_IRQ_MB_TX)
137 #define AT91_IRQ_ERRA (1 << 16)
138 #define AT91_IRQ_WARN (1 << 17)
139 #define AT91_IRQ_ERRP (1 << 18)
140 #define AT91_IRQ_BOFF (1 << 19)
141 #define AT91_IRQ_SLEEP (1 << 20)
142 #define AT91_IRQ_WAKEUP (1 << 21)
143 #define AT91_IRQ_TOVF (1 << 22)
144 #define AT91_IRQ_TSTP (1 << 23)
145 #define AT91_IRQ_CERR (1 << 24)
146 #define AT91_IRQ_SERR (1 << 25)
147 #define AT91_IRQ_AERR (1 << 26)
148 #define AT91_IRQ_FERR (1 << 27)
149 #define AT91_IRQ_BERR (1 << 28)
151 #define AT91_IRQ_ERR_ALL (0x1fff0000)
152 #define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \
153 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR)
154 #define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \
155 AT91_IRQ_ERRP | AT91_IRQ_BOFF)
157 #define AT91_IRQ_ALL (0x1fffffff)
160 struct can_priv can
; /* must be the first member! */
161 struct net_device
*dev
;
162 struct napi_struct napi
;
164 void __iomem
*reg_base
;
167 unsigned int tx_next
;
168 unsigned int tx_echo
;
169 unsigned int rx_next
;
172 struct at91_can_data
*pdata
;
175 static struct can_bittiming_const at91_bittiming_const
= {
186 static inline int get_tx_next_mb(const struct at91_priv
*priv
)
188 return (priv
->tx_next
& AT91_NEXT_MB_MASK
) + AT91_MB_TX_FIRST
;
191 static inline int get_tx_next_prio(const struct at91_priv
*priv
)
193 return (priv
->tx_next
>> AT91_NEXT_PRIO_SHIFT
) & 0xf;
196 static inline int get_tx_echo_mb(const struct at91_priv
*priv
)
198 return (priv
->tx_echo
& AT91_NEXT_MB_MASK
) + AT91_MB_TX_FIRST
;
201 static inline u32
at91_read(const struct at91_priv
*priv
, enum at91_reg reg
)
203 return readl(priv
->reg_base
+ reg
);
206 static inline void at91_write(const struct at91_priv
*priv
, enum at91_reg reg
,
209 writel(value
, priv
->reg_base
+ reg
);
212 static inline void set_mb_mode_prio(const struct at91_priv
*priv
,
213 unsigned int mb
, enum at91_mb_mode mode
, int prio
)
215 at91_write(priv
, AT91_MMR(mb
), (mode
<< 24) | (prio
<< 16));
218 static inline void set_mb_mode(const struct at91_priv
*priv
, unsigned int mb
,
219 enum at91_mb_mode mode
)
221 set_mb_mode_prio(priv
, mb
, mode
, 0);
225 * Swtich transceiver on or off
227 static void at91_transceiver_switch(const struct at91_priv
*priv
, int on
)
229 if (priv
->pdata
&& priv
->pdata
->transceiver_switch
)
230 priv
->pdata
->transceiver_switch(on
);
233 static void at91_setup_mailboxes(struct net_device
*dev
)
235 struct at91_priv
*priv
= netdev_priv(dev
);
239 * The first 12 mailboxes are used as a reception FIFO. The
240 * last mailbox is configured with overwrite option. The
241 * overwrite flag indicates a FIFO overflow.
243 for (i
= AT91_MB_RX_FIRST
; i
< AT91_MB_RX_LAST
; i
++)
244 set_mb_mode(priv
, i
, AT91_MB_MODE_RX
);
245 set_mb_mode(priv
, AT91_MB_RX_LAST
, AT91_MB_MODE_RX_OVRWR
);
247 /* The last 4 mailboxes are used for transmitting. */
248 for (i
= AT91_MB_TX_FIRST
; i
<= AT91_MB_TX_LAST
; i
++)
249 set_mb_mode_prio(priv
, i
, AT91_MB_MODE_TX
, 0);
251 /* Reset tx and rx helper pointers */
252 priv
->tx_next
= priv
->tx_echo
= priv
->rx_next
= 0;
255 static int at91_set_bittiming(struct net_device
*dev
)
257 const struct at91_priv
*priv
= netdev_priv(dev
);
258 const struct can_bittiming
*bt
= &priv
->can
.bittiming
;
261 reg_br
= ((priv
->can
.ctrlmode
& CAN_CTRLMODE_3_SAMPLES
) << 24) |
262 ((bt
->brp
- 1) << 16) | ((bt
->sjw
- 1) << 12) |
263 ((bt
->prop_seg
- 1) << 8) | ((bt
->phase_seg1
- 1) << 4) |
264 ((bt
->phase_seg2
- 1) << 0);
266 dev_info(dev
->dev
.parent
, "writing AT91_BR: 0x%08x\n", reg_br
);
268 at91_write(priv
, AT91_BR
, reg_br
);
273 static void at91_chip_start(struct net_device
*dev
)
275 struct at91_priv
*priv
= netdev_priv(dev
);
278 /* disable interrupts */
279 at91_write(priv
, AT91_IDR
, AT91_IRQ_ALL
);
282 reg_mr
= at91_read(priv
, AT91_MR
);
283 at91_write(priv
, AT91_MR
, reg_mr
& ~AT91_MR_CANEN
);
285 at91_setup_mailboxes(dev
);
286 at91_transceiver_switch(priv
, 1);
289 at91_write(priv
, AT91_MR
, AT91_MR_CANEN
);
291 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
293 /* Enable interrupts */
294 reg_ier
= AT91_IRQ_MB_RX
| AT91_IRQ_ERRP
| AT91_IRQ_ERR_FRAME
;
295 at91_write(priv
, AT91_IDR
, AT91_IRQ_ALL
);
296 at91_write(priv
, AT91_IER
, reg_ier
);
299 static void at91_chip_stop(struct net_device
*dev
, enum can_state state
)
301 struct at91_priv
*priv
= netdev_priv(dev
);
304 /* disable interrupts */
305 at91_write(priv
, AT91_IDR
, AT91_IRQ_ALL
);
307 reg_mr
= at91_read(priv
, AT91_MR
);
308 at91_write(priv
, AT91_MR
, reg_mr
& ~AT91_MR_CANEN
);
310 at91_transceiver_switch(priv
, 0);
311 priv
->can
.state
= state
;
315 * theory of operation:
317 * According to the datasheet priority 0 is the highest priority, 15
318 * is the lowest. If two mailboxes have the same priority level the
319 * message of the mailbox with the lowest number is sent first.
321 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then
322 * the next mailbox with prio 0, and so on, until all mailboxes are
323 * used. Then we start from the beginning with mailbox
324 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1
325 * prio 1. When we reach the last mailbox with prio 15, we have to
326 * stop sending, waiting for all messages to be delivered, then start
327 * again with mailbox AT91_MB_TX_FIRST prio 0.
329 * We use the priv->tx_next as counter for the next transmission
330 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits
331 * encode the mailbox number, the upper 4 bits the mailbox priority:
333 * priv->tx_next = (prio << AT91_NEXT_PRIO_SHIFT) ||
334 * (mb - AT91_MB_TX_FIRST);
337 static netdev_tx_t
at91_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
339 struct at91_priv
*priv
= netdev_priv(dev
);
340 struct net_device_stats
*stats
= &dev
->stats
;
341 struct can_frame
*cf
= (struct can_frame
*)skb
->data
;
342 unsigned int mb
, prio
;
343 u32 reg_mid
, reg_mcr
;
345 if (can_dropped_invalid_skb(dev
, skb
))
348 mb
= get_tx_next_mb(priv
);
349 prio
= get_tx_next_prio(priv
);
351 if (unlikely(!(at91_read(priv
, AT91_MSR(mb
)) & AT91_MSR_MRDY
))) {
352 netif_stop_queue(dev
);
354 dev_err(dev
->dev
.parent
,
355 "BUG! TX buffer full when queue awake!\n");
356 return NETDEV_TX_BUSY
;
359 if (cf
->can_id
& CAN_EFF_FLAG
)
360 reg_mid
= (cf
->can_id
& CAN_EFF_MASK
) | AT91_MID_MIDE
;
362 reg_mid
= (cf
->can_id
& CAN_SFF_MASK
) << 18;
364 reg_mcr
= ((cf
->can_id
& CAN_RTR_FLAG
) ? AT91_MCR_MRTR
: 0) |
365 (cf
->can_dlc
<< 16) | AT91_MCR_MTCR
;
367 /* disable MB while writing ID (see datasheet) */
368 set_mb_mode(priv
, mb
, AT91_MB_MODE_DISABLED
);
369 at91_write(priv
, AT91_MID(mb
), reg_mid
);
370 set_mb_mode_prio(priv
, mb
, AT91_MB_MODE_TX
, prio
);
372 at91_write(priv
, AT91_MDL(mb
), *(u32
*)(cf
->data
+ 0));
373 at91_write(priv
, AT91_MDH(mb
), *(u32
*)(cf
->data
+ 4));
375 /* This triggers transmission */
376 at91_write(priv
, AT91_MCR(mb
), reg_mcr
);
378 stats
->tx_bytes
+= cf
->can_dlc
;
379 dev
->trans_start
= jiffies
;
381 /* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */
382 can_put_echo_skb(skb
, dev
, mb
- AT91_MB_TX_FIRST
);
385 * we have to stop the queue and deliver all messages in case
386 * of a prio+mb counter wrap around. This is the case if
387 * tx_next buffer prio and mailbox equals 0.
389 * also stop the queue if next buffer is still in use
393 if (!(at91_read(priv
, AT91_MSR(get_tx_next_mb(priv
))) &
395 (priv
->tx_next
& AT91_NEXT_MASK
) == 0)
396 netif_stop_queue(dev
);
398 /* Enable interrupt for this mailbox */
399 at91_write(priv
, AT91_IER
, 1 << mb
);
405 * at91_activate_rx_low - activate lower rx mailboxes
408 * Reenables the lower mailboxes for reception of new CAN messages
410 static inline void at91_activate_rx_low(const struct at91_priv
*priv
)
412 u32 mask
= AT91_MB_RX_LOW_MASK
;
413 at91_write(priv
, AT91_TCR
, mask
);
417 * at91_activate_rx_mb - reactive single rx mailbox
419 * @mb: mailbox to reactivate
421 * Reenables given mailbox for reception of new CAN messages
423 static inline void at91_activate_rx_mb(const struct at91_priv
*priv
,
427 at91_write(priv
, AT91_TCR
, mask
);
431 * at91_rx_overflow_err - send error frame due to rx overflow
434 static void at91_rx_overflow_err(struct net_device
*dev
)
436 struct net_device_stats
*stats
= &dev
->stats
;
438 struct can_frame
*cf
;
440 dev_dbg(dev
->dev
.parent
, "RX buffer overflow\n");
441 stats
->rx_over_errors
++;
444 skb
= alloc_can_err_skb(dev
, &cf
);
448 cf
->can_id
|= CAN_ERR_CRTL
;
449 cf
->data
[1] = CAN_ERR_CRTL_RX_OVERFLOW
;
450 netif_receive_skb(skb
);
453 stats
->rx_bytes
+= cf
->can_dlc
;
457 * at91_read_mb - read CAN msg from mailbox (lowlevel impl)
459 * @mb: mailbox number to read from
460 * @cf: can frame where to store message
462 * Reads a CAN message from the given mailbox and stores data into
463 * given can frame. "mb" and "cf" must be valid.
465 static void at91_read_mb(struct net_device
*dev
, unsigned int mb
,
466 struct can_frame
*cf
)
468 const struct at91_priv
*priv
= netdev_priv(dev
);
469 u32 reg_msr
, reg_mid
;
471 reg_mid
= at91_read(priv
, AT91_MID(mb
));
472 if (reg_mid
& AT91_MID_MIDE
)
473 cf
->can_id
= ((reg_mid
>> 0) & CAN_EFF_MASK
) | CAN_EFF_FLAG
;
475 cf
->can_id
= (reg_mid
>> 18) & CAN_SFF_MASK
;
477 reg_msr
= at91_read(priv
, AT91_MSR(mb
));
478 if (reg_msr
& AT91_MSR_MRTR
)
479 cf
->can_id
|= CAN_RTR_FLAG
;
480 cf
->can_dlc
= get_can_dlc((reg_msr
>> 16) & 0xf);
482 *(u32
*)(cf
->data
+ 0) = at91_read(priv
, AT91_MDL(mb
));
483 *(u32
*)(cf
->data
+ 4) = at91_read(priv
, AT91_MDH(mb
));
485 if (unlikely(mb
== AT91_MB_RX_LAST
&& reg_msr
& AT91_MSR_MMI
))
486 at91_rx_overflow_err(dev
);
490 * at91_read_msg - read CAN message from mailbox
492 * @mb: mail box to read from
494 * Reads a CAN message from given mailbox, and put into linux network
495 * RX queue, does all housekeeping chores (stats, ...)
497 static void at91_read_msg(struct net_device
*dev
, unsigned int mb
)
499 struct net_device_stats
*stats
= &dev
->stats
;
500 struct can_frame
*cf
;
503 skb
= alloc_can_skb(dev
, &cf
);
504 if (unlikely(!skb
)) {
509 at91_read_mb(dev
, mb
, cf
);
510 netif_receive_skb(skb
);
513 stats
->rx_bytes
+= cf
->can_dlc
;
517 * at91_poll_rx - read multiple CAN messages from mailboxes
519 * @quota: max number of pkgs we're allowed to receive
521 * Theory of Operation:
523 * 12 of the 16 mailboxes on the chip are reserved for RX. we split
524 * them into 2 groups. The lower group holds 8 and upper 4 mailboxes.
526 * Like it or not, but the chip always saves a received CAN message
527 * into the first free mailbox it finds (starting with the
528 * lowest). This makes it very difficult to read the messages in the
529 * right order from the chip. This is how we work around that problem:
531 * The first message goes into mb nr. 0 and issues an interrupt. All
532 * rx ints are disabled in the interrupt handler and a napi poll is
533 * scheduled. We read the mailbox, but do _not_ reenable the mb (to
534 * receive another message).
537 * ______^______ __^__
539 * +-+-+-+-+-+-+-+-++-+-+-+-+
540 * |x|x|x|x|x|x|x|x|| | | | |
541 * +-+-+-+-+-+-+-+-++-+-+-+-+
542 * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail
543 * 0 1 2 3 4 5 6 7 8 9 0 1 / box
545 * The variable priv->rx_next points to the next mailbox to read a
546 * message from. As long we're in the lower mailboxes we just read the
547 * mailbox but not reenable it.
549 * With completion of the last of the lower mailboxes, we reenable the
550 * whole first group, but continue to look for filled mailboxes in the
551 * upper mailboxes. Imagine the second group like overflow mailboxes,
552 * which takes CAN messages if the lower goup is full. While in the
553 * upper group we reenable the mailbox right after reading it. Giving
554 * the chip more room to store messages.
556 * After finishing we look again in the lower group if we've still
560 static int at91_poll_rx(struct net_device
*dev
, int quota
)
562 struct at91_priv
*priv
= netdev_priv(dev
);
563 u32 reg_sr
= at91_read(priv
, AT91_SR
);
564 const unsigned long *addr
= (unsigned long *)®_sr
;
568 if (priv
->rx_next
> AT91_MB_RX_LOW_LAST
&&
569 reg_sr
& AT91_MB_RX_LOW_MASK
)
570 dev_info(dev
->dev
.parent
,
571 "order of incoming frames cannot be guaranteed\n");
574 for (mb
= find_next_bit(addr
, AT91_MB_RX_NUM
, priv
->rx_next
);
575 mb
< AT91_MB_RX_NUM
&& quota
> 0;
576 reg_sr
= at91_read(priv
, AT91_SR
),
577 mb
= find_next_bit(addr
, AT91_MB_RX_NUM
, ++priv
->rx_next
)) {
578 at91_read_msg(dev
, mb
);
580 /* reactivate mailboxes */
581 if (mb
== AT91_MB_RX_LOW_LAST
)
582 /* all lower mailboxed, if just finished it */
583 at91_activate_rx_low(priv
);
584 else if (mb
> AT91_MB_RX_LOW_LAST
)
585 /* only the mailbox we read */
586 at91_activate_rx_mb(priv
, mb
);
592 /* upper group completed, look again in lower */
593 if (priv
->rx_next
> AT91_MB_RX_LOW_LAST
&&
594 quota
> 0 && mb
>= AT91_MB_RX_NUM
) {
602 static void at91_poll_err_frame(struct net_device
*dev
,
603 struct can_frame
*cf
, u32 reg_sr
)
605 struct at91_priv
*priv
= netdev_priv(dev
);
608 if (reg_sr
& AT91_IRQ_CERR
) {
609 dev_dbg(dev
->dev
.parent
, "CERR irq\n");
610 dev
->stats
.rx_errors
++;
611 priv
->can
.can_stats
.bus_error
++;
612 cf
->can_id
|= CAN_ERR_PROT
| CAN_ERR_BUSERROR
;
616 if (reg_sr
& AT91_IRQ_SERR
) {
617 dev_dbg(dev
->dev
.parent
, "SERR irq\n");
618 dev
->stats
.rx_errors
++;
619 priv
->can
.can_stats
.bus_error
++;
620 cf
->can_id
|= CAN_ERR_PROT
| CAN_ERR_BUSERROR
;
621 cf
->data
[2] |= CAN_ERR_PROT_STUFF
;
624 /* Acknowledgement Error */
625 if (reg_sr
& AT91_IRQ_AERR
) {
626 dev_dbg(dev
->dev
.parent
, "AERR irq\n");
627 dev
->stats
.tx_errors
++;
628 cf
->can_id
|= CAN_ERR_ACK
;
632 if (reg_sr
& AT91_IRQ_FERR
) {
633 dev_dbg(dev
->dev
.parent
, "FERR irq\n");
634 dev
->stats
.rx_errors
++;
635 priv
->can
.can_stats
.bus_error
++;
636 cf
->can_id
|= CAN_ERR_PROT
| CAN_ERR_BUSERROR
;
637 cf
->data
[2] |= CAN_ERR_PROT_FORM
;
641 if (reg_sr
& AT91_IRQ_BERR
) {
642 dev_dbg(dev
->dev
.parent
, "BERR irq\n");
643 dev
->stats
.tx_errors
++;
644 priv
->can
.can_stats
.bus_error
++;
645 cf
->can_id
|= CAN_ERR_PROT
| CAN_ERR_BUSERROR
;
646 cf
->data
[2] |= CAN_ERR_PROT_BIT
;
650 static int at91_poll_err(struct net_device
*dev
, int quota
, u32 reg_sr
)
653 struct can_frame
*cf
;
658 skb
= alloc_can_err_skb(dev
, &cf
);
662 at91_poll_err_frame(dev
, cf
, reg_sr
);
663 netif_receive_skb(skb
);
665 dev
->last_rx
= jiffies
;
666 dev
->stats
.rx_packets
++;
667 dev
->stats
.rx_bytes
+= cf
->can_dlc
;
672 static int at91_poll(struct napi_struct
*napi
, int quota
)
674 struct net_device
*dev
= napi
->dev
;
675 const struct at91_priv
*priv
= netdev_priv(dev
);
676 u32 reg_sr
= at91_read(priv
, AT91_SR
);
679 if (reg_sr
& AT91_IRQ_MB_RX
)
680 work_done
+= at91_poll_rx(dev
, quota
- work_done
);
683 * The error bits are clear on read,
684 * so use saved value from irq handler.
686 reg_sr
|= priv
->reg_sr
;
687 if (reg_sr
& AT91_IRQ_ERR_FRAME
)
688 work_done
+= at91_poll_err(dev
, quota
- work_done
, reg_sr
);
690 if (work_done
< quota
) {
691 /* enable IRQs for frame errors and all mailboxes >= rx_next */
692 u32 reg_ier
= AT91_IRQ_ERR_FRAME
;
693 reg_ier
|= AT91_IRQ_MB_RX
& ~AT91_MB_RX_MASK(priv
->rx_next
);
696 at91_write(priv
, AT91_IER
, reg_ier
);
703 * theory of operation:
705 * priv->tx_echo holds the number of the oldest can_frame put for
706 * transmission into the hardware, but not yet ACKed by the CAN tx
709 * We iterate from priv->tx_echo to priv->tx_next and check if the
710 * packet has been transmitted, echo it back to the CAN framework. If
711 * we discover a not yet transmitted package, stop looking for more.
714 static void at91_irq_tx(struct net_device
*dev
, u32 reg_sr
)
716 struct at91_priv
*priv
= netdev_priv(dev
);
720 /* masking of reg_sr not needed, already done by at91_irq */
722 for (/* nix */; (priv
->tx_next
- priv
->tx_echo
) > 0; priv
->tx_echo
++) {
723 mb
= get_tx_echo_mb(priv
);
725 /* no event in mailbox? */
726 if (!(reg_sr
& (1 << mb
)))
729 /* Disable irq for this TX mailbox */
730 at91_write(priv
, AT91_IDR
, 1 << mb
);
733 * only echo if mailbox signals us a transfer
734 * complete (MSR_MRDY). Otherwise it's a tansfer
735 * abort. "can_bus_off()" takes care about the skbs
736 * parked in the echo queue.
738 reg_msr
= at91_read(priv
, AT91_MSR(mb
));
739 if (likely(reg_msr
& AT91_MSR_MRDY
&&
740 ~reg_msr
& AT91_MSR_MABT
)) {
741 /* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */
742 can_get_echo_skb(dev
, mb
- AT91_MB_TX_FIRST
);
743 dev
->stats
.tx_packets
++;
748 * restart queue if we don't have a wrap around but restart if
749 * we get a TX int for the last can frame directly before a
752 if ((priv
->tx_next
& AT91_NEXT_MASK
) != 0 ||
753 (priv
->tx_echo
& AT91_NEXT_MASK
) == 0)
754 netif_wake_queue(dev
);
757 static void at91_irq_err_state(struct net_device
*dev
,
758 struct can_frame
*cf
, enum can_state new_state
)
760 struct at91_priv
*priv
= netdev_priv(dev
);
761 u32 reg_idr
, reg_ier
, reg_ecr
;
764 reg_ecr
= at91_read(priv
, AT91_ECR
);
765 rec
= reg_ecr
& 0xff;
768 switch (priv
->can
.state
) {
769 case CAN_STATE_ERROR_ACTIVE
:
772 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
773 * => : there was a warning int
775 if (new_state
>= CAN_STATE_ERROR_WARNING
&&
776 new_state
<= CAN_STATE_BUS_OFF
) {
777 dev_dbg(dev
->dev
.parent
, "Error Warning IRQ\n");
778 priv
->can
.can_stats
.error_warning
++;
780 cf
->can_id
|= CAN_ERR_CRTL
;
781 cf
->data
[1] = (tec
> rec
) ?
782 CAN_ERR_CRTL_TX_WARNING
:
783 CAN_ERR_CRTL_RX_WARNING
;
785 case CAN_STATE_ERROR_WARNING
: /* fallthrough */
787 * from: ERROR_ACTIVE, ERROR_WARNING
788 * to : ERROR_PASSIVE, BUS_OFF
789 * => : error passive int
791 if (new_state
>= CAN_STATE_ERROR_PASSIVE
&&
792 new_state
<= CAN_STATE_BUS_OFF
) {
793 dev_dbg(dev
->dev
.parent
, "Error Passive IRQ\n");
794 priv
->can
.can_stats
.error_passive
++;
796 cf
->can_id
|= CAN_ERR_CRTL
;
797 cf
->data
[1] = (tec
> rec
) ?
798 CAN_ERR_CRTL_TX_PASSIVE
:
799 CAN_ERR_CRTL_RX_PASSIVE
;
802 case CAN_STATE_BUS_OFF
:
805 * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE
807 if (new_state
<= CAN_STATE_ERROR_PASSIVE
) {
808 cf
->can_id
|= CAN_ERR_RESTARTED
;
810 dev_dbg(dev
->dev
.parent
, "restarted\n");
811 priv
->can
.can_stats
.restarts
++;
813 netif_carrier_on(dev
);
814 netif_wake_queue(dev
);
822 /* process state changes depending on the new state */
824 case CAN_STATE_ERROR_ACTIVE
:
826 * actually we want to enable AT91_IRQ_WARN here, but
827 * it screws up the system under certain
828 * circumstances. so just enable AT91_IRQ_ERRP, thus
831 dev_dbg(dev
->dev
.parent
, "Error Active\n");
832 cf
->can_id
|= CAN_ERR_PROT
;
833 cf
->data
[2] = CAN_ERR_PROT_ACTIVE
;
834 case CAN_STATE_ERROR_WARNING
: /* fallthrough */
835 reg_idr
= AT91_IRQ_ERRA
| AT91_IRQ_WARN
| AT91_IRQ_BOFF
;
836 reg_ier
= AT91_IRQ_ERRP
;
838 case CAN_STATE_ERROR_PASSIVE
:
839 reg_idr
= AT91_IRQ_ERRA
| AT91_IRQ_WARN
| AT91_IRQ_ERRP
;
840 reg_ier
= AT91_IRQ_BOFF
;
842 case CAN_STATE_BUS_OFF
:
843 reg_idr
= AT91_IRQ_ERRA
| AT91_IRQ_ERRP
|
844 AT91_IRQ_WARN
| AT91_IRQ_BOFF
;
847 cf
->can_id
|= CAN_ERR_BUSOFF
;
849 dev_dbg(dev
->dev
.parent
, "bus-off\n");
850 netif_carrier_off(dev
);
851 priv
->can
.can_stats
.bus_off
++;
853 /* turn off chip, if restart is disabled */
854 if (!priv
->can
.restart_ms
) {
855 at91_chip_stop(dev
, CAN_STATE_BUS_OFF
);
863 at91_write(priv
, AT91_IDR
, reg_idr
);
864 at91_write(priv
, AT91_IER
, reg_ier
);
867 static void at91_irq_err(struct net_device
*dev
)
869 struct at91_priv
*priv
= netdev_priv(dev
);
871 struct can_frame
*cf
;
872 enum can_state new_state
;
875 reg_sr
= at91_read(priv
, AT91_SR
);
877 /* we need to look at the unmasked reg_sr */
878 if (unlikely(reg_sr
& AT91_IRQ_BOFF
))
879 new_state
= CAN_STATE_BUS_OFF
;
880 else if (unlikely(reg_sr
& AT91_IRQ_ERRP
))
881 new_state
= CAN_STATE_ERROR_PASSIVE
;
882 else if (unlikely(reg_sr
& AT91_IRQ_WARN
))
883 new_state
= CAN_STATE_ERROR_WARNING
;
884 else if (likely(reg_sr
& AT91_IRQ_ERRA
))
885 new_state
= CAN_STATE_ERROR_ACTIVE
;
887 dev_err(dev
->dev
.parent
, "BUG! hardware in undefined state\n");
891 /* state hasn't changed */
892 if (likely(new_state
== priv
->can
.state
))
895 skb
= alloc_can_err_skb(dev
, &cf
);
899 at91_irq_err_state(dev
, cf
, new_state
);
902 dev
->last_rx
= jiffies
;
903 dev
->stats
.rx_packets
++;
904 dev
->stats
.rx_bytes
+= cf
->can_dlc
;
906 priv
->can
.state
= new_state
;
912 static irqreturn_t
at91_irq(int irq
, void *dev_id
)
914 struct net_device
*dev
= dev_id
;
915 struct at91_priv
*priv
= netdev_priv(dev
);
916 irqreturn_t handled
= IRQ_NONE
;
919 reg_sr
= at91_read(priv
, AT91_SR
);
920 reg_imr
= at91_read(priv
, AT91_IMR
);
922 /* Ignore masked interrupts */
927 handled
= IRQ_HANDLED
;
929 /* Receive or error interrupt? -> napi */
930 if (reg_sr
& (AT91_IRQ_MB_RX
| AT91_IRQ_ERR_FRAME
)) {
932 * The error bits are clear on read,
933 * save for later use.
935 priv
->reg_sr
= reg_sr
;
936 at91_write(priv
, AT91_IDR
,
937 AT91_IRQ_MB_RX
| AT91_IRQ_ERR_FRAME
);
938 napi_schedule(&priv
->napi
);
941 /* Transmission complete interrupt */
942 if (reg_sr
& AT91_IRQ_MB_TX
)
943 at91_irq_tx(dev
, reg_sr
);
951 static int at91_open(struct net_device
*dev
)
953 struct at91_priv
*priv
= netdev_priv(dev
);
956 clk_enable(priv
->clk
);
958 /* check or determine and set bittime */
959 err
= open_candev(dev
);
963 /* register interrupt handler */
964 if (request_irq(dev
->irq
, at91_irq
, IRQF_SHARED
,
970 /* start chip and queuing */
971 at91_chip_start(dev
);
972 napi_enable(&priv
->napi
);
973 netif_start_queue(dev
);
980 clk_disable(priv
->clk
);
986 * stop CAN bus activity
988 static int at91_close(struct net_device
*dev
)
990 struct at91_priv
*priv
= netdev_priv(dev
);
992 netif_stop_queue(dev
);
993 napi_disable(&priv
->napi
);
994 at91_chip_stop(dev
, CAN_STATE_STOPPED
);
996 free_irq(dev
->irq
, dev
);
997 clk_disable(priv
->clk
);
1004 static int at91_set_mode(struct net_device
*dev
, enum can_mode mode
)
1007 case CAN_MODE_START
:
1008 at91_chip_start(dev
);
1009 netif_wake_queue(dev
);
1019 static const struct net_device_ops at91_netdev_ops
= {
1020 .ndo_open
= at91_open
,
1021 .ndo_stop
= at91_close
,
1022 .ndo_start_xmit
= at91_start_xmit
,
1025 static int __init
at91_can_probe(struct platform_device
*pdev
)
1027 struct net_device
*dev
;
1028 struct at91_priv
*priv
;
1029 struct resource
*res
;
1034 clk
= clk_get(&pdev
->dev
, "can_clk");
1036 dev_err(&pdev
->dev
, "no clock defined\n");
1041 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1042 irq
= platform_get_irq(pdev
, 0);
1043 if (!res
|| irq
<= 0) {
1048 if (!request_mem_region(res
->start
,
1055 addr
= ioremap_nocache(res
->start
, resource_size(res
));
1061 dev
= alloc_candev(sizeof(struct at91_priv
), AT91_MB_TX_NUM
);
1067 dev
->netdev_ops
= &at91_netdev_ops
;
1069 dev
->flags
|= IFF_ECHO
;
1071 priv
= netdev_priv(dev
);
1072 priv
->can
.clock
.freq
= clk_get_rate(clk
);
1073 priv
->can
.bittiming_const
= &at91_bittiming_const
;
1074 priv
->can
.do_set_bittiming
= at91_set_bittiming
;
1075 priv
->can
.do_set_mode
= at91_set_mode
;
1076 priv
->can
.ctrlmode_supported
= CAN_CTRLMODE_3_SAMPLES
;
1077 priv
->reg_base
= addr
;
1080 priv
->pdata
= pdev
->dev
.platform_data
;
1082 netif_napi_add(dev
, &priv
->napi
, at91_poll
, AT91_NAPI_WEIGHT
);
1084 dev_set_drvdata(&pdev
->dev
, dev
);
1085 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1087 err
= register_candev(dev
);
1089 dev_err(&pdev
->dev
, "registering netdev failed\n");
1093 dev_info(&pdev
->dev
, "device registered (reg_base=%p, irq=%d)\n",
1094 priv
->reg_base
, dev
->irq
);
1103 release_mem_region(res
->start
, resource_size(res
));
1110 static int __devexit
at91_can_remove(struct platform_device
*pdev
)
1112 struct net_device
*dev
= platform_get_drvdata(pdev
);
1113 struct at91_priv
*priv
= netdev_priv(dev
);
1114 struct resource
*res
;
1116 unregister_netdev(dev
);
1118 platform_set_drvdata(pdev
, NULL
);
1122 iounmap(priv
->reg_base
);
1124 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1125 release_mem_region(res
->start
, resource_size(res
));
1132 static struct platform_driver at91_can_driver
= {
1133 .probe
= at91_can_probe
,
1134 .remove
= __devexit_p(at91_can_remove
),
1137 .owner
= THIS_MODULE
,
1141 static int __init
at91_can_module_init(void)
1143 printk(KERN_INFO
"%s netdevice driver\n", DRV_NAME
);
1144 return platform_driver_register(&at91_can_driver
);
1147 static void __exit
at91_can_module_exit(void)
1149 platform_driver_unregister(&at91_can_driver
);
1150 printk(KERN_INFO
"%s: driver removed\n", DRV_NAME
);
1153 module_init(at91_can_module_init
);
1154 module_exit(at91_can_module_exit
);
1156 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
1157 MODULE_LICENSE("GPL v2");
1158 MODULE_DESCRIPTION(DRV_NAME
" CAN netdevice driver");