2 * arch/arm/mach-tegra/gpio.c
4 * Copyright (c) 2010 Google, Inc
7 * Erik Gilling <konkers@google.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/init.h>
21 #include <linux/irq.h>
22 #include <linux/interrupt.h>
24 #include <linux/gpio.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_device.h>
27 #include <linux/module.h>
28 #include <linux/irqdomain.h>
29 #include <linux/pinctrl/consumer.h>
31 #include <asm/mach/irq.h>
33 #define GPIO_BANK(x) ((x) >> 5)
34 #define GPIO_PORT(x) (((x) >> 3) & 0x3)
35 #define GPIO_BIT(x) ((x) & 0x7)
37 #define GPIO_REG(x) (GPIO_BANK(x) * tegra_gpio_bank_stride + \
40 #define GPIO_CNF(x) (GPIO_REG(x) + 0x00)
41 #define GPIO_OE(x) (GPIO_REG(x) + 0x10)
42 #define GPIO_OUT(x) (GPIO_REG(x) + 0X20)
43 #define GPIO_IN(x) (GPIO_REG(x) + 0x30)
44 #define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40)
45 #define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50)
46 #define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60)
47 #define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70)
49 #define GPIO_MSK_CNF(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)
50 #define GPIO_MSK_OE(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x10)
51 #define GPIO_MSK_OUT(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0X20)
52 #define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x40)
53 #define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x50)
54 #define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x60)
56 #define GPIO_INT_LVL_MASK 0x010101
57 #define GPIO_INT_LVL_EDGE_RISING 0x000101
58 #define GPIO_INT_LVL_EDGE_FALLING 0x000100
59 #define GPIO_INT_LVL_EDGE_BOTH 0x010100
60 #define GPIO_INT_LVL_LEVEL_HIGH 0x000001
61 #define GPIO_INT_LVL_LEVEL_LOW 0x000000
63 struct tegra_gpio_bank
{
66 spinlock_t lvl_lock
[4];
76 static struct irq_domain
*irq_domain
;
77 static void __iomem
*regs
;
78 static u32 tegra_gpio_bank_count
;
79 static u32 tegra_gpio_bank_stride
;
80 static u32 tegra_gpio_upper_offset
;
81 static struct tegra_gpio_bank
*tegra_gpio_banks
;
83 static inline void tegra_gpio_writel(u32 val
, u32 reg
)
85 __raw_writel(val
, regs
+ reg
);
88 static inline u32
tegra_gpio_readl(u32 reg
)
90 return __raw_readl(regs
+ reg
);
93 static int tegra_gpio_compose(int bank
, int port
, int bit
)
95 return (bank
<< 5) | ((port
& 0x3) << 3) | (bit
& 0x7);
98 static void tegra_gpio_mask_write(u32 reg
, int gpio
, int value
)
102 val
= 0x100 << GPIO_BIT(gpio
);
104 val
|= 1 << GPIO_BIT(gpio
);
105 tegra_gpio_writel(val
, reg
);
108 static void tegra_gpio_enable(int gpio
)
110 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio
), gpio
, 1);
112 EXPORT_SYMBOL_GPL(tegra_gpio_enable
);
114 static void tegra_gpio_disable(int gpio
)
116 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio
), gpio
, 0);
118 EXPORT_SYMBOL_GPL(tegra_gpio_disable
);
120 int tegra_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
122 return pinctrl_request_gpio(offset
);
125 void tegra_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
127 pinctrl_free_gpio(offset
);
128 tegra_gpio_disable(offset
);
131 static void tegra_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
133 tegra_gpio_mask_write(GPIO_MSK_OUT(offset
), offset
, value
);
136 static int tegra_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
138 return (tegra_gpio_readl(GPIO_IN(offset
)) >> GPIO_BIT(offset
)) & 0x1;
141 static int tegra_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
143 tegra_gpio_mask_write(GPIO_MSK_OE(offset
), offset
, 0);
144 tegra_gpio_enable(offset
);
148 static int tegra_gpio_direction_output(struct gpio_chip
*chip
, unsigned offset
,
151 tegra_gpio_set(chip
, offset
, value
);
152 tegra_gpio_mask_write(GPIO_MSK_OE(offset
), offset
, 1);
153 tegra_gpio_enable(offset
);
157 static int tegra_gpio_to_irq(struct gpio_chip
*chip
, unsigned offset
)
159 return irq_find_mapping(irq_domain
, offset
);
162 static struct gpio_chip tegra_gpio_chip
= {
163 .label
= "tegra-gpio",
164 .request
= tegra_gpio_request
,
165 .free
= tegra_gpio_free
,
166 .direction_input
= tegra_gpio_direction_input
,
167 .get
= tegra_gpio_get
,
168 .direction_output
= tegra_gpio_direction_output
,
169 .set
= tegra_gpio_set
,
170 .to_irq
= tegra_gpio_to_irq
,
174 static void tegra_gpio_irq_ack(struct irq_data
*d
)
178 tegra_gpio_writel(1 << GPIO_BIT(gpio
), GPIO_INT_CLR(gpio
));
181 static void tegra_gpio_irq_mask(struct irq_data
*d
)
185 tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio
), gpio
, 0);
188 static void tegra_gpio_irq_unmask(struct irq_data
*d
)
192 tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio
), gpio
, 1);
195 static int tegra_gpio_irq_set_type(struct irq_data
*d
, unsigned int type
)
198 struct tegra_gpio_bank
*bank
= irq_data_get_irq_chip_data(d
);
199 int port
= GPIO_PORT(gpio
);
204 switch (type
& IRQ_TYPE_SENSE_MASK
) {
205 case IRQ_TYPE_EDGE_RISING
:
206 lvl_type
= GPIO_INT_LVL_EDGE_RISING
;
209 case IRQ_TYPE_EDGE_FALLING
:
210 lvl_type
= GPIO_INT_LVL_EDGE_FALLING
;
213 case IRQ_TYPE_EDGE_BOTH
:
214 lvl_type
= GPIO_INT_LVL_EDGE_BOTH
;
217 case IRQ_TYPE_LEVEL_HIGH
:
218 lvl_type
= GPIO_INT_LVL_LEVEL_HIGH
;
221 case IRQ_TYPE_LEVEL_LOW
:
222 lvl_type
= GPIO_INT_LVL_LEVEL_LOW
;
229 spin_lock_irqsave(&bank
->lvl_lock
[port
], flags
);
231 val
= tegra_gpio_readl(GPIO_INT_LVL(gpio
));
232 val
&= ~(GPIO_INT_LVL_MASK
<< GPIO_BIT(gpio
));
233 val
|= lvl_type
<< GPIO_BIT(gpio
);
234 tegra_gpio_writel(val
, GPIO_INT_LVL(gpio
));
236 spin_unlock_irqrestore(&bank
->lvl_lock
[port
], flags
);
238 tegra_gpio_mask_write(GPIO_MSK_OE(gpio
), gpio
, 0);
239 tegra_gpio_enable(gpio
);
241 if (type
& (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_LEVEL_HIGH
))
242 __irq_set_handler_locked(d
->irq
, handle_level_irq
);
243 else if (type
& (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
244 __irq_set_handler_locked(d
->irq
, handle_edge_irq
);
249 static void tegra_gpio_irq_handler(unsigned int irq
, struct irq_desc
*desc
)
251 struct tegra_gpio_bank
*bank
;
255 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
257 chained_irq_enter(chip
, desc
);
259 bank
= irq_get_handler_data(irq
);
261 for (port
= 0; port
< 4; port
++) {
262 int gpio
= tegra_gpio_compose(bank
->bank
, port
, 0);
263 unsigned long sta
= tegra_gpio_readl(GPIO_INT_STA(gpio
)) &
264 tegra_gpio_readl(GPIO_INT_ENB(gpio
));
265 u32 lvl
= tegra_gpio_readl(GPIO_INT_LVL(gpio
));
267 for_each_set_bit(pin
, &sta
, 8) {
268 tegra_gpio_writel(1 << pin
, GPIO_INT_CLR(gpio
));
270 /* if gpio is edge triggered, clear condition
271 * before executing the hander so that we don't
274 if (lvl
& (0x100 << pin
)) {
276 chained_irq_exit(chip
, desc
);
279 generic_handle_irq(gpio_to_irq(gpio
+ pin
));
284 chained_irq_exit(chip
, desc
);
289 void tegra_gpio_resume(void)
295 local_irq_save(flags
);
297 for (b
= 0; b
< tegra_gpio_bank_count
; b
++) {
298 struct tegra_gpio_bank
*bank
= &tegra_gpio_banks
[b
];
300 for (p
= 0; p
< ARRAY_SIZE(bank
->oe
); p
++) {
301 unsigned int gpio
= (b
<<5) | (p
<<3);
302 tegra_gpio_writel(bank
->cnf
[p
], GPIO_CNF(gpio
));
303 tegra_gpio_writel(bank
->out
[p
], GPIO_OUT(gpio
));
304 tegra_gpio_writel(bank
->oe
[p
], GPIO_OE(gpio
));
305 tegra_gpio_writel(bank
->int_lvl
[p
], GPIO_INT_LVL(gpio
));
306 tegra_gpio_writel(bank
->int_enb
[p
], GPIO_INT_ENB(gpio
));
310 local_irq_restore(flags
);
313 void tegra_gpio_suspend(void)
319 local_irq_save(flags
);
320 for (b
= 0; b
< tegra_gpio_bank_count
; b
++) {
321 struct tegra_gpio_bank
*bank
= &tegra_gpio_banks
[b
];
323 for (p
= 0; p
< ARRAY_SIZE(bank
->oe
); p
++) {
324 unsigned int gpio
= (b
<<5) | (p
<<3);
325 bank
->cnf
[p
] = tegra_gpio_readl(GPIO_CNF(gpio
));
326 bank
->out
[p
] = tegra_gpio_readl(GPIO_OUT(gpio
));
327 bank
->oe
[p
] = tegra_gpio_readl(GPIO_OE(gpio
));
328 bank
->int_enb
[p
] = tegra_gpio_readl(GPIO_INT_ENB(gpio
));
329 bank
->int_lvl
[p
] = tegra_gpio_readl(GPIO_INT_LVL(gpio
));
332 local_irq_restore(flags
);
335 static int tegra_gpio_wake_enable(struct irq_data
*d
, unsigned int enable
)
337 struct tegra_gpio_bank
*bank
= irq_data_get_irq_chip_data(d
);
338 return irq_set_irq_wake(bank
->irq
, enable
);
342 static struct irq_chip tegra_gpio_irq_chip
= {
344 .irq_ack
= tegra_gpio_irq_ack
,
345 .irq_mask
= tegra_gpio_irq_mask
,
346 .irq_unmask
= tegra_gpio_irq_unmask
,
347 .irq_set_type
= tegra_gpio_irq_set_type
,
349 .irq_set_wake
= tegra_gpio_wake_enable
,
353 struct tegra_gpio_soc_config
{
358 static struct tegra_gpio_soc_config tegra20_gpio_config
= {
360 .upper_offset
= 0x800,
363 static struct tegra_gpio_soc_config tegra30_gpio_config
= {
364 .bank_stride
= 0x100,
365 .upper_offset
= 0x80,
368 static struct of_device_id tegra_gpio_of_match
[] __devinitdata
= {
369 { .compatible
= "nvidia,tegra30-gpio", .data
= &tegra30_gpio_config
},
370 { .compatible
= "nvidia,tegra20-gpio", .data
= &tegra20_gpio_config
},
374 /* This lock class tells lockdep that GPIO irqs are in a different
375 * category than their parents, so it won't report false recursion.
377 static struct lock_class_key gpio_lock_class
;
379 static int __devinit
tegra_gpio_probe(struct platform_device
*pdev
)
381 const struct of_device_id
*match
;
382 struct tegra_gpio_soc_config
*config
;
384 struct resource
*res
;
385 struct tegra_gpio_bank
*bank
;
390 match
= of_match_device(tegra_gpio_of_match
, &pdev
->dev
);
392 config
= (struct tegra_gpio_soc_config
*)match
->data
;
394 config
= &tegra20_gpio_config
;
396 tegra_gpio_bank_stride
= config
->bank_stride
;
397 tegra_gpio_upper_offset
= config
->upper_offset
;
400 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, tegra_gpio_bank_count
);
403 tegra_gpio_bank_count
++;
405 if (!tegra_gpio_bank_count
) {
406 dev_err(&pdev
->dev
, "Missing IRQ resource\n");
410 tegra_gpio_chip
.ngpio
= tegra_gpio_bank_count
* 32;
412 tegra_gpio_banks
= devm_kzalloc(&pdev
->dev
,
413 tegra_gpio_bank_count
* sizeof(*tegra_gpio_banks
),
415 if (!tegra_gpio_banks
) {
416 dev_err(&pdev
->dev
, "Couldn't allocate bank structure\n");
420 irq_base
= irq_alloc_descs(-1, 0, tegra_gpio_chip
.ngpio
, 0);
422 dev_err(&pdev
->dev
, "Couldn't allocate IRQ numbers\n");
425 irq_domain
= irq_domain_add_legacy(pdev
->dev
.of_node
,
426 tegra_gpio_chip
.ngpio
, irq_base
, 0,
427 &irq_domain_simple_ops
, NULL
);
429 for (i
= 0; i
< tegra_gpio_bank_count
; i
++) {
430 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, i
);
432 dev_err(&pdev
->dev
, "Missing IRQ resource\n");
436 bank
= &tegra_gpio_banks
[i
];
438 bank
->irq
= res
->start
;
441 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
443 dev_err(&pdev
->dev
, "Missing MEM resource\n");
447 regs
= devm_request_and_ioremap(&pdev
->dev
, res
);
449 dev_err(&pdev
->dev
, "Couldn't ioremap regs\n");
453 for (i
= 0; i
< tegra_gpio_bank_count
; i
++) {
454 for (j
= 0; j
< 4; j
++) {
455 int gpio
= tegra_gpio_compose(i
, j
, 0);
456 tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio
));
460 #ifdef CONFIG_OF_GPIO
461 tegra_gpio_chip
.of_node
= pdev
->dev
.of_node
;
464 gpiochip_add(&tegra_gpio_chip
);
466 for (gpio
= 0; gpio
< tegra_gpio_chip
.ngpio
; gpio
++) {
467 int irq
= irq_find_mapping(irq_domain
, gpio
);
468 /* No validity check; all Tegra GPIOs are valid IRQs */
470 bank
= &tegra_gpio_banks
[GPIO_BANK(gpio
)];
472 irq_set_lockdep_class(irq
, &gpio_lock_class
);
473 irq_set_chip_data(irq
, bank
);
474 irq_set_chip_and_handler(irq
, &tegra_gpio_irq_chip
,
476 set_irq_flags(irq
, IRQF_VALID
);
479 for (i
= 0; i
< tegra_gpio_bank_count
; i
++) {
480 bank
= &tegra_gpio_banks
[i
];
482 irq_set_chained_handler(bank
->irq
, tegra_gpio_irq_handler
);
483 irq_set_handler_data(bank
->irq
, bank
);
485 for (j
= 0; j
< 4; j
++)
486 spin_lock_init(&bank
->lvl_lock
[j
]);
492 static struct platform_driver tegra_gpio_driver
= {
494 .name
= "tegra-gpio",
495 .owner
= THIS_MODULE
,
496 .of_match_table
= tegra_gpio_of_match
,
498 .probe
= tegra_gpio_probe
,
501 static int __init
tegra_gpio_init(void)
503 return platform_driver_register(&tegra_gpio_driver
);
505 postcore_initcall(tegra_gpio_init
);
507 #ifdef CONFIG_DEBUG_FS
509 #include <linux/debugfs.h>
510 #include <linux/seq_file.h>
512 static int dbg_gpio_show(struct seq_file
*s
, void *unused
)
517 for (i
= 0; i
< tegra_gpio_bank_count
; i
++) {
518 for (j
= 0; j
< 4; j
++) {
519 int gpio
= tegra_gpio_compose(i
, j
, 0);
521 "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
523 tegra_gpio_readl(GPIO_CNF(gpio
)),
524 tegra_gpio_readl(GPIO_OE(gpio
)),
525 tegra_gpio_readl(GPIO_OUT(gpio
)),
526 tegra_gpio_readl(GPIO_IN(gpio
)),
527 tegra_gpio_readl(GPIO_INT_STA(gpio
)),
528 tegra_gpio_readl(GPIO_INT_ENB(gpio
)),
529 tegra_gpio_readl(GPIO_INT_LVL(gpio
)));
535 static int dbg_gpio_open(struct inode
*inode
, struct file
*file
)
537 return single_open(file
, dbg_gpio_show
, &inode
->i_private
);
540 static const struct file_operations debug_fops
= {
541 .open
= dbg_gpio_open
,
544 .release
= single_release
,
547 static int __init
tegra_gpio_debuginit(void)
549 (void) debugfs_create_file("tegra_gpio", S_IRUGO
,
550 NULL
, NULL
, &debug_fops
);
553 late_initcall(tegra_gpio_debuginit
);