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sfc: Reinitialise the PHY completely in case of a PHY or NIC reset
[linux-2.6/btrfs-unstable.git] / drivers / net / sfc / tenxpress.c
blobc9584619322ad3ff773aabbd2a218741b8a177de
1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2007-2008 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10 #include <linux/delay.h>
11 #include <linux/seq_file.h>
12 #include "efx.h"
13 #include "mdio_10g.h"
14 #include "falcon.h"
15 #include "phy.h"
16 #include "falcon_hwdefs.h"
17 #include "boards.h"
18 #include "workarounds.h"
19 #include "selftest.h"
20
21 /* We expect these MMDs to be in the package. SFT9001 also has a
22 * clause 22 extension MMD, but since it doesn't have all the generic
23 * MMD registers it is pointless to include it here.
24 */
25 #define TENXPRESS_REQUIRED_DEVS (MDIO_MMDREG_DEVS_PMAPMD | \
26 MDIO_MMDREG_DEVS_PCS | \
27 MDIO_MMDREG_DEVS_PHYXS | \
28 MDIO_MMDREG_DEVS_AN)
29
30 #define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \
31 (1 << LOOPBACK_PCS) | \
32 (1 << LOOPBACK_PMAPMD) | \
33 (1 << LOOPBACK_NETWORK))
34
35 #define SFT9001_LOOPBACKS ((1 << LOOPBACK_GPHY) | \
36 (1 << LOOPBACK_PHYXS) | \
37 (1 << LOOPBACK_PCS) | \
38 (1 << LOOPBACK_PMAPMD) | \
39 (1 << LOOPBACK_NETWORK))
40
41 /* We complain if we fail to see the link partner as 10G capable this many
42 * times in a row (must be > 1 as sampling the autoneg. registers is racy)
43 */
44 #define MAX_BAD_LP_TRIES (5)
45
46 /* LASI Control */
47 #define PMA_PMD_LASI_CTRL 36866
48 #define PMA_PMD_LASI_STATUS 36869
49 #define PMA_PMD_LS_ALARM_LBN 0
50 #define PMA_PMD_LS_ALARM_WIDTH 1
51 #define PMA_PMD_TX_ALARM_LBN 1
52 #define PMA_PMD_TX_ALARM_WIDTH 1
53 #define PMA_PMD_RX_ALARM_LBN 2
54 #define PMA_PMD_RX_ALARM_WIDTH 1
55 #define PMA_PMD_AN_ALARM_LBN 3
56 #define PMA_PMD_AN_ALARM_WIDTH 1
57
58 /* Extended control register */
59 #define PMA_PMD_XCONTROL_REG 49152
60 #define PMA_PMD_EXT_GMII_EN_LBN 1
61 #define PMA_PMD_EXT_GMII_EN_WIDTH 1
62 #define PMA_PMD_EXT_CLK_OUT_LBN 2
63 #define PMA_PMD_EXT_CLK_OUT_WIDTH 1
64 #define PMA_PMD_LNPGA_POWERDOWN_LBN 8 /* SFX7101 only */
65 #define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1
66 #define PMA_PMD_EXT_CLK312_LBN 8 /* SFT9001 only */
67 #define PMA_PMD_EXT_CLK312_WIDTH 1
68 #define PMA_PMD_EXT_LPOWER_LBN 12
69 #define PMA_PMD_EXT_LPOWER_WIDTH 1
70 #define PMA_PMD_EXT_ROBUST_LBN 14
71 #define PMA_PMD_EXT_ROBUST_WIDTH 1
72 #define PMA_PMD_EXT_SSR_LBN 15
73 #define PMA_PMD_EXT_SSR_WIDTH 1
74
75 /* extended status register */
76 #define PMA_PMD_XSTATUS_REG 49153
77 #define PMA_PMD_XSTAT_FLP_LBN (12)
78
79 /* LED control register */
80 #define PMA_PMD_LED_CTRL_REG 49159
81 #define PMA_PMA_LED_ACTIVITY_LBN (3)
82
83 /* LED function override register */
84 #define PMA_PMD_LED_OVERR_REG 49161
85 /* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
86 #define PMA_PMD_LED_LINK_LBN (0)
87 #define PMA_PMD_LED_SPEED_LBN (2)
88 #define PMA_PMD_LED_TX_LBN (4)
89 #define PMA_PMD_LED_RX_LBN (6)
90 /* Override settings */
91 #define PMA_PMD_LED_AUTO (0) /* H/W control */
92 #define PMA_PMD_LED_ON (1)
93 #define PMA_PMD_LED_OFF (2)
94 #define PMA_PMD_LED_FLASH (3)
95 #define PMA_PMD_LED_MASK 3
96 /* All LEDs under hardware control */
97 #define PMA_PMD_LED_FULL_AUTO (0)
98 /* Green and Amber under hardware control, Red off */
99 #define PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)
100
101 #define PMA_PMD_SPEED_ENABLE_REG 49192
102 #define PMA_PMD_100TX_ADV_LBN 1
103 #define PMA_PMD_100TX_ADV_WIDTH 1
104 #define PMA_PMD_1000T_ADV_LBN 2
105 #define PMA_PMD_1000T_ADV_WIDTH 1
106 #define PMA_PMD_10000T_ADV_LBN 3
107 #define PMA_PMD_10000T_ADV_WIDTH 1
108 #define PMA_PMD_SPEED_LBN 4
109 #define PMA_PMD_SPEED_WIDTH 4
110
111 /* Cable diagnostics - SFT9001 only */
112 #define PMA_PMD_CDIAG_CTRL_REG 49213
113 #define CDIAG_CTRL_IMMED_LBN 15
114 #define CDIAG_CTRL_BRK_LINK_LBN 12
115 #define CDIAG_CTRL_IN_PROG_LBN 11
116 #define CDIAG_CTRL_LEN_UNIT_LBN 10
117 #define CDIAG_CTRL_LEN_METRES 1
118 #define PMA_PMD_CDIAG_RES_REG 49174
119 #define CDIAG_RES_A_LBN 12
120 #define CDIAG_RES_B_LBN 8
121 #define CDIAG_RES_C_LBN 4
122 #define CDIAG_RES_D_LBN 0
123 #define CDIAG_RES_WIDTH 4
124 #define CDIAG_RES_OPEN 2
125 #define CDIAG_RES_OK 1
126 #define CDIAG_RES_INVALID 0
127 /* Set of 4 registers for pairs A-D */
128 #define PMA_PMD_CDIAG_LEN_REG 49175
129
130 /* Serdes control registers - SFT9001 only */
131 #define PMA_PMD_CSERDES_CTRL_REG 64258
132 /* Set the 156.25 MHz output to 312.5 MHz to drive Falcon's XMAC */
133 #define PMA_PMD_CSERDES_DEFAULT 0x000f
134
135 /* Misc register defines - SFX7101 only */
136 #define PCS_CLOCK_CTRL_REG 55297
137 #define PLL312_RST_N_LBN 2
138
139 #define PCS_SOFT_RST2_REG 55302
140 #define SERDES_RST_N_LBN 13
141 #define XGXS_RST_N_LBN 12
142
143 #define PCS_TEST_SELECT_REG 55303 /* PRM 10.5.8 */
144 #define CLK312_EN_LBN 3
145
146 /* PHYXS registers */
147 #define PHYXS_XCONTROL_REG 49152
148 #define PHYXS_RESET_LBN 15
149 #define PHYXS_RESET_WIDTH 1
150
151 #define PHYXS_TEST1 (49162)
152 #define LOOPBACK_NEAR_LBN (8)
153 #define LOOPBACK_NEAR_WIDTH (1)
154
155 #define PCS_10GBASET_STAT1 32
156 #define PCS_10GBASET_BLKLK_LBN 0
157 #define PCS_10GBASET_BLKLK_WIDTH 1
158
159 /* Boot status register */
160 #define PCS_BOOT_STATUS_REG 53248
161 #define PCS_BOOT_FATAL_ERR_LBN (0)
162 #define PCS_BOOT_PROGRESS_LBN (1)
163 #define PCS_BOOT_PROGRESS_WIDTH (2)
164 #define PCS_BOOT_COMPLETE_LBN (3)
165
166 #define PCS_BOOT_MAX_DELAY (100)
167 #define PCS_BOOT_POLL_DELAY (10)
168
169 /* 100M/1G PHY registers */
170 #define GPHY_XCONTROL_REG 49152
171 #define GPHY_ISOLATE_LBN 10
172 #define GPHY_ISOLATE_WIDTH 1
173 #define GPHY_DUPLEX_LBN 8
174 #define GPHY_DUPLEX_WIDTH 1
175 #define GPHY_LOOPBACK_NEAR_LBN 14
176 #define GPHY_LOOPBACK_NEAR_WIDTH 1
177
178 #define C22EXT_STATUS_REG 49153
179 #define C22EXT_STATUS_LINK_LBN 2
180 #define C22EXT_STATUS_LINK_WIDTH 1
181
182 #define C22EXT_MSTSLV_REG 49162
183 #define C22EXT_MSTSLV_1000_HD_LBN 10
184 #define C22EXT_MSTSLV_1000_HD_WIDTH 1
185 #define C22EXT_MSTSLV_1000_FD_LBN 11
186 #define C22EXT_MSTSLV_1000_FD_WIDTH 1
187
188 /* Time to wait between powering down the LNPGA and turning off the power
189 * rails */
190 #define LNPGA_PDOWN_WAIT (HZ / 5)
191
192 struct tenxpress_phy_data {
193 enum efx_loopback_mode loopback_mode;
194 enum efx_phy_mode phy_mode;
195 int bad_lp_tries;
196 };
197
198 static ssize_t show_phy_short_reach(struct device *dev,
199 struct device_attribute *attr, char *buf)
200 {
201 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
202 int reg;
203
204 reg = mdio_clause45_read(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
205 MDIO_PMAPMD_10GBT_TXPWR);
206 return sprintf(buf, "%d\n",
207 !!(reg & (1 << MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN)));
208 }
209
210 static ssize_t set_phy_short_reach(struct device *dev,
211 struct device_attribute *attr,
212 const char *buf, size_t count)
213 {
214 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
215
216 rtnl_lock();
217 mdio_clause45_set_flag(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
218 MDIO_PMAPMD_10GBT_TXPWR,
219 MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN,
220 count != 0 && *buf != '0');
221 efx_reconfigure_port(efx);
222 rtnl_unlock();
223
224 return count;
225 }
226
227 static DEVICE_ATTR(phy_short_reach, 0644, show_phy_short_reach,
228 set_phy_short_reach);
229
230 /* Check that the C166 has booted successfully */
231 static int tenxpress_phy_check(struct efx_nic *efx)
232 {
233 int phy_id = efx->mii.phy_id;
234 int count = PCS_BOOT_MAX_DELAY / PCS_BOOT_POLL_DELAY;
235 int boot_stat;
236
237 /* Wait for the boot to complete (or not) */
238 while (count) {
239 boot_stat = mdio_clause45_read(efx, phy_id,
240 MDIO_MMD_PCS,
241 PCS_BOOT_STATUS_REG);
242 if (boot_stat & (1 << PCS_BOOT_COMPLETE_LBN))
243 break;
244 count--;
245 udelay(PCS_BOOT_POLL_DELAY);
246 }
247
248 if (!count) {
249 EFX_ERR(efx, "%s: PHY boot timed out. Last status "
250 "%x\n", __func__,
251 (boot_stat >> PCS_BOOT_PROGRESS_LBN) &
252 ((1 << PCS_BOOT_PROGRESS_WIDTH) - 1));
253 return -ETIMEDOUT;
254 }
255
256 return 0;
257 }
258
259 static int tenxpress_init(struct efx_nic *efx)
260 {
261 int phy_id = efx->mii.phy_id;
262 int reg;
263 int rc;
264
265 if (efx->phy_type == PHY_TYPE_SFX7101) {
266 /* Enable 312.5 MHz clock */
267 mdio_clause45_write(efx, phy_id,
268 MDIO_MMD_PCS, PCS_TEST_SELECT_REG,
269 1 << CLK312_EN_LBN);
270 } else {
271 /* Enable 312.5 MHz clock and GMII */
272 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
273 PMA_PMD_XCONTROL_REG);
274 reg |= ((1 << PMA_PMD_EXT_GMII_EN_LBN) |
275 (1 << PMA_PMD_EXT_CLK_OUT_LBN) |
276 (1 << PMA_PMD_EXT_CLK312_LBN) |
277 (1 << PMA_PMD_EXT_ROBUST_LBN));
278
279 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
280 PMA_PMD_XCONTROL_REG, reg);
281 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT,
282 GPHY_XCONTROL_REG, GPHY_ISOLATE_LBN,
283 false);
284 }
285
286 rc = tenxpress_phy_check(efx);
287 if (rc < 0)
288 return rc;
289
290 /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
291 if (efx->phy_type == PHY_TYPE_SFX7101) {
292 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PMAPMD,
293 PMA_PMD_LED_CTRL_REG,
294 PMA_PMA_LED_ACTIVITY_LBN,
295 true);
296 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
297 PMA_PMD_LED_OVERR_REG, PMA_PMD_LED_DEFAULT);
298 }
299
300 return rc;
301 }
302
303 static int tenxpress_phy_init(struct efx_nic *efx)
304 {
305 struct tenxpress_phy_data *phy_data;
306 int rc = 0;
307
308 phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL);
309 if (!phy_data)
310 return -ENOMEM;
311 efx->phy_data = phy_data;
312 phy_data->phy_mode = efx->phy_mode;
313
314 if (!(efx->phy_mode & PHY_MODE_SPECIAL)) {
315 if (efx->phy_type == PHY_TYPE_SFT9001A) {
316 int reg;
317 reg = mdio_clause45_read(efx, efx->mii.phy_id,
318 MDIO_MMD_PMAPMD,
319 PMA_PMD_XCONTROL_REG);
320 reg |= (1 << PMA_PMD_EXT_SSR_LBN);
321 mdio_clause45_write(efx, efx->mii.phy_id,
322 MDIO_MMD_PMAPMD,
323 PMA_PMD_XCONTROL_REG, reg);
324 mdelay(200);
325 }
326
327 rc = mdio_clause45_wait_reset_mmds(efx,
328 TENXPRESS_REQUIRED_DEVS);
329 if (rc < 0)
330 goto fail;
331
332 rc = mdio_clause45_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0);
333 if (rc < 0)
334 goto fail;
335 }
336
337 rc = tenxpress_init(efx);
338 if (rc < 0)
339 goto fail;
340 mdio_clause45_set_pause(efx);
341
342 if (efx->phy_type == PHY_TYPE_SFT9001B) {
343 rc = device_create_file(&efx->pci_dev->dev,
344 &dev_attr_phy_short_reach);
345 if (rc)
346 goto fail;
347 }
348
349 schedule_timeout_uninterruptible(HZ / 5); /* 200ms */
350
351 /* Let XGXS and SerDes out of reset */
352 falcon_reset_xaui(efx);
353
354 return 0;
355
356 fail:
357 kfree(efx->phy_data);
358 efx->phy_data = NULL;
359 return rc;
360 }
361
362 /* Perform a "special software reset" on the PHY. The caller is
363 * responsible for saving and restoring the PHY hardware registers
364 * properly, and masking/unmasking LASI */
365 static int tenxpress_special_reset(struct efx_nic *efx)
366 {
367 int rc, reg;
368
369 /* The XGMAC clock is driven from the SFC7101/SFT9001 312MHz clock, so
370 * a special software reset can glitch the XGMAC sufficiently for stats
371 * requests to fail. Since we don't often special_reset, just lock. */
372 spin_lock(&efx->stats_lock);
373
374 /* Initiate reset */
375 reg = mdio_clause45_read(efx, efx->mii.phy_id,
376 MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG);
377 reg |= (1 << PMA_PMD_EXT_SSR_LBN);
378 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
379 PMA_PMD_XCONTROL_REG, reg);
380
381 mdelay(200);
382
383 /* Wait for the blocks to come out of reset */
384 rc = mdio_clause45_wait_reset_mmds(efx,
385 TENXPRESS_REQUIRED_DEVS);
386 if (rc < 0)
387 goto unlock;
388
389 /* Try and reconfigure the device */
390 rc = tenxpress_init(efx);
391 if (rc < 0)
392 goto unlock;
393
394 /* Wait for the XGXS state machine to churn */
395 mdelay(10);
396 unlock:
397 spin_unlock(&efx->stats_lock);
398 return rc;
399 }
400
401 static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok)
402 {
403 struct tenxpress_phy_data *pd = efx->phy_data;
404 int phy_id = efx->mii.phy_id;
405 bool bad_lp;
406 int reg;
407
408 if (link_ok) {
409 bad_lp = false;
410 } else {
411 /* Check that AN has started but not completed. */
412 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
413 MDIO_AN_STATUS);
414 if (!(reg & (1 << MDIO_AN_STATUS_LP_AN_CAP_LBN)))
415 return; /* LP status is unknown */
416 bad_lp = !(reg & (1 << MDIO_AN_STATUS_AN_DONE_LBN));
417 if (bad_lp)
418 pd->bad_lp_tries++;
419 }
420
421 /* Nothing to do if all is well and was previously so. */
422 if (!pd->bad_lp_tries)
423 return;
424
425 /* Use the RX (red) LED as an error indicator once we've seen AN
426 * failure several times in a row, and also log a message. */
427 if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) {
428 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
429 PMA_PMD_LED_OVERR_REG);
430 reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN);
431 if (!bad_lp) {
432 reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN;
433 } else {
434 reg |= PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN;
435 EFX_ERR(efx, "appears to be plugged into a port"
436 " that is not 10GBASE-T capable. The PHY"
437 " supports 10GBASE-T ONLY, so no link can"
438 " be established\n");
439 }
440 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
441 PMA_PMD_LED_OVERR_REG, reg);
442 pd->bad_lp_tries = bad_lp;
443 }
444 }
445
446 static bool sfx7101_link_ok(struct efx_nic *efx)
447 {
448 return mdio_clause45_links_ok(efx,
449 MDIO_MMDREG_DEVS_PMAPMD |
450 MDIO_MMDREG_DEVS_PCS |
451 MDIO_MMDREG_DEVS_PHYXS);
452 }
453
454 static bool sft9001_link_ok(struct efx_nic *efx, struct ethtool_cmd *ecmd)
455 {
456 int phy_id = efx->mii.phy_id;
457 u32 reg;
458
459 if (efx_phy_mode_disabled(efx->phy_mode))
460 return false;
461 else if (efx->loopback_mode == LOOPBACK_GPHY)
462 return true;
463 else if (efx->loopback_mode)
464 return mdio_clause45_links_ok(efx,
465 MDIO_MMDREG_DEVS_PMAPMD |
466 MDIO_MMDREG_DEVS_PHYXS);
467
468 /* We must use the same definition of link state as LASI,
469 * otherwise we can miss a link state transition
470 */
471 if (ecmd->speed == 10000) {
472 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PCS,
473 PCS_10GBASET_STAT1);
474 return reg & (1 << PCS_10GBASET_BLKLK_LBN);
475 } else {
476 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT,
477 C22EXT_STATUS_REG);
478 return reg & (1 << C22EXT_STATUS_LINK_LBN);
479 }
480 }
481
482 static void tenxpress_ext_loopback(struct efx_nic *efx)
483 {
484 int phy_id = efx->mii.phy_id;
485
486 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PHYXS,
487 PHYXS_TEST1, LOOPBACK_NEAR_LBN,
488 efx->loopback_mode == LOOPBACK_PHYXS);
489 if (efx->phy_type != PHY_TYPE_SFX7101)
490 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT,
491 GPHY_XCONTROL_REG,
492 GPHY_LOOPBACK_NEAR_LBN,
493 efx->loopback_mode == LOOPBACK_GPHY);
494 }
495
496 static void tenxpress_low_power(struct efx_nic *efx)
497 {
498 int phy_id = efx->mii.phy_id;
499
500 if (efx->phy_type == PHY_TYPE_SFX7101)
501 mdio_clause45_set_mmds_lpower(
502 efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER),
503 TENXPRESS_REQUIRED_DEVS);
504 else
505 mdio_clause45_set_flag(
506 efx, phy_id, MDIO_MMD_PMAPMD,
507 PMA_PMD_XCONTROL_REG, PMA_PMD_EXT_LPOWER_LBN,
508 !!(efx->phy_mode & PHY_MODE_LOW_POWER));
509 }
510
511 static void tenxpress_phy_reconfigure(struct efx_nic *efx)
512 {
513 struct tenxpress_phy_data *phy_data = efx->phy_data;
514 struct ethtool_cmd ecmd;
515 bool phy_mode_change, loop_reset;
516
517 if (efx->phy_mode & (PHY_MODE_OFF | PHY_MODE_SPECIAL)) {
518 phy_data->phy_mode = efx->phy_mode;
519 return;
520 }
521
522 tenxpress_low_power(efx);
523
524 phy_mode_change = (efx->phy_mode == PHY_MODE_NORMAL &&
525 phy_data->phy_mode != PHY_MODE_NORMAL);
526 loop_reset = (LOOPBACK_OUT_OF(phy_data, efx, efx->phy_op->loopbacks) ||
527 LOOPBACK_CHANGED(phy_data, efx, 1 << LOOPBACK_GPHY));
528
529 if (loop_reset || phy_mode_change) {
530 int rc;
531
532 efx->phy_op->get_settings(efx, &ecmd);
533
534 if (loop_reset || phy_mode_change) {
535 tenxpress_special_reset(efx);
536
537 /* Reset XAUI if we were in 10G, and are staying
538 * in 10G. If we're moving into and out of 10G
539 * then xaui will be reset anyway */
540 if (EFX_IS10G(efx))
541 falcon_reset_xaui(efx);
542 }
543
544 rc = efx->phy_op->set_settings(efx, &ecmd);
545 WARN_ON(rc);
546 }
547
548 mdio_clause45_transmit_disable(efx);
549 mdio_clause45_phy_reconfigure(efx);
550 tenxpress_ext_loopback(efx);
551
552 phy_data->loopback_mode = efx->loopback_mode;
553 phy_data->phy_mode = efx->phy_mode;
554
555 if (efx->phy_type == PHY_TYPE_SFX7101) {
556 efx->link_speed = 10000;
557 efx->link_fd = true;
558 efx->link_up = sfx7101_link_ok(efx);
559 } else {
560 efx->phy_op->get_settings(efx, &ecmd);
561 efx->link_speed = ecmd.speed;
562 efx->link_fd = ecmd.duplex == DUPLEX_FULL;
563 efx->link_up = sft9001_link_ok(efx, &ecmd);
564 }
565 efx->link_fc = mdio_clause45_get_pause(efx);
566 }
567
568 /* Poll PHY for interrupt */
569 static void tenxpress_phy_poll(struct efx_nic *efx)
570 {
571 struct tenxpress_phy_data *phy_data = efx->phy_data;
572 bool change = false, link_ok;
573 unsigned link_fc;
574
575 if (efx->phy_type == PHY_TYPE_SFX7101) {
576 link_ok = sfx7101_link_ok(efx);
577 if (link_ok != efx->link_up) {
578 change = true;
579 } else {
580 link_fc = mdio_clause45_get_pause(efx);
581 if (link_fc != efx->link_fc)
582 change = true;
583 }
584 sfx7101_check_bad_lp(efx, link_ok);
585 } else if (efx->loopback_mode) {
586 bool link_ok = sft9001_link_ok(efx, NULL);
587 if (link_ok != efx->link_up)
588 change = true;
589 } else {
590 u32 status = mdio_clause45_read(efx, efx->mii.phy_id,
591 MDIO_MMD_PMAPMD,
592 PMA_PMD_LASI_STATUS);
593 if (status & (1 << PMA_PMD_LS_ALARM_LBN))
594 change = true;
595 }
596
597 if (change)
598 falcon_sim_phy_event(efx);
599
600 if (phy_data->phy_mode != PHY_MODE_NORMAL)
601 return;
602 }
603
604 static void tenxpress_phy_fini(struct efx_nic *efx)
605 {
606 int reg;
607
608 if (efx->phy_type == PHY_TYPE_SFT9001B)
609 device_remove_file(&efx->pci_dev->dev,
610 &dev_attr_phy_short_reach);
611
612 if (efx->phy_type == PHY_TYPE_SFX7101) {
613 /* Power down the LNPGA */
614 reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN);
615 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
616 PMA_PMD_XCONTROL_REG, reg);
617
618 /* Waiting here ensures that the board fini, which can turn
619 * off the power to the PHY, won't get run until the LNPGA
620 * powerdown has been given long enough to complete. */
621 schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */
622 }
623
624 kfree(efx->phy_data);
625 efx->phy_data = NULL;
626 }
627
628
629 /* Set the RX and TX LEDs and Link LED flashing. The other LEDs
630 * (which probably aren't wired anyway) are left in AUTO mode */
631 void tenxpress_phy_blink(struct efx_nic *efx, bool blink)
632 {
633 int reg;
634
635 if (blink)
636 reg = (PMA_PMD_LED_FLASH << PMA_PMD_LED_TX_LBN) |
637 (PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN) |
638 (PMA_PMD_LED_FLASH << PMA_PMD_LED_LINK_LBN);
639 else
640 reg = PMA_PMD_LED_DEFAULT;
641
642 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
643 PMA_PMD_LED_OVERR_REG, reg);
644 }
645
646 static const char *const sfx7101_test_names[] = {
647 "bist"
648 };
649
650 static int
651 sfx7101_run_tests(struct efx_nic *efx, int *results, unsigned flags)
652 {
653 int rc;
654
655 if (!(flags & ETH_TEST_FL_OFFLINE))
656 return 0;
657
658 /* BIST is automatically run after a special software reset */
659 rc = tenxpress_special_reset(efx);
660 results[0] = rc ? -1 : 1;
661 return rc;
662 }
663
664 static const char *const sft9001_test_names[] = {
665 "bist",
666 "cable.pairA.status",
667 "cable.pairB.status",
668 "cable.pairC.status",
669 "cable.pairD.status",
670 "cable.pairA.length",
671 "cable.pairB.length",
672 "cable.pairC.length",
673 "cable.pairD.length",
674 };
675
676 static int sft9001_run_tests(struct efx_nic *efx, int *results, unsigned flags)
677 {
678 struct ethtool_cmd ecmd;
679 int phy_id = efx->mii.phy_id;
680 int rc = 0, rc2, i, res_reg;
681
682 if (!(flags & ETH_TEST_FL_OFFLINE))
683 return 0;
684
685 efx->phy_op->get_settings(efx, &ecmd);
686
687 /* Initialise cable diagnostic results to unknown failure */
688 for (i = 1; i < 9; ++i)
689 results[i] = -1;
690
691 /* Run cable diagnostics; wait up to 5 seconds for them to complete.
692 * A cable fault is not a self-test failure, but a timeout is. */
693 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
694 PMA_PMD_CDIAG_CTRL_REG,
695 (1 << CDIAG_CTRL_IMMED_LBN) |
696 (1 << CDIAG_CTRL_BRK_LINK_LBN) |
697 (CDIAG_CTRL_LEN_METRES << CDIAG_CTRL_LEN_UNIT_LBN));
698 i = 0;
699 while (mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
700 PMA_PMD_CDIAG_CTRL_REG) &
701 (1 << CDIAG_CTRL_IN_PROG_LBN)) {
702 if (++i == 50) {
703 rc = -ETIMEDOUT;
704 goto reset;
705 }
706 msleep(100);
707 }
708 res_reg = mdio_clause45_read(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
709 PMA_PMD_CDIAG_RES_REG);
710 for (i = 0; i < 4; i++) {
711 int pair_res =
712 (res_reg >> (CDIAG_RES_A_LBN - i * CDIAG_RES_WIDTH))
713 & ((1 << CDIAG_RES_WIDTH) - 1);
714 int len_reg = mdio_clause45_read(efx, efx->mii.phy_id,
715 MDIO_MMD_PMAPMD,
716 PMA_PMD_CDIAG_LEN_REG + i);
717 if (pair_res == CDIAG_RES_OK)
718 results[1 + i] = 1;
719 else if (pair_res == CDIAG_RES_INVALID)
720 results[1 + i] = -1;
721 else
722 results[1 + i] = -pair_res;
723 if (pair_res != CDIAG_RES_INVALID &&
724 pair_res != CDIAG_RES_OPEN &&
725 len_reg != 0xffff)
726 results[5 + i] = len_reg;
727 }
728
729 /* We must reset to exit cable diagnostic mode. The BIST will
730 * also run when we do this. */
731 reset:
732 rc2 = tenxpress_special_reset(efx);
733 results[0] = rc2 ? -1 : 1;
734 if (!rc)
735 rc = rc2;
736
737 rc2 = efx->phy_op->set_settings(efx, &ecmd);
738 if (!rc)
739 rc = rc2;
740
741 return rc;
742 }
743
744 static u32 tenxpress_get_xnp_lpa(struct efx_nic *efx)
745 {
746 int phy = efx->mii.phy_id;
747 u32 lpa = 0;
748 int reg;
749
750 if (efx->phy_type != PHY_TYPE_SFX7101) {
751 reg = mdio_clause45_read(efx, phy, MDIO_MMD_C22EXT,
752 C22EXT_MSTSLV_REG);
753 if (reg & (1 << C22EXT_MSTSLV_1000_HD_LBN))
754 lpa |= ADVERTISED_1000baseT_Half;
755 if (reg & (1 << C22EXT_MSTSLV_1000_FD_LBN))
756 lpa |= ADVERTISED_1000baseT_Full;
757 }
758 reg = mdio_clause45_read(efx, phy, MDIO_MMD_AN, MDIO_AN_10GBT_STATUS);
759 if (reg & (1 << MDIO_AN_10GBT_STATUS_LP_10G_LBN))
760 lpa |= ADVERTISED_10000baseT_Full;
761 return lpa;
762 }
763
764 static void sfx7101_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
765 {
766 mdio_clause45_get_settings_ext(efx, ecmd, ADVERTISED_10000baseT_Full,
767 tenxpress_get_xnp_lpa(efx));
768 ecmd->supported |= SUPPORTED_10000baseT_Full;
769 ecmd->advertising |= ADVERTISED_10000baseT_Full;
770 }
771
772 static void sft9001_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
773 {
774 int phy_id = efx->mii.phy_id;
775 u32 xnp_adv = 0;
776 int reg;
777
778 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
779 PMA_PMD_SPEED_ENABLE_REG);
780 if (EFX_WORKAROUND_13204(efx) && (reg & (1 << PMA_PMD_100TX_ADV_LBN)))
781 xnp_adv |= ADVERTISED_100baseT_Full;
782 if (reg & (1 << PMA_PMD_1000T_ADV_LBN))
783 xnp_adv |= ADVERTISED_1000baseT_Full;
784 if (reg & (1 << PMA_PMD_10000T_ADV_LBN))
785 xnp_adv |= ADVERTISED_10000baseT_Full;
786
787 mdio_clause45_get_settings_ext(efx, ecmd, xnp_adv,
788 tenxpress_get_xnp_lpa(efx));
789
790 ecmd->supported |= (SUPPORTED_100baseT_Half |
791 SUPPORTED_100baseT_Full |
792 SUPPORTED_1000baseT_Full);
793
794 /* Use the vendor defined C22ext register for duplex settings */
795 if (ecmd->speed != SPEED_10000 && !ecmd->autoneg) {
796 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT,
797 GPHY_XCONTROL_REG);
798 ecmd->duplex = (reg & (1 << GPHY_DUPLEX_LBN) ?
799 DUPLEX_FULL : DUPLEX_HALF);
800 }
801
802 /* In loopback, the PHY automatically brings up the correct interface,
803 * but doesn't advertise the correct speed. So override it */
804 if (efx->loopback_mode == LOOPBACK_GPHY)
805 ecmd->speed = SPEED_1000;
806 else if (LOOPBACK_MASK(efx) & SFT9001_LOOPBACKS)
807 ecmd->speed = SPEED_10000;
808 }
809
810 static int sft9001_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
811 {
812 int phy_id = efx->mii.phy_id;
813 int rc;
814
815 rc = mdio_clause45_set_settings(efx, ecmd);
816 if (rc)
817 return rc;
818
819 if (ecmd->speed != SPEED_10000 && !ecmd->autoneg)
820 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT,
821 GPHY_XCONTROL_REG, GPHY_DUPLEX_LBN,
822 ecmd->duplex == DUPLEX_FULL);
823
824 return rc;
825 }
826
827 static bool sft9001_set_xnp_advertise(struct efx_nic *efx, u32 advertising)
828 {
829 int phy = efx->mii.phy_id;
830 int reg = mdio_clause45_read(efx, phy, MDIO_MMD_PMAPMD,
831 PMA_PMD_SPEED_ENABLE_REG);
832 bool enabled;
833
834 reg &= ~((1 << 2) | (1 << 3));
835 if (EFX_WORKAROUND_13204(efx) &&
836 (advertising & ADVERTISED_100baseT_Full))
837 reg |= 1 << PMA_PMD_100TX_ADV_LBN;
838 if (advertising & ADVERTISED_1000baseT_Full)
839 reg |= 1 << PMA_PMD_1000T_ADV_LBN;
840 if (advertising & ADVERTISED_10000baseT_Full)
841 reg |= 1 << PMA_PMD_10000T_ADV_LBN;
842 mdio_clause45_write(efx, phy, MDIO_MMD_PMAPMD,
843 PMA_PMD_SPEED_ENABLE_REG, reg);
844
845 enabled = (advertising &
846 (ADVERTISED_1000baseT_Half |
847 ADVERTISED_1000baseT_Full |
848 ADVERTISED_10000baseT_Full));
849 if (EFX_WORKAROUND_13204(efx))
850 enabled |= (advertising & ADVERTISED_100baseT_Full);
851 return enabled;
852 }
853
854 struct efx_phy_operations falcon_sfx7101_phy_ops = {
855 .macs = EFX_XMAC,
856 .init = tenxpress_phy_init,
857 .reconfigure = tenxpress_phy_reconfigure,
858 .poll = tenxpress_phy_poll,
859 .fini = tenxpress_phy_fini,
860 .clear_interrupt = efx_port_dummy_op_void,
861 .get_settings = sfx7101_get_settings,
862 .set_settings = mdio_clause45_set_settings,
863 .num_tests = ARRAY_SIZE(sfx7101_test_names),
864 .test_names = sfx7101_test_names,
865 .run_tests = sfx7101_run_tests,
866 .mmds = TENXPRESS_REQUIRED_DEVS,
867 .loopbacks = SFX7101_LOOPBACKS,
868 };
869
870 struct efx_phy_operations falcon_sft9001_phy_ops = {
871 .macs = EFX_GMAC | EFX_XMAC,
872 .init = tenxpress_phy_init,
873 .reconfigure = tenxpress_phy_reconfigure,
874 .poll = tenxpress_phy_poll,
875 .fini = tenxpress_phy_fini,
876 .clear_interrupt = efx_port_dummy_op_void,
877 .get_settings = sft9001_get_settings,
878 .set_settings = sft9001_set_settings,
879 .set_xnp_advertise = sft9001_set_xnp_advertise,
880 .num_tests = ARRAY_SIZE(sft9001_test_names),
881 .test_names = sft9001_test_names,
882 .run_tests = sft9001_run_tests,
883 .mmds = TENXPRESS_REQUIRED_DEVS,
884 .loopbacks = SFT9001_LOOPBACKS,
885 };
(deprecated) Btrfs devel tree