drivers/net/ethernet/ti/davinci_mdio.c

   1 /*
   2  * DaVinci MDIO Module driver
   3  *
   4  * Copyright (C) 2010 Texas Instruments.
   5  *
   6  * Shamelessly ripped out of davinci_emac.c, original copyrights follow:
   7  *
   8  * Copyright (C) 2009 Texas Instruments.
   9  *
  10  * ---------------------------------------------------------------------------
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  * ---------------------------------------------------------------------------
  26  */
  27 #include <linux/module.h>
  28 #include <linux/kernel.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/delay.h>
  31 #include <linux/sched.h>
  32 #include <linux/slab.h>
  33 #include <linux/phy.h>
  34 #include <linux/clk.h>
  35 #include <linux/err.h>
  36 #include <linux/io.h>
  37 #include <linux/pm_runtime.h>
  38 #include <linux/davinci_emac.h>
  39 #include <linux/of.h>
  40 #include <linux/of_device.h>
  41
  42 /*
  43  * This timeout definition is a worst-case ultra defensive measure against
  44  * unexpected controller lock ups.  Ideally, we should never ever hit this
  45  * scenario in practice.
  46  */
  47 #define MDIO_TIMEOUT            100 /* msecs */
  48
  49 #define PHY_REG_MASK            0x1f
  50 #define PHY_ID_MASK             0x1f
  51
  52 #define DEF_OUT_FREQ            2200000         /* 2.2 MHz */
  53
  54 struct davinci_mdio_regs {
  55         u32     version;
  56         u32     control;
  57 #define CONTROL_IDLE            BIT(31)
  58 #define CONTROL_ENABLE          BIT(30)
  59 #define CONTROL_MAX_DIV         (0xffff)
  60
  61         u32     alive;
  62         u32     link;
  63         u32     linkintraw;
  64         u32     linkintmasked;
  65         u32     __reserved_0[2];
  66         u32     userintraw;
  67         u32     userintmasked;
  68         u32     userintmaskset;
  69         u32     userintmaskclr;
  70         u32     __reserved_1[20];
  71
  72         struct {
  73                 u32     access;
  74 #define USERACCESS_GO           BIT(31)
  75 #define USERACCESS_WRITE        BIT(30)
  76 #define USERACCESS_ACK          BIT(29)
  77 #define USERACCESS_READ         (0)
  78 #define USERACCESS_DATA         (0xffff)
  79
  80                 u32     physel;
  81         }       user[0];
  82 };
  83
  84 struct mdio_platform_data default_pdata = {
  85         .bus_freq = DEF_OUT_FREQ,
  86 };
  87
  88 struct davinci_mdio_data {
  89         struct mdio_platform_data pdata;
  90         struct davinci_mdio_regs __iomem *regs;
  91         spinlock_t      lock;
  92         struct clk      *clk;
  93         struct device   *dev;
  94         struct mii_bus  *bus;
  95         bool            suspended;
  96         unsigned long   access_time; /* jiffies */
  97 };
  98
  99 static void __davinci_mdio_reset(struct davinci_mdio_data *data)
 100 {
 101         u32 mdio_in, div, mdio_out_khz, access_time;
 102
 103         mdio_in = clk_get_rate(data->clk);
 104         div = (mdio_in / data->pdata.bus_freq) - 1;
 105         if (div > CONTROL_MAX_DIV)
 106                 div = CONTROL_MAX_DIV;
 107
 108         /* set enable and clock divider */
 109         __raw_writel(div | CONTROL_ENABLE, &data->regs->control);
 110
 111         /*
 112          * One mdio transaction consists of:
 113          *      32 bits of preamble
 114          *      32 bits of transferred data
 115          *      24 bits of bus yield (not needed unless shared?)
 116          */
 117         mdio_out_khz = mdio_in / (1000 * (div + 1));
 118         access_time  = (88 * 1000) / mdio_out_khz;
 119
 120         /*
 121          * In the worst case, we could be kicking off a user-access immediately
 122          * after the mdio bus scan state-machine triggered its own read.  If
 123          * so, our request could get deferred by one access cycle.  We
 124          * defensively allow for 4 access cycles.
 125          */
 126         data->access_time = usecs_to_jiffies(access_time * 4);
 127         if (!data->access_time)
 128                 data->access_time = 1;
 129 }
 130
 131 static int davinci_mdio_reset(struct mii_bus *bus)
 132 {
 133         struct davinci_mdio_data *data = bus->priv;
 134         u32 phy_mask, ver;
 135
 136         __davinci_mdio_reset(data);
 137
 138         /* wait for scan logic to settle */
 139         msleep(PHY_MAX_ADDR * data->access_time);
 140
 141         /* dump hardware version info */
 142         ver = __raw_readl(&data->regs->version);
 143         dev_info(data->dev, "davinci mdio revision %d.%d\n",
 144                  (ver >> 8) & 0xff, ver & 0xff);
 145
 146         /* get phy mask from the alive register */
 147         phy_mask = __raw_readl(&data->regs->alive);
 148         if (phy_mask) {
 149                 /* restrict mdio bus to live phys only */
 150                 dev_info(data->dev, "detected phy mask %x\n", ~phy_mask);
 151                 phy_mask = ~phy_mask;
 152         } else {
 153                 /* desperately scan all phys */
 154                 dev_warn(data->dev, "no live phy, scanning all\n");
 155                 phy_mask = 0;
 156         }
 157         data->bus->phy_mask = phy_mask;
 158
 159         return 0;
 160 }
 161
 162 /* wait until hardware is ready for another user access */
 163 static inline int wait_for_user_access(struct davinci_mdio_data *data)
 164 {
 165         struct davinci_mdio_regs __iomem *regs = data->regs;
 166         unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
 167         u32 reg;
 168
 169         while (time_after(timeout, jiffies)) {
 170                 reg = __raw_readl(&regs->user[0].access);
 171                 if ((reg & USERACCESS_GO) == 0)
 172                         return 0;
 173
 174                 reg = __raw_readl(&regs->control);
 175                 if ((reg & CONTROL_IDLE) == 0)
 176                         continue;
 177
 178                 /*
 179                  * An emac soft_reset may have clobbered the mdio controller's
 180                  * state machine.  We need to reset and retry the current
 181                  * operation
 182                  */
 183                 dev_warn(data->dev, "resetting idled controller\n");
 184                 __davinci_mdio_reset(data);
 185                 return -EAGAIN;
 186         }
 187
 188         reg = __raw_readl(&regs->user[0].access);
 189         if ((reg & USERACCESS_GO) == 0)
 190                 return 0;
 191
 192         dev_err(data->dev, "timed out waiting for user access\n");
 193         return -ETIMEDOUT;
 194 }
 195
 196 /* wait until hardware state machine is idle */
 197 static inline int wait_for_idle(struct davinci_mdio_data *data)
 198 {
 199         struct davinci_mdio_regs __iomem *regs = data->regs;
 200         unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
 201
 202         while (time_after(timeout, jiffies)) {
 203                 if (__raw_readl(&regs->control) & CONTROL_IDLE)
 204                         return 0;
 205         }
 206         dev_err(data->dev, "timed out waiting for idle\n");
 207         return -ETIMEDOUT;
 208 }
 209
 210 static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg)
 211 {
 212         struct davinci_mdio_data *data = bus->priv;
 213         u32 reg;
 214         int ret;
 215
 216         if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
 217                 return -EINVAL;
 218
 219         spin_lock(&data->lock);
 220
 221         if (data->suspended) {
 222                 spin_unlock(&data->lock);
 223                 return -ENODEV;
 224         }
 225
 226         reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
 227                (phy_id << 16));
 228
 229         while (1) {
 230                 ret = wait_for_user_access(data);
 231                 if (ret == -EAGAIN)
 232                         continue;
 233                 if (ret < 0)
 234                         break;
 235
 236                 __raw_writel(reg, &data->regs->user[0].access);
 237
 238                 ret = wait_for_user_access(data);
 239                 if (ret == -EAGAIN)
 240                         continue;
 241                 if (ret < 0)
 242                         break;
 243
 244                 reg = __raw_readl(&data->regs->user[0].access);
 245                 ret = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -EIO;
 246                 break;
 247         }
 248
 249         spin_unlock(&data->lock);
 250
 251         return ret;
 252 }
 253
 254 static int davinci_mdio_write(struct mii_bus *bus, int phy_id,
 255                               int phy_reg, u16 phy_data)
 256 {
 257         struct davinci_mdio_data *data = bus->priv;
 258         u32 reg;
 259         int ret;
 260
 261         if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
 262                 return -EINVAL;
 263
 264         spin_lock(&data->lock);
 265
 266         if (data->suspended) {
 267                 spin_unlock(&data->lock);
 268                 return -ENODEV;
 269         }
 270
 271         reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
 272                    (phy_id << 16) | (phy_data & USERACCESS_DATA));
 273
 274         while (1) {
 275                 ret = wait_for_user_access(data);
 276                 if (ret == -EAGAIN)
 277                         continue;
 278                 if (ret < 0)
 279                         break;
 280
 281                 __raw_writel(reg, &data->regs->user[0].access);
 282
 283                 ret = wait_for_user_access(data);
 284                 if (ret == -EAGAIN)
 285                         continue;
 286                 break;
 287         }
 288
 289         spin_unlock(&data->lock);
 290
 291         return 0;
 292 }
 293
 294 static int davinci_mdio_probe_dt(struct mdio_platform_data *data,
 295                          struct platform_device *pdev)
 296 {
 297         struct device_node *node = pdev->dev.of_node;
 298         u32 prop;
 299
 300         if (!node)
 301                 return -EINVAL;
 302
 303         if (of_property_read_u32(node, "bus_freq", &prop)) {
 304                 pr_err("Missing bus_freq property in the DT.\n");
 305                 return -EINVAL;
 306         }
 307         data->bus_freq = prop;
 308
 309         return 0;
 310 }
 311
 312
 313 static int davinci_mdio_probe(struct platform_device *pdev)
 314 {
 315         struct mdio_platform_data *pdata = pdev->dev.platform_data;
 316         struct device *dev = &pdev->dev;
 317         struct davinci_mdio_data *data;
 318         struct resource *res;
 319         struct phy_device *phy;
 320         int ret, addr;
 321
 322         data = kzalloc(sizeof(*data), GFP_KERNEL);
 323         if (!data)
 324                 return -ENOMEM;
 325
 326         data->bus = mdiobus_alloc();
 327         if (!data->bus) {
 328                 dev_err(dev, "failed to alloc mii bus\n");
 329                 ret = -ENOMEM;
 330                 goto bail_out;
 331         }
 332
 333         if (dev->of_node) {
 334                 if (davinci_mdio_probe_dt(&data->pdata, pdev))
 335                         data->pdata = default_pdata;
 336                 snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
 337         } else {
 338                 data->pdata = pdata ? (*pdata) : default_pdata;
 339                 snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s-%x",
 340                          pdev->name, pdev->id);
 341         }
 342
 343         data->bus->name         = dev_name(dev);
 344         data->bus->read         = davinci_mdio_read,
 345         data->bus->write        = davinci_mdio_write,
 346         data->bus->reset        = davinci_mdio_reset,
 347         data->bus->parent       = dev;
 348         data->bus->priv         = data;
 349
 350         pm_runtime_enable(&pdev->dev);
 351         pm_runtime_get_sync(&pdev->dev);
 352         data->clk = clk_get(&pdev->dev, "fck");
 353         if (IS_ERR(data->clk)) {
 354                 dev_err(dev, "failed to get device clock\n");
 355                 ret = PTR_ERR(data->clk);
 356                 data->clk = NULL;
 357                 goto bail_out;
 358         }
 359
 360         dev_set_drvdata(dev, data);
 361         data->dev = dev;
 362         spin_lock_init(&data->lock);
 363
 364         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 365         if (!res) {
 366                 dev_err(dev, "could not find register map resource\n");
 367                 ret = -ENOENT;
 368                 goto bail_out;
 369         }
 370
 371         res = devm_request_mem_region(dev, res->start, resource_size(res),
 372                                             dev_name(dev));
 373         if (!res) {
 374                 dev_err(dev, "could not allocate register map resource\n");
 375                 ret = -ENXIO;
 376                 goto bail_out;
 377         }
 378
 379         data->regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
 380         if (!data->regs) {
 381                 dev_err(dev, "could not map mdio registers\n");
 382                 ret = -ENOMEM;
 383                 goto bail_out;
 384         }
 385
 386         /* register the mii bus */
 387         ret = mdiobus_register(data->bus);
 388         if (ret)
 389                 goto bail_out;
 390
 391         /* scan and dump the bus */
 392         for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
 393                 phy = data->bus->phy_map[addr];
 394                 if (phy) {
 395                         dev_info(dev, "phy[%d]: device %s, driver %s\n",
 396                                  phy->addr, dev_name(&phy->dev),
 397                                  phy->drv ? phy->drv->name : "unknown");
 398                 }
 399         }
 400
 401         return 0;
 402
 403 bail_out:
 404         if (data->bus)
 405                 mdiobus_free(data->bus);
 406
 407         if (data->clk)
 408                 clk_put(data->clk);
 409         pm_runtime_put_sync(&pdev->dev);
 410         pm_runtime_disable(&pdev->dev);
 411
 412         kfree(data);
 413
 414         return ret;
 415 }
 416
 417 static int davinci_mdio_remove(struct platform_device *pdev)
 418 {
 419         struct device *dev = &pdev->dev;
 420         struct davinci_mdio_data *data = dev_get_drvdata(dev);
 421
 422         if (data->bus) {
 423                 mdiobus_unregister(data->bus);
 424                 mdiobus_free(data->bus);
 425         }
 426
 427         if (data->clk)
 428                 clk_put(data->clk);
 429         pm_runtime_put_sync(&pdev->dev);
 430         pm_runtime_disable(&pdev->dev);
 431
 432         dev_set_drvdata(dev, NULL);
 433
 434         kfree(data);
 435
 436         return 0;
 437 }
 438
 439 static int davinci_mdio_suspend(struct device *dev)
 440 {
 441         struct davinci_mdio_data *data = dev_get_drvdata(dev);
 442         u32 ctrl;
 443
 444         spin_lock(&data->lock);
 445
 446         /* shutdown the scan state machine */
 447         ctrl = __raw_readl(&data->regs->control);
 448         ctrl &= ~CONTROL_ENABLE;
 449         __raw_writel(ctrl, &data->regs->control);
 450         wait_for_idle(data);
 451
 452         pm_runtime_put_sync(data->dev);
 453
 454         data->suspended = true;
 455         spin_unlock(&data->lock);
 456
 457         return 0;
 458 }
 459
 460 static int davinci_mdio_resume(struct device *dev)
 461 {
 462         struct davinci_mdio_data *data = dev_get_drvdata(dev);
 463         u32 ctrl;
 464
 465         spin_lock(&data->lock);
 466         pm_runtime_get_sync(data->dev);
 467
 468         /* restart the scan state machine */
 469         ctrl = __raw_readl(&data->regs->control);
 470         ctrl |= CONTROL_ENABLE;
 471         __raw_writel(ctrl, &data->regs->control);
 472
 473         data->suspended = false;
 474         spin_unlock(&data->lock);
 475
 476         return 0;
 477 }
 478
 479 static const struct dev_pm_ops davinci_mdio_pm_ops = {
 480         .suspend        = davinci_mdio_suspend,
 481         .resume         = davinci_mdio_resume,
 482 };
 483
 484 static const struct of_device_id davinci_mdio_of_mtable[] = {
 485         { .compatible = "ti,davinci_mdio", },
 486         { /* sentinel */ },
 487 };
 488 MODULE_DEVICE_TABLE(of, davinci_mdio_of_mtable);
 489
 490 static struct platform_driver davinci_mdio_driver = {
 491         .driver = {
 492                 .name    = "davinci_mdio",
 493                 .owner   = THIS_MODULE,
 494                 .pm      = &davinci_mdio_pm_ops,
 495                 .of_match_table = of_match_ptr(davinci_mdio_of_mtable),
 496         },
 497         .probe = davinci_mdio_probe,
 498         .remove = davinci_mdio_remove,
 499 };
 500
 501 static int __init davinci_mdio_init(void)
 502 {
 503         return platform_driver_register(&davinci_mdio_driver);
 504 }
 505 device_initcall(davinci_mdio_init);
 506
 507 static void __exit davinci_mdio_exit(void)
 508 {
 509         platform_driver_unregister(&davinci_mdio_driver);
 510 }
 511 module_exit(davinci_mdio_exit);
 512
 513 MODULE_LICENSE("GPL");
 514 MODULE_DESCRIPTION("DaVinci MDIO driver");