arch/powerpc/platforms/chrp/setup.c

   1 /*
   2  *  arch/ppc/platforms/setup.c
   3  *
   4  *  Copyright (C) 1995  Linus Torvalds
   5  *  Adapted from 'alpha' version by Gary Thomas
   6  *  Modified by Cort Dougan (cort@cs.nmt.edu)
   7  */
   8
   9 /*
  10  * bootup setup stuff..
  11  */
  12
  13 #include <linux/config.h>
  14 #include <linux/errno.h>
  15 #include <linux/sched.h>
  16 #include <linux/kernel.h>
  17 #include <linux/mm.h>
  18 #include <linux/stddef.h>
  19 #include <linux/unistd.h>
  20 #include <linux/ptrace.h>
  21 #include <linux/slab.h>
  22 #include <linux/user.h>
  23 #include <linux/a.out.h>
  24 #include <linux/tty.h>
  25 #include <linux/major.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/reboot.h>
  28 #include <linux/init.h>
  29 #include <linux/pci.h>
  30 #include <linux/version.h>
  31 #include <linux/adb.h>
  32 #include <linux/module.h>
  33 #include <linux/delay.h>
  34 #include <linux/ide.h>
  35 #include <linux/console.h>
  36 #include <linux/seq_file.h>
  37 #include <linux/root_dev.h>
  38 #include <linux/initrd.h>
  39 #include <linux/module.h>
  40
  41 #include <asm/io.h>
  42 #include <asm/pgtable.h>
  43 #include <asm/prom.h>
  44 #include <asm/gg2.h>
  45 #include <asm/pci-bridge.h>
  46 #include <asm/dma.h>
  47 #include <asm/machdep.h>
  48 #include <asm/irq.h>
  49 #include <asm/hydra.h>
  50 #include <asm/sections.h>
  51 #include <asm/time.h>
  52 #include <asm/btext.h>
  53 #include <asm/i8259.h>
  54 #include <asm/mpic.h>
  55 #include <asm/rtas.h>
  56 #include <asm/xmon.h>
  57
  58 #include "chrp.h"
  59
  60 void rtas_indicator_progress(char *, unsigned short);
  61 void btext_progress(char *, unsigned short);
  62
  63 int _chrp_type;
  64 EXPORT_SYMBOL(_chrp_type);
  65
  66 struct mpic *chrp_mpic;
  67
  68 /*
  69  * XXX this should be in xmon.h, but putting it there means xmon.h
  70  * has to include <linux/interrupt.h> (to get irqreturn_t), which
  71  * causes all sorts of problems.  -- paulus
  72  */
  73 extern irqreturn_t xmon_irq(int, void *, struct pt_regs *);
  74
  75 extern unsigned long loops_per_jiffy;
  76
  77 #ifdef CONFIG_SMP
  78 extern struct smp_ops_t chrp_smp_ops;
  79 #endif
  80
  81 static const char *gg2_memtypes[4] = {
  82         "FPM", "SDRAM", "EDO", "BEDO"
  83 };
  84 static const char *gg2_cachesizes[4] = {
  85         "256 KB", "512 KB", "1 MB", "Reserved"
  86 };
  87 static const char *gg2_cachetypes[4] = {
  88         "Asynchronous", "Reserved", "Flow-Through Synchronous",
  89         "Pipelined Synchronous"
  90 };
  91 static const char *gg2_cachemodes[4] = {
  92         "Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
  93 };
  94
  95 void chrp_show_cpuinfo(struct seq_file *m)
  96 {
  97         int i, sdramen;
  98         unsigned int t;
  99         struct device_node *root;
 100         const char *model = "";
 101
 102         root = find_path_device("/");
 103         if (root)
 104                 model = get_property(root, "model", NULL);
 105         seq_printf(m, "machine\t\t: CHRP %s\n", model);
 106
 107         /* longtrail (goldengate) stuff */
 108         if (!strncmp(model, "IBM,LongTrail", 13)) {
 109                 /* VLSI VAS96011/12 `Golden Gate 2' */
 110                 /* Memory banks */
 111                 sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
 112                            >>31) & 1;
 113                 for (i = 0; i < (sdramen ? 4 : 6); i++) {
 114                         t = in_le32(gg2_pci_config_base+
 115                                                  GG2_PCI_DRAM_BANK0+
 116                                                  i*4);
 117                         if (!(t & 1))
 118                                 continue;
 119                         switch ((t>>8) & 0x1f) {
 120                         case 0x1f:
 121                                 model = "4 MB";
 122                                 break;
 123                         case 0x1e:
 124                                 model = "8 MB";
 125                                 break;
 126                         case 0x1c:
 127                                 model = "16 MB";
 128                                 break;
 129                         case 0x18:
 130                                 model = "32 MB";
 131                                 break;
 132                         case 0x10:
 133                                 model = "64 MB";
 134                                 break;
 135                         case 0x00:
 136                                 model = "128 MB";
 137                                 break;
 138                         default:
 139                                 model = "Reserved";
 140                                 break;
 141                         }
 142                         seq_printf(m, "memory bank %d\t: %s %s\n", i, model,
 143                                    gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]);
 144                 }
 145                 /* L2 cache */
 146                 t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
 147                 seq_printf(m, "board l2\t: %s %s (%s)\n",
 148                            gg2_cachesizes[(t>>7) & 3],
 149                            gg2_cachetypes[(t>>2) & 3],
 150                            gg2_cachemodes[t & 3]);
 151         }
 152 }
 153
 154 /*
 155  *  Fixes for the National Semiconductor PC78308VUL SuperI/O
 156  *
 157  *  Some versions of Open Firmware incorrectly initialize the IRQ settings
 158  *  for keyboard and mouse
 159  */
 160 static inline void __init sio_write(u8 val, u8 index)
 161 {
 162         outb(index, 0x15c);
 163         outb(val, 0x15d);
 164 }
 165
 166 static inline u8 __init sio_read(u8 index)
 167 {
 168         outb(index, 0x15c);
 169         return inb(0x15d);
 170 }
 171
 172 static void __init sio_fixup_irq(const char *name, u8 device, u8 level,
 173                                      u8 type)
 174 {
 175         u8 level0, type0, active;
 176
 177         /* select logical device */
 178         sio_write(device, 0x07);
 179         active = sio_read(0x30);
 180         level0 = sio_read(0x70);
 181         type0 = sio_read(0x71);
 182         if (level0 != level || type0 != type || !active) {
 183                 printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: "
 184                        "remapping to level %d, type %d, active\n",
 185                        name, level0, type0, !active ? "in" : "", level, type);
 186                 sio_write(0x01, 0x30);
 187                 sio_write(level, 0x70);
 188                 sio_write(type, 0x71);
 189         }
 190 }
 191
 192 static void __init sio_init(void)
 193 {
 194         struct device_node *root;
 195
 196         if ((root = find_path_device("/")) &&
 197             !strncmp(get_property(root, "model", NULL), "IBM,LongTrail", 13)) {
 198                 /* logical device 0 (KBC/Keyboard) */
 199                 sio_fixup_irq("keyboard", 0, 1, 2);
 200                 /* select logical device 1 (KBC/Mouse) */
 201                 sio_fixup_irq("mouse", 1, 12, 2);
 202         }
 203 }
 204
 205
 206 static void __init pegasos_set_l2cr(void)
 207 {
 208         struct device_node *np;
 209
 210         /* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
 211         if (_chrp_type != _CHRP_Pegasos)
 212                 return;
 213
 214         /* Enable L2 cache if needed */
 215         np = find_type_devices("cpu");
 216         if (np != NULL) {
 217                 unsigned int *l2cr = (unsigned int *)
 218                         get_property (np, "l2cr", NULL);
 219                 if (l2cr == NULL) {
 220                         printk ("Pegasos l2cr : no cpu l2cr property found\n");
 221                         return;
 222                 }
 223                 if (!((*l2cr) & 0x80000000)) {
 224                         printk ("Pegasos l2cr : L2 cache was not active, "
 225                                 "activating\n");
 226                         _set_L2CR(0);
 227                         _set_L2CR((*l2cr) | 0x80000000);
 228                 }
 229         }
 230 }
 231
 232 void __init chrp_setup_arch(void)
 233 {
 234         struct device_node *root = find_path_device ("/");
 235         char *machine = NULL;
 236         struct device_node *device;
 237         unsigned int *p = NULL;
 238
 239         /* init to some ~sane value until calibrate_delay() runs */
 240         loops_per_jiffy = 50000000/HZ;
 241
 242         if (root)
 243                 machine = get_property(root, "model", NULL);
 244         if (machine && strncmp(machine, "Pegasos", 7) == 0) {
 245                 _chrp_type = _CHRP_Pegasos;
 246         } else if (machine && strncmp(machine, "IBM", 3) == 0) {
 247                 _chrp_type = _CHRP_IBM;
 248         } else if (machine && strncmp(machine, "MOT", 3) == 0) {
 249                 _chrp_type = _CHRP_Motorola;
 250         } else {
 251                 /* Let's assume it is an IBM chrp if all else fails */
 252                 _chrp_type = _CHRP_IBM;
 253         }
 254         printk("chrp type = %x\n", _chrp_type);
 255
 256         rtas_initialize();
 257         if (rtas_token("display-character") >= 0)
 258                 ppc_md.progress = rtas_progress;
 259
 260         /* use RTAS time-of-day routines if available */
 261         if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) {
 262                 ppc_md.get_boot_time    = rtas_get_boot_time;
 263                 ppc_md.get_rtc_time     = rtas_get_rtc_time;
 264                 ppc_md.set_rtc_time     = rtas_set_rtc_time;
 265         }
 266
 267 #ifdef CONFIG_BOOTX_TEXT
 268         if (ppc_md.progress == NULL && boot_text_mapped)
 269                 ppc_md.progress = btext_progress;
 270 #endif
 271
 272 #ifdef CONFIG_BLK_DEV_INITRD
 273         /* this is fine for chrp */
 274         initrd_below_start_ok = 1;
 275
 276         if (initrd_start)
 277                 ROOT_DEV = Root_RAM0;
 278         else
 279 #endif
 280                 ROOT_DEV = Root_SDA2; /* sda2 (sda1 is for the kernel) */
 281
 282         /* On pegasos, enable the L2 cache if not already done by OF */
 283         pegasos_set_l2cr();
 284
 285         /* Lookup PCI host bridges */
 286         chrp_find_bridges();
 287
 288         /*
 289          *  Temporary fixes for PCI devices.
 290          *  -- Geert
 291          */
 292         hydra_init();           /* Mac I/O */
 293
 294         /*
 295          *  Fix the Super I/O configuration
 296          */
 297         sio_init();
 298
 299         /* Get the event scan rate for the rtas so we know how
 300          * often it expects a heartbeat. -- Cort
 301          */
 302         device = find_devices("rtas");
 303         if (device)
 304                 p = (unsigned int *) get_property
 305                         (device, "rtas-event-scan-rate", NULL);
 306         if (p && *p) {
 307                 ppc_md.heartbeat = chrp_event_scan;
 308                 ppc_md.heartbeat_reset = HZ / (*p * 30) - 1;
 309                 ppc_md.heartbeat_count = 1;
 310                 printk("RTAS Event Scan Rate: %u (%lu jiffies)\n",
 311                        *p, ppc_md.heartbeat_reset);
 312         }
 313
 314         pci_create_OF_bus_map();
 315
 316         /*
 317          * Print the banner, then scroll down so boot progress
 318          * can be printed.  -- Cort
 319          */
 320         if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
 321 }
 322
 323 void
 324 chrp_event_scan(void)
 325 {
 326         unsigned char log[1024];
 327         int ret = 0;
 328
 329         /* XXX: we should loop until the hardware says no more error logs -- Cort */
 330         rtas_call(rtas_token("event-scan"), 4, 1, &ret, 0xffffffff, 0,
 331                   __pa(log), 1024);
 332         ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
 333 }
 334
 335 /*
 336  * Finds the open-pic node and sets up the mpic driver.
 337  */
 338 static void __init chrp_find_openpic(void)
 339 {
 340         struct device_node *np, *root;
 341         int len, i, j, irq_count;
 342         int isu_size, idu_size;
 343         unsigned int *iranges, *opprop = NULL;
 344         int oplen = 0;
 345         unsigned long opaddr;
 346         int na = 1;
 347         unsigned char init_senses[NR_IRQS - NUM_8259_INTERRUPTS];
 348
 349         np = find_type_devices("open-pic");
 350         if (np == NULL)
 351                 return;
 352         root = find_path_device("/");
 353         if (root) {
 354                 opprop = (unsigned int *) get_property
 355                         (root, "platform-open-pic", &oplen);
 356                 na = prom_n_addr_cells(root);
 357         }
 358         if (opprop && oplen >= na * sizeof(unsigned int)) {
 359                 opaddr = opprop[na-1];  /* assume 32-bit */
 360                 oplen /= na * sizeof(unsigned int);
 361         } else {
 362                 if (np->n_addrs == 0)
 363                         return;
 364                 opaddr = np->addrs[0].address;
 365                 oplen = 0;
 366         }
 367
 368         printk(KERN_INFO "OpenPIC at %lx\n", opaddr);
 369
 370         irq_count = NR_IRQS - NUM_ISA_INTERRUPTS - 4; /* leave room for IPIs */
 371         prom_get_irq_senses(init_senses, NUM_ISA_INTERRUPTS, NR_IRQS - 4);
 372         /* i8259 cascade is always positive level */
 373         init_senses[0] = IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE;
 374
 375         iranges = (unsigned int *) get_property(np, "interrupt-ranges", &len);
 376         if (iranges == NULL)
 377                 len = 0;        /* non-distributed mpic */
 378         else
 379                 len /= 2 * sizeof(unsigned int);
 380
 381         /*
 382          * The first pair of cells in interrupt-ranges refers to the
 383          * IDU; subsequent pairs refer to the ISUs.
 384          */
 385         if (oplen < len) {
 386                 printk(KERN_ERR "Insufficient addresses for distributed"
 387                        " OpenPIC (%d < %d)\n", np->n_addrs, len);
 388                 len = oplen;
 389         }
 390
 391         isu_size = 0;
 392         idu_size = 0;
 393         if (len > 0 && iranges[1] != 0) {
 394                 printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n",
 395                        iranges[0], iranges[0] + iranges[1] - 1);
 396                 idu_size = iranges[1];
 397         }
 398         if (len > 1)
 399                 isu_size = iranges[3];
 400
 401         chrp_mpic = mpic_alloc(opaddr, MPIC_PRIMARY,
 402                                isu_size, NUM_ISA_INTERRUPTS, irq_count,
 403                                NR_IRQS - 4, init_senses, irq_count,
 404                                " MPIC    ");
 405         if (chrp_mpic == NULL) {
 406                 printk(KERN_ERR "Failed to allocate MPIC structure\n");
 407                 return;
 408         }
 409
 410         j = na - 1;
 411         for (i = 1; i < len; ++i) {
 412                 iranges += 2;
 413                 j += na;
 414                 printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n",
 415                        iranges[0], iranges[0] + iranges[1] - 1,
 416                        opprop[j]);
 417                 mpic_assign_isu(chrp_mpic, i - 1, opprop[j]);
 418         }
 419
 420         mpic_init(chrp_mpic);
 421         mpic_setup_cascade(NUM_ISA_INTERRUPTS, i8259_irq_cascade, NULL);
 422 }
 423
 424 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
 425 static struct irqaction xmon_irqaction = {
 426         .handler = xmon_irq,
 427         .mask = CPU_MASK_NONE,
 428         .name = "XMON break",
 429 };
 430 #endif
 431
 432 void __init chrp_init_IRQ(void)
 433 {
 434         struct device_node *np;
 435         unsigned long chrp_int_ack = 0;
 436 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
 437         struct device_node *kbd;
 438 #endif
 439
 440         for (np = find_devices("pci"); np != NULL; np = np->next) {
 441                 unsigned int *addrp = (unsigned int *)
 442                         get_property(np, "8259-interrupt-acknowledge", NULL);
 443
 444                 if (addrp == NULL)
 445                         continue;
 446                 chrp_int_ack = addrp[prom_n_addr_cells(np)-1];
 447                 break;
 448         }
 449         if (np == NULL)
 450                 printk(KERN_ERR "Cannot find PCI interrupt acknowledge address\n");
 451
 452         chrp_find_openpic();
 453
 454         i8259_init(chrp_int_ack, 0);
 455
 456         if (_chrp_type == _CHRP_Pegasos)
 457                 ppc_md.get_irq        = i8259_irq;
 458         else
 459                 ppc_md.get_irq        = mpic_get_irq;
 460
 461 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
 462         /* see if there is a keyboard in the device tree
 463            with a parent of type "adb" */
 464         for (kbd = find_devices("keyboard"); kbd; kbd = kbd->next)
 465                 if (kbd->parent && kbd->parent->type
 466                     && strcmp(kbd->parent->type, "adb") == 0)
 467                         break;
 468         if (kbd)
 469                 setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction);
 470 #endif
 471 }
 472
 473 void __init
 474 chrp_init2(void)
 475 {
 476 #ifdef CONFIG_NVRAM
 477         chrp_nvram_init();
 478 #endif
 479
 480         request_region(0x20,0x20,"pic1");
 481         request_region(0xa0,0x20,"pic2");
 482         request_region(0x00,0x20,"dma1");
 483         request_region(0x40,0x20,"timer");
 484         request_region(0x80,0x10,"dma page reg");
 485         request_region(0xc0,0x20,"dma2");
 486
 487         if (ppc_md.progress)
 488                 ppc_md.progress("  Have fun!    ", 0x7777);
 489 }
 490
 491 void __init chrp_init(void)
 492 {
 493         ISA_DMA_THRESHOLD = ~0L;
 494         DMA_MODE_READ = 0x44;
 495         DMA_MODE_WRITE = 0x48;
 496         isa_io_base = CHRP_ISA_IO_BASE;         /* default value */
 497         ppc_do_canonicalize_irqs = 1;
 498
 499         /* Assume we have an 8259... */
 500         __irq_offset_value = NUM_ISA_INTERRUPTS;
 501
 502         ppc_md.setup_arch     = chrp_setup_arch;
 503         ppc_md.show_cpuinfo   = chrp_show_cpuinfo;
 504
 505         ppc_md.init_IRQ       = chrp_init_IRQ;
 506         ppc_md.init           = chrp_init2;
 507
 508         ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
 509
 510         ppc_md.restart        = rtas_restart;
 511         ppc_md.power_off      = rtas_power_off;
 512         ppc_md.halt           = rtas_halt;
 513
 514         ppc_md.time_init      = chrp_time_init;
 515         ppc_md.calibrate_decr = chrp_calibrate_decr;
 516
 517         /* this may get overridden with rtas routines later... */
 518         ppc_md.set_rtc_time   = chrp_set_rtc_time;
 519         ppc_md.get_rtc_time   = chrp_get_rtc_time;
 520
 521 #ifdef CONFIG_SMP
 522         smp_ops = &chrp_smp_ops;
 523 #endif /* CONFIG_SMP */
 524 }
 525
 526 #ifdef CONFIG_BOOTX_TEXT
 527 void
 528 btext_progress(char *s, unsigned short hex)
 529 {
 530         btext_drawstring(s);
 531         btext_drawstring("\n");
 532 }
 533 #endif /* CONFIG_BOOTX_TEXT */