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PCI: mvebu: Move port parsing and resource claiming to separate function
[linux-2.6/btrfs-unstable.git] / drivers / pci / host / pci-mvebu.c
blob13ab0350f7fb92bad15d2a1416919c69b69eaf80
1 /*
2 * PCIe driver for Marvell Armada 370 and Armada XP SoCs
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/gpio.h>
14 #include <linux/module.h>
15 #include <linux/mbus.h>
16 #include <linux/msi.h>
17 #include <linux/slab.h>
18 #include <linux/platform_device.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_pci.h>
23 #include <linux/of_platform.h>
24
25 /*
26 * PCIe unit register offsets.
27 */
28 #define PCIE_DEV_ID_OFF 0x0000
29 #define PCIE_CMD_OFF 0x0004
30 #define PCIE_DEV_REV_OFF 0x0008
31 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
32 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
33 #define PCIE_HEADER_LOG_4_OFF 0x0128
34 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
35 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
36 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
37 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
38 #define PCIE_WIN5_CTRL_OFF 0x1880
39 #define PCIE_WIN5_BASE_OFF 0x1884
40 #define PCIE_WIN5_REMAP_OFF 0x188c
41 #define PCIE_CONF_ADDR_OFF 0x18f8
42 #define PCIE_CONF_ADDR_EN 0x80000000
43 #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
44 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
45 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
46 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
47 #define PCIE_CONF_ADDR(bus, devfn, where) \
48 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
49 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
50 PCIE_CONF_ADDR_EN)
51 #define PCIE_CONF_DATA_OFF 0x18fc
52 #define PCIE_MASK_OFF 0x1910
53 #define PCIE_MASK_ENABLE_INTS 0x0f000000
54 #define PCIE_CTRL_OFF 0x1a00
55 #define PCIE_CTRL_X1_MODE 0x0001
56 #define PCIE_STAT_OFF 0x1a04
57 #define PCIE_STAT_BUS 0xff00
58 #define PCIE_STAT_DEV 0x1f0000
59 #define PCIE_STAT_LINK_DOWN BIT(0)
60 #define PCIE_DEBUG_CTRL 0x1a60
61 #define PCIE_DEBUG_SOFT_RESET BIT(20)
62
63 /* PCI configuration space of a PCI-to-PCI bridge */
64 struct mvebu_sw_pci_bridge {
65 u16 vendor;
66 u16 device;
67 u16 command;
68 u16 class;
69 u8 interface;
70 u8 revision;
71 u8 bist;
72 u8 header_type;
73 u8 latency_timer;
74 u8 cache_line_size;
75 u32 bar[2];
76 u8 primary_bus;
77 u8 secondary_bus;
78 u8 subordinate_bus;
79 u8 secondary_latency_timer;
80 u8 iobase;
81 u8 iolimit;
82 u16 secondary_status;
83 u16 membase;
84 u16 memlimit;
85 u16 iobaseupper;
86 u16 iolimitupper;
87 u8 cappointer;
88 u8 reserved1;
89 u16 reserved2;
90 u32 romaddr;
91 u8 intline;
92 u8 intpin;
93 u16 bridgectrl;
94 };
95
96 struct mvebu_pcie_port;
97
98 /* Structure representing all PCIe interfaces */
99 struct mvebu_pcie {
100 struct platform_device *pdev;
101 struct mvebu_pcie_port *ports;
102 struct msi_controller *msi;
103 struct resource io;
104 struct resource realio;
105 struct resource mem;
106 struct resource busn;
107 int nports;
108 };
109
110 /* Structure representing one PCIe interface */
111 struct mvebu_pcie_port {
112 char *name;
113 void __iomem *base;
114 u32 port;
115 u32 lane;
116 int devfn;
117 unsigned int mem_target;
118 unsigned int mem_attr;
119 unsigned int io_target;
120 unsigned int io_attr;
121 struct clk *clk;
122 int reset_gpio;
123 int reset_active_low;
124 char *reset_name;
125 struct mvebu_sw_pci_bridge bridge;
126 struct device_node *dn;
127 struct mvebu_pcie *pcie;
128 phys_addr_t memwin_base;
129 size_t memwin_size;
130 phys_addr_t iowin_base;
131 size_t iowin_size;
132 u32 saved_pcie_stat;
133 };
134
135 static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
136 {
137 writel(val, port->base + reg);
138 }
139
140 static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg)
141 {
142 return readl(port->base + reg);
143 }
144
145 static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port)
146 {
147 return port->io_target != -1 && port->io_attr != -1;
148 }
149
150 static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
151 {
152 return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
153 }
154
155 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
156 {
157 u32 stat;
158
159 stat = mvebu_readl(port, PCIE_STAT_OFF);
160 stat &= ~PCIE_STAT_BUS;
161 stat |= nr << 8;
162 mvebu_writel(port, stat, PCIE_STAT_OFF);
163 }
164
165 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
166 {
167 u32 stat;
168
169 stat = mvebu_readl(port, PCIE_STAT_OFF);
170 stat &= ~PCIE_STAT_DEV;
171 stat |= nr << 16;
172 mvebu_writel(port, stat, PCIE_STAT_OFF);
173 }
174
175 /*
176 * Setup PCIE BARs and Address Decode Wins:
177 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
178 * WIN[0-3] -> DRAM bank[0-3]
179 */
180 static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
181 {
182 const struct mbus_dram_target_info *dram;
183 u32 size;
184 int i;
185
186 dram = mv_mbus_dram_info();
187
188 /* First, disable and clear BARs and windows. */
189 for (i = 1; i < 3; i++) {
190 mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
191 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
192 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
193 }
194
195 for (i = 0; i < 5; i++) {
196 mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
197 mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
198 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
199 }
200
201 mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
202 mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
203 mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
204
205 /* Setup windows for DDR banks. Count total DDR size on the fly. */
206 size = 0;
207 for (i = 0; i < dram->num_cs; i++) {
208 const struct mbus_dram_window *cs = dram->cs + i;
209
210 mvebu_writel(port, cs->base & 0xffff0000,
211 PCIE_WIN04_BASE_OFF(i));
212 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
213 mvebu_writel(port,
214 ((cs->size - 1) & 0xffff0000) |
215 (cs->mbus_attr << 8) |
216 (dram->mbus_dram_target_id << 4) | 1,
217 PCIE_WIN04_CTRL_OFF(i));
218
219 size += cs->size;
220 }
221
222 /* Round up 'size' to the nearest power of two. */
223 if ((size & (size - 1)) != 0)
224 size = 1 << fls(size);
225
226 /* Setup BAR[1] to all DRAM banks. */
227 mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));
228 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
229 mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
230 PCIE_BAR_CTRL_OFF(1));
231 }
232
233 static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
234 {
235 u32 cmd, mask;
236
237 /* Point PCIe unit MBUS decode windows to DRAM space. */
238 mvebu_pcie_setup_wins(port);
239
240 /* Master + slave enable. */
241 cmd = mvebu_readl(port, PCIE_CMD_OFF);
242 cmd |= PCI_COMMAND_IO;
243 cmd |= PCI_COMMAND_MEMORY;
244 cmd |= PCI_COMMAND_MASTER;
245 mvebu_writel(port, cmd, PCIE_CMD_OFF);
246
247 /* Enable interrupt lines A-D. */
248 mask = mvebu_readl(port, PCIE_MASK_OFF);
249 mask |= PCIE_MASK_ENABLE_INTS;
250 mvebu_writel(port, mask, PCIE_MASK_OFF);
251 }
252
253 static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
254 struct pci_bus *bus,
255 u32 devfn, int where, int size, u32 *val)
256 {
257 void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF;
258
259 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
260 PCIE_CONF_ADDR_OFF);
261
262 switch (size) {
263 case 1:
264 *val = readb_relaxed(conf_data + (where & 3));
265 break;
266 case 2:
267 *val = readw_relaxed(conf_data + (where & 2));
268 break;
269 case 4:
270 *val = readl_relaxed(conf_data);
271 break;
272 }
273
274 return PCIBIOS_SUCCESSFUL;
275 }
276
277 static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
278 struct pci_bus *bus,
279 u32 devfn, int where, int size, u32 val)
280 {
281 void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF;
282
283 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
284 PCIE_CONF_ADDR_OFF);
285
286 switch (size) {
287 case 1:
288 writeb(val, conf_data + (where & 3));
289 break;
290 case 2:
291 writew(val, conf_data + (where & 2));
292 break;
293 case 4:
294 writel(val, conf_data);
295 break;
296 default:
297 return PCIBIOS_BAD_REGISTER_NUMBER;
298 }
299
300 return PCIBIOS_SUCCESSFUL;
301 }
302
303 /*
304 * Remove windows, starting from the largest ones to the smallest
305 * ones.
306 */
307 static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port,
308 phys_addr_t base, size_t size)
309 {
310 while (size) {
311 size_t sz = 1 << (fls(size) - 1);
312
313 mvebu_mbus_del_window(base, sz);
314 base += sz;
315 size -= sz;
316 }
317 }
318
319 /*
320 * MBus windows can only have a power of two size, but PCI BARs do not
321 * have this constraint. Therefore, we have to split the PCI BAR into
322 * areas each having a power of two size. We start from the largest
323 * one (i.e highest order bit set in the size).
324 */
325 static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port,
326 unsigned int target, unsigned int attribute,
327 phys_addr_t base, size_t size,
328 phys_addr_t remap)
329 {
330 size_t size_mapped = 0;
331
332 while (size) {
333 size_t sz = 1 << (fls(size) - 1);
334 int ret;
335
336 ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base,
337 sz, remap);
338 if (ret) {
339 phys_addr_t end = base + sz - 1;
340
341 dev_err(&port->pcie->pdev->dev,
342 "Could not create MBus window at [mem %pa-%pa]: %d\n",
343 &base, &end, ret);
344 mvebu_pcie_del_windows(port, base - size_mapped,
345 size_mapped);
346 return;
347 }
348
349 size -= sz;
350 size_mapped += sz;
351 base += sz;
352 if (remap != MVEBU_MBUS_NO_REMAP)
353 remap += sz;
354 }
355 }
356
357 static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
358 {
359 phys_addr_t iobase;
360
361 /* Are the new iobase/iolimit values invalid? */
362 if (port->bridge.iolimit < port->bridge.iobase ||
363 port->bridge.iolimitupper < port->bridge.iobaseupper ||
364 !(port->bridge.command & PCI_COMMAND_IO)) {
365
366 /* If a window was configured, remove it */
367 if (port->iowin_base) {
368 mvebu_pcie_del_windows(port, port->iowin_base,
369 port->iowin_size);
370 port->iowin_base = 0;
371 port->iowin_size = 0;
372 }
373
374 return;
375 }
376
377 if (!mvebu_has_ioport(port)) {
378 dev_WARN(&port->pcie->pdev->dev,
379 "Attempt to set IO when IO is disabled\n");
380 return;
381 }
382
383 /*
384 * We read the PCI-to-PCI bridge emulated registers, and
385 * calculate the base address and size of the address decoding
386 * window to setup, according to the PCI-to-PCI bridge
387 * specifications. iobase is the bus address, port->iowin_base
388 * is the CPU address.
389 */
390 iobase = ((port->bridge.iobase & 0xF0) << 8) |
391 (port->bridge.iobaseupper << 16);
392 port->iowin_base = port->pcie->io.start + iobase;
393 port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
394 (port->bridge.iolimitupper << 16)) -
395 iobase) + 1;
396
397 mvebu_pcie_add_windows(port, port->io_target, port->io_attr,
398 port->iowin_base, port->iowin_size,
399 iobase);
400 }
401
402 static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
403 {
404 /* Are the new membase/memlimit values invalid? */
405 if (port->bridge.memlimit < port->bridge.membase ||
406 !(port->bridge.command & PCI_COMMAND_MEMORY)) {
407
408 /* If a window was configured, remove it */
409 if (port->memwin_base) {
410 mvebu_pcie_del_windows(port, port->memwin_base,
411 port->memwin_size);
412 port->memwin_base = 0;
413 port->memwin_size = 0;
414 }
415
416 return;
417 }
418
419 /*
420 * We read the PCI-to-PCI bridge emulated registers, and
421 * calculate the base address and size of the address decoding
422 * window to setup, according to the PCI-to-PCI bridge
423 * specifications.
424 */
425 port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16);
426 port->memwin_size =
427 (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
428 port->memwin_base + 1;
429
430 mvebu_pcie_add_windows(port, port->mem_target, port->mem_attr,
431 port->memwin_base, port->memwin_size,
432 MVEBU_MBUS_NO_REMAP);
433 }
434
435 /*
436 * Initialize the configuration space of the PCI-to-PCI bridge
437 * associated with the given PCIe interface.
438 */
439 static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
440 {
441 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
442
443 memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
444
445 bridge->class = PCI_CLASS_BRIDGE_PCI;
446 bridge->vendor = PCI_VENDOR_ID_MARVELL;
447 bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
448 bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;
449 bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
450 bridge->cache_line_size = 0x10;
451
452 /* We support 32 bits I/O addressing */
453 bridge->iobase = PCI_IO_RANGE_TYPE_32;
454 bridge->iolimit = PCI_IO_RANGE_TYPE_32;
455 }
456
457 /*
458 * Read the configuration space of the PCI-to-PCI bridge associated to
459 * the given PCIe interface.
460 */
461 static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
462 unsigned int where, int size, u32 *value)
463 {
464 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
465
466 switch (where & ~3) {
467 case PCI_VENDOR_ID:
468 *value = bridge->device << 16 | bridge->vendor;
469 break;
470
471 case PCI_COMMAND:
472 *value = bridge->command;
473 break;
474
475 case PCI_CLASS_REVISION:
476 *value = bridge->class << 16 | bridge->interface << 8 |
477 bridge->revision;
478 break;
479
480 case PCI_CACHE_LINE_SIZE:
481 *value = bridge->bist << 24 | bridge->header_type << 16 |
482 bridge->latency_timer << 8 | bridge->cache_line_size;
483 break;
484
485 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
486 *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
487 break;
488
489 case PCI_PRIMARY_BUS:
490 *value = (bridge->secondary_latency_timer << 24 |
491 bridge->subordinate_bus << 16 |
492 bridge->secondary_bus << 8 |
493 bridge->primary_bus);
494 break;
495
496 case PCI_IO_BASE:
497 if (!mvebu_has_ioport(port))
498 *value = bridge->secondary_status << 16;
499 else
500 *value = (bridge->secondary_status << 16 |
501 bridge->iolimit << 8 |
502 bridge->iobase);
503 break;
504
505 case PCI_MEMORY_BASE:
506 *value = (bridge->memlimit << 16 | bridge->membase);
507 break;
508
509 case PCI_PREF_MEMORY_BASE:
510 *value = 0;
511 break;
512
513 case PCI_IO_BASE_UPPER16:
514 *value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
515 break;
516
517 case PCI_ROM_ADDRESS1:
518 *value = 0;
519 break;
520
521 case PCI_INTERRUPT_LINE:
522 /* LINE PIN MIN_GNT MAX_LAT */
523 *value = 0;
524 break;
525
526 default:
527 /*
528 * PCI defines configuration read accesses to reserved or
529 * unimplemented registers to read as zero and complete
530 * normally.
531 */
532 *value = 0;
533 return PCIBIOS_SUCCESSFUL;
534 }
535
536 if (size == 2)
537 *value = (*value >> (8 * (where & 3))) & 0xffff;
538 else if (size == 1)
539 *value = (*value >> (8 * (where & 3))) & 0xff;
540
541 return PCIBIOS_SUCCESSFUL;
542 }
543
544 /* Write to the PCI-to-PCI bridge configuration space */
545 static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
546 unsigned int where, int size, u32 value)
547 {
548 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
549 u32 mask, reg;
550 int err;
551
552 if (size == 4)
553 mask = 0x0;
554 else if (size == 2)
555 mask = ~(0xffff << ((where & 3) * 8));
556 else if (size == 1)
557 mask = ~(0xff << ((where & 3) * 8));
558 else
559 return PCIBIOS_BAD_REGISTER_NUMBER;
560
561 err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, &reg);
562 if (err)
563 return err;
564
565 value = (reg & mask) | value << ((where & 3) * 8);
566
567 switch (where & ~3) {
568 case PCI_COMMAND:
569 {
570 u32 old = bridge->command;
571
572 if (!mvebu_has_ioport(port))
573 value &= ~PCI_COMMAND_IO;
574
575 bridge->command = value & 0xffff;
576 if ((old ^ bridge->command) & PCI_COMMAND_IO)
577 mvebu_pcie_handle_iobase_change(port);
578 if ((old ^ bridge->command) & PCI_COMMAND_MEMORY)
579 mvebu_pcie_handle_membase_change(port);
580 break;
581 }
582
583 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
584 bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
585 break;
586
587 case PCI_IO_BASE:
588 /*
589 * We also keep bit 1 set, it is a read-only bit that
590 * indicates we support 32 bits addressing for the
591 * I/O
592 */
593 bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
594 bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
595 mvebu_pcie_handle_iobase_change(port);
596 break;
597
598 case PCI_MEMORY_BASE:
599 bridge->membase = value & 0xffff;
600 bridge->memlimit = value >> 16;
601 mvebu_pcie_handle_membase_change(port);
602 break;
603
604 case PCI_IO_BASE_UPPER16:
605 bridge->iobaseupper = value & 0xffff;
606 bridge->iolimitupper = value >> 16;
607 mvebu_pcie_handle_iobase_change(port);
608 break;
609
610 case PCI_PRIMARY_BUS:
611 bridge->primary_bus = value & 0xff;
612 bridge->secondary_bus = (value >> 8) & 0xff;
613 bridge->subordinate_bus = (value >> 16) & 0xff;
614 bridge->secondary_latency_timer = (value >> 24) & 0xff;
615 mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
616 break;
617
618 default:
619 break;
620 }
621
622 return PCIBIOS_SUCCESSFUL;
623 }
624
625 static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
626 {
627 return sys->private_data;
628 }
629
630 static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie,
631 struct pci_bus *bus,
632 int devfn)
633 {
634 int i;
635
636 for (i = 0; i < pcie->nports; i++) {
637 struct mvebu_pcie_port *port = &pcie->ports[i];
638
639 if (bus->number == 0 && port->devfn == devfn)
640 return port;
641 if (bus->number != 0 &&
642 bus->number >= port->bridge.secondary_bus &&
643 bus->number <= port->bridge.subordinate_bus)
644 return port;
645 }
646
647 return NULL;
648 }
649
650 /* PCI configuration space write function */
651 static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
652 int where, int size, u32 val)
653 {
654 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
655 struct mvebu_pcie_port *port;
656 int ret;
657
658 port = mvebu_pcie_find_port(pcie, bus, devfn);
659 if (!port)
660 return PCIBIOS_DEVICE_NOT_FOUND;
661
662 /* Access the emulated PCI-to-PCI bridge */
663 if (bus->number == 0)
664 return mvebu_sw_pci_bridge_write(port, where, size, val);
665
666 if (!mvebu_pcie_link_up(port))
667 return PCIBIOS_DEVICE_NOT_FOUND;
668
669 /*
670 * On the secondary bus, we don't want to expose any other
671 * device than the device physically connected in the PCIe
672 * slot, visible in slot 0. In slot 1, there's a special
673 * Marvell device that only makes sense when the Armada is
674 * used as a PCIe endpoint.
675 */
676 if (bus->number == port->bridge.secondary_bus &&
677 PCI_SLOT(devfn) != 0)
678 return PCIBIOS_DEVICE_NOT_FOUND;
679
680 /* Access the real PCIe interface */
681 ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
682 where, size, val);
683
684 return ret;
685 }
686
687 /* PCI configuration space read function */
688 static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
689 int size, u32 *val)
690 {
691 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
692 struct mvebu_pcie_port *port;
693 int ret;
694
695 port = mvebu_pcie_find_port(pcie, bus, devfn);
696 if (!port) {
697 *val = 0xffffffff;
698 return PCIBIOS_DEVICE_NOT_FOUND;
699 }
700
701 /* Access the emulated PCI-to-PCI bridge */
702 if (bus->number == 0)
703 return mvebu_sw_pci_bridge_read(port, where, size, val);
704
705 if (!mvebu_pcie_link_up(port)) {
706 *val = 0xffffffff;
707 return PCIBIOS_DEVICE_NOT_FOUND;
708 }
709
710 /*
711 * On the secondary bus, we don't want to expose any other
712 * device than the device physically connected in the PCIe
713 * slot, visible in slot 0. In slot 1, there's a special
714 * Marvell device that only makes sense when the Armada is
715 * used as a PCIe endpoint.
716 */
717 if (bus->number == port->bridge.secondary_bus &&
718 PCI_SLOT(devfn) != 0) {
719 *val = 0xffffffff;
720 return PCIBIOS_DEVICE_NOT_FOUND;
721 }
722
723 /* Access the real PCIe interface */
724 ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
725 where, size, val);
726
727 return ret;
728 }
729
730 static struct pci_ops mvebu_pcie_ops = {
731 .read = mvebu_pcie_rd_conf,
732 .write = mvebu_pcie_wr_conf,
733 };
734
735 static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
736 {
737 struct mvebu_pcie *pcie = sys_to_pcie(sys);
738 int i;
739
740 pcie->mem.name = "PCI MEM";
741 pcie->realio.name = "PCI I/O";
742
743 if (request_resource(&iomem_resource, &pcie->mem))
744 return 0;
745
746 if (resource_size(&pcie->realio) != 0) {
747 if (request_resource(&ioport_resource, &pcie->realio)) {
748 release_resource(&pcie->mem);
749 return 0;
750 }
751 pci_add_resource_offset(&sys->resources, &pcie->realio,
752 sys->io_offset);
753 }
754 pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
755 pci_add_resource(&sys->resources, &pcie->busn);
756
757 for (i = 0; i < pcie->nports; i++) {
758 struct mvebu_pcie_port *port = &pcie->ports[i];
759
760 if (!port->base)
761 continue;
762 mvebu_pcie_setup_hw(port);
763 }
764
765 return 1;
766 }
767
768 static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
769 const struct resource *res,
770 resource_size_t start,
771 resource_size_t size,
772 resource_size_t align)
773 {
774 if (dev->bus->number != 0)
775 return start;
776
777 /*
778 * On the PCI-to-PCI bridge side, the I/O windows must have at
779 * least a 64 KB size and the memory windows must have at
780 * least a 1 MB size. Moreover, MBus windows need to have a
781 * base address aligned on their size, and their size must be
782 * a power of two. This means that if the BAR doesn't have a
783 * power of two size, several MBus windows will actually be
784 * created. We need to ensure that the biggest MBus window
785 * (which will be the first one) is aligned on its size, which
786 * explains the rounddown_pow_of_two() being done here.
787 */
788 if (res->flags & IORESOURCE_IO)
789 return round_up(start, max_t(resource_size_t, SZ_64K,
790 rounddown_pow_of_two(size)));
791 else if (res->flags & IORESOURCE_MEM)
792 return round_up(start, max_t(resource_size_t, SZ_1M,
793 rounddown_pow_of_two(size)));
794 else
795 return start;
796 }
797
798 static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
799 {
800 struct hw_pci hw;
801
802 memset(&hw, 0, sizeof(hw));
803
804 #ifdef CONFIG_PCI_MSI
805 hw.msi_ctrl = pcie->msi;
806 #endif
807
808 hw.nr_controllers = 1;
809 hw.private_data = (void **)&pcie;
810 hw.setup = mvebu_pcie_setup;
811 hw.map_irq = of_irq_parse_and_map_pci;
812 hw.ops = &mvebu_pcie_ops;
813 hw.align_resource = mvebu_pcie_align_resource;
814
815 pci_common_init_dev(&pcie->pdev->dev, &hw);
816 }
817
818 /*
819 * Looks up the list of register addresses encoded into the reg =
820 * <...> property for one that matches the given port/lane. Once
821 * found, maps it.
822 */
823 static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev,
824 struct device_node *np,
825 struct mvebu_pcie_port *port)
826 {
827 struct resource regs;
828 int ret = 0;
829
830 ret = of_address_to_resource(np, 0, &regs);
831 if (ret)
832 return ERR_PTR(ret);
833
834 return devm_ioremap_resource(&pdev->dev, &regs);
835 }
836
837 #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
838 #define DT_TYPE_IO 0x1
839 #define DT_TYPE_MEM32 0x2
840 #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
841 #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
842
843 static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
844 unsigned long type,
845 unsigned int *tgt,
846 unsigned int *attr)
847 {
848 const int na = 3, ns = 2;
849 const __be32 *range;
850 int rlen, nranges, rangesz, pna, i;
851
852 *tgt = -1;
853 *attr = -1;
854
855 range = of_get_property(np, "ranges", &rlen);
856 if (!range)
857 return -EINVAL;
858
859 pna = of_n_addr_cells(np);
860 rangesz = pna + na + ns;
861 nranges = rlen / sizeof(__be32) / rangesz;
862
863 for (i = 0; i < nranges; i++, range += rangesz) {
864 u32 flags = of_read_number(range, 1);
865 u32 slot = of_read_number(range + 1, 1);
866 u64 cpuaddr = of_read_number(range + na, pna);
867 unsigned long rtype;
868
869 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
870 rtype = IORESOURCE_IO;
871 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
872 rtype = IORESOURCE_MEM;
873 else
874 continue;
875
876 if (slot == PCI_SLOT(devfn) && type == rtype) {
877 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
878 *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
879 return 0;
880 }
881 }
882
883 return -ENOENT;
884 }
885
886 static void mvebu_pcie_msi_enable(struct mvebu_pcie *pcie)
887 {
888 struct device_node *msi_node;
889
890 msi_node = of_parse_phandle(pcie->pdev->dev.of_node,
891 "msi-parent", 0);
892 if (!msi_node)
893 return;
894
895 pcie->msi = of_pci_find_msi_chip_by_node(msi_node);
896 of_node_put(msi_node);
897
898 if (pcie->msi)
899 pcie->msi->dev = &pcie->pdev->dev;
900 }
901
902 static int mvebu_pcie_suspend(struct device *dev)
903 {
904 struct mvebu_pcie *pcie;
905 int i;
906
907 pcie = dev_get_drvdata(dev);
908 for (i = 0; i < pcie->nports; i++) {
909 struct mvebu_pcie_port *port = pcie->ports + i;
910 port->saved_pcie_stat = mvebu_readl(port, PCIE_STAT_OFF);
911 }
912
913 return 0;
914 }
915
916 static int mvebu_pcie_resume(struct device *dev)
917 {
918 struct mvebu_pcie *pcie;
919 int i;
920
921 pcie = dev_get_drvdata(dev);
922 for (i = 0; i < pcie->nports; i++) {
923 struct mvebu_pcie_port *port = pcie->ports + i;
924 mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF);
925 mvebu_pcie_setup_hw(port);
926 }
927
928 return 0;
929 }
930
931 static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie,
932 struct mvebu_pcie_port *port, struct device_node *child)
933 {
934 struct device *dev = &pcie->pdev->dev;
935 enum of_gpio_flags flags;
936 int ret;
937
938 port->pcie = pcie;
939
940 if (of_property_read_u32(child, "marvell,pcie-port", &port->port)) {
941 dev_warn(dev, "ignoring %s, missing pcie-port property\n",
942 of_node_full_name(child));
943 goto skip;
944 }
945
946 if (of_property_read_u32(child, "marvell,pcie-lane", &port->lane))
947 port->lane = 0;
948
949 port->name = kasprintf(GFP_KERNEL, "pcie%d.%d", port->port, port->lane);
950
951 port->devfn = of_pci_get_devfn(child);
952 if (port->devfn < 0)
953 goto skip;
954
955 ret = mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_MEM,
956 &port->mem_target, &port->mem_attr);
957 if (ret < 0) {
958 dev_err(dev, "%s: cannot get tgt/attr for mem window\n",
959 port->name);
960 goto skip;
961 }
962
963 if (resource_size(&pcie->io) != 0)
964 mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_IO,
965 &port->io_target, &port->io_attr);
966 else {
967 port->io_target = -1;
968 port->io_attr = -1;
969 }
970
971 port->reset_gpio = of_get_named_gpio_flags(child, "reset-gpios", 0,
972 &flags);
973 if (gpio_is_valid(port->reset_gpio)) {
974 port->reset_active_low = flags & OF_GPIO_ACTIVE_LOW;
975 port->reset_name = kasprintf(GFP_KERNEL, "%s-reset",
976 port->name);
977
978 ret = devm_gpio_request_one(dev, port->reset_gpio,
979 GPIOF_DIR_OUT, port->reset_name);
980 if (ret) {
981 if (ret == -EPROBE_DEFER)
982 goto err;
983 goto skip;
984 }
985 }
986
987 port->clk = of_clk_get_by_name(child, NULL);
988 if (IS_ERR(port->clk)) {
989 dev_err(dev, "%s: cannot get clock\n", port->name);
990 goto skip;
991 }
992
993 return 1;
994
995 skip:
996 ret = 0;
997 err:
998 return ret;
999 }
1000
1001 static int mvebu_pcie_probe(struct platform_device *pdev)
1002 {
1003 struct mvebu_pcie *pcie;
1004 struct device_node *np = pdev->dev.of_node;
1005 struct device_node *child;
1006 int num, i, ret;
1007
1008 pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
1009 GFP_KERNEL);
1010 if (!pcie)
1011 return -ENOMEM;
1012
1013 pcie->pdev = pdev;
1014 platform_set_drvdata(pdev, pcie);
1015
1016 /* Get the PCIe memory and I/O aperture */
1017 mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
1018 if (resource_size(&pcie->mem) == 0) {
1019 dev_err(&pdev->dev, "invalid memory aperture size\n");
1020 return -EINVAL;
1021 }
1022
1023 mvebu_mbus_get_pcie_io_aperture(&pcie->io);
1024
1025 if (resource_size(&pcie->io) != 0) {
1026 pcie->realio.flags = pcie->io.flags;
1027 pcie->realio.start = PCIBIOS_MIN_IO;
1028 pcie->realio.end = min_t(resource_size_t,
1029 IO_SPACE_LIMIT,
1030 resource_size(&pcie->io));
1031 } else
1032 pcie->realio = pcie->io;
1033
1034 /* Get the bus range */
1035 ret = of_pci_parse_bus_range(np, &pcie->busn);
1036 if (ret) {
1037 dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
1038 ret);
1039 return ret;
1040 }
1041
1042 num = of_get_available_child_count(pdev->dev.of_node);
1043
1044 pcie->ports = devm_kzalloc(&pdev->dev, num *
1045 sizeof(struct mvebu_pcie_port),
1046 GFP_KERNEL);
1047 if (!pcie->ports)
1048 return -ENOMEM;
1049
1050 i = 0;
1051 for_each_available_child_of_node(pdev->dev.of_node, child) {
1052 struct mvebu_pcie_port *port = &pcie->ports[i];
1053
1054 ret = mvebu_pcie_parse_port(pcie, port, child);
1055 if (ret < 0)
1056 return ret;
1057 else if (ret == 0)
1058 continue;
1059
1060 if (gpio_is_valid(port->reset_gpio)) {
1061 u32 reset_udelay = 20000;
1062
1063 of_property_read_u32(child, "reset-delay-us",
1064 &reset_udelay);
1065
1066 gpio_set_value(port->reset_gpio,
1067 (port->reset_active_low) ? 1 : 0);
1068 msleep(reset_udelay/1000);
1069 }
1070
1071 ret = clk_prepare_enable(port->clk);
1072 if (ret)
1073 continue;
1074
1075 port->base = mvebu_pcie_map_registers(pdev, child, port);
1076 if (IS_ERR(port->base)) {
1077 dev_err(&pdev->dev, "%s: cannot map registers\n",
1078 port->name);
1079 port->base = NULL;
1080 clk_disable_unprepare(port->clk);
1081 continue;
1082 }
1083
1084 mvebu_pcie_set_local_dev_nr(port, 1);
1085
1086 port->dn = child;
1087 mvebu_sw_pci_bridge_init(port);
1088 i++;
1089 }
1090
1091 pcie->nports = i;
1092
1093 for (i = 0; i < (IO_SPACE_LIMIT - SZ_64K); i += SZ_64K)
1094 pci_ioremap_io(i, pcie->io.start + i);
1095
1096 mvebu_pcie_msi_enable(pcie);
1097 mvebu_pcie_enable(pcie);
1098
1099 platform_set_drvdata(pdev, pcie);
1100
1101 return 0;
1102 }
1103
1104 static const struct of_device_id mvebu_pcie_of_match_table[] = {
1105 { .compatible = "marvell,armada-xp-pcie", },
1106 { .compatible = "marvell,armada-370-pcie", },
1107 { .compatible = "marvell,dove-pcie", },
1108 { .compatible = "marvell,kirkwood-pcie", },
1109 {},
1110 };
1111 MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
1112
1113 static struct dev_pm_ops mvebu_pcie_pm_ops = {
1114 .suspend_noirq = mvebu_pcie_suspend,
1115 .resume_noirq = mvebu_pcie_resume,
1116 };
1117
1118 static struct platform_driver mvebu_pcie_driver = {
1119 .driver = {
1120 .name = "mvebu-pcie",
1121 .of_match_table = mvebu_pcie_of_match_table,
1122 /* driver unloading/unbinding currently not supported */
1123 .suppress_bind_attrs = true,
1124 .pm = &mvebu_pcie_pm_ops,
1125 },
1126 .probe = mvebu_pcie_probe,
1127 };
1128 module_platform_driver(mvebu_pcie_driver);
1129
1130 MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
1131 MODULE_DESCRIPTION("Marvell EBU PCIe driver");
1132 MODULE_LICENSE("GPL v2");
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