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KVM: Fix mov cr0 #GP at wrong instruction
[linux-2.6/btrfs-unstable.git] / arch / x86 / kvm / vmx.c
blob1baf4b2d98ee77269253fc75af54680de0a0b73f
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affilates.
9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
19 #include "irq.h"
20 #include "mmu.h"
21
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
33 #include "x86.h"
34
35 #include <asm/io.h>
36 #include <asm/desc.h>
37 #include <asm/vmx.h>
38 #include <asm/virtext.h>
39 #include <asm/mce.h>
40 #include <asm/i387.h>
41 #include <asm/xcr.h>
42
43 #include "trace.h"
44
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46
47 MODULE_AUTHOR("Qumranet");
48 MODULE_LICENSE("GPL");
49
50 static int __read_mostly bypass_guest_pf = 1;
51 module_param(bypass_guest_pf, bool, S_IRUGO);
52
53 static int __read_mostly enable_vpid = 1;
54 module_param_named(vpid, enable_vpid, bool, 0444);
55
56 static int __read_mostly flexpriority_enabled = 1;
57 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
58
59 static int __read_mostly enable_ept = 1;
60 module_param_named(ept, enable_ept, bool, S_IRUGO);
61
62 static int __read_mostly enable_unrestricted_guest = 1;
63 module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
65
66 static int __read_mostly emulate_invalid_guest_state = 0;
67 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
68
69 static int __read_mostly vmm_exclusive = 1;
70 module_param(vmm_exclusive, bool, S_IRUGO);
71
72 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
73 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
74 #define KVM_GUEST_CR0_MASK \
75 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
76 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
77 (X86_CR0_WP | X86_CR0_NE)
78 #define KVM_VM_CR0_ALWAYS_ON \
79 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
80 #define KVM_CR4_GUEST_OWNED_BITS \
81 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
82 | X86_CR4_OSXMMEXCPT)
83
84 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
85 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
86
87 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
88
89 /*
90 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
91 * ple_gap: upper bound on the amount of time between two successive
92 * executions of PAUSE in a loop. Also indicate if ple enabled.
93 * According to test, this time is usually small than 41 cycles.
94 * ple_window: upper bound on the amount of time a guest is allowed to execute
95 * in a PAUSE loop. Tests indicate that most spinlocks are held for
96 * less than 2^12 cycles
97 * Time is measured based on a counter that runs at the same rate as the TSC,
98 * refer SDM volume 3b section 21.6.13 & 22.1.3.
99 */
100 #define KVM_VMX_DEFAULT_PLE_GAP 41
101 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
102 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
103 module_param(ple_gap, int, S_IRUGO);
104
105 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
106 module_param(ple_window, int, S_IRUGO);
107
108 #define NR_AUTOLOAD_MSRS 1
109
110 struct vmcs {
111 u32 revision_id;
112 u32 abort;
113 char data[0];
114 };
115
116 struct shared_msr_entry {
117 unsigned index;
118 u64 data;
119 u64 mask;
120 };
121
122 struct vcpu_vmx {
123 struct kvm_vcpu vcpu;
124 struct list_head local_vcpus_link;
125 unsigned long host_rsp;
126 int launched;
127 u8 fail;
128 u32 idt_vectoring_info;
129 struct shared_msr_entry *guest_msrs;
130 int nmsrs;
131 int save_nmsrs;
132 #ifdef CONFIG_X86_64
133 u64 msr_host_kernel_gs_base;
134 u64 msr_guest_kernel_gs_base;
135 #endif
136 struct vmcs *vmcs;
137 struct msr_autoload {
138 unsigned nr;
139 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
140 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
141 } msr_autoload;
142 struct {
143 int loaded;
144 u16 fs_sel, gs_sel, ldt_sel;
145 int gs_ldt_reload_needed;
146 int fs_reload_needed;
147 } host_state;
148 struct {
149 int vm86_active;
150 ulong save_rflags;
151 struct kvm_save_segment {
152 u16 selector;
153 unsigned long base;
154 u32 limit;
155 u32 ar;
156 } tr, es, ds, fs, gs;
157 struct {
158 bool pending;
159 u8 vector;
160 unsigned rip;
161 } irq;
162 } rmode;
163 int vpid;
164 bool emulation_required;
165
166 /* Support for vnmi-less CPUs */
167 int soft_vnmi_blocked;
168 ktime_t entry_time;
169 s64 vnmi_blocked_time;
170 u32 exit_reason;
171
172 bool rdtscp_enabled;
173 };
174
175 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
176 {
177 return container_of(vcpu, struct vcpu_vmx, vcpu);
178 }
179
180 static int init_rmode(struct kvm *kvm);
181 static u64 construct_eptp(unsigned long root_hpa);
182 static void kvm_cpu_vmxon(u64 addr);
183 static void kvm_cpu_vmxoff(void);
184
185 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
186 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
187 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
188
189 static unsigned long *vmx_io_bitmap_a;
190 static unsigned long *vmx_io_bitmap_b;
191 static unsigned long *vmx_msr_bitmap_legacy;
192 static unsigned long *vmx_msr_bitmap_longmode;
193
194 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
195 static DEFINE_SPINLOCK(vmx_vpid_lock);
196
197 static struct vmcs_config {
198 int size;
199 int order;
200 u32 revision_id;
201 u32 pin_based_exec_ctrl;
202 u32 cpu_based_exec_ctrl;
203 u32 cpu_based_2nd_exec_ctrl;
204 u32 vmexit_ctrl;
205 u32 vmentry_ctrl;
206 } vmcs_config;
207
208 static struct vmx_capability {
209 u32 ept;
210 u32 vpid;
211 } vmx_capability;
212
213 #define VMX_SEGMENT_FIELD(seg) \
214 [VCPU_SREG_##seg] = { \
215 .selector = GUEST_##seg##_SELECTOR, \
216 .base = GUEST_##seg##_BASE, \
217 .limit = GUEST_##seg##_LIMIT, \
218 .ar_bytes = GUEST_##seg##_AR_BYTES, \
219 }
220
221 static struct kvm_vmx_segment_field {
222 unsigned selector;
223 unsigned base;
224 unsigned limit;
225 unsigned ar_bytes;
226 } kvm_vmx_segment_fields[] = {
227 VMX_SEGMENT_FIELD(CS),
228 VMX_SEGMENT_FIELD(DS),
229 VMX_SEGMENT_FIELD(ES),
230 VMX_SEGMENT_FIELD(FS),
231 VMX_SEGMENT_FIELD(GS),
232 VMX_SEGMENT_FIELD(SS),
233 VMX_SEGMENT_FIELD(TR),
234 VMX_SEGMENT_FIELD(LDTR),
235 };
236
237 static u64 host_efer;
238
239 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
240
241 /*
242 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
243 * away by decrementing the array size.
244 */
245 static const u32 vmx_msr_index[] = {
246 #ifdef CONFIG_X86_64
247 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
248 #endif
249 MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
250 };
251 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
252
253 static inline bool is_page_fault(u32 intr_info)
254 {
255 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
256 INTR_INFO_VALID_MASK)) ==
257 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
258 }
259
260 static inline bool is_no_device(u32 intr_info)
261 {
262 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
263 INTR_INFO_VALID_MASK)) ==
264 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
265 }
266
267 static inline bool is_invalid_opcode(u32 intr_info)
268 {
269 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
270 INTR_INFO_VALID_MASK)) ==
271 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
272 }
273
274 static inline bool is_external_interrupt(u32 intr_info)
275 {
276 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
277 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
278 }
279
280 static inline bool is_machine_check(u32 intr_info)
281 {
282 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
283 INTR_INFO_VALID_MASK)) ==
284 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
285 }
286
287 static inline bool cpu_has_vmx_msr_bitmap(void)
288 {
289 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
290 }
291
292 static inline bool cpu_has_vmx_tpr_shadow(void)
293 {
294 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
295 }
296
297 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
298 {
299 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
300 }
301
302 static inline bool cpu_has_secondary_exec_ctrls(void)
303 {
304 return vmcs_config.cpu_based_exec_ctrl &
305 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
306 }
307
308 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
309 {
310 return vmcs_config.cpu_based_2nd_exec_ctrl &
311 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
312 }
313
314 static inline bool cpu_has_vmx_flexpriority(void)
315 {
316 return cpu_has_vmx_tpr_shadow() &&
317 cpu_has_vmx_virtualize_apic_accesses();
318 }
319
320 static inline bool cpu_has_vmx_ept_execute_only(void)
321 {
322 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
323 }
324
325 static inline bool cpu_has_vmx_eptp_uncacheable(void)
326 {
327 return vmx_capability.ept & VMX_EPTP_UC_BIT;
328 }
329
330 static inline bool cpu_has_vmx_eptp_writeback(void)
331 {
332 return vmx_capability.ept & VMX_EPTP_WB_BIT;
333 }
334
335 static inline bool cpu_has_vmx_ept_2m_page(void)
336 {
337 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
338 }
339
340 static inline bool cpu_has_vmx_ept_1g_page(void)
341 {
342 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
343 }
344
345 static inline bool cpu_has_vmx_ept_4levels(void)
346 {
347 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
348 }
349
350 static inline bool cpu_has_vmx_invept_individual_addr(void)
351 {
352 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
353 }
354
355 static inline bool cpu_has_vmx_invept_context(void)
356 {
357 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
358 }
359
360 static inline bool cpu_has_vmx_invept_global(void)
361 {
362 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
363 }
364
365 static inline bool cpu_has_vmx_invvpid_single(void)
366 {
367 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
368 }
369
370 static inline bool cpu_has_vmx_invvpid_global(void)
371 {
372 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
373 }
374
375 static inline bool cpu_has_vmx_ept(void)
376 {
377 return vmcs_config.cpu_based_2nd_exec_ctrl &
378 SECONDARY_EXEC_ENABLE_EPT;
379 }
380
381 static inline bool cpu_has_vmx_unrestricted_guest(void)
382 {
383 return vmcs_config.cpu_based_2nd_exec_ctrl &
384 SECONDARY_EXEC_UNRESTRICTED_GUEST;
385 }
386
387 static inline bool cpu_has_vmx_ple(void)
388 {
389 return vmcs_config.cpu_based_2nd_exec_ctrl &
390 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
391 }
392
393 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
394 {
395 return flexpriority_enabled && irqchip_in_kernel(kvm);
396 }
397
398 static inline bool cpu_has_vmx_vpid(void)
399 {
400 return vmcs_config.cpu_based_2nd_exec_ctrl &
401 SECONDARY_EXEC_ENABLE_VPID;
402 }
403
404 static inline bool cpu_has_vmx_rdtscp(void)
405 {
406 return vmcs_config.cpu_based_2nd_exec_ctrl &
407 SECONDARY_EXEC_RDTSCP;
408 }
409
410 static inline bool cpu_has_virtual_nmis(void)
411 {
412 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
413 }
414
415 static inline bool report_flexpriority(void)
416 {
417 return flexpriority_enabled;
418 }
419
420 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
421 {
422 int i;
423
424 for (i = 0; i < vmx->nmsrs; ++i)
425 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
426 return i;
427 return -1;
428 }
429
430 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
431 {
432 struct {
433 u64 vpid : 16;
434 u64 rsvd : 48;
435 u64 gva;
436 } operand = { vpid, 0, gva };
437
438 asm volatile (__ex(ASM_VMX_INVVPID)
439 /* CF==1 or ZF==1 --> rc = -1 */
440 "; ja 1f ; ud2 ; 1:"
441 : : "a"(&operand), "c"(ext) : "cc", "memory");
442 }
443
444 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
445 {
446 struct {
447 u64 eptp, gpa;
448 } operand = {eptp, gpa};
449
450 asm volatile (__ex(ASM_VMX_INVEPT)
451 /* CF==1 or ZF==1 --> rc = -1 */
452 "; ja 1f ; ud2 ; 1:\n"
453 : : "a" (&operand), "c" (ext) : "cc", "memory");
454 }
455
456 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
457 {
458 int i;
459
460 i = __find_msr_index(vmx, msr);
461 if (i >= 0)
462 return &vmx->guest_msrs[i];
463 return NULL;
464 }
465
466 static void vmcs_clear(struct vmcs *vmcs)
467 {
468 u64 phys_addr = __pa(vmcs);
469 u8 error;
470
471 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
472 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
473 : "cc", "memory");
474 if (error)
475 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
476 vmcs, phys_addr);
477 }
478
479 static void vmcs_load(struct vmcs *vmcs)
480 {
481 u64 phys_addr = __pa(vmcs);
482 u8 error;
483
484 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
485 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
486 : "cc", "memory");
487 if (error)
488 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
489 vmcs, phys_addr);
490 }
491
492 static void __vcpu_clear(void *arg)
493 {
494 struct vcpu_vmx *vmx = arg;
495 int cpu = raw_smp_processor_id();
496
497 if (vmx->vcpu.cpu == cpu)
498 vmcs_clear(vmx->vmcs);
499 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
500 per_cpu(current_vmcs, cpu) = NULL;
501 rdtscll(vmx->vcpu.arch.host_tsc);
502 list_del(&vmx->local_vcpus_link);
503 vmx->vcpu.cpu = -1;
504 vmx->launched = 0;
505 }
506
507 static void vcpu_clear(struct vcpu_vmx *vmx)
508 {
509 if (vmx->vcpu.cpu == -1)
510 return;
511 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
512 }
513
514 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
515 {
516 if (vmx->vpid == 0)
517 return;
518
519 if (cpu_has_vmx_invvpid_single())
520 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
521 }
522
523 static inline void vpid_sync_vcpu_global(void)
524 {
525 if (cpu_has_vmx_invvpid_global())
526 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
527 }
528
529 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
530 {
531 if (cpu_has_vmx_invvpid_single())
532 vpid_sync_vcpu_single(vmx);
533 else
534 vpid_sync_vcpu_global();
535 }
536
537 static inline void ept_sync_global(void)
538 {
539 if (cpu_has_vmx_invept_global())
540 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
541 }
542
543 static inline void ept_sync_context(u64 eptp)
544 {
545 if (enable_ept) {
546 if (cpu_has_vmx_invept_context())
547 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
548 else
549 ept_sync_global();
550 }
551 }
552
553 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
554 {
555 if (enable_ept) {
556 if (cpu_has_vmx_invept_individual_addr())
557 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
558 eptp, gpa);
559 else
560 ept_sync_context(eptp);
561 }
562 }
563
564 static unsigned long vmcs_readl(unsigned long field)
565 {
566 unsigned long value;
567
568 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
569 : "=a"(value) : "d"(field) : "cc");
570 return value;
571 }
572
573 static u16 vmcs_read16(unsigned long field)
574 {
575 return vmcs_readl(field);
576 }
577
578 static u32 vmcs_read32(unsigned long field)
579 {
580 return vmcs_readl(field);
581 }
582
583 static u64 vmcs_read64(unsigned long field)
584 {
585 #ifdef CONFIG_X86_64
586 return vmcs_readl(field);
587 #else
588 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
589 #endif
590 }
591
592 static noinline void vmwrite_error(unsigned long field, unsigned long value)
593 {
594 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
595 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
596 dump_stack();
597 }
598
599 static void vmcs_writel(unsigned long field, unsigned long value)
600 {
601 u8 error;
602
603 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
604 : "=q"(error) : "a"(value), "d"(field) : "cc");
605 if (unlikely(error))
606 vmwrite_error(field, value);
607 }
608
609 static void vmcs_write16(unsigned long field, u16 value)
610 {
611 vmcs_writel(field, value);
612 }
613
614 static void vmcs_write32(unsigned long field, u32 value)
615 {
616 vmcs_writel(field, value);
617 }
618
619 static void vmcs_write64(unsigned long field, u64 value)
620 {
621 vmcs_writel(field, value);
622 #ifndef CONFIG_X86_64
623 asm volatile ("");
624 vmcs_writel(field+1, value >> 32);
625 #endif
626 }
627
628 static void vmcs_clear_bits(unsigned long field, u32 mask)
629 {
630 vmcs_writel(field, vmcs_readl(field) & ~mask);
631 }
632
633 static void vmcs_set_bits(unsigned long field, u32 mask)
634 {
635 vmcs_writel(field, vmcs_readl(field) | mask);
636 }
637
638 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
639 {
640 u32 eb;
641
642 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
643 (1u << NM_VECTOR) | (1u << DB_VECTOR);
644 if ((vcpu->guest_debug &
645 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
646 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
647 eb |= 1u << BP_VECTOR;
648 if (to_vmx(vcpu)->rmode.vm86_active)
649 eb = ~0;
650 if (enable_ept)
651 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
652 if (vcpu->fpu_active)
653 eb &= ~(1u << NM_VECTOR);
654 vmcs_write32(EXCEPTION_BITMAP, eb);
655 }
656
657 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
658 {
659 unsigned i;
660 struct msr_autoload *m = &vmx->msr_autoload;
661
662 for (i = 0; i < m->nr; ++i)
663 if (m->guest[i].index == msr)
664 break;
665
666 if (i == m->nr)
667 return;
668 --m->nr;
669 m->guest[i] = m->guest[m->nr];
670 m->host[i] = m->host[m->nr];
671 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
672 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
673 }
674
675 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
676 u64 guest_val, u64 host_val)
677 {
678 unsigned i;
679 struct msr_autoload *m = &vmx->msr_autoload;
680
681 for (i = 0; i < m->nr; ++i)
682 if (m->guest[i].index == msr)
683 break;
684
685 if (i == m->nr) {
686 ++m->nr;
687 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
688 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
689 }
690
691 m->guest[i].index = msr;
692 m->guest[i].value = guest_val;
693 m->host[i].index = msr;
694 m->host[i].value = host_val;
695 }
696
697 static void reload_tss(void)
698 {
699 /*
700 * VT restores TR but not its size. Useless.
701 */
702 struct desc_ptr gdt;
703 struct desc_struct *descs;
704
705 native_store_gdt(&gdt);
706 descs = (void *)gdt.address;
707 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
708 load_TR_desc();
709 }
710
711 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
712 {
713 u64 guest_efer;
714 u64 ignore_bits;
715
716 guest_efer = vmx->vcpu.arch.efer;
717
718 /*
719 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
720 * outside long mode
721 */
722 ignore_bits = EFER_NX | EFER_SCE;
723 #ifdef CONFIG_X86_64
724 ignore_bits |= EFER_LMA | EFER_LME;
725 /* SCE is meaningful only in long mode on Intel */
726 if (guest_efer & EFER_LMA)
727 ignore_bits &= ~(u64)EFER_SCE;
728 #endif
729 guest_efer &= ~ignore_bits;
730 guest_efer |= host_efer & ignore_bits;
731 vmx->guest_msrs[efer_offset].data = guest_efer;
732 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
733
734 clear_atomic_switch_msr(vmx, MSR_EFER);
735 /* On ept, can't emulate nx, and must switch nx atomically */
736 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
737 guest_efer = vmx->vcpu.arch.efer;
738 if (!(guest_efer & EFER_LMA))
739 guest_efer &= ~EFER_LME;
740 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
741 return false;
742 }
743
744 return true;
745 }
746
747 static unsigned long segment_base(u16 selector)
748 {
749 struct desc_ptr gdt;
750 struct desc_struct *d;
751 unsigned long table_base;
752 unsigned long v;
753
754 if (!(selector & ~3))
755 return 0;
756
757 native_store_gdt(&gdt);
758 table_base = gdt.address;
759
760 if (selector & 4) { /* from ldt */
761 u16 ldt_selector = kvm_read_ldt();
762
763 if (!(ldt_selector & ~3))
764 return 0;
765
766 table_base = segment_base(ldt_selector);
767 }
768 d = (struct desc_struct *)(table_base + (selector & ~7));
769 v = get_desc_base(d);
770 #ifdef CONFIG_X86_64
771 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
772 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
773 #endif
774 return v;
775 }
776
777 static inline unsigned long kvm_read_tr_base(void)
778 {
779 u16 tr;
780 asm("str %0" : "=g"(tr));
781 return segment_base(tr);
782 }
783
784 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
785 {
786 struct vcpu_vmx *vmx = to_vmx(vcpu);
787 int i;
788
789 if (vmx->host_state.loaded)
790 return;
791
792 vmx->host_state.loaded = 1;
793 /*
794 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
795 * allow segment selectors with cpl > 0 or ti == 1.
796 */
797 vmx->host_state.ldt_sel = kvm_read_ldt();
798 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
799 vmx->host_state.fs_sel = kvm_read_fs();
800 if (!(vmx->host_state.fs_sel & 7)) {
801 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
802 vmx->host_state.fs_reload_needed = 0;
803 } else {
804 vmcs_write16(HOST_FS_SELECTOR, 0);
805 vmx->host_state.fs_reload_needed = 1;
806 }
807 vmx->host_state.gs_sel = kvm_read_gs();
808 if (!(vmx->host_state.gs_sel & 7))
809 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
810 else {
811 vmcs_write16(HOST_GS_SELECTOR, 0);
812 vmx->host_state.gs_ldt_reload_needed = 1;
813 }
814
815 #ifdef CONFIG_X86_64
816 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
817 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
818 #else
819 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
820 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
821 #endif
822
823 #ifdef CONFIG_X86_64
824 if (is_long_mode(&vmx->vcpu)) {
825 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
826 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
827 }
828 #endif
829 for (i = 0; i < vmx->save_nmsrs; ++i)
830 kvm_set_shared_msr(vmx->guest_msrs[i].index,
831 vmx->guest_msrs[i].data,
832 vmx->guest_msrs[i].mask);
833 }
834
835 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
836 {
837 unsigned long flags;
838
839 if (!vmx->host_state.loaded)
840 return;
841
842 ++vmx->vcpu.stat.host_state_reload;
843 vmx->host_state.loaded = 0;
844 if (vmx->host_state.fs_reload_needed)
845 kvm_load_fs(vmx->host_state.fs_sel);
846 if (vmx->host_state.gs_ldt_reload_needed) {
847 kvm_load_ldt(vmx->host_state.ldt_sel);
848 /*
849 * If we have to reload gs, we must take care to
850 * preserve our gs base.
851 */
852 local_irq_save(flags);
853 kvm_load_gs(vmx->host_state.gs_sel);
854 #ifdef CONFIG_X86_64
855 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
856 #endif
857 local_irq_restore(flags);
858 }
859 reload_tss();
860 #ifdef CONFIG_X86_64
861 if (is_long_mode(&vmx->vcpu)) {
862 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
863 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
864 }
865 #endif
866 if (current_thread_info()->status & TS_USEDFPU)
867 clts();
868 }
869
870 static void vmx_load_host_state(struct vcpu_vmx *vmx)
871 {
872 preempt_disable();
873 __vmx_load_host_state(vmx);
874 preempt_enable();
875 }
876
877 /*
878 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
879 * vcpu mutex is already taken.
880 */
881 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
882 {
883 struct vcpu_vmx *vmx = to_vmx(vcpu);
884 u64 tsc_this, delta, new_offset;
885 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
886
887 if (!vmm_exclusive)
888 kvm_cpu_vmxon(phys_addr);
889 else if (vcpu->cpu != cpu)
890 vcpu_clear(vmx);
891
892 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
893 per_cpu(current_vmcs, cpu) = vmx->vmcs;
894 vmcs_load(vmx->vmcs);
895 }
896
897 if (vcpu->cpu != cpu) {
898 struct desc_ptr dt;
899 unsigned long sysenter_esp;
900
901 kvm_migrate_timers(vcpu);
902 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
903 local_irq_disable();
904 list_add(&vmx->local_vcpus_link,
905 &per_cpu(vcpus_on_cpu, cpu));
906 local_irq_enable();
907
908 vcpu->cpu = cpu;
909 /*
910 * Linux uses per-cpu TSS and GDT, so set these when switching
911 * processors.
912 */
913 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
914 native_store_gdt(&dt);
915 vmcs_writel(HOST_GDTR_BASE, dt.address); /* 22.2.4 */
916
917 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
918 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
919
920 /*
921 * Make sure the time stamp counter is monotonous.
922 */
923 rdtscll(tsc_this);
924 if (tsc_this < vcpu->arch.host_tsc) {
925 delta = vcpu->arch.host_tsc - tsc_this;
926 new_offset = vmcs_read64(TSC_OFFSET) + delta;
927 vmcs_write64(TSC_OFFSET, new_offset);
928 }
929 }
930 }
931
932 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
933 {
934 __vmx_load_host_state(to_vmx(vcpu));
935 if (!vmm_exclusive) {
936 __vcpu_clear(to_vmx(vcpu));
937 kvm_cpu_vmxoff();
938 }
939 }
940
941 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
942 {
943 ulong cr0;
944
945 if (vcpu->fpu_active)
946 return;
947 vcpu->fpu_active = 1;
948 cr0 = vmcs_readl(GUEST_CR0);
949 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
950 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
951 vmcs_writel(GUEST_CR0, cr0);
952 update_exception_bitmap(vcpu);
953 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
954 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
955 }
956
957 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
958
959 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
960 {
961 vmx_decache_cr0_guest_bits(vcpu);
962 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
963 update_exception_bitmap(vcpu);
964 vcpu->arch.cr0_guest_owned_bits = 0;
965 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
966 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
967 }
968
969 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
970 {
971 unsigned long rflags, save_rflags;
972
973 rflags = vmcs_readl(GUEST_RFLAGS);
974 if (to_vmx(vcpu)->rmode.vm86_active) {
975 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
976 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
977 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
978 }
979 return rflags;
980 }
981
982 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
983 {
984 if (to_vmx(vcpu)->rmode.vm86_active) {
985 to_vmx(vcpu)->rmode.save_rflags = rflags;
986 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
987 }
988 vmcs_writel(GUEST_RFLAGS, rflags);
989 }
990
991 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
992 {
993 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
994 int ret = 0;
995
996 if (interruptibility & GUEST_INTR_STATE_STI)
997 ret |= KVM_X86_SHADOW_INT_STI;
998 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
999 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1000
1001 return ret & mask;
1002 }
1003
1004 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1005 {
1006 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1007 u32 interruptibility = interruptibility_old;
1008
1009 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1010
1011 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1012 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1013 else if (mask & KVM_X86_SHADOW_INT_STI)
1014 interruptibility |= GUEST_INTR_STATE_STI;
1015
1016 if ((interruptibility != interruptibility_old))
1017 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1018 }
1019
1020 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1021 {
1022 unsigned long rip;
1023
1024 rip = kvm_rip_read(vcpu);
1025 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1026 kvm_rip_write(vcpu, rip);
1027
1028 /* skipping an emulated instruction also counts */
1029 vmx_set_interrupt_shadow(vcpu, 0);
1030 }
1031
1032 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1033 bool has_error_code, u32 error_code,
1034 bool reinject)
1035 {
1036 struct vcpu_vmx *vmx = to_vmx(vcpu);
1037 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1038
1039 if (has_error_code) {
1040 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1041 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1042 }
1043
1044 if (vmx->rmode.vm86_active) {
1045 vmx->rmode.irq.pending = true;
1046 vmx->rmode.irq.vector = nr;
1047 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
1048 if (kvm_exception_is_soft(nr))
1049 vmx->rmode.irq.rip +=
1050 vmx->vcpu.arch.event_exit_inst_len;
1051 intr_info |= INTR_TYPE_SOFT_INTR;
1052 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1053 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1054 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
1055 return;
1056 }
1057
1058 if (kvm_exception_is_soft(nr)) {
1059 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1060 vmx->vcpu.arch.event_exit_inst_len);
1061 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1062 } else
1063 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1064
1065 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1066 }
1067
1068 static bool vmx_rdtscp_supported(void)
1069 {
1070 return cpu_has_vmx_rdtscp();
1071 }
1072
1073 /*
1074 * Swap MSR entry in host/guest MSR entry array.
1075 */
1076 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1077 {
1078 struct shared_msr_entry tmp;
1079
1080 tmp = vmx->guest_msrs[to];
1081 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1082 vmx->guest_msrs[from] = tmp;
1083 }
1084
1085 /*
1086 * Set up the vmcs to automatically save and restore system
1087 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1088 * mode, as fiddling with msrs is very expensive.
1089 */
1090 static void setup_msrs(struct vcpu_vmx *vmx)
1091 {
1092 int save_nmsrs, index;
1093 unsigned long *msr_bitmap;
1094
1095 vmx_load_host_state(vmx);
1096 save_nmsrs = 0;
1097 #ifdef CONFIG_X86_64
1098 if (is_long_mode(&vmx->vcpu)) {
1099 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1100 if (index >= 0)
1101 move_msr_up(vmx, index, save_nmsrs++);
1102 index = __find_msr_index(vmx, MSR_LSTAR);
1103 if (index >= 0)
1104 move_msr_up(vmx, index, save_nmsrs++);
1105 index = __find_msr_index(vmx, MSR_CSTAR);
1106 if (index >= 0)
1107 move_msr_up(vmx, index, save_nmsrs++);
1108 index = __find_msr_index(vmx, MSR_TSC_AUX);
1109 if (index >= 0 && vmx->rdtscp_enabled)
1110 move_msr_up(vmx, index, save_nmsrs++);
1111 /*
1112 * MSR_K6_STAR is only needed on long mode guests, and only
1113 * if efer.sce is enabled.
1114 */
1115 index = __find_msr_index(vmx, MSR_K6_STAR);
1116 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1117 move_msr_up(vmx, index, save_nmsrs++);
1118 }
1119 #endif
1120 index = __find_msr_index(vmx, MSR_EFER);
1121 if (index >= 0 && update_transition_efer(vmx, index))
1122 move_msr_up(vmx, index, save_nmsrs++);
1123
1124 vmx->save_nmsrs = save_nmsrs;
1125
1126 if (cpu_has_vmx_msr_bitmap()) {
1127 if (is_long_mode(&vmx->vcpu))
1128 msr_bitmap = vmx_msr_bitmap_longmode;
1129 else
1130 msr_bitmap = vmx_msr_bitmap_legacy;
1131
1132 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1133 }
1134 }
1135
1136 /*
1137 * reads and returns guest's timestamp counter "register"
1138 * guest_tsc = host_tsc + tsc_offset -- 21.3
1139 */
1140 static u64 guest_read_tsc(void)
1141 {
1142 u64 host_tsc, tsc_offset;
1143
1144 rdtscll(host_tsc);
1145 tsc_offset = vmcs_read64(TSC_OFFSET);
1146 return host_tsc + tsc_offset;
1147 }
1148
1149 /*
1150 * writes 'guest_tsc' into guest's timestamp counter "register"
1151 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
1152 */
1153 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
1154 {
1155 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
1156 }
1157
1158 /*
1159 * Reads an msr value (of 'msr_index') into 'pdata'.
1160 * Returns 0 on success, non-0 otherwise.
1161 * Assumes vcpu_load() was already called.
1162 */
1163 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1164 {
1165 u64 data;
1166 struct shared_msr_entry *msr;
1167
1168 if (!pdata) {
1169 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1170 return -EINVAL;
1171 }
1172
1173 switch (msr_index) {
1174 #ifdef CONFIG_X86_64
1175 case MSR_FS_BASE:
1176 data = vmcs_readl(GUEST_FS_BASE);
1177 break;
1178 case MSR_GS_BASE:
1179 data = vmcs_readl(GUEST_GS_BASE);
1180 break;
1181 case MSR_KERNEL_GS_BASE:
1182 vmx_load_host_state(to_vmx(vcpu));
1183 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1184 break;
1185 #endif
1186 case MSR_EFER:
1187 return kvm_get_msr_common(vcpu, msr_index, pdata);
1188 case MSR_IA32_TSC:
1189 data = guest_read_tsc();
1190 break;
1191 case MSR_IA32_SYSENTER_CS:
1192 data = vmcs_read32(GUEST_SYSENTER_CS);
1193 break;
1194 case MSR_IA32_SYSENTER_EIP:
1195 data = vmcs_readl(GUEST_SYSENTER_EIP);
1196 break;
1197 case MSR_IA32_SYSENTER_ESP:
1198 data = vmcs_readl(GUEST_SYSENTER_ESP);
1199 break;
1200 case MSR_TSC_AUX:
1201 if (!to_vmx(vcpu)->rdtscp_enabled)
1202 return 1;
1203 /* Otherwise falls through */
1204 default:
1205 vmx_load_host_state(to_vmx(vcpu));
1206 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1207 if (msr) {
1208 vmx_load_host_state(to_vmx(vcpu));
1209 data = msr->data;
1210 break;
1211 }
1212 return kvm_get_msr_common(vcpu, msr_index, pdata);
1213 }
1214
1215 *pdata = data;
1216 return 0;
1217 }
1218
1219 /*
1220 * Writes msr value into into the appropriate "register".
1221 * Returns 0 on success, non-0 otherwise.
1222 * Assumes vcpu_load() was already called.
1223 */
1224 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1225 {
1226 struct vcpu_vmx *vmx = to_vmx(vcpu);
1227 struct shared_msr_entry *msr;
1228 u64 host_tsc;
1229 int ret = 0;
1230
1231 switch (msr_index) {
1232 case MSR_EFER:
1233 vmx_load_host_state(vmx);
1234 ret = kvm_set_msr_common(vcpu, msr_index, data);
1235 break;
1236 #ifdef CONFIG_X86_64
1237 case MSR_FS_BASE:
1238 vmcs_writel(GUEST_FS_BASE, data);
1239 break;
1240 case MSR_GS_BASE:
1241 vmcs_writel(GUEST_GS_BASE, data);
1242 break;
1243 case MSR_KERNEL_GS_BASE:
1244 vmx_load_host_state(vmx);
1245 vmx->msr_guest_kernel_gs_base = data;
1246 break;
1247 #endif
1248 case MSR_IA32_SYSENTER_CS:
1249 vmcs_write32(GUEST_SYSENTER_CS, data);
1250 break;
1251 case MSR_IA32_SYSENTER_EIP:
1252 vmcs_writel(GUEST_SYSENTER_EIP, data);
1253 break;
1254 case MSR_IA32_SYSENTER_ESP:
1255 vmcs_writel(GUEST_SYSENTER_ESP, data);
1256 break;
1257 case MSR_IA32_TSC:
1258 rdtscll(host_tsc);
1259 guest_write_tsc(data, host_tsc);
1260 break;
1261 case MSR_IA32_CR_PAT:
1262 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1263 vmcs_write64(GUEST_IA32_PAT, data);
1264 vcpu->arch.pat = data;
1265 break;
1266 }
1267 ret = kvm_set_msr_common(vcpu, msr_index, data);
1268 break;
1269 case MSR_TSC_AUX:
1270 if (!vmx->rdtscp_enabled)
1271 return 1;
1272 /* Check reserved bit, higher 32 bits should be zero */
1273 if ((data >> 32) != 0)
1274 return 1;
1275 /* Otherwise falls through */
1276 default:
1277 msr = find_msr_entry(vmx, msr_index);
1278 if (msr) {
1279 vmx_load_host_state(vmx);
1280 msr->data = data;
1281 break;
1282 }
1283 ret = kvm_set_msr_common(vcpu, msr_index, data);
1284 }
1285
1286 return ret;
1287 }
1288
1289 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1290 {
1291 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1292 switch (reg) {
1293 case VCPU_REGS_RSP:
1294 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1295 break;
1296 case VCPU_REGS_RIP:
1297 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1298 break;
1299 case VCPU_EXREG_PDPTR:
1300 if (enable_ept)
1301 ept_save_pdptrs(vcpu);
1302 break;
1303 default:
1304 break;
1305 }
1306 }
1307
1308 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1309 {
1310 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1311 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1312 else
1313 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1314
1315 update_exception_bitmap(vcpu);
1316 }
1317
1318 static __init int cpu_has_kvm_support(void)
1319 {
1320 return cpu_has_vmx();
1321 }
1322
1323 static __init int vmx_disabled_by_bios(void)
1324 {
1325 u64 msr;
1326
1327 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1328 if (msr & FEATURE_CONTROL_LOCKED) {
1329 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1330 && tboot_enabled())
1331 return 1;
1332 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1333 && !tboot_enabled())
1334 return 1;
1335 }
1336
1337 return 0;
1338 /* locked but not enabled */
1339 }
1340
1341 static void kvm_cpu_vmxon(u64 addr)
1342 {
1343 asm volatile (ASM_VMX_VMXON_RAX
1344 : : "a"(&addr), "m"(addr)
1345 : "memory", "cc");
1346 }
1347
1348 static int hardware_enable(void *garbage)
1349 {
1350 int cpu = raw_smp_processor_id();
1351 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1352 u64 old, test_bits;
1353
1354 if (read_cr4() & X86_CR4_VMXE)
1355 return -EBUSY;
1356
1357 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1358 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1359
1360 test_bits = FEATURE_CONTROL_LOCKED;
1361 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1362 if (tboot_enabled())
1363 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1364
1365 if ((old & test_bits) != test_bits) {
1366 /* enable and lock */
1367 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1368 }
1369 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1370
1371 if (vmm_exclusive) {
1372 kvm_cpu_vmxon(phys_addr);
1373 ept_sync_global();
1374 }
1375
1376 return 0;
1377 }
1378
1379 static void vmclear_local_vcpus(void)
1380 {
1381 int cpu = raw_smp_processor_id();
1382 struct vcpu_vmx *vmx, *n;
1383
1384 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1385 local_vcpus_link)
1386 __vcpu_clear(vmx);
1387 }
1388
1389
1390 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1391 * tricks.
1392 */
1393 static void kvm_cpu_vmxoff(void)
1394 {
1395 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1396 }
1397
1398 static void hardware_disable(void *garbage)
1399 {
1400 if (vmm_exclusive) {
1401 vmclear_local_vcpus();
1402 kvm_cpu_vmxoff();
1403 }
1404 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1405 }
1406
1407 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1408 u32 msr, u32 *result)
1409 {
1410 u32 vmx_msr_low, vmx_msr_high;
1411 u32 ctl = ctl_min | ctl_opt;
1412
1413 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1414
1415 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1416 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1417
1418 /* Ensure minimum (required) set of control bits are supported. */
1419 if (ctl_min & ~ctl)
1420 return -EIO;
1421
1422 *result = ctl;
1423 return 0;
1424 }
1425
1426 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1427 {
1428 u32 vmx_msr_low, vmx_msr_high;
1429 u32 min, opt, min2, opt2;
1430 u32 _pin_based_exec_control = 0;
1431 u32 _cpu_based_exec_control = 0;
1432 u32 _cpu_based_2nd_exec_control = 0;
1433 u32 _vmexit_control = 0;
1434 u32 _vmentry_control = 0;
1435
1436 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1437 opt = PIN_BASED_VIRTUAL_NMIS;
1438 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1439 &_pin_based_exec_control) < 0)
1440 return -EIO;
1441
1442 min = CPU_BASED_HLT_EXITING |
1443 #ifdef CONFIG_X86_64
1444 CPU_BASED_CR8_LOAD_EXITING |
1445 CPU_BASED_CR8_STORE_EXITING |
1446 #endif
1447 CPU_BASED_CR3_LOAD_EXITING |
1448 CPU_BASED_CR3_STORE_EXITING |
1449 CPU_BASED_USE_IO_BITMAPS |
1450 CPU_BASED_MOV_DR_EXITING |
1451 CPU_BASED_USE_TSC_OFFSETING |
1452 CPU_BASED_MWAIT_EXITING |
1453 CPU_BASED_MONITOR_EXITING |
1454 CPU_BASED_INVLPG_EXITING;
1455 opt = CPU_BASED_TPR_SHADOW |
1456 CPU_BASED_USE_MSR_BITMAPS |
1457 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1458 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1459 &_cpu_based_exec_control) < 0)
1460 return -EIO;
1461 #ifdef CONFIG_X86_64
1462 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1463 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1464 ~CPU_BASED_CR8_STORE_EXITING;
1465 #endif
1466 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1467 min2 = 0;
1468 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1469 SECONDARY_EXEC_WBINVD_EXITING |
1470 SECONDARY_EXEC_ENABLE_VPID |
1471 SECONDARY_EXEC_ENABLE_EPT |
1472 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1473 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1474 SECONDARY_EXEC_RDTSCP;
1475 if (adjust_vmx_controls(min2, opt2,
1476 MSR_IA32_VMX_PROCBASED_CTLS2,
1477 &_cpu_based_2nd_exec_control) < 0)
1478 return -EIO;
1479 }
1480 #ifndef CONFIG_X86_64
1481 if (!(_cpu_based_2nd_exec_control &
1482 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1483 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1484 #endif
1485 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1486 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1487 enabled */
1488 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1489 CPU_BASED_CR3_STORE_EXITING |
1490 CPU_BASED_INVLPG_EXITING);
1491 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1492 vmx_capability.ept, vmx_capability.vpid);
1493 }
1494
1495 min = 0;
1496 #ifdef CONFIG_X86_64
1497 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1498 #endif
1499 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1500 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1501 &_vmexit_control) < 0)
1502 return -EIO;
1503
1504 min = 0;
1505 opt = VM_ENTRY_LOAD_IA32_PAT;
1506 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1507 &_vmentry_control) < 0)
1508 return -EIO;
1509
1510 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1511
1512 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1513 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1514 return -EIO;
1515
1516 #ifdef CONFIG_X86_64
1517 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1518 if (vmx_msr_high & (1u<<16))
1519 return -EIO;
1520 #endif
1521
1522 /* Require Write-Back (WB) memory type for VMCS accesses. */
1523 if (((vmx_msr_high >> 18) & 15) != 6)
1524 return -EIO;
1525
1526 vmcs_conf->size = vmx_msr_high & 0x1fff;
1527 vmcs_conf->order = get_order(vmcs_config.size);
1528 vmcs_conf->revision_id = vmx_msr_low;
1529
1530 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1531 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1532 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1533 vmcs_conf->vmexit_ctrl = _vmexit_control;
1534 vmcs_conf->vmentry_ctrl = _vmentry_control;
1535
1536 return 0;
1537 }
1538
1539 static struct vmcs *alloc_vmcs_cpu(int cpu)
1540 {
1541 int node = cpu_to_node(cpu);
1542 struct page *pages;
1543 struct vmcs *vmcs;
1544
1545 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1546 if (!pages)
1547 return NULL;
1548 vmcs = page_address(pages);
1549 memset(vmcs, 0, vmcs_config.size);
1550 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1551 return vmcs;
1552 }
1553
1554 static struct vmcs *alloc_vmcs(void)
1555 {
1556 return alloc_vmcs_cpu(raw_smp_processor_id());
1557 }
1558
1559 static void free_vmcs(struct vmcs *vmcs)
1560 {
1561 free_pages((unsigned long)vmcs, vmcs_config.order);
1562 }
1563
1564 static void free_kvm_area(void)
1565 {
1566 int cpu;
1567
1568 for_each_possible_cpu(cpu) {
1569 free_vmcs(per_cpu(vmxarea, cpu));
1570 per_cpu(vmxarea, cpu) = NULL;
1571 }
1572 }
1573
1574 static __init int alloc_kvm_area(void)
1575 {
1576 int cpu;
1577
1578 for_each_possible_cpu(cpu) {
1579 struct vmcs *vmcs;
1580
1581 vmcs = alloc_vmcs_cpu(cpu);
1582 if (!vmcs) {
1583 free_kvm_area();
1584 return -ENOMEM;
1585 }
1586
1587 per_cpu(vmxarea, cpu) = vmcs;
1588 }
1589 return 0;
1590 }
1591
1592 static __init int hardware_setup(void)
1593 {
1594 if (setup_vmcs_config(&vmcs_config) < 0)
1595 return -EIO;
1596
1597 if (boot_cpu_has(X86_FEATURE_NX))
1598 kvm_enable_efer_bits(EFER_NX);
1599
1600 if (!cpu_has_vmx_vpid())
1601 enable_vpid = 0;
1602
1603 if (!cpu_has_vmx_ept() ||
1604 !cpu_has_vmx_ept_4levels()) {
1605 enable_ept = 0;
1606 enable_unrestricted_guest = 0;
1607 }
1608
1609 if (!cpu_has_vmx_unrestricted_guest())
1610 enable_unrestricted_guest = 0;
1611
1612 if (!cpu_has_vmx_flexpriority())
1613 flexpriority_enabled = 0;
1614
1615 if (!cpu_has_vmx_tpr_shadow())
1616 kvm_x86_ops->update_cr8_intercept = NULL;
1617
1618 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1619 kvm_disable_largepages();
1620
1621 if (!cpu_has_vmx_ple())
1622 ple_gap = 0;
1623
1624 return alloc_kvm_area();
1625 }
1626
1627 static __exit void hardware_unsetup(void)
1628 {
1629 free_kvm_area();
1630 }
1631
1632 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1633 {
1634 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1635
1636 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1637 vmcs_write16(sf->selector, save->selector);
1638 vmcs_writel(sf->base, save->base);
1639 vmcs_write32(sf->limit, save->limit);
1640 vmcs_write32(sf->ar_bytes, save->ar);
1641 } else {
1642 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1643 << AR_DPL_SHIFT;
1644 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1645 }
1646 }
1647
1648 static void enter_pmode(struct kvm_vcpu *vcpu)
1649 {
1650 unsigned long flags;
1651 struct vcpu_vmx *vmx = to_vmx(vcpu);
1652
1653 vmx->emulation_required = 1;
1654 vmx->rmode.vm86_active = 0;
1655
1656 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1657 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1658 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1659
1660 flags = vmcs_readl(GUEST_RFLAGS);
1661 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1662 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1663 vmcs_writel(GUEST_RFLAGS, flags);
1664
1665 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1666 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1667
1668 update_exception_bitmap(vcpu);
1669
1670 if (emulate_invalid_guest_state)
1671 return;
1672
1673 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1674 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1675 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1676 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1677
1678 vmcs_write16(GUEST_SS_SELECTOR, 0);
1679 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1680
1681 vmcs_write16(GUEST_CS_SELECTOR,
1682 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1683 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1684 }
1685
1686 static gva_t rmode_tss_base(struct kvm *kvm)
1687 {
1688 if (!kvm->arch.tss_addr) {
1689 struct kvm_memslots *slots;
1690 gfn_t base_gfn;
1691
1692 slots = kvm_memslots(kvm);
1693 base_gfn = slots->memslots[0].base_gfn +
1694 kvm->memslots->memslots[0].npages - 3;
1695 return base_gfn << PAGE_SHIFT;
1696 }
1697 return kvm->arch.tss_addr;
1698 }
1699
1700 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1701 {
1702 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1703
1704 save->selector = vmcs_read16(sf->selector);
1705 save->base = vmcs_readl(sf->base);
1706 save->limit = vmcs_read32(sf->limit);
1707 save->ar = vmcs_read32(sf->ar_bytes);
1708 vmcs_write16(sf->selector, save->base >> 4);
1709 vmcs_write32(sf->base, save->base & 0xfffff);
1710 vmcs_write32(sf->limit, 0xffff);
1711 vmcs_write32(sf->ar_bytes, 0xf3);
1712 }
1713
1714 static void enter_rmode(struct kvm_vcpu *vcpu)
1715 {
1716 unsigned long flags;
1717 struct vcpu_vmx *vmx = to_vmx(vcpu);
1718
1719 if (enable_unrestricted_guest)
1720 return;
1721
1722 vmx->emulation_required = 1;
1723 vmx->rmode.vm86_active = 1;
1724
1725 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1726 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1727
1728 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1729 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1730
1731 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1732 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1733
1734 flags = vmcs_readl(GUEST_RFLAGS);
1735 vmx->rmode.save_rflags = flags;
1736
1737 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1738
1739 vmcs_writel(GUEST_RFLAGS, flags);
1740 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1741 update_exception_bitmap(vcpu);
1742
1743 if (emulate_invalid_guest_state)
1744 goto continue_rmode;
1745
1746 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1747 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1748 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1749
1750 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1751 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1752 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1753 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1754 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1755
1756 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1757 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1758 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1759 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1760
1761 continue_rmode:
1762 kvm_mmu_reset_context(vcpu);
1763 init_rmode(vcpu->kvm);
1764 }
1765
1766 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1767 {
1768 struct vcpu_vmx *vmx = to_vmx(vcpu);
1769 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1770
1771 if (!msr)
1772 return;
1773
1774 /*
1775 * Force kernel_gs_base reloading before EFER changes, as control
1776 * of this msr depends on is_long_mode().
1777 */
1778 vmx_load_host_state(to_vmx(vcpu));
1779 vcpu->arch.efer = efer;
1780 if (efer & EFER_LMA) {
1781 vmcs_write32(VM_ENTRY_CONTROLS,
1782 vmcs_read32(VM_ENTRY_CONTROLS) |
1783 VM_ENTRY_IA32E_MODE);
1784 msr->data = efer;
1785 } else {
1786 vmcs_write32(VM_ENTRY_CONTROLS,
1787 vmcs_read32(VM_ENTRY_CONTROLS) &
1788 ~VM_ENTRY_IA32E_MODE);
1789
1790 msr->data = efer & ~EFER_LME;
1791 }
1792 setup_msrs(vmx);
1793 }
1794
1795 #ifdef CONFIG_X86_64
1796
1797 static void enter_lmode(struct kvm_vcpu *vcpu)
1798 {
1799 u32 guest_tr_ar;
1800
1801 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1802 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1803 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1804 __func__);
1805 vmcs_write32(GUEST_TR_AR_BYTES,
1806 (guest_tr_ar & ~AR_TYPE_MASK)
1807 | AR_TYPE_BUSY_64_TSS);
1808 }
1809 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
1810 }
1811
1812 static void exit_lmode(struct kvm_vcpu *vcpu)
1813 {
1814 vmcs_write32(VM_ENTRY_CONTROLS,
1815 vmcs_read32(VM_ENTRY_CONTROLS)
1816 & ~VM_ENTRY_IA32E_MODE);
1817 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
1818 }
1819
1820 #endif
1821
1822 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1823 {
1824 vpid_sync_context(to_vmx(vcpu));
1825 if (enable_ept)
1826 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1827 }
1828
1829 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1830 {
1831 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1832
1833 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1834 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1835 }
1836
1837 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1838 {
1839 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1840
1841 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1842 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1843 }
1844
1845 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1846 {
1847 if (!test_bit(VCPU_EXREG_PDPTR,
1848 (unsigned long *)&vcpu->arch.regs_dirty))
1849 return;
1850
1851 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1852 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1853 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1854 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1855 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1856 }
1857 }
1858
1859 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1860 {
1861 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1862 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1863 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1864 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1865 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1866 }
1867
1868 __set_bit(VCPU_EXREG_PDPTR,
1869 (unsigned long *)&vcpu->arch.regs_avail);
1870 __set_bit(VCPU_EXREG_PDPTR,
1871 (unsigned long *)&vcpu->arch.regs_dirty);
1872 }
1873
1874 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1875
1876 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1877 unsigned long cr0,
1878 struct kvm_vcpu *vcpu)
1879 {
1880 if (!(cr0 & X86_CR0_PG)) {
1881 /* From paging/starting to nonpaging */
1882 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1883 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1884 (CPU_BASED_CR3_LOAD_EXITING |
1885 CPU_BASED_CR3_STORE_EXITING));
1886 vcpu->arch.cr0 = cr0;
1887 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1888 } else if (!is_paging(vcpu)) {
1889 /* From nonpaging to paging */
1890 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1891 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1892 ~(CPU_BASED_CR3_LOAD_EXITING |
1893 CPU_BASED_CR3_STORE_EXITING));
1894 vcpu->arch.cr0 = cr0;
1895 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1896 }
1897
1898 if (!(cr0 & X86_CR0_WP))
1899 *hw_cr0 &= ~X86_CR0_WP;
1900 }
1901
1902 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1903 {
1904 struct vcpu_vmx *vmx = to_vmx(vcpu);
1905 unsigned long hw_cr0;
1906
1907 if (enable_unrestricted_guest)
1908 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1909 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1910 else
1911 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1912
1913 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1914 enter_pmode(vcpu);
1915
1916 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1917 enter_rmode(vcpu);
1918
1919 #ifdef CONFIG_X86_64
1920 if (vcpu->arch.efer & EFER_LME) {
1921 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1922 enter_lmode(vcpu);
1923 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1924 exit_lmode(vcpu);
1925 }
1926 #endif
1927
1928 if (enable_ept)
1929 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1930
1931 if (!vcpu->fpu_active)
1932 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1933
1934 vmcs_writel(CR0_READ_SHADOW, cr0);
1935 vmcs_writel(GUEST_CR0, hw_cr0);
1936 vcpu->arch.cr0 = cr0;
1937 }
1938
1939 static u64 construct_eptp(unsigned long root_hpa)
1940 {
1941 u64 eptp;
1942
1943 /* TODO write the value reading from MSR */
1944 eptp = VMX_EPT_DEFAULT_MT |
1945 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1946 eptp |= (root_hpa & PAGE_MASK);
1947
1948 return eptp;
1949 }
1950
1951 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1952 {
1953 unsigned long guest_cr3;
1954 u64 eptp;
1955
1956 guest_cr3 = cr3;
1957 if (enable_ept) {
1958 eptp = construct_eptp(cr3);
1959 vmcs_write64(EPT_POINTER, eptp);
1960 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1961 vcpu->kvm->arch.ept_identity_map_addr;
1962 ept_load_pdptrs(vcpu);
1963 }
1964
1965 vmx_flush_tlb(vcpu);
1966 vmcs_writel(GUEST_CR3, guest_cr3);
1967 }
1968
1969 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1970 {
1971 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1972 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1973
1974 vcpu->arch.cr4 = cr4;
1975 if (enable_ept) {
1976 if (!is_paging(vcpu)) {
1977 hw_cr4 &= ~X86_CR4_PAE;
1978 hw_cr4 |= X86_CR4_PSE;
1979 } else if (!(cr4 & X86_CR4_PAE)) {
1980 hw_cr4 &= ~X86_CR4_PAE;
1981 }
1982 }
1983
1984 vmcs_writel(CR4_READ_SHADOW, cr4);
1985 vmcs_writel(GUEST_CR4, hw_cr4);
1986 }
1987
1988 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1989 {
1990 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1991
1992 return vmcs_readl(sf->base);
1993 }
1994
1995 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1996 struct kvm_segment *var, int seg)
1997 {
1998 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1999 u32 ar;
2000
2001 var->base = vmcs_readl(sf->base);
2002 var->limit = vmcs_read32(sf->limit);
2003 var->selector = vmcs_read16(sf->selector);
2004 ar = vmcs_read32(sf->ar_bytes);
2005 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2006 ar = 0;
2007 var->type = ar & 15;
2008 var->s = (ar >> 4) & 1;
2009 var->dpl = (ar >> 5) & 3;
2010 var->present = (ar >> 7) & 1;
2011 var->avl = (ar >> 12) & 1;
2012 var->l = (ar >> 13) & 1;
2013 var->db = (ar >> 14) & 1;
2014 var->g = (ar >> 15) & 1;
2015 var->unusable = (ar >> 16) & 1;
2016 }
2017
2018 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2019 {
2020 if (!is_protmode(vcpu))
2021 return 0;
2022
2023 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2024 return 3;
2025
2026 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2027 }
2028
2029 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2030 {
2031 u32 ar;
2032
2033 if (var->unusable)
2034 ar = 1 << 16;
2035 else {
2036 ar = var->type & 15;
2037 ar |= (var->s & 1) << 4;
2038 ar |= (var->dpl & 3) << 5;
2039 ar |= (var->present & 1) << 7;
2040 ar |= (var->avl & 1) << 12;
2041 ar |= (var->l & 1) << 13;
2042 ar |= (var->db & 1) << 14;
2043 ar |= (var->g & 1) << 15;
2044 }
2045 if (ar == 0) /* a 0 value means unusable */
2046 ar = AR_UNUSABLE_MASK;
2047
2048 return ar;
2049 }
2050
2051 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2052 struct kvm_segment *var, int seg)
2053 {
2054 struct vcpu_vmx *vmx = to_vmx(vcpu);
2055 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2056 u32 ar;
2057
2058 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2059 vmx->rmode.tr.selector = var->selector;
2060 vmx->rmode.tr.base = var->base;
2061 vmx->rmode.tr.limit = var->limit;
2062 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2063 return;
2064 }
2065 vmcs_writel(sf->base, var->base);
2066 vmcs_write32(sf->limit, var->limit);
2067 vmcs_write16(sf->selector, var->selector);
2068 if (vmx->rmode.vm86_active && var->s) {
2069 /*
2070 * Hack real-mode segments into vm86 compatibility.
2071 */
2072 if (var->base == 0xffff0000 && var->selector == 0xf000)
2073 vmcs_writel(sf->base, 0xf0000);
2074 ar = 0xf3;
2075 } else
2076 ar = vmx_segment_access_rights(var);
2077
2078 /*
2079 * Fix the "Accessed" bit in AR field of segment registers for older
2080 * qemu binaries.
2081 * IA32 arch specifies that at the time of processor reset the
2082 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2083 * is setting it to 0 in the usedland code. This causes invalid guest
2084 * state vmexit when "unrestricted guest" mode is turned on.
2085 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2086 * tree. Newer qemu binaries with that qemu fix would not need this
2087 * kvm hack.
2088 */
2089 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2090 ar |= 0x1; /* Accessed */
2091
2092 vmcs_write32(sf->ar_bytes, ar);
2093 }
2094
2095 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2096 {
2097 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2098
2099 *db = (ar >> 14) & 1;
2100 *l = (ar >> 13) & 1;
2101 }
2102
2103 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2104 {
2105 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2106 dt->address = vmcs_readl(GUEST_IDTR_BASE);
2107 }
2108
2109 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2110 {
2111 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2112 vmcs_writel(GUEST_IDTR_BASE, dt->address);
2113 }
2114
2115 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2116 {
2117 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2118 dt->address = vmcs_readl(GUEST_GDTR_BASE);
2119 }
2120
2121 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2122 {
2123 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2124 vmcs_writel(GUEST_GDTR_BASE, dt->address);
2125 }
2126
2127 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2128 {
2129 struct kvm_segment var;
2130 u32 ar;
2131
2132 vmx_get_segment(vcpu, &var, seg);
2133 ar = vmx_segment_access_rights(&var);
2134
2135 if (var.base != (var.selector << 4))
2136 return false;
2137 if (var.limit != 0xffff)
2138 return false;
2139 if (ar != 0xf3)
2140 return false;
2141
2142 return true;
2143 }
2144
2145 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2146 {
2147 struct kvm_segment cs;
2148 unsigned int cs_rpl;
2149
2150 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2151 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2152
2153 if (cs.unusable)
2154 return false;
2155 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2156 return false;
2157 if (!cs.s)
2158 return false;
2159 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2160 if (cs.dpl > cs_rpl)
2161 return false;
2162 } else {
2163 if (cs.dpl != cs_rpl)
2164 return false;
2165 }
2166 if (!cs.present)
2167 return false;
2168
2169 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2170 return true;
2171 }
2172
2173 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2174 {
2175 struct kvm_segment ss;
2176 unsigned int ss_rpl;
2177
2178 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2179 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2180
2181 if (ss.unusable)
2182 return true;
2183 if (ss.type != 3 && ss.type != 7)
2184 return false;
2185 if (!ss.s)
2186 return false;
2187 if (ss.dpl != ss_rpl) /* DPL != RPL */
2188 return false;
2189 if (!ss.present)
2190 return false;
2191
2192 return true;
2193 }
2194
2195 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2196 {
2197 struct kvm_segment var;
2198 unsigned int rpl;
2199
2200 vmx_get_segment(vcpu, &var, seg);
2201 rpl = var.selector & SELECTOR_RPL_MASK;
2202
2203 if (var.unusable)
2204 return true;
2205 if (!var.s)
2206 return false;
2207 if (!var.present)
2208 return false;
2209 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2210 if (var.dpl < rpl) /* DPL < RPL */
2211 return false;
2212 }
2213
2214 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2215 * rights flags
2216 */
2217 return true;
2218 }
2219
2220 static bool tr_valid(struct kvm_vcpu *vcpu)
2221 {
2222 struct kvm_segment tr;
2223
2224 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2225
2226 if (tr.unusable)
2227 return false;
2228 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2229 return false;
2230 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2231 return false;
2232 if (!tr.present)
2233 return false;
2234
2235 return true;
2236 }
2237
2238 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2239 {
2240 struct kvm_segment ldtr;
2241
2242 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2243
2244 if (ldtr.unusable)
2245 return true;
2246 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2247 return false;
2248 if (ldtr.type != 2)
2249 return false;
2250 if (!ldtr.present)
2251 return false;
2252
2253 return true;
2254 }
2255
2256 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2257 {
2258 struct kvm_segment cs, ss;
2259
2260 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2261 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2262
2263 return ((cs.selector & SELECTOR_RPL_MASK) ==
2264 (ss.selector & SELECTOR_RPL_MASK));
2265 }
2266
2267 /*
2268 * Check if guest state is valid. Returns true if valid, false if
2269 * not.
2270 * We assume that registers are always usable
2271 */
2272 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2273 {
2274 /* real mode guest state checks */
2275 if (!is_protmode(vcpu)) {
2276 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2277 return false;
2278 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2279 return false;
2280 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2281 return false;
2282 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2283 return false;
2284 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2285 return false;
2286 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2287 return false;
2288 } else {
2289 /* protected mode guest state checks */
2290 if (!cs_ss_rpl_check(vcpu))
2291 return false;
2292 if (!code_segment_valid(vcpu))
2293 return false;
2294 if (!stack_segment_valid(vcpu))
2295 return false;
2296 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2297 return false;
2298 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2299 return false;
2300 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2301 return false;
2302 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2303 return false;
2304 if (!tr_valid(vcpu))
2305 return false;
2306 if (!ldtr_valid(vcpu))
2307 return false;
2308 }
2309 /* TODO:
2310 * - Add checks on RIP
2311 * - Add checks on RFLAGS
2312 */
2313
2314 return true;
2315 }
2316
2317 static int init_rmode_tss(struct kvm *kvm)
2318 {
2319 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2320 u16 data = 0;
2321 int ret = 0;
2322 int r;
2323
2324 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2325 if (r < 0)
2326 goto out;
2327 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2328 r = kvm_write_guest_page(kvm, fn++, &data,
2329 TSS_IOPB_BASE_OFFSET, sizeof(u16));
2330 if (r < 0)
2331 goto out;
2332 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2333 if (r < 0)
2334 goto out;
2335 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2336 if (r < 0)
2337 goto out;
2338 data = ~0;
2339 r = kvm_write_guest_page(kvm, fn, &data,
2340 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2341 sizeof(u8));
2342 if (r < 0)
2343 goto out;
2344
2345 ret = 1;
2346 out:
2347 return ret;
2348 }
2349
2350 static int init_rmode_identity_map(struct kvm *kvm)
2351 {
2352 int i, r, ret;
2353 pfn_t identity_map_pfn;
2354 u32 tmp;
2355
2356 if (!enable_ept)
2357 return 1;
2358 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2359 printk(KERN_ERR "EPT: identity-mapping pagetable "
2360 "haven't been allocated!\n");
2361 return 0;
2362 }
2363 if (likely(kvm->arch.ept_identity_pagetable_done))
2364 return 1;
2365 ret = 0;
2366 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2367 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2368 if (r < 0)
2369 goto out;
2370 /* Set up identity-mapping pagetable for EPT in real mode */
2371 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2372 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2373 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2374 r = kvm_write_guest_page(kvm, identity_map_pfn,
2375 &tmp, i * sizeof(tmp), sizeof(tmp));
2376 if (r < 0)
2377 goto out;
2378 }
2379 kvm->arch.ept_identity_pagetable_done = true;
2380 ret = 1;
2381 out:
2382 return ret;
2383 }
2384
2385 static void seg_setup(int seg)
2386 {
2387 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2388 unsigned int ar;
2389
2390 vmcs_write16(sf->selector, 0);
2391 vmcs_writel(sf->base, 0);
2392 vmcs_write32(sf->limit, 0xffff);
2393 if (enable_unrestricted_guest) {
2394 ar = 0x93;
2395 if (seg == VCPU_SREG_CS)
2396 ar |= 0x08; /* code segment */
2397 } else
2398 ar = 0xf3;
2399
2400 vmcs_write32(sf->ar_bytes, ar);
2401 }
2402
2403 static int alloc_apic_access_page(struct kvm *kvm)
2404 {
2405 struct kvm_userspace_memory_region kvm_userspace_mem;
2406 int r = 0;
2407
2408 mutex_lock(&kvm->slots_lock);
2409 if (kvm->arch.apic_access_page)
2410 goto out;
2411 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2412 kvm_userspace_mem.flags = 0;
2413 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2414 kvm_userspace_mem.memory_size = PAGE_SIZE;
2415 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2416 if (r)
2417 goto out;
2418
2419 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2420 out:
2421 mutex_unlock(&kvm->slots_lock);
2422 return r;
2423 }
2424
2425 static int alloc_identity_pagetable(struct kvm *kvm)
2426 {
2427 struct kvm_userspace_memory_region kvm_userspace_mem;
2428 int r = 0;
2429
2430 mutex_lock(&kvm->slots_lock);
2431 if (kvm->arch.ept_identity_pagetable)
2432 goto out;
2433 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2434 kvm_userspace_mem.flags = 0;
2435 kvm_userspace_mem.guest_phys_addr =
2436 kvm->arch.ept_identity_map_addr;
2437 kvm_userspace_mem.memory_size = PAGE_SIZE;
2438 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2439 if (r)
2440 goto out;
2441
2442 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2443 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2444 out:
2445 mutex_unlock(&kvm->slots_lock);
2446 return r;
2447 }
2448
2449 static void allocate_vpid(struct vcpu_vmx *vmx)
2450 {
2451 int vpid;
2452
2453 vmx->vpid = 0;
2454 if (!enable_vpid)
2455 return;
2456 spin_lock(&vmx_vpid_lock);
2457 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2458 if (vpid < VMX_NR_VPIDS) {
2459 vmx->vpid = vpid;
2460 __set_bit(vpid, vmx_vpid_bitmap);
2461 }
2462 spin_unlock(&vmx_vpid_lock);
2463 }
2464
2465 static void free_vpid(struct vcpu_vmx *vmx)
2466 {
2467 if (!enable_vpid)
2468 return;
2469 spin_lock(&vmx_vpid_lock);
2470 if (vmx->vpid != 0)
2471 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2472 spin_unlock(&vmx_vpid_lock);
2473 }
2474
2475 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2476 {
2477 int f = sizeof(unsigned long);
2478
2479 if (!cpu_has_vmx_msr_bitmap())
2480 return;
2481
2482 /*
2483 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2484 * have the write-low and read-high bitmap offsets the wrong way round.
2485 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2486 */
2487 if (msr <= 0x1fff) {
2488 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2489 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2490 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2491 msr &= 0x1fff;
2492 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2493 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2494 }
2495 }
2496
2497 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2498 {
2499 if (!longmode_only)
2500 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2501 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2502 }
2503
2504 /*
2505 * Sets up the vmcs for emulated real mode.
2506 */
2507 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2508 {
2509 u32 host_sysenter_cs, msr_low, msr_high;
2510 u32 junk;
2511 u64 host_pat, tsc_this, tsc_base;
2512 unsigned long a;
2513 struct desc_ptr dt;
2514 int i;
2515 unsigned long kvm_vmx_return;
2516 u32 exec_control;
2517
2518 /* I/O */
2519 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2520 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2521
2522 if (cpu_has_vmx_msr_bitmap())
2523 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2524
2525 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2526
2527 /* Control */
2528 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2529 vmcs_config.pin_based_exec_ctrl);
2530
2531 exec_control = vmcs_config.cpu_based_exec_ctrl;
2532 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2533 exec_control &= ~CPU_BASED_TPR_SHADOW;
2534 #ifdef CONFIG_X86_64
2535 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2536 CPU_BASED_CR8_LOAD_EXITING;
2537 #endif
2538 }
2539 if (!enable_ept)
2540 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2541 CPU_BASED_CR3_LOAD_EXITING |
2542 CPU_BASED_INVLPG_EXITING;
2543 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2544
2545 if (cpu_has_secondary_exec_ctrls()) {
2546 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2547 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2548 exec_control &=
2549 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2550 if (vmx->vpid == 0)
2551 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2552 if (!enable_ept) {
2553 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2554 enable_unrestricted_guest = 0;
2555 }
2556 if (!enable_unrestricted_guest)
2557 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2558 if (!ple_gap)
2559 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2560 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2561 }
2562
2563 if (ple_gap) {
2564 vmcs_write32(PLE_GAP, ple_gap);
2565 vmcs_write32(PLE_WINDOW, ple_window);
2566 }
2567
2568 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2569 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2570 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2571
2572 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
2573 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2574 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2575
2576 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2577 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2578 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2579 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2580 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
2581 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2582 #ifdef CONFIG_X86_64
2583 rdmsrl(MSR_FS_BASE, a);
2584 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2585 rdmsrl(MSR_GS_BASE, a);
2586 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2587 #else
2588 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2589 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2590 #endif
2591
2592 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2593
2594 native_store_idt(&dt);
2595 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
2596
2597 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2598 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2599 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2600 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2601 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2602 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2603 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2604
2605 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2606 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2607 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2608 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2609 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2610 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2611
2612 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2613 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2614 host_pat = msr_low | ((u64) msr_high << 32);
2615 vmcs_write64(HOST_IA32_PAT, host_pat);
2616 }
2617 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2618 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2619 host_pat = msr_low | ((u64) msr_high << 32);
2620 /* Write the default value follow host pat */
2621 vmcs_write64(GUEST_IA32_PAT, host_pat);
2622 /* Keep arch.pat sync with GUEST_IA32_PAT */
2623 vmx->vcpu.arch.pat = host_pat;
2624 }
2625
2626 for (i = 0; i < NR_VMX_MSR; ++i) {
2627 u32 index = vmx_msr_index[i];
2628 u32 data_low, data_high;
2629 int j = vmx->nmsrs;
2630
2631 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2632 continue;
2633 if (wrmsr_safe(index, data_low, data_high) < 0)
2634 continue;
2635 vmx->guest_msrs[j].index = i;
2636 vmx->guest_msrs[j].data = 0;
2637 vmx->guest_msrs[j].mask = -1ull;
2638 ++vmx->nmsrs;
2639 }
2640
2641 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2642
2643 /* 22.2.1, 20.8.1 */
2644 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2645
2646 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2647 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2648 if (enable_ept)
2649 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2650 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2651
2652 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2653 rdtscll(tsc_this);
2654 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2655 tsc_base = tsc_this;
2656
2657 guest_write_tsc(0, tsc_base);
2658
2659 return 0;
2660 }
2661
2662 static int init_rmode(struct kvm *kvm)
2663 {
2664 int idx, ret = 0;
2665
2666 idx = srcu_read_lock(&kvm->srcu);
2667 if (!init_rmode_tss(kvm))
2668 goto exit;
2669 if (!init_rmode_identity_map(kvm))
2670 goto exit;
2671
2672 ret = 1;
2673 exit:
2674 srcu_read_unlock(&kvm->srcu, idx);
2675 return ret;
2676 }
2677
2678 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2679 {
2680 struct vcpu_vmx *vmx = to_vmx(vcpu);
2681 u64 msr;
2682 int ret;
2683
2684 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2685 if (!init_rmode(vmx->vcpu.kvm)) {
2686 ret = -ENOMEM;
2687 goto out;
2688 }
2689
2690 vmx->rmode.vm86_active = 0;
2691
2692 vmx->soft_vnmi_blocked = 0;
2693
2694 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2695 kvm_set_cr8(&vmx->vcpu, 0);
2696 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2697 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2698 msr |= MSR_IA32_APICBASE_BSP;
2699 kvm_set_apic_base(&vmx->vcpu, msr);
2700
2701 ret = fx_init(&vmx->vcpu);
2702 if (ret != 0)
2703 goto out;
2704
2705 seg_setup(VCPU_SREG_CS);
2706 /*
2707 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2708 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2709 */
2710 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2711 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2712 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2713 } else {
2714 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2715 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2716 }
2717
2718 seg_setup(VCPU_SREG_DS);
2719 seg_setup(VCPU_SREG_ES);
2720 seg_setup(VCPU_SREG_FS);
2721 seg_setup(VCPU_SREG_GS);
2722 seg_setup(VCPU_SREG_SS);
2723
2724 vmcs_write16(GUEST_TR_SELECTOR, 0);
2725 vmcs_writel(GUEST_TR_BASE, 0);
2726 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2727 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2728
2729 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2730 vmcs_writel(GUEST_LDTR_BASE, 0);
2731 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2732 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2733
2734 vmcs_write32(GUEST_SYSENTER_CS, 0);
2735 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2736 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2737
2738 vmcs_writel(GUEST_RFLAGS, 0x02);
2739 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2740 kvm_rip_write(vcpu, 0xfff0);
2741 else
2742 kvm_rip_write(vcpu, 0);
2743 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2744
2745 vmcs_writel(GUEST_DR7, 0x400);
2746
2747 vmcs_writel(GUEST_GDTR_BASE, 0);
2748 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2749
2750 vmcs_writel(GUEST_IDTR_BASE, 0);
2751 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2752
2753 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2754 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2755 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2756
2757 /* Special registers */
2758 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2759
2760 setup_msrs(vmx);
2761
2762 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2763
2764 if (cpu_has_vmx_tpr_shadow()) {
2765 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2766 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2767 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2768 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2769 vmcs_write32(TPR_THRESHOLD, 0);
2770 }
2771
2772 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2773 vmcs_write64(APIC_ACCESS_ADDR,
2774 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2775
2776 if (vmx->vpid != 0)
2777 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2778
2779 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2780 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2781 vmx_set_cr4(&vmx->vcpu, 0);
2782 vmx_set_efer(&vmx->vcpu, 0);
2783 vmx_fpu_activate(&vmx->vcpu);
2784 update_exception_bitmap(&vmx->vcpu);
2785
2786 vpid_sync_context(vmx);
2787
2788 ret = 0;
2789
2790 /* HACK: Don't enable emulation on guest boot/reset */
2791 vmx->emulation_required = 0;
2792
2793 out:
2794 return ret;
2795 }
2796
2797 static void enable_irq_window(struct kvm_vcpu *vcpu)
2798 {
2799 u32 cpu_based_vm_exec_control;
2800
2801 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2802 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2803 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2804 }
2805
2806 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2807 {
2808 u32 cpu_based_vm_exec_control;
2809
2810 if (!cpu_has_virtual_nmis()) {
2811 enable_irq_window(vcpu);
2812 return;
2813 }
2814
2815 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2816 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2817 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2818 }
2819
2820 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2821 {
2822 struct vcpu_vmx *vmx = to_vmx(vcpu);
2823 uint32_t intr;
2824 int irq = vcpu->arch.interrupt.nr;
2825
2826 trace_kvm_inj_virq(irq);
2827
2828 ++vcpu->stat.irq_injections;
2829 if (vmx->rmode.vm86_active) {
2830 vmx->rmode.irq.pending = true;
2831 vmx->rmode.irq.vector = irq;
2832 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2833 if (vcpu->arch.interrupt.soft)
2834 vmx->rmode.irq.rip +=
2835 vmx->vcpu.arch.event_exit_inst_len;
2836 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2837 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2838 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2839 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2840 return;
2841 }
2842 intr = irq | INTR_INFO_VALID_MASK;
2843 if (vcpu->arch.interrupt.soft) {
2844 intr |= INTR_TYPE_SOFT_INTR;
2845 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2846 vmx->vcpu.arch.event_exit_inst_len);
2847 } else
2848 intr |= INTR_TYPE_EXT_INTR;
2849 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2850 }
2851
2852 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2853 {
2854 struct vcpu_vmx *vmx = to_vmx(vcpu);
2855
2856 if (!cpu_has_virtual_nmis()) {
2857 /*
2858 * Tracking the NMI-blocked state in software is built upon
2859 * finding the next open IRQ window. This, in turn, depends on
2860 * well-behaving guests: They have to keep IRQs disabled at
2861 * least as long as the NMI handler runs. Otherwise we may
2862 * cause NMI nesting, maybe breaking the guest. But as this is
2863 * highly unlikely, we can live with the residual risk.
2864 */
2865 vmx->soft_vnmi_blocked = 1;
2866 vmx->vnmi_blocked_time = 0;
2867 }
2868
2869 ++vcpu->stat.nmi_injections;
2870 if (vmx->rmode.vm86_active) {
2871 vmx->rmode.irq.pending = true;
2872 vmx->rmode.irq.vector = NMI_VECTOR;
2873 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2874 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2875 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2876 INTR_INFO_VALID_MASK);
2877 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2878 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2879 return;
2880 }
2881 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2882 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2883 }
2884
2885 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2886 {
2887 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2888 return 0;
2889
2890 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2891 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI));
2892 }
2893
2894 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2895 {
2896 if (!cpu_has_virtual_nmis())
2897 return to_vmx(vcpu)->soft_vnmi_blocked;
2898 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
2899 }
2900
2901 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2902 {
2903 struct vcpu_vmx *vmx = to_vmx(vcpu);
2904
2905 if (!cpu_has_virtual_nmis()) {
2906 if (vmx->soft_vnmi_blocked != masked) {
2907 vmx->soft_vnmi_blocked = masked;
2908 vmx->vnmi_blocked_time = 0;
2909 }
2910 } else {
2911 if (masked)
2912 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2913 GUEST_INTR_STATE_NMI);
2914 else
2915 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2916 GUEST_INTR_STATE_NMI);
2917 }
2918 }
2919
2920 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2921 {
2922 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2923 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2924 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2925 }
2926
2927 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2928 {
2929 int ret;
2930 struct kvm_userspace_memory_region tss_mem = {
2931 .slot = TSS_PRIVATE_MEMSLOT,
2932 .guest_phys_addr = addr,
2933 .memory_size = PAGE_SIZE * 3,
2934 .flags = 0,
2935 };
2936
2937 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2938 if (ret)
2939 return ret;
2940 kvm->arch.tss_addr = addr;
2941 return 0;
2942 }
2943
2944 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2945 int vec, u32 err_code)
2946 {
2947 /*
2948 * Instruction with address size override prefix opcode 0x67
2949 * Cause the #SS fault with 0 error code in VM86 mode.
2950 */
2951 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2952 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2953 return 1;
2954 /*
2955 * Forward all other exceptions that are valid in real mode.
2956 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2957 * the required debugging infrastructure rework.
2958 */
2959 switch (vec) {
2960 case DB_VECTOR:
2961 if (vcpu->guest_debug &
2962 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2963 return 0;
2964 kvm_queue_exception(vcpu, vec);
2965 return 1;
2966 case BP_VECTOR:
2967 /*
2968 * Update instruction length as we may reinject the exception
2969 * from user space while in guest debugging mode.
2970 */
2971 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2972 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2973 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2974 return 0;
2975 /* fall through */
2976 case DE_VECTOR:
2977 case OF_VECTOR:
2978 case BR_VECTOR:
2979 case UD_VECTOR:
2980 case DF_VECTOR:
2981 case SS_VECTOR:
2982 case GP_VECTOR:
2983 case MF_VECTOR:
2984 kvm_queue_exception(vcpu, vec);
2985 return 1;
2986 }
2987 return 0;
2988 }
2989
2990 /*
2991 * Trigger machine check on the host. We assume all the MSRs are already set up
2992 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2993 * We pass a fake environment to the machine check handler because we want
2994 * the guest to be always treated like user space, no matter what context
2995 * it used internally.
2996 */
2997 static void kvm_machine_check(void)
2998 {
2999 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3000 struct pt_regs regs = {
3001 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3002 .flags = X86_EFLAGS_IF,
3003 };
3004
3005 do_machine_check(&regs, 0);
3006 #endif
3007 }
3008
3009 static int handle_machine_check(struct kvm_vcpu *vcpu)
3010 {
3011 /* already handled by vcpu_run */
3012 return 1;
3013 }
3014
3015 static int handle_exception(struct kvm_vcpu *vcpu)
3016 {
3017 struct vcpu_vmx *vmx = to_vmx(vcpu);
3018 struct kvm_run *kvm_run = vcpu->run;
3019 u32 intr_info, ex_no, error_code;
3020 unsigned long cr2, rip, dr6;
3021 u32 vect_info;
3022 enum emulation_result er;
3023
3024 vect_info = vmx->idt_vectoring_info;
3025 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3026
3027 if (is_machine_check(intr_info))
3028 return handle_machine_check(vcpu);
3029
3030 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3031 !is_page_fault(intr_info)) {
3032 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3033 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3034 vcpu->run->internal.ndata = 2;
3035 vcpu->run->internal.data[0] = vect_info;
3036 vcpu->run->internal.data[1] = intr_info;
3037 return 0;
3038 }
3039
3040 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3041 return 1; /* already handled by vmx_vcpu_run() */
3042
3043 if (is_no_device(intr_info)) {
3044 vmx_fpu_activate(vcpu);
3045 return 1;
3046 }
3047
3048 if (is_invalid_opcode(intr_info)) {
3049 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
3050 if (er != EMULATE_DONE)
3051 kvm_queue_exception(vcpu, UD_VECTOR);
3052 return 1;
3053 }
3054
3055 error_code = 0;
3056 rip = kvm_rip_read(vcpu);
3057 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3058 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3059 if (is_page_fault(intr_info)) {
3060 /* EPT won't cause page fault directly */
3061 if (enable_ept)
3062 BUG();
3063 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3064 trace_kvm_page_fault(cr2, error_code);
3065
3066 if (kvm_event_needs_reinjection(vcpu))
3067 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3068 return kvm_mmu_page_fault(vcpu, cr2, error_code);
3069 }
3070
3071 if (vmx->rmode.vm86_active &&
3072 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3073 error_code)) {
3074 if (vcpu->arch.halt_request) {
3075 vcpu->arch.halt_request = 0;
3076 return kvm_emulate_halt(vcpu);
3077 }
3078 return 1;
3079 }
3080
3081 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3082 switch (ex_no) {
3083 case DB_VECTOR:
3084 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3085 if (!(vcpu->guest_debug &
3086 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3087 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3088 kvm_queue_exception(vcpu, DB_VECTOR);
3089 return 1;
3090 }
3091 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3092 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3093 /* fall through */
3094 case BP_VECTOR:
3095 /*
3096 * Update instruction length as we may reinject #BP from
3097 * user space while in guest debugging mode. Reading it for
3098 * #DB as well causes no harm, it is not used in that case.
3099 */
3100 vmx->vcpu.arch.event_exit_inst_len =
3101 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3102 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3103 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3104 kvm_run->debug.arch.exception = ex_no;
3105 break;
3106 default:
3107 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3108 kvm_run->ex.exception = ex_no;
3109 kvm_run->ex.error_code = error_code;
3110 break;
3111 }
3112 return 0;
3113 }
3114
3115 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3116 {
3117 ++vcpu->stat.irq_exits;
3118 return 1;
3119 }
3120
3121 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3122 {
3123 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3124 return 0;
3125 }
3126
3127 static int handle_io(struct kvm_vcpu *vcpu)
3128 {
3129 unsigned long exit_qualification;
3130 int size, in, string;
3131 unsigned port;
3132
3133 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3134 string = (exit_qualification & 16) != 0;
3135 in = (exit_qualification & 8) != 0;
3136
3137 ++vcpu->stat.io_exits;
3138
3139 if (string || in)
3140 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3141
3142 port = exit_qualification >> 16;
3143 size = (exit_qualification & 7) + 1;
3144 skip_emulated_instruction(vcpu);
3145
3146 return kvm_fast_pio_out(vcpu, size, port);
3147 }
3148
3149 static void
3150 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3151 {
3152 /*
3153 * Patch in the VMCALL instruction:
3154 */
3155 hypercall[0] = 0x0f;
3156 hypercall[1] = 0x01;
3157 hypercall[2] = 0xc1;
3158 }
3159
3160 static void complete_insn_gp(struct kvm_vcpu *vcpu, int err)
3161 {
3162 if (err)
3163 kvm_inject_gp(vcpu, 0);
3164 else
3165 skip_emulated_instruction(vcpu);
3166 }
3167
3168 static int handle_cr(struct kvm_vcpu *vcpu)
3169 {
3170 unsigned long exit_qualification, val;
3171 int cr;
3172 int reg;
3173 int err;
3174
3175 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3176 cr = exit_qualification & 15;
3177 reg = (exit_qualification >> 8) & 15;
3178 switch ((exit_qualification >> 4) & 3) {
3179 case 0: /* mov to cr */
3180 val = kvm_register_read(vcpu, reg);
3181 trace_kvm_cr_write(cr, val);
3182 switch (cr) {
3183 case 0:
3184 err = kvm_set_cr0(vcpu, val);
3185 complete_insn_gp(vcpu, err);
3186 return 1;
3187 case 3:
3188 kvm_set_cr3(vcpu, val);
3189 skip_emulated_instruction(vcpu);
3190 return 1;
3191 case 4:
3192 kvm_set_cr4(vcpu, val);
3193 skip_emulated_instruction(vcpu);
3194 return 1;
3195 case 8: {
3196 u8 cr8_prev = kvm_get_cr8(vcpu);
3197 u8 cr8 = kvm_register_read(vcpu, reg);
3198 kvm_set_cr8(vcpu, cr8);
3199 skip_emulated_instruction(vcpu);
3200 if (irqchip_in_kernel(vcpu->kvm))
3201 return 1;
3202 if (cr8_prev <= cr8)
3203 return 1;
3204 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3205 return 0;
3206 }
3207 };
3208 break;
3209 case 2: /* clts */
3210 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3211 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3212 skip_emulated_instruction(vcpu);
3213 vmx_fpu_activate(vcpu);
3214 return 1;
3215 case 1: /*mov from cr*/
3216 switch (cr) {
3217 case 3:
3218 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
3219 trace_kvm_cr_read(cr, vcpu->arch.cr3);
3220 skip_emulated_instruction(vcpu);
3221 return 1;
3222 case 8:
3223 val = kvm_get_cr8(vcpu);
3224 kvm_register_write(vcpu, reg, val);
3225 trace_kvm_cr_read(cr, val);
3226 skip_emulated_instruction(vcpu);
3227 return 1;
3228 }
3229 break;
3230 case 3: /* lmsw */
3231 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3232 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3233 kvm_lmsw(vcpu, val);
3234
3235 skip_emulated_instruction(vcpu);
3236 return 1;
3237 default:
3238 break;
3239 }
3240 vcpu->run->exit_reason = 0;
3241 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3242 (int)(exit_qualification >> 4) & 3, cr);
3243 return 0;
3244 }
3245
3246 static int handle_dr(struct kvm_vcpu *vcpu)
3247 {
3248 unsigned long exit_qualification;
3249 int dr, reg;
3250
3251 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3252 if (!kvm_require_cpl(vcpu, 0))
3253 return 1;
3254 dr = vmcs_readl(GUEST_DR7);
3255 if (dr & DR7_GD) {
3256 /*
3257 * As the vm-exit takes precedence over the debug trap, we
3258 * need to emulate the latter, either for the host or the
3259 * guest debugging itself.
3260 */
3261 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3262 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3263 vcpu->run->debug.arch.dr7 = dr;
3264 vcpu->run->debug.arch.pc =
3265 vmcs_readl(GUEST_CS_BASE) +
3266 vmcs_readl(GUEST_RIP);
3267 vcpu->run->debug.arch.exception = DB_VECTOR;
3268 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3269 return 0;
3270 } else {
3271 vcpu->arch.dr7 &= ~DR7_GD;
3272 vcpu->arch.dr6 |= DR6_BD;
3273 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3274 kvm_queue_exception(vcpu, DB_VECTOR);
3275 return 1;
3276 }
3277 }
3278
3279 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3280 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3281 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3282 if (exit_qualification & TYPE_MOV_FROM_DR) {
3283 unsigned long val;
3284 if (!kvm_get_dr(vcpu, dr, &val))
3285 kvm_register_write(vcpu, reg, val);
3286 } else
3287 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3288 skip_emulated_instruction(vcpu);
3289 return 1;
3290 }
3291
3292 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3293 {
3294 vmcs_writel(GUEST_DR7, val);
3295 }
3296
3297 static int handle_cpuid(struct kvm_vcpu *vcpu)
3298 {
3299 kvm_emulate_cpuid(vcpu);
3300 return 1;
3301 }
3302
3303 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3304 {
3305 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3306 u64 data;
3307
3308 if (vmx_get_msr(vcpu, ecx, &data)) {
3309 trace_kvm_msr_read_ex(ecx);
3310 kvm_inject_gp(vcpu, 0);
3311 return 1;
3312 }
3313
3314 trace_kvm_msr_read(ecx, data);
3315
3316 /* FIXME: handling of bits 32:63 of rax, rdx */
3317 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3318 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3319 skip_emulated_instruction(vcpu);
3320 return 1;
3321 }
3322
3323 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3324 {
3325 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3326 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3327 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3328
3329 if (vmx_set_msr(vcpu, ecx, data) != 0) {
3330 trace_kvm_msr_write_ex(ecx, data);
3331 kvm_inject_gp(vcpu, 0);
3332 return 1;
3333 }
3334
3335 trace_kvm_msr_write(ecx, data);
3336 skip_emulated_instruction(vcpu);
3337 return 1;
3338 }
3339
3340 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3341 {
3342 return 1;
3343 }
3344
3345 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3346 {
3347 u32 cpu_based_vm_exec_control;
3348
3349 /* clear pending irq */
3350 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3351 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3352 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3353
3354 ++vcpu->stat.irq_window_exits;
3355
3356 /*
3357 * If the user space waits to inject interrupts, exit as soon as
3358 * possible
3359 */
3360 if (!irqchip_in_kernel(vcpu->kvm) &&
3361 vcpu->run->request_interrupt_window &&
3362 !kvm_cpu_has_interrupt(vcpu)) {
3363 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3364 return 0;
3365 }
3366 return 1;
3367 }
3368
3369 static int handle_halt(struct kvm_vcpu *vcpu)
3370 {
3371 skip_emulated_instruction(vcpu);
3372 return kvm_emulate_halt(vcpu);
3373 }
3374
3375 static int handle_vmcall(struct kvm_vcpu *vcpu)
3376 {
3377 skip_emulated_instruction(vcpu);
3378 kvm_emulate_hypercall(vcpu);
3379 return 1;
3380 }
3381
3382 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3383 {
3384 kvm_queue_exception(vcpu, UD_VECTOR);
3385 return 1;
3386 }
3387
3388 static int handle_invlpg(struct kvm_vcpu *vcpu)
3389 {
3390 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3391
3392 kvm_mmu_invlpg(vcpu, exit_qualification);
3393 skip_emulated_instruction(vcpu);
3394 return 1;
3395 }
3396
3397 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3398 {
3399 skip_emulated_instruction(vcpu);
3400 /* TODO: Add support for VT-d/pass-through device */
3401 return 1;
3402 }
3403
3404 static int handle_xsetbv(struct kvm_vcpu *vcpu)
3405 {
3406 u64 new_bv = kvm_read_edx_eax(vcpu);
3407 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3408
3409 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3410 skip_emulated_instruction(vcpu);
3411 return 1;
3412 }
3413
3414 static int handle_apic_access(struct kvm_vcpu *vcpu)
3415 {
3416 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3417 }
3418
3419 static int handle_task_switch(struct kvm_vcpu *vcpu)
3420 {
3421 struct vcpu_vmx *vmx = to_vmx(vcpu);
3422 unsigned long exit_qualification;
3423 bool has_error_code = false;
3424 u32 error_code = 0;
3425 u16 tss_selector;
3426 int reason, type, idt_v;
3427
3428 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3429 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3430
3431 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3432
3433 reason = (u32)exit_qualification >> 30;
3434 if (reason == TASK_SWITCH_GATE && idt_v) {
3435 switch (type) {
3436 case INTR_TYPE_NMI_INTR:
3437 vcpu->arch.nmi_injected = false;
3438 if (cpu_has_virtual_nmis())
3439 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3440 GUEST_INTR_STATE_NMI);
3441 break;
3442 case INTR_TYPE_EXT_INTR:
3443 case INTR_TYPE_SOFT_INTR:
3444 kvm_clear_interrupt_queue(vcpu);
3445 break;
3446 case INTR_TYPE_HARD_EXCEPTION:
3447 if (vmx->idt_vectoring_info &
3448 VECTORING_INFO_DELIVER_CODE_MASK) {
3449 has_error_code = true;
3450 error_code =
3451 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3452 }
3453 /* fall through */
3454 case INTR_TYPE_SOFT_EXCEPTION:
3455 kvm_clear_exception_queue(vcpu);
3456 break;
3457 default:
3458 break;
3459 }
3460 }
3461 tss_selector = exit_qualification;
3462
3463 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3464 type != INTR_TYPE_EXT_INTR &&
3465 type != INTR_TYPE_NMI_INTR))
3466 skip_emulated_instruction(vcpu);
3467
3468 if (kvm_task_switch(vcpu, tss_selector, reason,
3469 has_error_code, error_code) == EMULATE_FAIL) {
3470 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3471 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3472 vcpu->run->internal.ndata = 0;
3473 return 0;
3474 }
3475
3476 /* clear all local breakpoint enable flags */
3477 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3478
3479 /*
3480 * TODO: What about debug traps on tss switch?
3481 * Are we supposed to inject them and update dr6?
3482 */
3483
3484 return 1;
3485 }
3486
3487 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3488 {
3489 unsigned long exit_qualification;
3490 gpa_t gpa;
3491 int gla_validity;
3492
3493 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3494
3495 if (exit_qualification & (1 << 6)) {
3496 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3497 return -EINVAL;
3498 }
3499
3500 gla_validity = (exit_qualification >> 7) & 0x3;
3501 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3502 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3503 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3504 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3505 vmcs_readl(GUEST_LINEAR_ADDRESS));
3506 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3507 (long unsigned int)exit_qualification);
3508 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3509 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3510 return 0;
3511 }
3512
3513 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3514 trace_kvm_page_fault(gpa, exit_qualification);
3515 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3516 }
3517
3518 static u64 ept_rsvd_mask(u64 spte, int level)
3519 {
3520 int i;
3521 u64 mask = 0;
3522
3523 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3524 mask |= (1ULL << i);
3525
3526 if (level > 2)
3527 /* bits 7:3 reserved */
3528 mask |= 0xf8;
3529 else if (level == 2) {
3530 if (spte & (1ULL << 7))
3531 /* 2MB ref, bits 20:12 reserved */
3532 mask |= 0x1ff000;
3533 else
3534 /* bits 6:3 reserved */
3535 mask |= 0x78;
3536 }
3537
3538 return mask;
3539 }
3540
3541 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3542 int level)
3543 {
3544 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3545
3546 /* 010b (write-only) */
3547 WARN_ON((spte & 0x7) == 0x2);
3548
3549 /* 110b (write/execute) */
3550 WARN_ON((spte & 0x7) == 0x6);
3551
3552 /* 100b (execute-only) and value not supported by logical processor */
3553 if (!cpu_has_vmx_ept_execute_only())
3554 WARN_ON((spte & 0x7) == 0x4);
3555
3556 /* not 000b */
3557 if ((spte & 0x7)) {
3558 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3559
3560 if (rsvd_bits != 0) {
3561 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3562 __func__, rsvd_bits);
3563 WARN_ON(1);
3564 }
3565
3566 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3567 u64 ept_mem_type = (spte & 0x38) >> 3;
3568
3569 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3570 ept_mem_type == 7) {
3571 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3572 __func__, ept_mem_type);
3573 WARN_ON(1);
3574 }
3575 }
3576 }
3577 }
3578
3579 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3580 {
3581 u64 sptes[4];
3582 int nr_sptes, i;
3583 gpa_t gpa;
3584
3585 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3586
3587 printk(KERN_ERR "EPT: Misconfiguration.\n");
3588 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3589
3590 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3591
3592 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3593 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3594
3595 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3596 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3597
3598 return 0;
3599 }
3600
3601 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3602 {
3603 u32 cpu_based_vm_exec_control;
3604
3605 /* clear pending NMI */
3606 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3607 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3608 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3609 ++vcpu->stat.nmi_window_exits;
3610
3611 return 1;
3612 }
3613
3614 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3615 {
3616 struct vcpu_vmx *vmx = to_vmx(vcpu);
3617 enum emulation_result err = EMULATE_DONE;
3618 int ret = 1;
3619
3620 while (!guest_state_valid(vcpu)) {
3621 err = emulate_instruction(vcpu, 0, 0, 0);
3622
3623 if (err == EMULATE_DO_MMIO) {
3624 ret = 0;
3625 goto out;
3626 }
3627
3628 if (err != EMULATE_DONE)
3629 return 0;
3630
3631 if (signal_pending(current))
3632 goto out;
3633 if (need_resched())
3634 schedule();
3635 }
3636
3637 vmx->emulation_required = 0;
3638 out:
3639 return ret;
3640 }
3641
3642 /*
3643 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3644 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3645 */
3646 static int handle_pause(struct kvm_vcpu *vcpu)
3647 {
3648 skip_emulated_instruction(vcpu);
3649 kvm_vcpu_on_spin(vcpu);
3650
3651 return 1;
3652 }
3653
3654 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3655 {
3656 kvm_queue_exception(vcpu, UD_VECTOR);
3657 return 1;
3658 }
3659
3660 /*
3661 * The exit handlers return 1 if the exit was handled fully and guest execution
3662 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3663 * to be done to userspace and return 0.
3664 */
3665 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3666 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3667 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3668 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3669 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3670 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3671 [EXIT_REASON_CR_ACCESS] = handle_cr,
3672 [EXIT_REASON_DR_ACCESS] = handle_dr,
3673 [EXIT_REASON_CPUID] = handle_cpuid,
3674 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3675 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3676 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3677 [EXIT_REASON_HLT] = handle_halt,
3678 [EXIT_REASON_INVLPG] = handle_invlpg,
3679 [EXIT_REASON_VMCALL] = handle_vmcall,
3680 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3681 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3682 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3683 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3684 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3685 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3686 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3687 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3688 [EXIT_REASON_VMON] = handle_vmx_insn,
3689 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3690 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3691 [EXIT_REASON_WBINVD] = handle_wbinvd,
3692 [EXIT_REASON_XSETBV] = handle_xsetbv,
3693 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3694 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3695 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3696 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
3697 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
3698 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3699 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
3700 };
3701
3702 static const int kvm_vmx_max_exit_handlers =
3703 ARRAY_SIZE(kvm_vmx_exit_handlers);
3704
3705 /*
3706 * The guest has exited. See if we can fix it or if we need userspace
3707 * assistance.
3708 */
3709 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3710 {
3711 struct vcpu_vmx *vmx = to_vmx(vcpu);
3712 u32 exit_reason = vmx->exit_reason;
3713 u32 vectoring_info = vmx->idt_vectoring_info;
3714
3715 trace_kvm_exit(exit_reason, vcpu);
3716
3717 /* If guest state is invalid, start emulating */
3718 if (vmx->emulation_required && emulate_invalid_guest_state)
3719 return handle_invalid_guest_state(vcpu);
3720
3721 /* Access CR3 don't cause VMExit in paging mode, so we need
3722 * to sync with guest real CR3. */
3723 if (enable_ept && is_paging(vcpu))
3724 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3725
3726 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3727 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3728 vcpu->run->fail_entry.hardware_entry_failure_reason
3729 = exit_reason;
3730 return 0;
3731 }
3732
3733 if (unlikely(vmx->fail)) {
3734 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3735 vcpu->run->fail_entry.hardware_entry_failure_reason
3736 = vmcs_read32(VM_INSTRUCTION_ERROR);
3737 return 0;
3738 }
3739
3740 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3741 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3742 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3743 exit_reason != EXIT_REASON_TASK_SWITCH))
3744 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3745 "(0x%x) and exit reason is 0x%x\n",
3746 __func__, vectoring_info, exit_reason);
3747
3748 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3749 if (vmx_interrupt_allowed(vcpu)) {
3750 vmx->soft_vnmi_blocked = 0;
3751 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3752 vcpu->arch.nmi_pending) {
3753 /*
3754 * This CPU don't support us in finding the end of an
3755 * NMI-blocked window if the guest runs with IRQs
3756 * disabled. So we pull the trigger after 1 s of
3757 * futile waiting, but inform the user about this.
3758 */
3759 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3760 "state on VCPU %d after 1 s timeout\n",
3761 __func__, vcpu->vcpu_id);
3762 vmx->soft_vnmi_blocked = 0;
3763 }
3764 }
3765
3766 if (exit_reason < kvm_vmx_max_exit_handlers
3767 && kvm_vmx_exit_handlers[exit_reason])
3768 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3769 else {
3770 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3771 vcpu->run->hw.hardware_exit_reason = exit_reason;
3772 }
3773 return 0;
3774 }
3775
3776 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3777 {
3778 if (irr == -1 || tpr < irr) {
3779 vmcs_write32(TPR_THRESHOLD, 0);
3780 return;
3781 }
3782
3783 vmcs_write32(TPR_THRESHOLD, irr);
3784 }
3785
3786 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3787 {
3788 u32 exit_intr_info;
3789 u32 idt_vectoring_info = vmx->idt_vectoring_info;
3790 bool unblock_nmi;
3791 u8 vector;
3792 int type;
3793 bool idtv_info_valid;
3794
3795 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3796
3797 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3798
3799 /* Handle machine checks before interrupts are enabled */
3800 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3801 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3802 && is_machine_check(exit_intr_info)))
3803 kvm_machine_check();
3804
3805 /* We need to handle NMIs before interrupts are enabled */
3806 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3807 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3808 kvm_before_handle_nmi(&vmx->vcpu);
3809 asm("int $2");
3810 kvm_after_handle_nmi(&vmx->vcpu);
3811 }
3812
3813 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3814
3815 if (cpu_has_virtual_nmis()) {
3816 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3817 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3818 /*
3819 * SDM 3: 27.7.1.2 (September 2008)
3820 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3821 * a guest IRET fault.
3822 * SDM 3: 23.2.2 (September 2008)
3823 * Bit 12 is undefined in any of the following cases:
3824 * If the VM exit sets the valid bit in the IDT-vectoring
3825 * information field.
3826 * If the VM exit is due to a double fault.
3827 */
3828 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3829 vector != DF_VECTOR && !idtv_info_valid)
3830 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3831 GUEST_INTR_STATE_NMI);
3832 } else if (unlikely(vmx->soft_vnmi_blocked))
3833 vmx->vnmi_blocked_time +=
3834 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3835
3836 vmx->vcpu.arch.nmi_injected = false;
3837 kvm_clear_exception_queue(&vmx->vcpu);
3838 kvm_clear_interrupt_queue(&vmx->vcpu);
3839
3840 if (!idtv_info_valid)
3841 return;
3842
3843 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3844 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3845
3846 switch (type) {
3847 case INTR_TYPE_NMI_INTR:
3848 vmx->vcpu.arch.nmi_injected = true;
3849 /*
3850 * SDM 3: 27.7.1.2 (September 2008)
3851 * Clear bit "block by NMI" before VM entry if a NMI
3852 * delivery faulted.
3853 */
3854 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3855 GUEST_INTR_STATE_NMI);
3856 break;
3857 case INTR_TYPE_SOFT_EXCEPTION:
3858 vmx->vcpu.arch.event_exit_inst_len =
3859 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3860 /* fall through */
3861 case INTR_TYPE_HARD_EXCEPTION:
3862 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3863 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3864 kvm_queue_exception_e(&vmx->vcpu, vector, err);
3865 } else
3866 kvm_queue_exception(&vmx->vcpu, vector);
3867 break;
3868 case INTR_TYPE_SOFT_INTR:
3869 vmx->vcpu.arch.event_exit_inst_len =
3870 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3871 /* fall through */
3872 case INTR_TYPE_EXT_INTR:
3873 kvm_queue_interrupt(&vmx->vcpu, vector,
3874 type == INTR_TYPE_SOFT_INTR);
3875 break;
3876 default:
3877 break;
3878 }
3879 }
3880
3881 /*
3882 * Failure to inject an interrupt should give us the information
3883 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3884 * when fetching the interrupt redirection bitmap in the real-mode
3885 * tss, this doesn't happen. So we do it ourselves.
3886 */
3887 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3888 {
3889 vmx->rmode.irq.pending = 0;
3890 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3891 return;
3892 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3893 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3894 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3895 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3896 return;
3897 }
3898 vmx->idt_vectoring_info =
3899 VECTORING_INFO_VALID_MASK
3900 | INTR_TYPE_EXT_INTR
3901 | vmx->rmode.irq.vector;
3902 }
3903
3904 #ifdef CONFIG_X86_64
3905 #define R "r"
3906 #define Q "q"
3907 #else
3908 #define R "e"
3909 #define Q "l"
3910 #endif
3911
3912 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3913 {
3914 struct vcpu_vmx *vmx = to_vmx(vcpu);
3915
3916 /* Record the guest's net vcpu time for enforced NMI injections. */
3917 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3918 vmx->entry_time = ktime_get();
3919
3920 /* Don't enter VMX if guest state is invalid, let the exit handler
3921 start emulation until we arrive back to a valid state */
3922 if (vmx->emulation_required && emulate_invalid_guest_state)
3923 return;
3924
3925 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3926 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3927 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3928 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3929
3930 /* When single-stepping over STI and MOV SS, we must clear the
3931 * corresponding interruptibility bits in the guest state. Otherwise
3932 * vmentry fails as it then expects bit 14 (BS) in pending debug
3933 * exceptions being set, but that's not correct for the guest debugging
3934 * case. */
3935 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3936 vmx_set_interrupt_shadow(vcpu, 0);
3937
3938 asm(
3939 /* Store host registers */
3940 "push %%"R"dx; push %%"R"bp;"
3941 "push %%"R"cx \n\t"
3942 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3943 "je 1f \n\t"
3944 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3945 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3946 "1: \n\t"
3947 /* Reload cr2 if changed */
3948 "mov %c[cr2](%0), %%"R"ax \n\t"
3949 "mov %%cr2, %%"R"dx \n\t"
3950 "cmp %%"R"ax, %%"R"dx \n\t"
3951 "je 2f \n\t"
3952 "mov %%"R"ax, %%cr2 \n\t"
3953 "2: \n\t"
3954 /* Check if vmlaunch of vmresume is needed */
3955 "cmpl $0, %c[launched](%0) \n\t"
3956 /* Load guest registers. Don't clobber flags. */
3957 "mov %c[rax](%0), %%"R"ax \n\t"
3958 "mov %c[rbx](%0), %%"R"bx \n\t"
3959 "mov %c[rdx](%0), %%"R"dx \n\t"
3960 "mov %c[rsi](%0), %%"R"si \n\t"
3961 "mov %c[rdi](%0), %%"R"di \n\t"
3962 "mov %c[rbp](%0), %%"R"bp \n\t"
3963 #ifdef CONFIG_X86_64
3964 "mov %c[r8](%0), %%r8 \n\t"
3965 "mov %c[r9](%0), %%r9 \n\t"
3966 "mov %c[r10](%0), %%r10 \n\t"
3967 "mov %c[r11](%0), %%r11 \n\t"
3968 "mov %c[r12](%0), %%r12 \n\t"
3969 "mov %c[r13](%0), %%r13 \n\t"
3970 "mov %c[r14](%0), %%r14 \n\t"
3971 "mov %c[r15](%0), %%r15 \n\t"
3972 #endif
3973 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3974
3975 /* Enter guest mode */
3976 "jne .Llaunched \n\t"
3977 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3978 "jmp .Lkvm_vmx_return \n\t"
3979 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3980 ".Lkvm_vmx_return: "
3981 /* Save guest registers, load host registers, keep flags */
3982 "xchg %0, (%%"R"sp) \n\t"
3983 "mov %%"R"ax, %c[rax](%0) \n\t"
3984 "mov %%"R"bx, %c[rbx](%0) \n\t"
3985 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3986 "mov %%"R"dx, %c[rdx](%0) \n\t"
3987 "mov %%"R"si, %c[rsi](%0) \n\t"
3988 "mov %%"R"di, %c[rdi](%0) \n\t"
3989 "mov %%"R"bp, %c[rbp](%0) \n\t"
3990 #ifdef CONFIG_X86_64
3991 "mov %%r8, %c[r8](%0) \n\t"
3992 "mov %%r9, %c[r9](%0) \n\t"
3993 "mov %%r10, %c[r10](%0) \n\t"
3994 "mov %%r11, %c[r11](%0) \n\t"
3995 "mov %%r12, %c[r12](%0) \n\t"
3996 "mov %%r13, %c[r13](%0) \n\t"
3997 "mov %%r14, %c[r14](%0) \n\t"
3998 "mov %%r15, %c[r15](%0) \n\t"
3999 #endif
4000 "mov %%cr2, %%"R"ax \n\t"
4001 "mov %%"R"ax, %c[cr2](%0) \n\t"
4002
4003 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
4004 "setbe %c[fail](%0) \n\t"
4005 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4006 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4007 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
4008 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
4009 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4010 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4011 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4012 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4013 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4014 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4015 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
4016 #ifdef CONFIG_X86_64
4017 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4018 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4019 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4020 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4021 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4022 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4023 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4024 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
4025 #endif
4026 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
4027 : "cc", "memory"
4028 , R"bx", R"di", R"si"
4029 #ifdef CONFIG_X86_64
4030 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4031 #endif
4032 );
4033
4034 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4035 | (1 << VCPU_EXREG_PDPTR));
4036 vcpu->arch.regs_dirty = 0;
4037
4038 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4039 if (vmx->rmode.irq.pending)
4040 fixup_rmode_irq(vmx);
4041
4042 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
4043 vmx->launched = 1;
4044
4045 vmx_complete_interrupts(vmx);
4046 }
4047
4048 #undef R
4049 #undef Q
4050
4051 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4052 {
4053 struct vcpu_vmx *vmx = to_vmx(vcpu);
4054
4055 if (vmx->vmcs) {
4056 vcpu_clear(vmx);
4057 free_vmcs(vmx->vmcs);
4058 vmx->vmcs = NULL;
4059 }
4060 }
4061
4062 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4063 {
4064 struct vcpu_vmx *vmx = to_vmx(vcpu);
4065
4066 free_vpid(vmx);
4067 vmx_free_vmcs(vcpu);
4068 kfree(vmx->guest_msrs);
4069 kvm_vcpu_uninit(vcpu);
4070 kmem_cache_free(kvm_vcpu_cache, vmx);
4071 }
4072
4073 static inline void vmcs_init(struct vmcs *vmcs)
4074 {
4075 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4076
4077 if (!vmm_exclusive)
4078 kvm_cpu_vmxon(phys_addr);
4079
4080 vmcs_clear(vmcs);
4081
4082 if (!vmm_exclusive)
4083 kvm_cpu_vmxoff();
4084 }
4085
4086 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4087 {
4088 int err;
4089 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4090 int cpu;
4091
4092 if (!vmx)
4093 return ERR_PTR(-ENOMEM);
4094
4095 allocate_vpid(vmx);
4096
4097 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4098 if (err)
4099 goto free_vcpu;
4100
4101 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4102 if (!vmx->guest_msrs) {
4103 err = -ENOMEM;
4104 goto uninit_vcpu;
4105 }
4106
4107 vmx->vmcs = alloc_vmcs();
4108 if (!vmx->vmcs)
4109 goto free_msrs;
4110
4111 vmcs_init(vmx->vmcs);
4112
4113 cpu = get_cpu();
4114 vmx_vcpu_load(&vmx->vcpu, cpu);
4115 err = vmx_vcpu_setup(vmx);
4116 vmx_vcpu_put(&vmx->vcpu);
4117 put_cpu();
4118 if (err)
4119 goto free_vmcs;
4120 if (vm_need_virtualize_apic_accesses(kvm))
4121 if (alloc_apic_access_page(kvm) != 0)
4122 goto free_vmcs;
4123
4124 if (enable_ept) {
4125 if (!kvm->arch.ept_identity_map_addr)
4126 kvm->arch.ept_identity_map_addr =
4127 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4128 if (alloc_identity_pagetable(kvm) != 0)
4129 goto free_vmcs;
4130 }
4131
4132 return &vmx->vcpu;
4133
4134 free_vmcs:
4135 free_vmcs(vmx->vmcs);
4136 free_msrs:
4137 kfree(vmx->guest_msrs);
4138 uninit_vcpu:
4139 kvm_vcpu_uninit(&vmx->vcpu);
4140 free_vcpu:
4141 free_vpid(vmx);
4142 kmem_cache_free(kvm_vcpu_cache, vmx);
4143 return ERR_PTR(err);
4144 }
4145
4146 static void __init vmx_check_processor_compat(void *rtn)
4147 {
4148 struct vmcs_config vmcs_conf;
4149
4150 *(int *)rtn = 0;
4151 if (setup_vmcs_config(&vmcs_conf) < 0)
4152 *(int *)rtn = -EIO;
4153 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4154 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4155 smp_processor_id());
4156 *(int *)rtn = -EIO;
4157 }
4158 }
4159
4160 static int get_ept_level(void)
4161 {
4162 return VMX_EPT_DEFAULT_GAW + 1;
4163 }
4164
4165 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4166 {
4167 u64 ret;
4168
4169 /* For VT-d and EPT combination
4170 * 1. MMIO: always map as UC
4171 * 2. EPT with VT-d:
4172 * a. VT-d without snooping control feature: can't guarantee the
4173 * result, try to trust guest.
4174 * b. VT-d with snooping control feature: snooping control feature of
4175 * VT-d engine can guarantee the cache correctness. Just set it
4176 * to WB to keep consistent with host. So the same as item 3.
4177 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4178 * consistent with host MTRR
4179 */
4180 if (is_mmio)
4181 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4182 else if (vcpu->kvm->arch.iommu_domain &&
4183 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4184 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4185 VMX_EPT_MT_EPTE_SHIFT;
4186 else
4187 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4188 | VMX_EPT_IPAT_BIT;
4189
4190 return ret;
4191 }
4192
4193 #define _ER(x) { EXIT_REASON_##x, #x }
4194
4195 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4196 _ER(EXCEPTION_NMI),
4197 _ER(EXTERNAL_INTERRUPT),
4198 _ER(TRIPLE_FAULT),
4199 _ER(PENDING_INTERRUPT),
4200 _ER(NMI_WINDOW),
4201 _ER(TASK_SWITCH),
4202 _ER(CPUID),
4203 _ER(HLT),
4204 _ER(INVLPG),
4205 _ER(RDPMC),
4206 _ER(RDTSC),
4207 _ER(VMCALL),
4208 _ER(VMCLEAR),
4209 _ER(VMLAUNCH),
4210 _ER(VMPTRLD),
4211 _ER(VMPTRST),
4212 _ER(VMREAD),
4213 _ER(VMRESUME),
4214 _ER(VMWRITE),
4215 _ER(VMOFF),
4216 _ER(VMON),
4217 _ER(CR_ACCESS),
4218 _ER(DR_ACCESS),
4219 _ER(IO_INSTRUCTION),
4220 _ER(MSR_READ),
4221 _ER(MSR_WRITE),
4222 _ER(MWAIT_INSTRUCTION),
4223 _ER(MONITOR_INSTRUCTION),
4224 _ER(PAUSE_INSTRUCTION),
4225 _ER(MCE_DURING_VMENTRY),
4226 _ER(TPR_BELOW_THRESHOLD),
4227 _ER(APIC_ACCESS),
4228 _ER(EPT_VIOLATION),
4229 _ER(EPT_MISCONFIG),
4230 _ER(WBINVD),
4231 { -1, NULL }
4232 };
4233
4234 #undef _ER
4235
4236 static int vmx_get_lpage_level(void)
4237 {
4238 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4239 return PT_DIRECTORY_LEVEL;
4240 else
4241 /* For shadow and EPT supported 1GB page */
4242 return PT_PDPE_LEVEL;
4243 }
4244
4245 static inline u32 bit(int bitno)
4246 {
4247 return 1 << (bitno & 31);
4248 }
4249
4250 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4251 {
4252 struct kvm_cpuid_entry2 *best;
4253 struct vcpu_vmx *vmx = to_vmx(vcpu);
4254 u32 exec_control;
4255
4256 vmx->rdtscp_enabled = false;
4257 if (vmx_rdtscp_supported()) {
4258 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4259 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4260 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4261 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4262 vmx->rdtscp_enabled = true;
4263 else {
4264 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4265 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4266 exec_control);
4267 }
4268 }
4269 }
4270 }
4271
4272 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4273 {
4274 }
4275
4276 static struct kvm_x86_ops vmx_x86_ops = {
4277 .cpu_has_kvm_support = cpu_has_kvm_support,
4278 .disabled_by_bios = vmx_disabled_by_bios,
4279 .hardware_setup = hardware_setup,
4280 .hardware_unsetup = hardware_unsetup,
4281 .check_processor_compatibility = vmx_check_processor_compat,
4282 .hardware_enable = hardware_enable,
4283 .hardware_disable = hardware_disable,
4284 .cpu_has_accelerated_tpr = report_flexpriority,
4285
4286 .vcpu_create = vmx_create_vcpu,
4287 .vcpu_free = vmx_free_vcpu,
4288 .vcpu_reset = vmx_vcpu_reset,
4289
4290 .prepare_guest_switch = vmx_save_host_state,
4291 .vcpu_load = vmx_vcpu_load,
4292 .vcpu_put = vmx_vcpu_put,
4293
4294 .set_guest_debug = set_guest_debug,
4295 .get_msr = vmx_get_msr,
4296 .set_msr = vmx_set_msr,
4297 .get_segment_base = vmx_get_segment_base,
4298 .get_segment = vmx_get_segment,
4299 .set_segment = vmx_set_segment,
4300 .get_cpl = vmx_get_cpl,
4301 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4302 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4303 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4304 .set_cr0 = vmx_set_cr0,
4305 .set_cr3 = vmx_set_cr3,
4306 .set_cr4 = vmx_set_cr4,
4307 .set_efer = vmx_set_efer,
4308 .get_idt = vmx_get_idt,
4309 .set_idt = vmx_set_idt,
4310 .get_gdt = vmx_get_gdt,
4311 .set_gdt = vmx_set_gdt,
4312 .set_dr7 = vmx_set_dr7,
4313 .cache_reg = vmx_cache_reg,
4314 .get_rflags = vmx_get_rflags,
4315 .set_rflags = vmx_set_rflags,
4316 .fpu_activate = vmx_fpu_activate,
4317 .fpu_deactivate = vmx_fpu_deactivate,
4318
4319 .tlb_flush = vmx_flush_tlb,
4320
4321 .run = vmx_vcpu_run,
4322 .handle_exit = vmx_handle_exit,
4323 .skip_emulated_instruction = skip_emulated_instruction,
4324 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4325 .get_interrupt_shadow = vmx_get_interrupt_shadow,
4326 .patch_hypercall = vmx_patch_hypercall,
4327 .set_irq = vmx_inject_irq,
4328 .set_nmi = vmx_inject_nmi,
4329 .queue_exception = vmx_queue_exception,
4330 .interrupt_allowed = vmx_interrupt_allowed,
4331 .nmi_allowed = vmx_nmi_allowed,
4332 .get_nmi_mask = vmx_get_nmi_mask,
4333 .set_nmi_mask = vmx_set_nmi_mask,
4334 .enable_nmi_window = enable_nmi_window,
4335 .enable_irq_window = enable_irq_window,
4336 .update_cr8_intercept = update_cr8_intercept,
4337
4338 .set_tss_addr = vmx_set_tss_addr,
4339 .get_tdp_level = get_ept_level,
4340 .get_mt_mask = vmx_get_mt_mask,
4341
4342 .exit_reasons_str = vmx_exit_reasons_str,
4343 .get_lpage_level = vmx_get_lpage_level,
4344
4345 .cpuid_update = vmx_cpuid_update,
4346
4347 .rdtscp_supported = vmx_rdtscp_supported,
4348
4349 .set_supported_cpuid = vmx_set_supported_cpuid,
4350 };
4351
4352 static int __init vmx_init(void)
4353 {
4354 int r, i;
4355
4356 rdmsrl_safe(MSR_EFER, &host_efer);
4357
4358 for (i = 0; i < NR_VMX_MSR; ++i)
4359 kvm_define_shared_msr(i, vmx_msr_index[i]);
4360
4361 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4362 if (!vmx_io_bitmap_a)
4363 return -ENOMEM;
4364
4365 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4366 if (!vmx_io_bitmap_b) {
4367 r = -ENOMEM;
4368 goto out;
4369 }
4370
4371 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4372 if (!vmx_msr_bitmap_legacy) {
4373 r = -ENOMEM;
4374 goto out1;
4375 }
4376
4377 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4378 if (!vmx_msr_bitmap_longmode) {
4379 r = -ENOMEM;
4380 goto out2;
4381 }
4382
4383 /*
4384 * Allow direct access to the PC debug port (it is often used for I/O
4385 * delays, but the vmexits simply slow things down).
4386 */
4387 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4388 clear_bit(0x80, vmx_io_bitmap_a);
4389
4390 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4391
4392 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4393 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4394
4395 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4396
4397 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4398 __alignof__(struct vcpu_vmx), THIS_MODULE);
4399 if (r)
4400 goto out3;
4401
4402 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4403 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4404 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4405 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4406 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4407 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4408
4409 if (enable_ept) {
4410 bypass_guest_pf = 0;
4411 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4412 VMX_EPT_WRITABLE_MASK);
4413 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4414 VMX_EPT_EXECUTABLE_MASK);
4415 kvm_enable_tdp();
4416 } else
4417 kvm_disable_tdp();
4418
4419 if (bypass_guest_pf)
4420 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4421
4422 return 0;
4423
4424 out3:
4425 free_page((unsigned long)vmx_msr_bitmap_longmode);
4426 out2:
4427 free_page((unsigned long)vmx_msr_bitmap_legacy);
4428 out1:
4429 free_page((unsigned long)vmx_io_bitmap_b);
4430 out:
4431 free_page((unsigned long)vmx_io_bitmap_a);
4432 return r;
4433 }
4434
4435 static void __exit vmx_exit(void)
4436 {
4437 free_page((unsigned long)vmx_msr_bitmap_legacy);
4438 free_page((unsigned long)vmx_msr_bitmap_longmode);
4439 free_page((unsigned long)vmx_io_bitmap_b);
4440 free_page((unsigned long)vmx_io_bitmap_a);
4441
4442 kvm_exit();
4443 }
4444
4445 module_init(vmx_init)
4446 module_exit(vmx_exit)
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