drivers/usb/musb/blackfin.c

   1 /*
   2  * MUSB OTG controller driver for Blackfin Processors
   3  *
   4  * Copyright 2006-2008 Analog Devices Inc.
   5  *
   6  * Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * Licensed under the GPL-2 or later.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/sched.h>
  14 #include <linux/init.h>
  15 #include <linux/list.h>
  16 #include <linux/gpio.h>
  17 #include <linux/io.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/dma-mapping.h>
  20
  21 #include <asm/cacheflush.h>
  22
  23 #include "musb_core.h"
  24 #include "blackfin.h"
  25
  26 struct bfin_glue {
  27         struct device           *dev;
  28         struct platform_device  *musb;
  29 };
  30
  31 /*
  32  * Load an endpoint's FIFO
  33  */
  34 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
  35 {
  36         void __iomem *fifo = hw_ep->fifo;
  37         void __iomem *epio = hw_ep->regs;
  38         u8 epnum = hw_ep->epnum;
  39
  40         prefetch((u8 *)src);
  41
  42         musb_writew(epio, MUSB_TXCOUNT, len);
  43
  44         DBG(4, "TX ep%d fifo %p count %d buf %p, epio %p\n",
  45                         hw_ep->epnum, fifo, len, src, epio);
  46
  47         dump_fifo_data(src, len);
  48
  49         if (!ANOMALY_05000380 && epnum != 0) {
  50                 u16 dma_reg;
  51
  52                 flush_dcache_range((unsigned long)src,
  53                         (unsigned long)(src + len));
  54
  55                 /* Setup DMA address register */
  56                 dma_reg = (u32)src;
  57                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
  58                 SSYNC();
  59
  60                 dma_reg = (u32)src >> 16;
  61                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
  62                 SSYNC();
  63
  64                 /* Setup DMA count register */
  65                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
  66                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
  67                 SSYNC();
  68
  69                 /* Enable the DMA */
  70                 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION;
  71                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
  72                 SSYNC();
  73
  74                 /* Wait for compelete */
  75                 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
  76                         cpu_relax();
  77
  78                 /* acknowledge dma interrupt */
  79                 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
  80                 SSYNC();
  81
  82                 /* Reset DMA */
  83                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
  84                 SSYNC();
  85         } else {
  86                 SSYNC();
  87
  88                 if (unlikely((unsigned long)src & 0x01))
  89                         outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
  90                 else
  91                         outsw((unsigned long)fifo, src, (len + 1) >> 1);
  92         }
  93 }
  94 /*
  95  * Unload an endpoint's FIFO
  96  */
  97 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
  98 {
  99         void __iomem *fifo = hw_ep->fifo;
 100         u8 epnum = hw_ep->epnum;
 101
 102         if (ANOMALY_05000467 && epnum != 0) {
 103                 u16 dma_reg;
 104
 105                 invalidate_dcache_range((unsigned long)dst,
 106                         (unsigned long)(dst + len));
 107
 108                 /* Setup DMA address register */
 109                 dma_reg = (u32)dst;
 110                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
 111                 SSYNC();
 112
 113                 dma_reg = (u32)dst >> 16;
 114                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
 115                 SSYNC();
 116
 117                 /* Setup DMA count register */
 118                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
 119                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
 120                 SSYNC();
 121
 122                 /* Enable the DMA */
 123                 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
 124                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
 125                 SSYNC();
 126
 127                 /* Wait for compelete */
 128                 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
 129                         cpu_relax();
 130
 131                 /* acknowledge dma interrupt */
 132                 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
 133                 SSYNC();
 134
 135                 /* Reset DMA */
 136                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
 137                 SSYNC();
 138         } else {
 139                 SSYNC();
 140                 /* Read the last byte of packet with odd size from address fifo + 4
 141                  * to trigger 1 byte access to EP0 FIFO.
 142                  */
 143                 if (len == 1)
 144                         *dst = (u8)inw((unsigned long)fifo + 4);
 145                 else {
 146                         if (unlikely((unsigned long)dst & 0x01))
 147                                 insw_8((unsigned long)fifo, dst, len >> 1);
 148                         else
 149                                 insw((unsigned long)fifo, dst, len >> 1);
 150
 151                         if (len & 0x01)
 152                                 *(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
 153                 }
 154         }
 155         DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
 156                         'R', hw_ep->epnum, fifo, len, dst);
 157
 158         dump_fifo_data(dst, len);
 159 }
 160
 161 static irqreturn_t blackfin_interrupt(int irq, void *__hci)
 162 {
 163         unsigned long   flags;
 164         irqreturn_t     retval = IRQ_NONE;
 165         struct musb     *musb = __hci;
 166
 167         spin_lock_irqsave(&musb->lock, flags);
 168
 169         musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
 170         musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
 171         musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
 172
 173         if (musb->int_usb || musb->int_tx || musb->int_rx) {
 174                 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
 175                 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
 176                 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
 177                 retval = musb_interrupt(musb);
 178         }
 179
 180         /* Start sampling ID pin, when plug is removed from MUSB */
 181         if (is_otg_enabled(musb) && (musb->xceiv->state == OTG_STATE_B_IDLE
 182                 || musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
 183                 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
 184                 musb->a_wait_bcon = TIMER_DELAY;
 185         }
 186
 187         spin_unlock_irqrestore(&musb->lock, flags);
 188
 189         return retval;
 190 }
 191
 192 static void musb_conn_timer_handler(unsigned long _musb)
 193 {
 194         struct musb *musb = (void *)_musb;
 195         unsigned long flags;
 196         u16 val;
 197         static u8 toggle;
 198
 199         spin_lock_irqsave(&musb->lock, flags);
 200         switch (musb->xceiv->state) {
 201         case OTG_STATE_A_IDLE:
 202         case OTG_STATE_A_WAIT_BCON:
 203                 /* Start a new session */
 204                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
 205                 val &= ~MUSB_DEVCTL_SESSION;
 206                 musb_writew(musb->mregs, MUSB_DEVCTL, val);
 207                 val |= MUSB_DEVCTL_SESSION;
 208                 musb_writew(musb->mregs, MUSB_DEVCTL, val);
 209                 /* Check if musb is host or peripheral. */
 210                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
 211
 212                 if (!(val & MUSB_DEVCTL_BDEVICE)) {
 213                         gpio_set_value(musb->config->gpio_vrsel, 1);
 214                         musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
 215                 } else {
 216                         gpio_set_value(musb->config->gpio_vrsel, 0);
 217                         /* Ignore VBUSERROR and SUSPEND IRQ */
 218                         val = musb_readb(musb->mregs, MUSB_INTRUSBE);
 219                         val &= ~MUSB_INTR_VBUSERROR;
 220                         musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
 221
 222                         val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
 223                         musb_writeb(musb->mregs, MUSB_INTRUSB, val);
 224                         if (is_otg_enabled(musb))
 225                                 musb->xceiv->state = OTG_STATE_B_IDLE;
 226                         else
 227                                 musb_writeb(musb->mregs, MUSB_POWER, MUSB_POWER_HSENAB);
 228                 }
 229                 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
 230                 break;
 231         case OTG_STATE_B_IDLE:
 232
 233                 if (!is_peripheral_enabled(musb))
 234                         break;
 235                 /* Start a new session.  It seems that MUSB needs taking
 236                  * some time to recognize the type of the plug inserted?
 237                  */
 238                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
 239                 val |= MUSB_DEVCTL_SESSION;
 240                 musb_writew(musb->mregs, MUSB_DEVCTL, val);
 241                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
 242
 243                 if (!(val & MUSB_DEVCTL_BDEVICE)) {
 244                         gpio_set_value(musb->config->gpio_vrsel, 1);
 245                         musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
 246                 } else {
 247                         gpio_set_value(musb->config->gpio_vrsel, 0);
 248
 249                         /* Ignore VBUSERROR and SUSPEND IRQ */
 250                         val = musb_readb(musb->mregs, MUSB_INTRUSBE);
 251                         val &= ~MUSB_INTR_VBUSERROR;
 252                         musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
 253
 254                         val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
 255                         musb_writeb(musb->mregs, MUSB_INTRUSB, val);
 256
 257                         /* Toggle the Soft Conn bit, so that we can response to
 258                          * the inserting of either A-plug or B-plug.
 259                          */
 260                         if (toggle) {
 261                                 val = musb_readb(musb->mregs, MUSB_POWER);
 262                                 val &= ~MUSB_POWER_SOFTCONN;
 263                                 musb_writeb(musb->mregs, MUSB_POWER, val);
 264                                 toggle = 0;
 265                         } else {
 266                                 val = musb_readb(musb->mregs, MUSB_POWER);
 267                                 val |= MUSB_POWER_SOFTCONN;
 268                                 musb_writeb(musb->mregs, MUSB_POWER, val);
 269                                 toggle = 1;
 270                         }
 271                         /* The delay time is set to 1/4 second by default,
 272                          * shortening it, if accelerating A-plug detection
 273                          * is needed in OTG mode.
 274                          */
 275                         mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY / 4);
 276                 }
 277                 break;
 278         default:
 279                 DBG(1, "%s state not handled\n", otg_state_string(musb));
 280                 break;
 281         }
 282         spin_unlock_irqrestore(&musb->lock, flags);
 283
 284         DBG(4, "state is %s\n", otg_state_string(musb));
 285 }
 286
 287 static void bfin_musb_enable(struct musb *musb)
 288 {
 289         if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
 290                 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
 291                 musb->a_wait_bcon = TIMER_DELAY;
 292         }
 293 }
 294
 295 static void bfin_musb_disable(struct musb *musb)
 296 {
 297 }
 298
 299 static void bfin_musb_set_vbus(struct musb *musb, int is_on)
 300 {
 301         int value = musb->config->gpio_vrsel_active;
 302         if (!is_on)
 303                 value = !value;
 304         gpio_set_value(musb->config->gpio_vrsel, value);
 305
 306         DBG(1, "VBUS %s, devctl %02x "
 307                 /* otg %3x conf %08x prcm %08x */ "\n",
 308                 otg_state_string(musb),
 309                 musb_readb(musb->mregs, MUSB_DEVCTL));
 310 }
 311
 312 static int bfin_musb_set_power(struct otg_transceiver *x, unsigned mA)
 313 {
 314         return 0;
 315 }
 316
 317 static void bfin_musb_try_idle(struct musb *musb, unsigned long timeout)
 318 {
 319         if (!is_otg_enabled(musb) && is_host_enabled(musb))
 320                 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
 321 }
 322
 323 static int bfin_musb_get_vbus_status(struct musb *musb)
 324 {
 325         return 0;
 326 }
 327
 328 static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
 329 {
 330         return -EIO;
 331 }
 332
 333 static void bfin_musb_reg_init(struct musb *musb)
 334 {
 335         if (ANOMALY_05000346) {
 336                 bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
 337                 SSYNC();
 338         }
 339
 340         if (ANOMALY_05000347) {
 341                 bfin_write_USB_APHY_CNTRL(0x0);
 342                 SSYNC();
 343         }
 344
 345         /* Configure PLL oscillator register */
 346         bfin_write_USB_PLLOSC_CTRL(0x30a8);
 347         SSYNC();
 348
 349         bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
 350         SSYNC();
 351
 352         bfin_write_USB_EP_NI0_RXMAXP(64);
 353         SSYNC();
 354
 355         bfin_write_USB_EP_NI0_TXMAXP(64);
 356         SSYNC();
 357
 358         /* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
 359         bfin_write_USB_GLOBINTR(0x7);
 360         SSYNC();
 361
 362         bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
 363                                 EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
 364                                 EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
 365                                 EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
 366                                 EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
 367         SSYNC();
 368 }
 369
 370 static int bfin_musb_init(struct musb *musb)
 371 {
 372
 373         /*
 374          * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
 375          * and OTG HOST modes, while rev 1.1 and greater require PE7 to
 376          * be low for DEVICE mode and high for HOST mode. We set it high
 377          * here because we are in host mode
 378          */
 379
 380         if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
 381                 printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
 382                         musb->config->gpio_vrsel);
 383                 return -ENODEV;
 384         }
 385         gpio_direction_output(musb->config->gpio_vrsel, 0);
 386
 387         usb_nop_xceiv_register();
 388         musb->xceiv = otg_get_transceiver();
 389         if (!musb->xceiv) {
 390                 gpio_free(musb->config->gpio_vrsel);
 391                 return -ENODEV;
 392         }
 393
 394         bfin_musb_reg_init(musb);
 395
 396         if (is_host_enabled(musb)) {
 397                 musb->board_set_vbus = bfin_musb_set_vbus;
 398                 setup_timer(&musb_conn_timer,
 399                         musb_conn_timer_handler, (unsigned long) musb);
 400         }
 401         if (is_peripheral_enabled(musb))
 402                 musb->xceiv->set_power = bfin_musb_set_power;
 403
 404         musb->isr = blackfin_interrupt;
 405
 406         return 0;
 407 }
 408
 409 static int bfin_musb_suspend(struct musb *musb)
 410 {
 411         if (is_host_active(musb))
 412                 /*
 413                  * During hibernate gpio_vrsel will change from high to low
 414                  * low which will generate wakeup event resume the system
 415                  * immediately.  Set it to 0 before hibernate to avoid this
 416                  * wakeup event.
 417                  */
 418                 gpio_set_value(musb->config->gpio_vrsel, 0);
 419
 420         return 0;
 421 }
 422
 423 static int bfin_musb_resume(struct musb *musb)
 424 {
 425         bfin_musb_reg_init(musb);
 426
 427         return 0;
 428 }
 429
 430 static int bfin_musb_exit(struct musb *musb)
 431 {
 432         gpio_free(musb->config->gpio_vrsel);
 433
 434         otg_put_transceiver(musb->xceiv);
 435         usb_nop_xceiv_unregister();
 436         return 0;
 437 }
 438
 439 static const struct musb_platform_ops bfin_ops = {
 440         .init           = bfin_musb_init,
 441         .exit           = bfin_musb_exit,
 442
 443         .enable         = bfin_musb_enable,
 444         .disable        = bfin_musb_disable,
 445
 446         .set_mode       = bfin_musb_set_mode,
 447         .try_idle       = bfin_musb_try_idle,
 448
 449         .suspend        = bfin_musb_suspend,
 450         .resume         = bfin_musb_resume,
 451
 452         .vbus_status    = bfin_musb_vbus_status,
 453         .set_vbus       = bfin_musb_set_vbus,
 454 };
 455
 456 static u64 bfin_dmamask = DMA_BIT_MASK(32);
 457
 458 static int __init bfin_probe(struct platform_device *pdev)
 459 {
 460         struct musb_hdrc_platform_data  *pdata = pdev->dev.platform_data;
 461         struct platform_device          *musb;
 462         struct bfin_glue                *glue;
 463
 464         int                             ret = -ENOMEM;
 465
 466         glue = kzalloc(sizeof(*glue), GFP_KERNEL);
 467         if (!glue) {
 468                 dev_err(&pdev->dev, "failed to allocate glue context\n");
 469                 goto err0;
 470         }
 471
 472         musb = platform_device_alloc("musb-hdrc", -1);
 473         if (!musb) {
 474                 dev_err(&pdev->dev, "failed to allocate musb device\n");
 475                 goto err1;
 476         }
 477
 478         musb->dev.parent                = &pdev->dev;
 479         musb->dev.dma_mask              = &bfin_dmamask;
 480         musb->dev.coherent_dma_mask     = bfin_dmamask;
 481
 482         glue->dev                       = &pdev->dev;
 483         glue->musb                      = musb;
 484
 485         pdata->platform_ops             = &bfin_ops;
 486
 487         platform_set_drvdata(pdev, glue);
 488
 489         ret = platform_device_add_resources(musb, pdev->resource,
 490                         pdev->num_resources);
 491         if (ret) {
 492                 dev_err(&pdev->dev, "failed to add resources\n");
 493                 goto err2;
 494         }
 495
 496         ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
 497         if (ret) {
 498                 dev_err(&pdev->dev, "failed to add platform_data\n");
 499                 goto err2;
 500         }
 501
 502         ret = platform_device_add(musb);
 503         if (ret) {
 504                 dev_err(&pdev->dev, "failed to register musb device\n");
 505                 goto err2;
 506         }
 507
 508         return 0;
 509
 510 err2:
 511         platform_device_put(musb);
 512
 513 err1:
 514         kfree(glue);
 515
 516 err0:
 517         return ret;
 518 }
 519
 520 static int __exit bfin_remove(struct platform_device *pdev)
 521 {
 522         struct bfin_glue                *glue = platform_get_drvdata(pdev);
 523
 524         platform_device_del(glue->musb);
 525         platform_device_put(glue->musb);
 526         kfree(glue);
 527
 528         return 0;
 529 }
 530
 531 static struct platform_driver bfin_driver = {
 532         .remove         = __exit_p(bfin_remove),
 533         .driver         = {
 534                 .name   = "musb-bfin",
 535         },
 536 };
 537
 538 MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
 539 MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
 540 MODULE_LICENSE("GPL v2");
 541
 542 static int __init bfin_init(void)
 543 {
 544         return platform_driver_probe(&bfin_driver, bfin_probe);
 545 }
 546 subsys_initcall(bfin_init);
 547
 548 static void __exit bfin_exit(void)
 549 {
 550         platform_driver_unregister(&bfin_driver);
 551 }
 552 module_exit(bfin_exit);