drivers/mtd/nand/orion_nand.c

   1 /*
   2  * drivers/mtd/nand/orion_nand.c
   3  *
   4  * NAND support for Marvell Orion SoC platforms
   5  *
   6  * Tzachi Perelstein <tzachi@marvell.com>
   7  *
   8  * This file is licensed under  the terms of the GNU General Public
   9  * License version 2. This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/slab.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/of.h>
  17 #include <linux/mtd/mtd.h>
  18 #include <linux/mtd/nand.h>
  19 #include <linux/mtd/partitions.h>
  20 #include <linux/clk.h>
  21 #include <linux/err.h>
  22 #include <asm/io.h>
  23 #include <asm/sizes.h>
  24 #include <linux/platform_data/mtd-orion_nand.h>
  25
  26 static void orion_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  27 {
  28         struct nand_chip *nc = mtd->priv;
  29         struct orion_nand_data *board = nc->priv;
  30         u32 offs;
  31
  32         if (cmd == NAND_CMD_NONE)
  33                 return;
  34
  35         if (ctrl & NAND_CLE)
  36                 offs = (1 << board->cle);
  37         else if (ctrl & NAND_ALE)
  38                 offs = (1 << board->ale);
  39         else
  40                 return;
  41
  42         if (nc->options & NAND_BUSWIDTH_16)
  43                 offs <<= 1;
  44
  45         writeb(cmd, nc->IO_ADDR_W + offs);
  46 }
  47
  48 static void orion_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  49 {
  50         struct nand_chip *chip = mtd->priv;
  51         void __iomem *io_base = chip->IO_ADDR_R;
  52         uint64_t *buf64;
  53         int i = 0;
  54
  55         while (len && (unsigned long)buf & 7) {
  56                 *buf++ = readb(io_base);
  57                 len--;
  58         }
  59         buf64 = (uint64_t *)buf;
  60         while (i < len/8) {
  61                 /*
  62                  * Since GCC has no proper constraint (PR 43518)
  63                  * force x variable to r2/r3 registers as ldrd instruction
  64                  * requires first register to be even.
  65                  */
  66                 register uint64_t x asm ("r2");
  67
  68                 asm volatile ("ldrd\t%0, [%1]" : "=&r" (x) : "r" (io_base));
  69                 buf64[i++] = x;
  70         }
  71         i *= 8;
  72         while (i < len)
  73                 buf[i++] = readb(io_base);
  74 }
  75
  76 static int __init orion_nand_probe(struct platform_device *pdev)
  77 {
  78         struct mtd_info *mtd;
  79         struct mtd_part_parser_data ppdata = {};
  80         struct nand_chip *nc;
  81         struct orion_nand_data *board;
  82         struct resource *res;
  83         struct clk *clk;
  84         void __iomem *io_base;
  85         int ret = 0;
  86         u32 val = 0;
  87
  88         nc = kzalloc(sizeof(struct nand_chip) + sizeof(struct mtd_info), GFP_KERNEL);
  89         if (!nc) {
  90                 ret = -ENOMEM;
  91                 goto no_res;
  92         }
  93         mtd = (struct mtd_info *)(nc + 1);
  94
  95         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  96         if (!res) {
  97                 ret = -ENODEV;
  98                 goto no_res;
  99         }
 100
 101         io_base = ioremap(res->start, resource_size(res));
 102         if (!io_base) {
 103                 dev_err(&pdev->dev, "ioremap failed\n");
 104                 ret = -EIO;
 105                 goto no_res;
 106         }
 107
 108         if (pdev->dev.of_node) {
 109                 board = devm_kzalloc(&pdev->dev, sizeof(struct orion_nand_data),
 110                                         GFP_KERNEL);
 111                 if (!board) {
 112                         ret = -ENOMEM;
 113                         goto no_res;
 114                 }
 115                 if (!of_property_read_u32(pdev->dev.of_node, "cle", &val))
 116                         board->cle = (u8)val;
 117                 else
 118                         board->cle = 0;
 119                 if (!of_property_read_u32(pdev->dev.of_node, "ale", &val))
 120                         board->ale = (u8)val;
 121                 else
 122                         board->ale = 1;
 123                 if (!of_property_read_u32(pdev->dev.of_node,
 124                                                 "bank-width", &val))
 125                         board->width = (u8)val * 8;
 126                 else
 127                         board->width = 8;
 128                 if (!of_property_read_u32(pdev->dev.of_node,
 129                                                 "chip-delay", &val))
 130                         board->chip_delay = (u8)val;
 131         } else {
 132                 board = dev_get_platdata(&pdev->dev);
 133         }
 134
 135         mtd->priv = nc;
 136         mtd->owner = THIS_MODULE;
 137
 138         nc->priv = board;
 139         nc->IO_ADDR_R = nc->IO_ADDR_W = io_base;
 140         nc->cmd_ctrl = orion_nand_cmd_ctrl;
 141         nc->read_buf = orion_nand_read_buf;
 142         nc->ecc.mode = NAND_ECC_SOFT;
 143
 144         if (board->chip_delay)
 145                 nc->chip_delay = board->chip_delay;
 146
 147         WARN(board->width > 16,
 148                 "%d bit bus width out of range",
 149                 board->width);
 150
 151         if (board->width == 16)
 152                 nc->options |= NAND_BUSWIDTH_16;
 153
 154         if (board->dev_ready)
 155                 nc->dev_ready = board->dev_ready;
 156
 157         platform_set_drvdata(pdev, mtd);
 158
 159         /* Not all platforms can gate the clock, so it is not
 160            an error if the clock does not exists. */
 161         clk = clk_get(&pdev->dev, NULL);
 162         if (!IS_ERR(clk)) {
 163                 clk_prepare_enable(clk);
 164                 clk_put(clk);
 165         }
 166
 167         if (nand_scan(mtd, 1)) {
 168                 ret = -ENXIO;
 169                 goto no_dev;
 170         }
 171
 172         mtd->name = "orion_nand";
 173         ppdata.of_node = pdev->dev.of_node;
 174         ret = mtd_device_parse_register(mtd, NULL, &ppdata,
 175                         board->parts, board->nr_parts);
 176         if (ret) {
 177                 nand_release(mtd);
 178                 goto no_dev;
 179         }
 180
 181         return 0;
 182
 183 no_dev:
 184         if (!IS_ERR(clk)) {
 185                 clk_disable_unprepare(clk);
 186                 clk_put(clk);
 187         }
 188         iounmap(io_base);
 189 no_res:
 190         kfree(nc);
 191
 192         return ret;
 193 }
 194
 195 static int orion_nand_remove(struct platform_device *pdev)
 196 {
 197         struct mtd_info *mtd = platform_get_drvdata(pdev);
 198         struct nand_chip *nc = mtd->priv;
 199         struct clk *clk;
 200
 201         nand_release(mtd);
 202
 203         iounmap(nc->IO_ADDR_W);
 204
 205         kfree(nc);
 206
 207         clk = clk_get(&pdev->dev, NULL);
 208         if (!IS_ERR(clk)) {
 209                 clk_disable_unprepare(clk);
 210                 clk_put(clk);
 211         }
 212
 213         return 0;
 214 }
 215
 216 #ifdef CONFIG_OF
 217 static struct of_device_id orion_nand_of_match_table[] = {
 218         { .compatible = "marvell,orion-nand", },
 219         {},
 220 };
 221 #endif
 222
 223 static struct platform_driver orion_nand_driver = {
 224         .remove         = orion_nand_remove,
 225         .driver         = {
 226                 .name   = "orion_nand",
 227                 .owner  = THIS_MODULE,
 228                 .of_match_table = of_match_ptr(orion_nand_of_match_table),
 229         },
 230 };
 231
 232 module_platform_driver_probe(orion_nand_driver, orion_nand_probe);
 233
 234 MODULE_LICENSE("GPL");
 235 MODULE_AUTHOR("Tzachi Perelstein");
 236 MODULE_DESCRIPTION("NAND glue for Orion platforms");
 237 MODULE_ALIAS("platform:orion_nand");