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r6040: place comments before code
[linux-2.6/btrfs-unstable.git] / drivers / net / ethernet / rdc / r6040.c
blob87aa43935070839e6734b55e5e4d7fc210eea213
1 /*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7 * Florian Fainelli <florian@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23 */
24
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/string.h>
29 #include <linux/timer.h>
30 #include <linux/errno.h>
31 #include <linux/ioport.h>
32 #include <linux/interrupt.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/mii.h>
40 #include <linux/ethtool.h>
41 #include <linux/crc32.h>
42 #include <linux/spinlock.h>
43 #include <linux/bitops.h>
44 #include <linux/io.h>
45 #include <linux/irq.h>
46 #include <linux/uaccess.h>
47 #include <linux/phy.h>
48
49 #include <asm/processor.h>
50
51 #define DRV_NAME "r6040"
52 #define DRV_VERSION "0.28"
53 #define DRV_RELDATE "07Oct2011"
54
55 /* Time in jiffies before concluding the transmitter is hung. */
56 #define TX_TIMEOUT (6000 * HZ / 1000)
57
58 /* RDC MAC I/O Size */
59 #define R6040_IO_SIZE 256
60
61 /* MAX RDC MAC */
62 #define MAX_MAC 2
63
64 /* MAC registers */
65 #define MCR0 0x00 /* Control register 0 */
66 #define MCR0_RCVEN 0x0002 /* Receive enable */
67 #define MCR0_PROMISC 0x0020 /* Promiscuous mode */
68 #define MCR0_HASH_EN 0x0100 /* Enable multicast hash table function */
69 #define MCR0_XMTEN 0x1000 /* Transmission enable */
70 #define MCR0_FD 0x8000 /* Full/Half duplex */
71 #define MCR1 0x04 /* Control register 1 */
72 #define MAC_RST 0x0001 /* Reset the MAC */
73 #define MBCR 0x08 /* Bus control */
74 #define MT_ICR 0x0C /* TX interrupt control */
75 #define MR_ICR 0x10 /* RX interrupt control */
76 #define MTPR 0x14 /* TX poll command register */
77 #define MR_BSR 0x18 /* RX buffer size */
78 #define MR_DCR 0x1A /* RX descriptor control */
79 #define MLSR 0x1C /* Last status */
80 #define MMDIO 0x20 /* MDIO control register */
81 #define MDIO_WRITE 0x4000 /* MDIO write */
82 #define MDIO_READ 0x2000 /* MDIO read */
83 #define MMRD 0x24 /* MDIO read data register */
84 #define MMWD 0x28 /* MDIO write data register */
85 #define MTD_SA0 0x2C /* TX descriptor start address 0 */
86 #define MTD_SA1 0x30 /* TX descriptor start address 1 */
87 #define MRD_SA0 0x34 /* RX descriptor start address 0 */
88 #define MRD_SA1 0x38 /* RX descriptor start address 1 */
89 #define MISR 0x3C /* Status register */
90 #define MIER 0x40 /* INT enable register */
91 #define MSK_INT 0x0000 /* Mask off interrupts */
92 #define RX_FINISH 0x0001 /* RX finished */
93 #define RX_NO_DESC 0x0002 /* No RX descriptor available */
94 #define RX_FIFO_FULL 0x0004 /* RX FIFO full */
95 #define RX_EARLY 0x0008 /* RX early */
96 #define TX_FINISH 0x0010 /* TX finished */
97 #define TX_EARLY 0x0080 /* TX early */
98 #define EVENT_OVRFL 0x0100 /* Event counter overflow */
99 #define LINK_CHANGED 0x0200 /* PHY link changed */
100 #define ME_CISR 0x44 /* Event counter INT status */
101 #define ME_CIER 0x48 /* Event counter INT enable */
102 #define MR_CNT 0x50 /* Successfully received packet counter */
103 #define ME_CNT0 0x52 /* Event counter 0 */
104 #define ME_CNT1 0x54 /* Event counter 1 */
105 #define ME_CNT2 0x56 /* Event counter 2 */
106 #define ME_CNT3 0x58 /* Event counter 3 */
107 #define MT_CNT 0x5A /* Successfully transmit packet counter */
108 #define ME_CNT4 0x5C /* Event counter 4 */
109 #define MP_CNT 0x5E /* Pause frame counter register */
110 #define MAR0 0x60 /* Hash table 0 */
111 #define MAR1 0x62 /* Hash table 1 */
112 #define MAR2 0x64 /* Hash table 2 */
113 #define MAR3 0x66 /* Hash table 3 */
114 #define MID_0L 0x68 /* Multicast address MID0 Low */
115 #define MID_0M 0x6A /* Multicast address MID0 Medium */
116 #define MID_0H 0x6C /* Multicast address MID0 High */
117 #define MID_1L 0x70 /* MID1 Low */
118 #define MID_1M 0x72 /* MID1 Medium */
119 #define MID_1H 0x74 /* MID1 High */
120 #define MID_2L 0x78 /* MID2 Low */
121 #define MID_2M 0x7A /* MID2 Medium */
122 #define MID_2H 0x7C /* MID2 High */
123 #define MID_3L 0x80 /* MID3 Low */
124 #define MID_3M 0x82 /* MID3 Medium */
125 #define MID_3H 0x84 /* MID3 High */
126 #define PHY_CC 0x88 /* PHY status change configuration register */
127 #define PHY_ST 0x8A /* PHY status register */
128 #define MAC_SM 0xAC /* MAC status machine */
129 #define MAC_SM_RST 0x0002 /* MAC status machine reset */
130 #define MAC_ID 0xBE /* Identifier register */
131
132 #define TX_DCNT 0x80 /* TX descriptor count */
133 #define RX_DCNT 0x80 /* RX descriptor count */
134 #define MAX_BUF_SIZE 0x600
135 #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
136 #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
137 #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
138 #define MCAST_MAX 3 /* Max number multicast addresses to filter */
139
140 /* Descriptor status */
141 #define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */
142 #define DSC_RX_OK 0x4000 /* RX was successful */
143 #define DSC_RX_ERR 0x0800 /* RX PHY error */
144 #define DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */
145 #define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */
146 #define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */
147 #define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */
148 #define DSC_RX_ERR_CRC 0x0040 /* RX CRC error */
149 #define DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */
150 #define DSC_RX_MCAST 0x0010 /* RX multicast (no error) */
151 #define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */
152 #define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */
153 #define DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */
154
155 MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
156 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
157 "Florian Fainelli <florian@openwrt.org>");
158 MODULE_LICENSE("GPL");
159 MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
160 MODULE_VERSION(DRV_VERSION " " DRV_RELDATE);
161
162 /* RX and TX interrupts that we handle */
163 #define RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH)
164 #define TX_INTS (TX_FINISH)
165 #define INT_MASK (RX_INTS | TX_INTS)
166
167 struct r6040_descriptor {
168 u16 status, len; /* 0-3 */
169 __le32 buf; /* 4-7 */
170 __le32 ndesc; /* 8-B */
171 u32 rev1; /* C-F */
172 char *vbufp; /* 10-13 */
173 struct r6040_descriptor *vndescp; /* 14-17 */
174 struct sk_buff *skb_ptr; /* 18-1B */
175 u32 rev2; /* 1C-1F */
176 } __aligned(32);
177
178 struct r6040_private {
179 spinlock_t lock; /* driver lock */
180 struct pci_dev *pdev;
181 struct r6040_descriptor *rx_insert_ptr;
182 struct r6040_descriptor *rx_remove_ptr;
183 struct r6040_descriptor *tx_insert_ptr;
184 struct r6040_descriptor *tx_remove_ptr;
185 struct r6040_descriptor *rx_ring;
186 struct r6040_descriptor *tx_ring;
187 dma_addr_t rx_ring_dma;
188 dma_addr_t tx_ring_dma;
189 u16 tx_free_desc;
190 u16 mcr0, mcr1;
191 struct net_device *dev;
192 struct mii_bus *mii_bus;
193 struct napi_struct napi;
194 void __iomem *base;
195 struct phy_device *phydev;
196 int old_link;
197 int old_duplex;
198 };
199
200 static char version[] __devinitdata = DRV_NAME
201 ": RDC R6040 NAPI net driver,"
202 "version "DRV_VERSION " (" DRV_RELDATE ")";
203
204 /* Read a word data from PHY Chip */
205 static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
206 {
207 int limit = 2048;
208 u16 cmd;
209
210 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
211 /* Wait for the read bit to be cleared */
212 while (limit--) {
213 cmd = ioread16(ioaddr + MMDIO);
214 if (!(cmd & MDIO_READ))
215 break;
216 }
217
218 return ioread16(ioaddr + MMRD);
219 }
220
221 /* Write a word data from PHY Chip */
222 static void r6040_phy_write(void __iomem *ioaddr,
223 int phy_addr, int reg, u16 val)
224 {
225 int limit = 2048;
226 u16 cmd;
227
228 iowrite16(val, ioaddr + MMWD);
229 /* Write the command to the MDIO bus */
230 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
231 /* Wait for the write bit to be cleared */
232 while (limit--) {
233 cmd = ioread16(ioaddr + MMDIO);
234 if (!(cmd & MDIO_WRITE))
235 break;
236 }
237 }
238
239 static int r6040_mdiobus_read(struct mii_bus *bus, int phy_addr, int reg)
240 {
241 struct net_device *dev = bus->priv;
242 struct r6040_private *lp = netdev_priv(dev);
243 void __iomem *ioaddr = lp->base;
244
245 return r6040_phy_read(ioaddr, phy_addr, reg);
246 }
247
248 static int r6040_mdiobus_write(struct mii_bus *bus, int phy_addr,
249 int reg, u16 value)
250 {
251 struct net_device *dev = bus->priv;
252 struct r6040_private *lp = netdev_priv(dev);
253 void __iomem *ioaddr = lp->base;
254
255 r6040_phy_write(ioaddr, phy_addr, reg, value);
256
257 return 0;
258 }
259
260 static int r6040_mdiobus_reset(struct mii_bus *bus)
261 {
262 return 0;
263 }
264
265 static void r6040_free_txbufs(struct net_device *dev)
266 {
267 struct r6040_private *lp = netdev_priv(dev);
268 int i;
269
270 for (i = 0; i < TX_DCNT; i++) {
271 if (lp->tx_insert_ptr->skb_ptr) {
272 pci_unmap_single(lp->pdev,
273 le32_to_cpu(lp->tx_insert_ptr->buf),
274 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
275 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
276 lp->tx_insert_ptr->skb_ptr = NULL;
277 }
278 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
279 }
280 }
281
282 static void r6040_free_rxbufs(struct net_device *dev)
283 {
284 struct r6040_private *lp = netdev_priv(dev);
285 int i;
286
287 for (i = 0; i < RX_DCNT; i++) {
288 if (lp->rx_insert_ptr->skb_ptr) {
289 pci_unmap_single(lp->pdev,
290 le32_to_cpu(lp->rx_insert_ptr->buf),
291 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
292 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
293 lp->rx_insert_ptr->skb_ptr = NULL;
294 }
295 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
296 }
297 }
298
299 static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
300 dma_addr_t desc_dma, int size)
301 {
302 struct r6040_descriptor *desc = desc_ring;
303 dma_addr_t mapping = desc_dma;
304
305 while (size-- > 0) {
306 mapping += sizeof(*desc);
307 desc->ndesc = cpu_to_le32(mapping);
308 desc->vndescp = desc + 1;
309 desc++;
310 }
311 desc--;
312 desc->ndesc = cpu_to_le32(desc_dma);
313 desc->vndescp = desc_ring;
314 }
315
316 static void r6040_init_txbufs(struct net_device *dev)
317 {
318 struct r6040_private *lp = netdev_priv(dev);
319
320 lp->tx_free_desc = TX_DCNT;
321
322 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
323 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
324 }
325
326 static int r6040_alloc_rxbufs(struct net_device *dev)
327 {
328 struct r6040_private *lp = netdev_priv(dev);
329 struct r6040_descriptor *desc;
330 struct sk_buff *skb;
331 int rc;
332
333 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
334 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
335
336 /* Allocate skbs for the rx descriptors */
337 desc = lp->rx_ring;
338 do {
339 skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
340 if (!skb) {
341 netdev_err(dev, "failed to alloc skb for rx\n");
342 rc = -ENOMEM;
343 goto err_exit;
344 }
345 desc->skb_ptr = skb;
346 desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
347 desc->skb_ptr->data,
348 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
349 desc->status = DSC_OWNER_MAC;
350 desc = desc->vndescp;
351 } while (desc != lp->rx_ring);
352
353 return 0;
354
355 err_exit:
356 /* Deallocate all previously allocated skbs */
357 r6040_free_rxbufs(dev);
358 return rc;
359 }
360
361 static void r6040_init_mac_regs(struct net_device *dev)
362 {
363 struct r6040_private *lp = netdev_priv(dev);
364 void __iomem *ioaddr = lp->base;
365 int limit = 2048;
366 u16 cmd;
367
368 /* Mask Off Interrupt */
369 iowrite16(MSK_INT, ioaddr + MIER);
370
371 /* Reset RDC MAC */
372 iowrite16(MAC_RST, ioaddr + MCR1);
373 while (limit--) {
374 cmd = ioread16(ioaddr + MCR1);
375 if (cmd & MAC_RST)
376 break;
377 }
378 /* Reset internal state machine */
379 iowrite16(MAC_SM_RST, ioaddr + MAC_SM);
380 iowrite16(0, ioaddr + MAC_SM);
381 mdelay(5);
382
383 /* MAC Bus Control Register */
384 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
385
386 /* Buffer Size Register */
387 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
388
389 /* Write TX ring start address */
390 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
391 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
392
393 /* Write RX ring start address */
394 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
395 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
396
397 /* Set interrupt waiting time and packet numbers */
398 iowrite16(0, ioaddr + MT_ICR);
399 iowrite16(0, ioaddr + MR_ICR);
400
401 /* Enable interrupts */
402 iowrite16(INT_MASK, ioaddr + MIER);
403
404 /* Enable TX and RX */
405 iowrite16(lp->mcr0 | MCR0_RCVEN, ioaddr);
406
407 /* Let TX poll the descriptors
408 * we may got called by r6040_tx_timeout which has left
409 * some unsent tx buffers */
410 iowrite16(0x01, ioaddr + MTPR);
411 }
412
413 static void r6040_tx_timeout(struct net_device *dev)
414 {
415 struct r6040_private *priv = netdev_priv(dev);
416 void __iomem *ioaddr = priv->base;
417
418 netdev_warn(dev, "transmit timed out, int enable %4.4x "
419 "status %4.4x\n",
420 ioread16(ioaddr + MIER),
421 ioread16(ioaddr + MISR));
422
423 dev->stats.tx_errors++;
424
425 /* Reset MAC and re-init all registers */
426 r6040_init_mac_regs(dev);
427 }
428
429 static struct net_device_stats *r6040_get_stats(struct net_device *dev)
430 {
431 struct r6040_private *priv = netdev_priv(dev);
432 void __iomem *ioaddr = priv->base;
433 unsigned long flags;
434
435 spin_lock_irqsave(&priv->lock, flags);
436 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
437 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
438 spin_unlock_irqrestore(&priv->lock, flags);
439
440 return &dev->stats;
441 }
442
443 /* Stop RDC MAC and Free the allocated resource */
444 static void r6040_down(struct net_device *dev)
445 {
446 struct r6040_private *lp = netdev_priv(dev);
447 void __iomem *ioaddr = lp->base;
448 int limit = 2048;
449 u16 *adrp;
450 u16 cmd;
451
452 /* Stop MAC */
453 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
454 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
455 while (limit--) {
456 cmd = ioread16(ioaddr + MCR1);
457 if (cmd & MAC_RST)
458 break;
459 }
460
461 /* Restore MAC Address to MIDx */
462 adrp = (u16 *) dev->dev_addr;
463 iowrite16(adrp[0], ioaddr + MID_0L);
464 iowrite16(adrp[1], ioaddr + MID_0M);
465 iowrite16(adrp[2], ioaddr + MID_0H);
466
467 phy_stop(lp->phydev);
468 }
469
470 static int r6040_close(struct net_device *dev)
471 {
472 struct r6040_private *lp = netdev_priv(dev);
473 struct pci_dev *pdev = lp->pdev;
474
475 spin_lock_irq(&lp->lock);
476 napi_disable(&lp->napi);
477 netif_stop_queue(dev);
478 r6040_down(dev);
479
480 free_irq(dev->irq, dev);
481
482 /* Free RX buffer */
483 r6040_free_rxbufs(dev);
484
485 /* Free TX buffer */
486 r6040_free_txbufs(dev);
487
488 spin_unlock_irq(&lp->lock);
489
490 /* Free Descriptor memory */
491 if (lp->rx_ring) {
492 pci_free_consistent(pdev,
493 RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
494 lp->rx_ring = NULL;
495 }
496
497 if (lp->tx_ring) {
498 pci_free_consistent(pdev,
499 TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
500 lp->tx_ring = NULL;
501 }
502
503 return 0;
504 }
505
506 static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
507 {
508 struct r6040_private *lp = netdev_priv(dev);
509
510 if (!lp->phydev)
511 return -EINVAL;
512
513 return phy_mii_ioctl(lp->phydev, rq, cmd);
514 }
515
516 static int r6040_rx(struct net_device *dev, int limit)
517 {
518 struct r6040_private *priv = netdev_priv(dev);
519 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
520 struct sk_buff *skb_ptr, *new_skb;
521 int count = 0;
522 u16 err;
523
524 /* Limit not reached and the descriptor belongs to the CPU */
525 while (count < limit && !(descptr->status & DSC_OWNER_MAC)) {
526 /* Read the descriptor status */
527 err = descptr->status;
528 /* Global error status set */
529 if (err & DSC_RX_ERR) {
530 /* RX dribble */
531 if (err & DSC_RX_ERR_DRI)
532 dev->stats.rx_frame_errors++;
533 /* Buffer length exceeded */
534 if (err & DSC_RX_ERR_BUF)
535 dev->stats.rx_length_errors++;
536 /* Packet too long */
537 if (err & DSC_RX_ERR_LONG)
538 dev->stats.rx_length_errors++;
539 /* Packet < 64 bytes */
540 if (err & DSC_RX_ERR_RUNT)
541 dev->stats.rx_length_errors++;
542 /* CRC error */
543 if (err & DSC_RX_ERR_CRC) {
544 spin_lock(&priv->lock);
545 dev->stats.rx_crc_errors++;
546 spin_unlock(&priv->lock);
547 }
548 goto next_descr;
549 }
550
551 /* Packet successfully received */
552 new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
553 if (!new_skb) {
554 dev->stats.rx_dropped++;
555 goto next_descr;
556 }
557 skb_ptr = descptr->skb_ptr;
558 skb_ptr->dev = priv->dev;
559
560 /* Do not count the CRC */
561 skb_put(skb_ptr, descptr->len - 4);
562 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
563 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
564 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
565
566 /* Send to upper layer */
567 netif_receive_skb(skb_ptr);
568 dev->stats.rx_packets++;
569 dev->stats.rx_bytes += descptr->len - 4;
570
571 /* put new skb into descriptor */
572 descptr->skb_ptr = new_skb;
573 descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
574 descptr->skb_ptr->data,
575 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
576
577 next_descr:
578 /* put the descriptor back to the MAC */
579 descptr->status = DSC_OWNER_MAC;
580 descptr = descptr->vndescp;
581 count++;
582 }
583 priv->rx_remove_ptr = descptr;
584
585 return count;
586 }
587
588 static void r6040_tx(struct net_device *dev)
589 {
590 struct r6040_private *priv = netdev_priv(dev);
591 struct r6040_descriptor *descptr;
592 void __iomem *ioaddr = priv->base;
593 struct sk_buff *skb_ptr;
594 u16 err;
595
596 spin_lock(&priv->lock);
597 descptr = priv->tx_remove_ptr;
598 while (priv->tx_free_desc < TX_DCNT) {
599 /* Check for errors */
600 err = ioread16(ioaddr + MLSR);
601
602 if (err & 0x0200)
603 dev->stats.rx_fifo_errors++;
604 if (err & (0x2000 | 0x4000))
605 dev->stats.tx_carrier_errors++;
606
607 if (descptr->status & DSC_OWNER_MAC)
608 break; /* Not complete */
609 skb_ptr = descptr->skb_ptr;
610 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
611 skb_ptr->len, PCI_DMA_TODEVICE);
612 /* Free buffer */
613 dev_kfree_skb_irq(skb_ptr);
614 descptr->skb_ptr = NULL;
615 /* To next descriptor */
616 descptr = descptr->vndescp;
617 priv->tx_free_desc++;
618 }
619 priv->tx_remove_ptr = descptr;
620
621 if (priv->tx_free_desc)
622 netif_wake_queue(dev);
623 spin_unlock(&priv->lock);
624 }
625
626 static int r6040_poll(struct napi_struct *napi, int budget)
627 {
628 struct r6040_private *priv =
629 container_of(napi, struct r6040_private, napi);
630 struct net_device *dev = priv->dev;
631 void __iomem *ioaddr = priv->base;
632 int work_done;
633
634 work_done = r6040_rx(dev, budget);
635
636 if (work_done < budget) {
637 napi_complete(napi);
638 /* Enable RX interrupt */
639 iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
640 }
641 return work_done;
642 }
643
644 /* The RDC interrupt handler. */
645 static irqreturn_t r6040_interrupt(int irq, void *dev_id)
646 {
647 struct net_device *dev = dev_id;
648 struct r6040_private *lp = netdev_priv(dev);
649 void __iomem *ioaddr = lp->base;
650 u16 misr, status;
651
652 /* Save MIER */
653 misr = ioread16(ioaddr + MIER);
654 /* Mask off RDC MAC interrupt */
655 iowrite16(MSK_INT, ioaddr + MIER);
656 /* Read MISR status and clear */
657 status = ioread16(ioaddr + MISR);
658
659 if (status == 0x0000 || status == 0xffff) {
660 /* Restore RDC MAC interrupt */
661 iowrite16(misr, ioaddr + MIER);
662 return IRQ_NONE;
663 }
664
665 /* RX interrupt request */
666 if (status & RX_INTS) {
667 if (status & RX_NO_DESC) {
668 /* RX descriptor unavailable */
669 dev->stats.rx_dropped++;
670 dev->stats.rx_missed_errors++;
671 }
672 if (status & RX_FIFO_FULL)
673 dev->stats.rx_fifo_errors++;
674
675 if (likely(napi_schedule_prep(&lp->napi))) {
676 /* Mask off RX interrupt */
677 misr &= ~RX_INTS;
678 __napi_schedule(&lp->napi);
679 }
680 }
681
682 /* TX interrupt request */
683 if (status & TX_INTS)
684 r6040_tx(dev);
685
686 /* Restore RDC MAC interrupt */
687 iowrite16(misr, ioaddr + MIER);
688
689 return IRQ_HANDLED;
690 }
691
692 #ifdef CONFIG_NET_POLL_CONTROLLER
693 static void r6040_poll_controller(struct net_device *dev)
694 {
695 disable_irq(dev->irq);
696 r6040_interrupt(dev->irq, dev);
697 enable_irq(dev->irq);
698 }
699 #endif
700
701 /* Init RDC MAC */
702 static int r6040_up(struct net_device *dev)
703 {
704 struct r6040_private *lp = netdev_priv(dev);
705 void __iomem *ioaddr = lp->base;
706 int ret;
707
708 /* Initialise and alloc RX/TX buffers */
709 r6040_init_txbufs(dev);
710 ret = r6040_alloc_rxbufs(dev);
711 if (ret)
712 return ret;
713
714 /* improve performance (by RDC guys) */
715 r6040_phy_write(ioaddr, 30, 17,
716 (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
717 r6040_phy_write(ioaddr, 30, 17,
718 ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
719 r6040_phy_write(ioaddr, 0, 19, 0x0000);
720 r6040_phy_write(ioaddr, 0, 30, 0x01F0);
721
722 /* Initialize all MAC registers */
723 r6040_init_mac_regs(dev);
724
725 phy_start(lp->phydev);
726
727 return 0;
728 }
729
730
731 /* Read/set MAC address routines */
732 static void r6040_mac_address(struct net_device *dev)
733 {
734 struct r6040_private *lp = netdev_priv(dev);
735 void __iomem *ioaddr = lp->base;
736 u16 *adrp;
737
738 /* Reset MAC */
739 iowrite16(MAC_RST, ioaddr + MCR1);
740 /* Reset internal state machine */
741 iowrite16(MAC_SM_RST, ioaddr + MAC_SM);
742 iowrite16(0, ioaddr + MAC_SM);
743 mdelay(5);
744
745 /* Restore MAC Address */
746 adrp = (u16 *) dev->dev_addr;
747 iowrite16(adrp[0], ioaddr + MID_0L);
748 iowrite16(adrp[1], ioaddr + MID_0M);
749 iowrite16(adrp[2], ioaddr + MID_0H);
750
751 /* Store MAC Address in perm_addr */
752 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
753 }
754
755 static int r6040_open(struct net_device *dev)
756 {
757 struct r6040_private *lp = netdev_priv(dev);
758 int ret;
759
760 /* Request IRQ and Register interrupt handler */
761 ret = request_irq(dev->irq, r6040_interrupt,
762 IRQF_SHARED, dev->name, dev);
763 if (ret)
764 goto out;
765
766 /* Set MAC address */
767 r6040_mac_address(dev);
768
769 /* Allocate Descriptor memory */
770 lp->rx_ring =
771 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
772 if (!lp->rx_ring) {
773 ret = -ENOMEM;
774 goto err_free_irq;
775 }
776
777 lp->tx_ring =
778 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
779 if (!lp->tx_ring) {
780 ret = -ENOMEM;
781 goto err_free_rx_ring;
782 }
783
784 ret = r6040_up(dev);
785 if (ret)
786 goto err_free_tx_ring;
787
788 napi_enable(&lp->napi);
789 netif_start_queue(dev);
790
791 return 0;
792
793 err_free_tx_ring:
794 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
795 lp->tx_ring_dma);
796 err_free_rx_ring:
797 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
798 lp->rx_ring_dma);
799 err_free_irq:
800 free_irq(dev->irq, dev);
801 out:
802 return ret;
803 }
804
805 static netdev_tx_t r6040_start_xmit(struct sk_buff *skb,
806 struct net_device *dev)
807 {
808 struct r6040_private *lp = netdev_priv(dev);
809 struct r6040_descriptor *descptr;
810 void __iomem *ioaddr = lp->base;
811 unsigned long flags;
812
813 /* Critical Section */
814 spin_lock_irqsave(&lp->lock, flags);
815
816 /* TX resource check */
817 if (!lp->tx_free_desc) {
818 spin_unlock_irqrestore(&lp->lock, flags);
819 netif_stop_queue(dev);
820 netdev_err(dev, ": no tx descriptor\n");
821 return NETDEV_TX_BUSY;
822 }
823
824 /* Statistic Counter */
825 dev->stats.tx_packets++;
826 dev->stats.tx_bytes += skb->len;
827 /* Set TX descriptor & Transmit it */
828 lp->tx_free_desc--;
829 descptr = lp->tx_insert_ptr;
830 if (skb->len < MISR)
831 descptr->len = MISR;
832 else
833 descptr->len = skb->len;
834
835 descptr->skb_ptr = skb;
836 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
837 skb->data, skb->len, PCI_DMA_TODEVICE));
838 descptr->status = DSC_OWNER_MAC;
839
840 skb_tx_timestamp(skb);
841
842 /* Trigger the MAC to check the TX descriptor */
843 iowrite16(0x01, ioaddr + MTPR);
844 lp->tx_insert_ptr = descptr->vndescp;
845
846 /* If no tx resource, stop */
847 if (!lp->tx_free_desc)
848 netif_stop_queue(dev);
849
850 spin_unlock_irqrestore(&lp->lock, flags);
851
852 return NETDEV_TX_OK;
853 }
854
855 static void r6040_multicast_list(struct net_device *dev)
856 {
857 struct r6040_private *lp = netdev_priv(dev);
858 void __iomem *ioaddr = lp->base;
859 unsigned long flags;
860 struct netdev_hw_addr *ha;
861 int i;
862 u16 *adrp;
863 u16 hash_table[4] = { 0 };
864
865 spin_lock_irqsave(&lp->lock, flags);
866
867 /* Keep our MAC Address */
868 adrp = (u16 *)dev->dev_addr;
869 iowrite16(adrp[0], ioaddr + MID_0L);
870 iowrite16(adrp[1], ioaddr + MID_0M);
871 iowrite16(adrp[2], ioaddr + MID_0H);
872
873 /* Clear AMCP & PROM bits */
874 lp->mcr0 = ioread16(ioaddr + MCR0) & ~(MCR0_PROMISC | MCR0_HASH_EN);
875
876 /* Promiscuous mode */
877 if (dev->flags & IFF_PROMISC)
878 lp->mcr0 |= MCR0_PROMISC;
879
880 /* Enable multicast hash table function to
881 * receive all multicast packets. */
882 else if (dev->flags & IFF_ALLMULTI) {
883 lp->mcr0 |= MCR0_HASH_EN;
884
885 for (i = 0; i < MCAST_MAX ; i++) {
886 iowrite16(0, ioaddr + MID_1L + 8 * i);
887 iowrite16(0, ioaddr + MID_1M + 8 * i);
888 iowrite16(0, ioaddr + MID_1H + 8 * i);
889 }
890
891 for (i = 0; i < 4; i++)
892 hash_table[i] = 0xffff;
893 }
894 /* Use internal multicast address registers if the number of
895 * multicast addresses is not greater than MCAST_MAX. */
896 else if (netdev_mc_count(dev) <= MCAST_MAX) {
897 i = 0;
898 netdev_for_each_mc_addr(ha, dev) {
899 u16 *adrp = (u16 *) ha->addr;
900 iowrite16(adrp[0], ioaddr + MID_1L + 8 * i);
901 iowrite16(adrp[1], ioaddr + MID_1M + 8 * i);
902 iowrite16(adrp[2], ioaddr + MID_1H + 8 * i);
903 i++;
904 }
905 while (i < MCAST_MAX) {
906 iowrite16(0, ioaddr + MID_1L + 8 * i);
907 iowrite16(0, ioaddr + MID_1M + 8 * i);
908 iowrite16(0, ioaddr + MID_1H + 8 * i);
909 i++;
910 }
911 }
912 /* Otherwise, Enable multicast hash table function. */
913 else {
914 u32 crc;
915
916 lp->mcr0 |= MCR0_HASH_EN;
917
918 for (i = 0; i < MCAST_MAX ; i++) {
919 iowrite16(0, ioaddr + MID_1L + 8 * i);
920 iowrite16(0, ioaddr + MID_1M + 8 * i);
921 iowrite16(0, ioaddr + MID_1H + 8 * i);
922 }
923
924 /* Build multicast hash table */
925 netdev_for_each_mc_addr(ha, dev) {
926 u8 *addrs = ha->addr;
927
928 crc = ether_crc(ETH_ALEN, addrs);
929 crc >>= 26;
930 hash_table[crc >> 4] |= 1 << (crc & 0xf);
931 }
932 }
933
934 iowrite16(lp->mcr0, ioaddr + MCR0);
935
936 /* Fill the MAC hash tables with their values */
937 if (lp->mcr0 & MCR0_HASH_EN) {
938 iowrite16(hash_table[0], ioaddr + MAR0);
939 iowrite16(hash_table[1], ioaddr + MAR1);
940 iowrite16(hash_table[2], ioaddr + MAR2);
941 iowrite16(hash_table[3], ioaddr + MAR3);
942 }
943
944 spin_unlock_irqrestore(&lp->lock, flags);
945 }
946
947 static void netdev_get_drvinfo(struct net_device *dev,
948 struct ethtool_drvinfo *info)
949 {
950 struct r6040_private *rp = netdev_priv(dev);
951
952 strcpy(info->driver, DRV_NAME);
953 strcpy(info->version, DRV_VERSION);
954 strcpy(info->bus_info, pci_name(rp->pdev));
955 }
956
957 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
958 {
959 struct r6040_private *rp = netdev_priv(dev);
960
961 return phy_ethtool_gset(rp->phydev, cmd);
962 }
963
964 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
965 {
966 struct r6040_private *rp = netdev_priv(dev);
967
968 return phy_ethtool_sset(rp->phydev, cmd);
969 }
970
971 static const struct ethtool_ops netdev_ethtool_ops = {
972 .get_drvinfo = netdev_get_drvinfo,
973 .get_settings = netdev_get_settings,
974 .set_settings = netdev_set_settings,
975 .get_link = ethtool_op_get_link,
976 };
977
978 static const struct net_device_ops r6040_netdev_ops = {
979 .ndo_open = r6040_open,
980 .ndo_stop = r6040_close,
981 .ndo_start_xmit = r6040_start_xmit,
982 .ndo_get_stats = r6040_get_stats,
983 .ndo_set_rx_mode = r6040_multicast_list,
984 .ndo_change_mtu = eth_change_mtu,
985 .ndo_validate_addr = eth_validate_addr,
986 .ndo_set_mac_address = eth_mac_addr,
987 .ndo_do_ioctl = r6040_ioctl,
988 .ndo_tx_timeout = r6040_tx_timeout,
989 #ifdef CONFIG_NET_POLL_CONTROLLER
990 .ndo_poll_controller = r6040_poll_controller,
991 #endif
992 };
993
994 static void r6040_adjust_link(struct net_device *dev)
995 {
996 struct r6040_private *lp = netdev_priv(dev);
997 struct phy_device *phydev = lp->phydev;
998 int status_changed = 0;
999 void __iomem *ioaddr = lp->base;
1000
1001 BUG_ON(!phydev);
1002
1003 if (lp->old_link != phydev->link) {
1004 status_changed = 1;
1005 lp->old_link = phydev->link;
1006 }
1007
1008 /* reflect duplex change */
1009 if (phydev->link && (lp->old_duplex != phydev->duplex)) {
1010 lp->mcr0 |= (phydev->duplex == DUPLEX_FULL ? MCR0_FD : 0);
1011 iowrite16(lp->mcr0, ioaddr);
1012
1013 status_changed = 1;
1014 lp->old_duplex = phydev->duplex;
1015 }
1016
1017 if (status_changed) {
1018 pr_info("%s: link %s", dev->name, phydev->link ?
1019 "UP" : "DOWN");
1020 if (phydev->link)
1021 pr_cont(" - %d/%s", phydev->speed,
1022 DUPLEX_FULL == phydev->duplex ? "full" : "half");
1023 pr_cont("\n");
1024 }
1025 }
1026
1027 static int r6040_mii_probe(struct net_device *dev)
1028 {
1029 struct r6040_private *lp = netdev_priv(dev);
1030 struct phy_device *phydev = NULL;
1031
1032 phydev = phy_find_first(lp->mii_bus);
1033 if (!phydev) {
1034 dev_err(&lp->pdev->dev, "no PHY found\n");
1035 return -ENODEV;
1036 }
1037
1038 phydev = phy_connect(dev, dev_name(&phydev->dev), &r6040_adjust_link,
1039 0, PHY_INTERFACE_MODE_MII);
1040
1041 if (IS_ERR(phydev)) {
1042 dev_err(&lp->pdev->dev, "could not attach to PHY\n");
1043 return PTR_ERR(phydev);
1044 }
1045
1046 /* mask with MAC supported features */
1047 phydev->supported &= (SUPPORTED_10baseT_Half
1048 | SUPPORTED_10baseT_Full
1049 | SUPPORTED_100baseT_Half
1050 | SUPPORTED_100baseT_Full
1051 | SUPPORTED_Autoneg
1052 | SUPPORTED_MII
1053 | SUPPORTED_TP);
1054
1055 phydev->advertising = phydev->supported;
1056 lp->phydev = phydev;
1057 lp->old_link = 0;
1058 lp->old_duplex = -1;
1059
1060 dev_info(&lp->pdev->dev, "attached PHY driver [%s] "
1061 "(mii_bus:phy_addr=%s)\n",
1062 phydev->drv->name, dev_name(&phydev->dev));
1063
1064 return 0;
1065 }
1066
1067 static int __devinit r6040_init_one(struct pci_dev *pdev,
1068 const struct pci_device_id *ent)
1069 {
1070 struct net_device *dev;
1071 struct r6040_private *lp;
1072 void __iomem *ioaddr;
1073 int err, io_size = R6040_IO_SIZE;
1074 static int card_idx = -1;
1075 int bar = 0;
1076 u16 *adrp;
1077 int i;
1078
1079 pr_info("%s\n", version);
1080
1081 err = pci_enable_device(pdev);
1082 if (err)
1083 goto err_out;
1084
1085 /* this should always be supported */
1086 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1087 if (err) {
1088 dev_err(&pdev->dev, "32-bit PCI DMA addresses"
1089 "not supported by the card\n");
1090 goto err_out;
1091 }
1092 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1093 if (err) {
1094 dev_err(&pdev->dev, "32-bit PCI DMA addresses"
1095 "not supported by the card\n");
1096 goto err_out;
1097 }
1098
1099 /* IO Size check */
1100 if (pci_resource_len(pdev, bar) < io_size) {
1101 dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n");
1102 err = -EIO;
1103 goto err_out;
1104 }
1105
1106 pci_set_master(pdev);
1107
1108 dev = alloc_etherdev(sizeof(struct r6040_private));
1109 if (!dev) {
1110 dev_err(&pdev->dev, "Failed to allocate etherdev\n");
1111 err = -ENOMEM;
1112 goto err_out;
1113 }
1114 SET_NETDEV_DEV(dev, &pdev->dev);
1115 lp = netdev_priv(dev);
1116
1117 err = pci_request_regions(pdev, DRV_NAME);
1118
1119 if (err) {
1120 dev_err(&pdev->dev, "Failed to request PCI regions\n");
1121 goto err_out_free_dev;
1122 }
1123
1124 ioaddr = pci_iomap(pdev, bar, io_size);
1125 if (!ioaddr) {
1126 dev_err(&pdev->dev, "ioremap failed for device\n");
1127 err = -EIO;
1128 goto err_out_free_res;
1129 }
1130 /* If PHY status change register is still set to zero it means the
1131 * bootloader didn't initialize it */
1132 if (ioread16(ioaddr + PHY_CC) == 0)
1133 iowrite16(0x9f07, ioaddr + PHY_CC);
1134
1135 /* Init system & device */
1136 lp->base = ioaddr;
1137 dev->irq = pdev->irq;
1138
1139 spin_lock_init(&lp->lock);
1140 pci_set_drvdata(pdev, dev);
1141
1142 /* Set MAC address */
1143 card_idx++;
1144
1145 adrp = (u16 *)dev->dev_addr;
1146 adrp[0] = ioread16(ioaddr + MID_0L);
1147 adrp[1] = ioread16(ioaddr + MID_0M);
1148 adrp[2] = ioread16(ioaddr + MID_0H);
1149
1150 /* Some bootloader/BIOSes do not initialize
1151 * MAC address, warn about that */
1152 if (!(adrp[0] || adrp[1] || adrp[2])) {
1153 netdev_warn(dev, "MAC address not initialized, "
1154 "generating random\n");
1155 random_ether_addr(dev->dev_addr);
1156 }
1157
1158 /* Link new device into r6040_root_dev */
1159 lp->pdev = pdev;
1160 lp->dev = dev;
1161
1162 /* Init RDC private data */
1163 lp->mcr0 = MCR0_XMTEN | MCR0;
1164
1165 /* The RDC-specific entries in the device structure. */
1166 dev->netdev_ops = &r6040_netdev_ops;
1167 dev->ethtool_ops = &netdev_ethtool_ops;
1168 dev->watchdog_timeo = TX_TIMEOUT;
1169
1170 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1171
1172 lp->mii_bus = mdiobus_alloc();
1173 if (!lp->mii_bus) {
1174 dev_err(&pdev->dev, "mdiobus_alloc() failed\n");
1175 err = -ENOMEM;
1176 goto err_out_unmap;
1177 }
1178
1179 lp->mii_bus->priv = dev;
1180 lp->mii_bus->read = r6040_mdiobus_read;
1181 lp->mii_bus->write = r6040_mdiobus_write;
1182 lp->mii_bus->reset = r6040_mdiobus_reset;
1183 lp->mii_bus->name = "r6040_eth_mii";
1184 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1185 dev_name(&pdev->dev), card_idx);
1186 lp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1187 if (!lp->mii_bus->irq) {
1188 dev_err(&pdev->dev, "mii_bus irq allocation failed\n");
1189 err = -ENOMEM;
1190 goto err_out_mdio;
1191 }
1192
1193 for (i = 0; i < PHY_MAX_ADDR; i++)
1194 lp->mii_bus->irq[i] = PHY_POLL;
1195
1196 err = mdiobus_register(lp->mii_bus);
1197 if (err) {
1198 dev_err(&pdev->dev, "failed to register MII bus\n");
1199 goto err_out_mdio_irq;
1200 }
1201
1202 err = r6040_mii_probe(dev);
1203 if (err) {
1204 dev_err(&pdev->dev, "failed to probe MII bus\n");
1205 goto err_out_mdio_unregister;
1206 }
1207
1208 /* Register net device. After this dev->name assign */
1209 err = register_netdev(dev);
1210 if (err) {
1211 dev_err(&pdev->dev, "Failed to register net device\n");
1212 goto err_out_mdio_unregister;
1213 }
1214 return 0;
1215
1216 err_out_mdio_unregister:
1217 mdiobus_unregister(lp->mii_bus);
1218 err_out_mdio_irq:
1219 kfree(lp->mii_bus->irq);
1220 err_out_mdio:
1221 mdiobus_free(lp->mii_bus);
1222 err_out_unmap:
1223 pci_iounmap(pdev, ioaddr);
1224 err_out_free_res:
1225 pci_release_regions(pdev);
1226 err_out_free_dev:
1227 free_netdev(dev);
1228 err_out:
1229 return err;
1230 }
1231
1232 static void __devexit r6040_remove_one(struct pci_dev *pdev)
1233 {
1234 struct net_device *dev = pci_get_drvdata(pdev);
1235 struct r6040_private *lp = netdev_priv(dev);
1236
1237 unregister_netdev(dev);
1238 mdiobus_unregister(lp->mii_bus);
1239 kfree(lp->mii_bus->irq);
1240 mdiobus_free(lp->mii_bus);
1241 pci_release_regions(pdev);
1242 free_netdev(dev);
1243 pci_disable_device(pdev);
1244 pci_set_drvdata(pdev, NULL);
1245 }
1246
1247
1248 static DEFINE_PCI_DEVICE_TABLE(r6040_pci_tbl) = {
1249 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1250 { 0 }
1251 };
1252 MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1253
1254 static struct pci_driver r6040_driver = {
1255 .name = DRV_NAME,
1256 .id_table = r6040_pci_tbl,
1257 .probe = r6040_init_one,
1258 .remove = __devexit_p(r6040_remove_one),
1259 };
1260
1261
1262 static int __init r6040_init(void)
1263 {
1264 return pci_register_driver(&r6040_driver);
1265 }
1266
1267
1268 static void __exit r6040_cleanup(void)
1269 {
1270 pci_unregister_driver(&r6040_driver);
1271 }
1272
1273 module_init(r6040_init);
1274 module_exit(r6040_cleanup);
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