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spi: atmel: add support for the internal chip-select of the spi controller
[linux-2.6/btrfs-unstable.git] / drivers / spi / spi-atmel.c
blobaa7d202d6905fab00c2b3383fdbcda500f1fd0e5
1 /*
2 * Driver for Atmel AT32 and AT91 SPI Controllers
3 *
4 * Copyright (C) 2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/dmaengine.h>
18 #include <linux/err.h>
19 #include <linux/interrupt.h>
20 #include <linux/spi/spi.h>
21 #include <linux/slab.h>
22 #include <linux/platform_data/atmel.h>
23 #include <linux/platform_data/dma-atmel.h>
24 #include <linux/of.h>
25
26 #include <linux/io.h>
27 #include <linux/gpio.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/pm_runtime.h>
30
31 /* SPI register offsets */
32 #define SPI_CR 0x0000
33 #define SPI_MR 0x0004
34 #define SPI_RDR 0x0008
35 #define SPI_TDR 0x000c
36 #define SPI_SR 0x0010
37 #define SPI_IER 0x0014
38 #define SPI_IDR 0x0018
39 #define SPI_IMR 0x001c
40 #define SPI_CSR0 0x0030
41 #define SPI_CSR1 0x0034
42 #define SPI_CSR2 0x0038
43 #define SPI_CSR3 0x003c
44 #define SPI_VERSION 0x00fc
45 #define SPI_RPR 0x0100
46 #define SPI_RCR 0x0104
47 #define SPI_TPR 0x0108
48 #define SPI_TCR 0x010c
49 #define SPI_RNPR 0x0110
50 #define SPI_RNCR 0x0114
51 #define SPI_TNPR 0x0118
52 #define SPI_TNCR 0x011c
53 #define SPI_PTCR 0x0120
54 #define SPI_PTSR 0x0124
55
56 /* Bitfields in CR */
57 #define SPI_SPIEN_OFFSET 0
58 #define SPI_SPIEN_SIZE 1
59 #define SPI_SPIDIS_OFFSET 1
60 #define SPI_SPIDIS_SIZE 1
61 #define SPI_SWRST_OFFSET 7
62 #define SPI_SWRST_SIZE 1
63 #define SPI_LASTXFER_OFFSET 24
64 #define SPI_LASTXFER_SIZE 1
65
66 /* Bitfields in MR */
67 #define SPI_MSTR_OFFSET 0
68 #define SPI_MSTR_SIZE 1
69 #define SPI_PS_OFFSET 1
70 #define SPI_PS_SIZE 1
71 #define SPI_PCSDEC_OFFSET 2
72 #define SPI_PCSDEC_SIZE 1
73 #define SPI_FDIV_OFFSET 3
74 #define SPI_FDIV_SIZE 1
75 #define SPI_MODFDIS_OFFSET 4
76 #define SPI_MODFDIS_SIZE 1
77 #define SPI_WDRBT_OFFSET 5
78 #define SPI_WDRBT_SIZE 1
79 #define SPI_LLB_OFFSET 7
80 #define SPI_LLB_SIZE 1
81 #define SPI_PCS_OFFSET 16
82 #define SPI_PCS_SIZE 4
83 #define SPI_DLYBCS_OFFSET 24
84 #define SPI_DLYBCS_SIZE 8
85
86 /* Bitfields in RDR */
87 #define SPI_RD_OFFSET 0
88 #define SPI_RD_SIZE 16
89
90 /* Bitfields in TDR */
91 #define SPI_TD_OFFSET 0
92 #define SPI_TD_SIZE 16
93
94 /* Bitfields in SR */
95 #define SPI_RDRF_OFFSET 0
96 #define SPI_RDRF_SIZE 1
97 #define SPI_TDRE_OFFSET 1
98 #define SPI_TDRE_SIZE 1
99 #define SPI_MODF_OFFSET 2
100 #define SPI_MODF_SIZE 1
101 #define SPI_OVRES_OFFSET 3
102 #define SPI_OVRES_SIZE 1
103 #define SPI_ENDRX_OFFSET 4
104 #define SPI_ENDRX_SIZE 1
105 #define SPI_ENDTX_OFFSET 5
106 #define SPI_ENDTX_SIZE 1
107 #define SPI_RXBUFF_OFFSET 6
108 #define SPI_RXBUFF_SIZE 1
109 #define SPI_TXBUFE_OFFSET 7
110 #define SPI_TXBUFE_SIZE 1
111 #define SPI_NSSR_OFFSET 8
112 #define SPI_NSSR_SIZE 1
113 #define SPI_TXEMPTY_OFFSET 9
114 #define SPI_TXEMPTY_SIZE 1
115 #define SPI_SPIENS_OFFSET 16
116 #define SPI_SPIENS_SIZE 1
117
118 /* Bitfields in CSR0 */
119 #define SPI_CPOL_OFFSET 0
120 #define SPI_CPOL_SIZE 1
121 #define SPI_NCPHA_OFFSET 1
122 #define SPI_NCPHA_SIZE 1
123 #define SPI_CSAAT_OFFSET 3
124 #define SPI_CSAAT_SIZE 1
125 #define SPI_BITS_OFFSET 4
126 #define SPI_BITS_SIZE 4
127 #define SPI_SCBR_OFFSET 8
128 #define SPI_SCBR_SIZE 8
129 #define SPI_DLYBS_OFFSET 16
130 #define SPI_DLYBS_SIZE 8
131 #define SPI_DLYBCT_OFFSET 24
132 #define SPI_DLYBCT_SIZE 8
133
134 /* Bitfields in RCR */
135 #define SPI_RXCTR_OFFSET 0
136 #define SPI_RXCTR_SIZE 16
137
138 /* Bitfields in TCR */
139 #define SPI_TXCTR_OFFSET 0
140 #define SPI_TXCTR_SIZE 16
141
142 /* Bitfields in RNCR */
143 #define SPI_RXNCR_OFFSET 0
144 #define SPI_RXNCR_SIZE 16
145
146 /* Bitfields in TNCR */
147 #define SPI_TXNCR_OFFSET 0
148 #define SPI_TXNCR_SIZE 16
149
150 /* Bitfields in PTCR */
151 #define SPI_RXTEN_OFFSET 0
152 #define SPI_RXTEN_SIZE 1
153 #define SPI_RXTDIS_OFFSET 1
154 #define SPI_RXTDIS_SIZE 1
155 #define SPI_TXTEN_OFFSET 8
156 #define SPI_TXTEN_SIZE 1
157 #define SPI_TXTDIS_OFFSET 9
158 #define SPI_TXTDIS_SIZE 1
159
160 /* Constants for BITS */
161 #define SPI_BITS_8_BPT 0
162 #define SPI_BITS_9_BPT 1
163 #define SPI_BITS_10_BPT 2
164 #define SPI_BITS_11_BPT 3
165 #define SPI_BITS_12_BPT 4
166 #define SPI_BITS_13_BPT 5
167 #define SPI_BITS_14_BPT 6
168 #define SPI_BITS_15_BPT 7
169 #define SPI_BITS_16_BPT 8
170
171 /* Bit manipulation macros */
172 #define SPI_BIT(name) \
173 (1 << SPI_##name##_OFFSET)
174 #define SPI_BF(name, value) \
175 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
176 #define SPI_BFEXT(name, value) \
177 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
178 #define SPI_BFINS(name, value, old) \
179 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
180 | SPI_BF(name, value))
181
182 /* Register access macros */
183 #ifdef CONFIG_AVR32
184 #define spi_readl(port, reg) \
185 __raw_readl((port)->regs + SPI_##reg)
186 #define spi_writel(port, reg, value) \
187 __raw_writel((value), (port)->regs + SPI_##reg)
188 #else
189 #define spi_readl(port, reg) \
190 readl_relaxed((port)->regs + SPI_##reg)
191 #define spi_writel(port, reg, value) \
192 writel_relaxed((value), (port)->regs + SPI_##reg)
193 #endif
194 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
195 * cache operations; better heuristics consider wordsize and bitrate.
196 */
197 #define DMA_MIN_BYTES 16
198
199 #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
200
201 #define AUTOSUSPEND_TIMEOUT 2000
202
203 struct atmel_spi_dma {
204 struct dma_chan *chan_rx;
205 struct dma_chan *chan_tx;
206 struct scatterlist sgrx;
207 struct scatterlist sgtx;
208 struct dma_async_tx_descriptor *data_desc_rx;
209 struct dma_async_tx_descriptor *data_desc_tx;
210
211 struct at_dma_slave dma_slave;
212 };
213
214 struct atmel_spi_caps {
215 bool is_spi2;
216 bool has_wdrbt;
217 bool has_dma_support;
218 };
219
220 /*
221 * The core SPI transfer engine just talks to a register bank to set up
222 * DMA transfers; transfer queue progress is driven by IRQs. The clock
223 * framework provides the base clock, subdivided for each spi_device.
224 */
225 struct atmel_spi {
226 spinlock_t lock;
227 unsigned long flags;
228
229 phys_addr_t phybase;
230 void __iomem *regs;
231 int irq;
232 struct clk *clk;
233 struct platform_device *pdev;
234
235 struct spi_transfer *current_transfer;
236 int current_remaining_bytes;
237 int done_status;
238
239 struct completion xfer_completion;
240
241 /* scratch buffer */
242 void *buffer;
243 dma_addr_t buffer_dma;
244
245 struct atmel_spi_caps caps;
246
247 bool use_dma;
248 bool use_pdc;
249 bool use_cs_gpios;
250 /* dmaengine data */
251 struct atmel_spi_dma dma;
252
253 bool keep_cs;
254 bool cs_active;
255 };
256
257 /* Controller-specific per-slave state */
258 struct atmel_spi_device {
259 unsigned int npcs_pin;
260 u32 csr;
261 };
262
263 #define BUFFER_SIZE PAGE_SIZE
264 #define INVALID_DMA_ADDRESS 0xffffffff
265
266 /*
267 * Version 2 of the SPI controller has
268 * - CR.LASTXFER
269 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
270 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
271 * - SPI_CSRx.CSAAT
272 * - SPI_CSRx.SBCR allows faster clocking
273 */
274 static bool atmel_spi_is_v2(struct atmel_spi *as)
275 {
276 return as->caps.is_spi2;
277 }
278
279 /*
280 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
281 * they assume that spi slave device state will not change on deselect, so
282 * that automagic deselection is OK. ("NPCSx rises if no data is to be
283 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
284 * controllers have CSAAT and friends.
285 *
286 * Since the CSAAT functionality is a bit weird on newer controllers as
287 * well, we use GPIO to control nCSx pins on all controllers, updating
288 * MR.PCS to avoid confusing the controller. Using GPIOs also lets us
289 * support active-high chipselects despite the controller's belief that
290 * only active-low devices/systems exists.
291 *
292 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
293 * right when driven with GPIO. ("Mode Fault does not allow more than one
294 * Master on Chip Select 0.") No workaround exists for that ... so for
295 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
296 * and (c) will trigger that first erratum in some cases.
297 */
298
299 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
300 {
301 struct atmel_spi_device *asd = spi->controller_state;
302 unsigned active = spi->mode & SPI_CS_HIGH;
303 u32 mr;
304
305 if (atmel_spi_is_v2(as)) {
306 spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr);
307 /* For the low SPI version, there is a issue that PDC transfer
308 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
309 */
310 spi_writel(as, CSR0, asd->csr);
311 if (as->caps.has_wdrbt) {
312 spi_writel(as, MR,
313 SPI_BF(PCS, ~(0x01 << spi->chip_select))
314 | SPI_BIT(WDRBT)
315 | SPI_BIT(MODFDIS)
316 | SPI_BIT(MSTR));
317 } else {
318 spi_writel(as, MR,
319 SPI_BF(PCS, ~(0x01 << spi->chip_select))
320 | SPI_BIT(MODFDIS)
321 | SPI_BIT(MSTR));
322 }
323
324 mr = spi_readl(as, MR);
325 if (as->use_cs_gpios)
326 gpio_set_value(asd->npcs_pin, active);
327 } else {
328 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
329 int i;
330 u32 csr;
331
332 /* Make sure clock polarity is correct */
333 for (i = 0; i < spi->master->num_chipselect; i++) {
334 csr = spi_readl(as, CSR0 + 4 * i);
335 if ((csr ^ cpol) & SPI_BIT(CPOL))
336 spi_writel(as, CSR0 + 4 * i,
337 csr ^ SPI_BIT(CPOL));
338 }
339
340 mr = spi_readl(as, MR);
341 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
342 if (as->use_cs_gpios && spi->chip_select != 0)
343 gpio_set_value(asd->npcs_pin, active);
344 spi_writel(as, MR, mr);
345 }
346
347 dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
348 asd->npcs_pin, active ? " (high)" : "",
349 mr);
350 }
351
352 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
353 {
354 struct atmel_spi_device *asd = spi->controller_state;
355 unsigned active = spi->mode & SPI_CS_HIGH;
356 u32 mr;
357
358 /* only deactivate *this* device; sometimes transfers to
359 * another device may be active when this routine is called.
360 */
361 mr = spi_readl(as, MR);
362 if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
363 mr = SPI_BFINS(PCS, 0xf, mr);
364 spi_writel(as, MR, mr);
365 }
366
367 dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
368 asd->npcs_pin, active ? " (low)" : "",
369 mr);
370
371 if (!as->use_cs_gpios)
372 spi_writel(as, CR, SPI_BIT(LASTXFER));
373 else if (atmel_spi_is_v2(as) || spi->chip_select != 0)
374 gpio_set_value(asd->npcs_pin, !active);
375 }
376
377 static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
378 {
379 spin_lock_irqsave(&as->lock, as->flags);
380 }
381
382 static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
383 {
384 spin_unlock_irqrestore(&as->lock, as->flags);
385 }
386
387 static inline bool atmel_spi_use_dma(struct atmel_spi *as,
388 struct spi_transfer *xfer)
389 {
390 return as->use_dma && xfer->len >= DMA_MIN_BYTES;
391 }
392
393 static int atmel_spi_dma_slave_config(struct atmel_spi *as,
394 struct dma_slave_config *slave_config,
395 u8 bits_per_word)
396 {
397 int err = 0;
398
399 if (bits_per_word > 8) {
400 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
401 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
402 } else {
403 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
404 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
405 }
406
407 slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
408 slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
409 slave_config->src_maxburst = 1;
410 slave_config->dst_maxburst = 1;
411 slave_config->device_fc = false;
412
413 slave_config->direction = DMA_MEM_TO_DEV;
414 if (dmaengine_slave_config(as->dma.chan_tx, slave_config)) {
415 dev_err(&as->pdev->dev,
416 "failed to configure tx dma channel\n");
417 err = -EINVAL;
418 }
419
420 slave_config->direction = DMA_DEV_TO_MEM;
421 if (dmaengine_slave_config(as->dma.chan_rx, slave_config)) {
422 dev_err(&as->pdev->dev,
423 "failed to configure rx dma channel\n");
424 err = -EINVAL;
425 }
426
427 return err;
428 }
429
430 static int atmel_spi_configure_dma(struct atmel_spi *as)
431 {
432 struct dma_slave_config slave_config;
433 struct device *dev = &as->pdev->dev;
434 int err;
435
436 dma_cap_mask_t mask;
437 dma_cap_zero(mask);
438 dma_cap_set(DMA_SLAVE, mask);
439
440 as->dma.chan_tx = dma_request_slave_channel_reason(dev, "tx");
441 if (IS_ERR(as->dma.chan_tx)) {
442 err = PTR_ERR(as->dma.chan_tx);
443 if (err == -EPROBE_DEFER) {
444 dev_warn(dev, "no DMA channel available at the moment\n");
445 return err;
446 }
447 dev_err(dev,
448 "DMA TX channel not available, SPI unable to use DMA\n");
449 err = -EBUSY;
450 goto error;
451 }
452
453 /*
454 * No reason to check EPROBE_DEFER here since we have already requested
455 * tx channel. If it fails here, it's for another reason.
456 */
457 as->dma.chan_rx = dma_request_slave_channel(dev, "rx");
458
459 if (!as->dma.chan_rx) {
460 dev_err(dev,
461 "DMA RX channel not available, SPI unable to use DMA\n");
462 err = -EBUSY;
463 goto error;
464 }
465
466 err = atmel_spi_dma_slave_config(as, &slave_config, 8);
467 if (err)
468 goto error;
469
470 dev_info(&as->pdev->dev,
471 "Using %s (tx) and %s (rx) for DMA transfers\n",
472 dma_chan_name(as->dma.chan_tx),
473 dma_chan_name(as->dma.chan_rx));
474 return 0;
475 error:
476 if (as->dma.chan_rx)
477 dma_release_channel(as->dma.chan_rx);
478 if (!IS_ERR(as->dma.chan_tx))
479 dma_release_channel(as->dma.chan_tx);
480 return err;
481 }
482
483 static void atmel_spi_stop_dma(struct atmel_spi *as)
484 {
485 if (as->dma.chan_rx)
486 dmaengine_terminate_all(as->dma.chan_rx);
487 if (as->dma.chan_tx)
488 dmaengine_terminate_all(as->dma.chan_tx);
489 }
490
491 static void atmel_spi_release_dma(struct atmel_spi *as)
492 {
493 if (as->dma.chan_rx)
494 dma_release_channel(as->dma.chan_rx);
495 if (as->dma.chan_tx)
496 dma_release_channel(as->dma.chan_tx);
497 }
498
499 /* This function is called by the DMA driver from tasklet context */
500 static void dma_callback(void *data)
501 {
502 struct spi_master *master = data;
503 struct atmel_spi *as = spi_master_get_devdata(master);
504
505 complete(&as->xfer_completion);
506 }
507
508 /*
509 * Next transfer using PIO.
510 */
511 static void atmel_spi_next_xfer_pio(struct spi_master *master,
512 struct spi_transfer *xfer)
513 {
514 struct atmel_spi *as = spi_master_get_devdata(master);
515 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
516
517 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
518
519 /* Make sure data is not remaining in RDR */
520 spi_readl(as, RDR);
521 while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
522 spi_readl(as, RDR);
523 cpu_relax();
524 }
525
526 if (xfer->tx_buf) {
527 if (xfer->bits_per_word > 8)
528 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
529 else
530 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
531 } else {
532 spi_writel(as, TDR, 0);
533 }
534
535 dev_dbg(master->dev.parent,
536 " start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
537 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
538 xfer->bits_per_word);
539
540 /* Enable relevant interrupts */
541 spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
542 }
543
544 /*
545 * Submit next transfer for DMA.
546 */
547 static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
548 struct spi_transfer *xfer,
549 u32 *plen)
550 {
551 struct atmel_spi *as = spi_master_get_devdata(master);
552 struct dma_chan *rxchan = as->dma.chan_rx;
553 struct dma_chan *txchan = as->dma.chan_tx;
554 struct dma_async_tx_descriptor *rxdesc;
555 struct dma_async_tx_descriptor *txdesc;
556 struct dma_slave_config slave_config;
557 dma_cookie_t cookie;
558 u32 len = *plen;
559
560 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
561
562 /* Check that the channels are available */
563 if (!rxchan || !txchan)
564 return -ENODEV;
565
566 /* release lock for DMA operations */
567 atmel_spi_unlock(as);
568
569 /* prepare the RX dma transfer */
570 sg_init_table(&as->dma.sgrx, 1);
571 if (xfer->rx_buf) {
572 as->dma.sgrx.dma_address = xfer->rx_dma + xfer->len - *plen;
573 } else {
574 as->dma.sgrx.dma_address = as->buffer_dma;
575 if (len > BUFFER_SIZE)
576 len = BUFFER_SIZE;
577 }
578
579 /* prepare the TX dma transfer */
580 sg_init_table(&as->dma.sgtx, 1);
581 if (xfer->tx_buf) {
582 as->dma.sgtx.dma_address = xfer->tx_dma + xfer->len - *plen;
583 } else {
584 as->dma.sgtx.dma_address = as->buffer_dma;
585 if (len > BUFFER_SIZE)
586 len = BUFFER_SIZE;
587 memset(as->buffer, 0, len);
588 }
589
590 sg_dma_len(&as->dma.sgtx) = len;
591 sg_dma_len(&as->dma.sgrx) = len;
592
593 *plen = len;
594
595 if (atmel_spi_dma_slave_config(as, &slave_config, 8))
596 goto err_exit;
597
598 /* Send both scatterlists */
599 rxdesc = dmaengine_prep_slave_sg(rxchan, &as->dma.sgrx, 1,
600 DMA_FROM_DEVICE,
601 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
602 if (!rxdesc)
603 goto err_dma;
604
605 txdesc = dmaengine_prep_slave_sg(txchan, &as->dma.sgtx, 1,
606 DMA_TO_DEVICE,
607 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
608 if (!txdesc)
609 goto err_dma;
610
611 dev_dbg(master->dev.parent,
612 " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
613 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
614 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
615
616 /* Enable relevant interrupts */
617 spi_writel(as, IER, SPI_BIT(OVRES));
618
619 /* Put the callback on the RX transfer only, that should finish last */
620 rxdesc->callback = dma_callback;
621 rxdesc->callback_param = master;
622
623 /* Submit and fire RX and TX with TX last so we're ready to read! */
624 cookie = rxdesc->tx_submit(rxdesc);
625 if (dma_submit_error(cookie))
626 goto err_dma;
627 cookie = txdesc->tx_submit(txdesc);
628 if (dma_submit_error(cookie))
629 goto err_dma;
630 rxchan->device->device_issue_pending(rxchan);
631 txchan->device->device_issue_pending(txchan);
632
633 /* take back lock */
634 atmel_spi_lock(as);
635 return 0;
636
637 err_dma:
638 spi_writel(as, IDR, SPI_BIT(OVRES));
639 atmel_spi_stop_dma(as);
640 err_exit:
641 atmel_spi_lock(as);
642 return -ENOMEM;
643 }
644
645 static void atmel_spi_next_xfer_data(struct spi_master *master,
646 struct spi_transfer *xfer,
647 dma_addr_t *tx_dma,
648 dma_addr_t *rx_dma,
649 u32 *plen)
650 {
651 struct atmel_spi *as = spi_master_get_devdata(master);
652 u32 len = *plen;
653
654 /* use scratch buffer only when rx or tx data is unspecified */
655 if (xfer->rx_buf)
656 *rx_dma = xfer->rx_dma + xfer->len - *plen;
657 else {
658 *rx_dma = as->buffer_dma;
659 if (len > BUFFER_SIZE)
660 len = BUFFER_SIZE;
661 }
662
663 if (xfer->tx_buf)
664 *tx_dma = xfer->tx_dma + xfer->len - *plen;
665 else {
666 *tx_dma = as->buffer_dma;
667 if (len > BUFFER_SIZE)
668 len = BUFFER_SIZE;
669 memset(as->buffer, 0, len);
670 dma_sync_single_for_device(&as->pdev->dev,
671 as->buffer_dma, len, DMA_TO_DEVICE);
672 }
673
674 *plen = len;
675 }
676
677 static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
678 struct spi_device *spi,
679 struct spi_transfer *xfer)
680 {
681 u32 scbr, csr;
682 unsigned long bus_hz;
683
684 /* v1 chips start out at half the peripheral bus speed. */
685 bus_hz = clk_get_rate(as->clk);
686 if (!atmel_spi_is_v2(as))
687 bus_hz /= 2;
688
689 /*
690 * Calculate the lowest divider that satisfies the
691 * constraint, assuming div32/fdiv/mbz == 0.
692 */
693 if (xfer->speed_hz)
694 scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
695 else
696 /*
697 * This can happend if max_speed is null.
698 * In this case, we set the lowest possible speed
699 */
700 scbr = 0xff;
701
702 /*
703 * If the resulting divider doesn't fit into the
704 * register bitfield, we can't satisfy the constraint.
705 */
706 if (scbr >= (1 << SPI_SCBR_SIZE)) {
707 dev_err(&spi->dev,
708 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
709 xfer->speed_hz, scbr, bus_hz/255);
710 return -EINVAL;
711 }
712 if (scbr == 0) {
713 dev_err(&spi->dev,
714 "setup: %d Hz too high, scbr %u; max %ld Hz\n",
715 xfer->speed_hz, scbr, bus_hz);
716 return -EINVAL;
717 }
718 csr = spi_readl(as, CSR0 + 4 * spi->chip_select);
719 csr = SPI_BFINS(SCBR, scbr, csr);
720 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
721
722 return 0;
723 }
724
725 /*
726 * Submit next transfer for PDC.
727 * lock is held, spi irq is blocked
728 */
729 static void atmel_spi_pdc_next_xfer(struct spi_master *master,
730 struct spi_message *msg,
731 struct spi_transfer *xfer)
732 {
733 struct atmel_spi *as = spi_master_get_devdata(master);
734 u32 len;
735 dma_addr_t tx_dma, rx_dma;
736
737 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
738
739 len = as->current_remaining_bytes;
740 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
741 as->current_remaining_bytes -= len;
742
743 spi_writel(as, RPR, rx_dma);
744 spi_writel(as, TPR, tx_dma);
745
746 if (msg->spi->bits_per_word > 8)
747 len >>= 1;
748 spi_writel(as, RCR, len);
749 spi_writel(as, TCR, len);
750
751 dev_dbg(&msg->spi->dev,
752 " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
753 xfer, xfer->len, xfer->tx_buf,
754 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
755 (unsigned long long)xfer->rx_dma);
756
757 if (as->current_remaining_bytes) {
758 len = as->current_remaining_bytes;
759 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
760 as->current_remaining_bytes -= len;
761
762 spi_writel(as, RNPR, rx_dma);
763 spi_writel(as, TNPR, tx_dma);
764
765 if (msg->spi->bits_per_word > 8)
766 len >>= 1;
767 spi_writel(as, RNCR, len);
768 spi_writel(as, TNCR, len);
769
770 dev_dbg(&msg->spi->dev,
771 " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
772 xfer, xfer->len, xfer->tx_buf,
773 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
774 (unsigned long long)xfer->rx_dma);
775 }
776
777 /* REVISIT: We're waiting for RXBUFF before we start the next
778 * transfer because we need to handle some difficult timing
779 * issues otherwise. If we wait for TXBUFE in one transfer and
780 * then starts waiting for RXBUFF in the next, it's difficult
781 * to tell the difference between the RXBUFF interrupt we're
782 * actually waiting for and the RXBUFF interrupt of the
783 * previous transfer.
784 *
785 * It should be doable, though. Just not now...
786 */
787 spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES));
788 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
789 }
790
791 /*
792 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
793 * - The buffer is either valid for CPU access, else NULL
794 * - If the buffer is valid, so is its DMA address
795 *
796 * This driver manages the dma address unless message->is_dma_mapped.
797 */
798 static int
799 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
800 {
801 struct device *dev = &as->pdev->dev;
802
803 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
804 if (xfer->tx_buf) {
805 /* tx_buf is a const void* where we need a void * for the dma
806 * mapping */
807 void *nonconst_tx = (void *)xfer->tx_buf;
808
809 xfer->tx_dma = dma_map_single(dev,
810 nonconst_tx, xfer->len,
811 DMA_TO_DEVICE);
812 if (dma_mapping_error(dev, xfer->tx_dma))
813 return -ENOMEM;
814 }
815 if (xfer->rx_buf) {
816 xfer->rx_dma = dma_map_single(dev,
817 xfer->rx_buf, xfer->len,
818 DMA_FROM_DEVICE);
819 if (dma_mapping_error(dev, xfer->rx_dma)) {
820 if (xfer->tx_buf)
821 dma_unmap_single(dev,
822 xfer->tx_dma, xfer->len,
823 DMA_TO_DEVICE);
824 return -ENOMEM;
825 }
826 }
827 return 0;
828 }
829
830 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
831 struct spi_transfer *xfer)
832 {
833 if (xfer->tx_dma != INVALID_DMA_ADDRESS)
834 dma_unmap_single(master->dev.parent, xfer->tx_dma,
835 xfer->len, DMA_TO_DEVICE);
836 if (xfer->rx_dma != INVALID_DMA_ADDRESS)
837 dma_unmap_single(master->dev.parent, xfer->rx_dma,
838 xfer->len, DMA_FROM_DEVICE);
839 }
840
841 static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
842 {
843 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
844 }
845
846 /* Called from IRQ
847 *
848 * Must update "current_remaining_bytes" to keep track of data
849 * to transfer.
850 */
851 static void
852 atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
853 {
854 u8 *rxp;
855 u16 *rxp16;
856 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
857
858 if (xfer->rx_buf) {
859 if (xfer->bits_per_word > 8) {
860 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
861 *rxp16 = spi_readl(as, RDR);
862 } else {
863 rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
864 *rxp = spi_readl(as, RDR);
865 }
866 } else {
867 spi_readl(as, RDR);
868 }
869 if (xfer->bits_per_word > 8) {
870 if (as->current_remaining_bytes > 2)
871 as->current_remaining_bytes -= 2;
872 else
873 as->current_remaining_bytes = 0;
874 } else {
875 as->current_remaining_bytes--;
876 }
877 }
878
879 /* Interrupt
880 *
881 * No need for locking in this Interrupt handler: done_status is the
882 * only information modified.
883 */
884 static irqreturn_t
885 atmel_spi_pio_interrupt(int irq, void *dev_id)
886 {
887 struct spi_master *master = dev_id;
888 struct atmel_spi *as = spi_master_get_devdata(master);
889 u32 status, pending, imr;
890 struct spi_transfer *xfer;
891 int ret = IRQ_NONE;
892
893 imr = spi_readl(as, IMR);
894 status = spi_readl(as, SR);
895 pending = status & imr;
896
897 if (pending & SPI_BIT(OVRES)) {
898 ret = IRQ_HANDLED;
899 spi_writel(as, IDR, SPI_BIT(OVRES));
900 dev_warn(master->dev.parent, "overrun\n");
901
902 /*
903 * When we get an overrun, we disregard the current
904 * transfer. Data will not be copied back from any
905 * bounce buffer and msg->actual_len will not be
906 * updated with the last xfer.
907 *
908 * We will also not process any remaning transfers in
909 * the message.
910 */
911 as->done_status = -EIO;
912 smp_wmb();
913
914 /* Clear any overrun happening while cleaning up */
915 spi_readl(as, SR);
916
917 complete(&as->xfer_completion);
918
919 } else if (pending & SPI_BIT(RDRF)) {
920 atmel_spi_lock(as);
921
922 if (as->current_remaining_bytes) {
923 ret = IRQ_HANDLED;
924 xfer = as->current_transfer;
925 atmel_spi_pump_pio_data(as, xfer);
926 if (!as->current_remaining_bytes)
927 spi_writel(as, IDR, pending);
928
929 complete(&as->xfer_completion);
930 }
931
932 atmel_spi_unlock(as);
933 } else {
934 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
935 ret = IRQ_HANDLED;
936 spi_writel(as, IDR, pending);
937 }
938
939 return ret;
940 }
941
942 static irqreturn_t
943 atmel_spi_pdc_interrupt(int irq, void *dev_id)
944 {
945 struct spi_master *master = dev_id;
946 struct atmel_spi *as = spi_master_get_devdata(master);
947 u32 status, pending, imr;
948 int ret = IRQ_NONE;
949
950 imr = spi_readl(as, IMR);
951 status = spi_readl(as, SR);
952 pending = status & imr;
953
954 if (pending & SPI_BIT(OVRES)) {
955
956 ret = IRQ_HANDLED;
957
958 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
959 | SPI_BIT(OVRES)));
960
961 /* Clear any overrun happening while cleaning up */
962 spi_readl(as, SR);
963
964 as->done_status = -EIO;
965
966 complete(&as->xfer_completion);
967
968 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
969 ret = IRQ_HANDLED;
970
971 spi_writel(as, IDR, pending);
972
973 complete(&as->xfer_completion);
974 }
975
976 return ret;
977 }
978
979 static int atmel_spi_setup(struct spi_device *spi)
980 {
981 struct atmel_spi *as;
982 struct atmel_spi_device *asd;
983 u32 csr;
984 unsigned int bits = spi->bits_per_word;
985 unsigned int npcs_pin;
986 int ret;
987
988 as = spi_master_get_devdata(spi->master);
989
990 /* see notes above re chipselect */
991 if (!atmel_spi_is_v2(as)
992 && spi->chip_select == 0
993 && (spi->mode & SPI_CS_HIGH)) {
994 dev_dbg(&spi->dev, "setup: can't be active-high\n");
995 return -EINVAL;
996 }
997
998 csr = SPI_BF(BITS, bits - 8);
999 if (spi->mode & SPI_CPOL)
1000 csr |= SPI_BIT(CPOL);
1001 if (!(spi->mode & SPI_CPHA))
1002 csr |= SPI_BIT(NCPHA);
1003 if (!as->use_cs_gpios)
1004 csr |= SPI_BIT(CSAAT);
1005
1006 /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
1007 *
1008 * DLYBCT would add delays between words, slowing down transfers.
1009 * It could potentially be useful to cope with DMA bottlenecks, but
1010 * in those cases it's probably best to just use a lower bitrate.
1011 */
1012 csr |= SPI_BF(DLYBS, 0);
1013 csr |= SPI_BF(DLYBCT, 0);
1014
1015 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
1016 npcs_pin = (unsigned long)spi->controller_data;
1017
1018 if (!as->use_cs_gpios)
1019 npcs_pin = spi->chip_select;
1020 else if (gpio_is_valid(spi->cs_gpio))
1021 npcs_pin = spi->cs_gpio;
1022
1023 asd = spi->controller_state;
1024 if (!asd) {
1025 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1026 if (!asd)
1027 return -ENOMEM;
1028
1029 if (as->use_cs_gpios) {
1030 ret = gpio_request(npcs_pin, dev_name(&spi->dev));
1031 if (ret) {
1032 kfree(asd);
1033 return ret;
1034 }
1035
1036 gpio_direction_output(npcs_pin,
1037 !(spi->mode & SPI_CS_HIGH));
1038 }
1039
1040 asd->npcs_pin = npcs_pin;
1041 spi->controller_state = asd;
1042 }
1043
1044 asd->csr = csr;
1045
1046 dev_dbg(&spi->dev,
1047 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1048 bits, spi->mode, spi->chip_select, csr);
1049
1050 if (!atmel_spi_is_v2(as))
1051 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
1052
1053 return 0;
1054 }
1055
1056 static int atmel_spi_one_transfer(struct spi_master *master,
1057 struct spi_message *msg,
1058 struct spi_transfer *xfer)
1059 {
1060 struct atmel_spi *as;
1061 struct spi_device *spi = msg->spi;
1062 u8 bits;
1063 u32 len;
1064 struct atmel_spi_device *asd;
1065 int timeout;
1066 int ret;
1067 unsigned long dma_timeout;
1068
1069 as = spi_master_get_devdata(master);
1070
1071 if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1072 dev_dbg(&spi->dev, "missing rx or tx buf\n");
1073 return -EINVAL;
1074 }
1075
1076 if (xfer->bits_per_word) {
1077 asd = spi->controller_state;
1078 bits = (asd->csr >> 4) & 0xf;
1079 if (bits != xfer->bits_per_word - 8) {
1080 dev_dbg(&spi->dev,
1081 "you can't yet change bits_per_word in transfers\n");
1082 return -ENOPROTOOPT;
1083 }
1084 }
1085
1086 /*
1087 * DMA map early, for performance (empties dcache ASAP) and
1088 * better fault reporting.
1089 */
1090 if ((!msg->is_dma_mapped)
1091 && (atmel_spi_use_dma(as, xfer) || as->use_pdc)) {
1092 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1093 return -ENOMEM;
1094 }
1095
1096 atmel_spi_set_xfer_speed(as, msg->spi, xfer);
1097
1098 as->done_status = 0;
1099 as->current_transfer = xfer;
1100 as->current_remaining_bytes = xfer->len;
1101 while (as->current_remaining_bytes) {
1102 reinit_completion(&as->xfer_completion);
1103
1104 if (as->use_pdc) {
1105 atmel_spi_pdc_next_xfer(master, msg, xfer);
1106 } else if (atmel_spi_use_dma(as, xfer)) {
1107 len = as->current_remaining_bytes;
1108 ret = atmel_spi_next_xfer_dma_submit(master,
1109 xfer, &len);
1110 if (ret) {
1111 dev_err(&spi->dev,
1112 "unable to use DMA, fallback to PIO\n");
1113 atmel_spi_next_xfer_pio(master, xfer);
1114 } else {
1115 as->current_remaining_bytes -= len;
1116 if (as->current_remaining_bytes < 0)
1117 as->current_remaining_bytes = 0;
1118 }
1119 } else {
1120 atmel_spi_next_xfer_pio(master, xfer);
1121 }
1122
1123 /* interrupts are disabled, so free the lock for schedule */
1124 atmel_spi_unlock(as);
1125 dma_timeout = wait_for_completion_timeout(&as->xfer_completion,
1126 SPI_DMA_TIMEOUT);
1127 atmel_spi_lock(as);
1128 if (WARN_ON(dma_timeout == 0)) {
1129 dev_err(&spi->dev, "spi transfer timeout\n");
1130 as->done_status = -EIO;
1131 }
1132
1133 if (as->done_status)
1134 break;
1135 }
1136
1137 if (as->done_status) {
1138 if (as->use_pdc) {
1139 dev_warn(master->dev.parent,
1140 "overrun (%u/%u remaining)\n",
1141 spi_readl(as, TCR), spi_readl(as, RCR));
1142
1143 /*
1144 * Clean up DMA registers and make sure the data
1145 * registers are empty.
1146 */
1147 spi_writel(as, RNCR, 0);
1148 spi_writel(as, TNCR, 0);
1149 spi_writel(as, RCR, 0);
1150 spi_writel(as, TCR, 0);
1151 for (timeout = 1000; timeout; timeout--)
1152 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1153 break;
1154 if (!timeout)
1155 dev_warn(master->dev.parent,
1156 "timeout waiting for TXEMPTY");
1157 while (spi_readl(as, SR) & SPI_BIT(RDRF))
1158 spi_readl(as, RDR);
1159
1160 /* Clear any overrun happening while cleaning up */
1161 spi_readl(as, SR);
1162
1163 } else if (atmel_spi_use_dma(as, xfer)) {
1164 atmel_spi_stop_dma(as);
1165 }
1166
1167 if (!msg->is_dma_mapped
1168 && (atmel_spi_use_dma(as, xfer) || as->use_pdc))
1169 atmel_spi_dma_unmap_xfer(master, xfer);
1170
1171 return 0;
1172
1173 } else {
1174 /* only update length if no error */
1175 msg->actual_length += xfer->len;
1176 }
1177
1178 if (!msg->is_dma_mapped
1179 && (atmel_spi_use_dma(as, xfer) || as->use_pdc))
1180 atmel_spi_dma_unmap_xfer(master, xfer);
1181
1182 if (xfer->delay_usecs)
1183 udelay(xfer->delay_usecs);
1184
1185 if (xfer->cs_change) {
1186 if (list_is_last(&xfer->transfer_list,
1187 &msg->transfers)) {
1188 as->keep_cs = true;
1189 } else {
1190 as->cs_active = !as->cs_active;
1191 if (as->cs_active)
1192 cs_activate(as, msg->spi);
1193 else
1194 cs_deactivate(as, msg->spi);
1195 }
1196 }
1197
1198 return 0;
1199 }
1200
1201 static int atmel_spi_transfer_one_message(struct spi_master *master,
1202 struct spi_message *msg)
1203 {
1204 struct atmel_spi *as;
1205 struct spi_transfer *xfer;
1206 struct spi_device *spi = msg->spi;
1207 int ret = 0;
1208
1209 as = spi_master_get_devdata(master);
1210
1211 dev_dbg(&spi->dev, "new message %p submitted for %s\n",
1212 msg, dev_name(&spi->dev));
1213
1214 atmel_spi_lock(as);
1215 cs_activate(as, spi);
1216
1217 as->cs_active = true;
1218 as->keep_cs = false;
1219
1220 msg->status = 0;
1221 msg->actual_length = 0;
1222
1223 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1224 ret = atmel_spi_one_transfer(master, msg, xfer);
1225 if (ret)
1226 goto msg_done;
1227 }
1228
1229 if (as->use_pdc)
1230 atmel_spi_disable_pdc_transfer(as);
1231
1232 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1233 dev_dbg(&spi->dev,
1234 " xfer %p: len %u tx %p/%pad rx %p/%pad\n",
1235 xfer, xfer->len,
1236 xfer->tx_buf, &xfer->tx_dma,
1237 xfer->rx_buf, &xfer->rx_dma);
1238 }
1239
1240 msg_done:
1241 if (!as->keep_cs)
1242 cs_deactivate(as, msg->spi);
1243
1244 atmel_spi_unlock(as);
1245
1246 msg->status = as->done_status;
1247 spi_finalize_current_message(spi->master);
1248
1249 return ret;
1250 }
1251
1252 static void atmel_spi_cleanup(struct spi_device *spi)
1253 {
1254 struct atmel_spi_device *asd = spi->controller_state;
1255 unsigned gpio = (unsigned long) spi->controller_data;
1256
1257 if (!asd)
1258 return;
1259
1260 spi->controller_state = NULL;
1261 gpio_free(gpio);
1262 kfree(asd);
1263 }
1264
1265 static inline unsigned int atmel_get_version(struct atmel_spi *as)
1266 {
1267 return spi_readl(as, VERSION) & 0x00000fff;
1268 }
1269
1270 static void atmel_get_caps(struct atmel_spi *as)
1271 {
1272 unsigned int version;
1273
1274 version = atmel_get_version(as);
1275 dev_info(&as->pdev->dev, "version: 0x%x\n", version);
1276
1277 as->caps.is_spi2 = version > 0x121;
1278 as->caps.has_wdrbt = version >= 0x210;
1279 as->caps.has_dma_support = version >= 0x212;
1280 }
1281
1282 /*-------------------------------------------------------------------------*/
1283
1284 static int atmel_spi_probe(struct platform_device *pdev)
1285 {
1286 struct resource *regs;
1287 int irq;
1288 struct clk *clk;
1289 int ret;
1290 struct spi_master *master;
1291 struct atmel_spi *as;
1292
1293 /* Select default pin state */
1294 pinctrl_pm_select_default_state(&pdev->dev);
1295
1296 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1297 if (!regs)
1298 return -ENXIO;
1299
1300 irq = platform_get_irq(pdev, 0);
1301 if (irq < 0)
1302 return irq;
1303
1304 clk = devm_clk_get(&pdev->dev, "spi_clk");
1305 if (IS_ERR(clk))
1306 return PTR_ERR(clk);
1307
1308 /* setup spi core then atmel-specific driver state */
1309 ret = -ENOMEM;
1310 master = spi_alloc_master(&pdev->dev, sizeof(*as));
1311 if (!master)
1312 goto out_free;
1313
1314 /* the spi->mode bits understood by this driver: */
1315 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1316 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
1317 master->dev.of_node = pdev->dev.of_node;
1318 master->bus_num = pdev->id;
1319 master->num_chipselect = master->dev.of_node ? 0 : 4;
1320 master->setup = atmel_spi_setup;
1321 master->transfer_one_message = atmel_spi_transfer_one_message;
1322 master->cleanup = atmel_spi_cleanup;
1323 master->auto_runtime_pm = true;
1324 platform_set_drvdata(pdev, master);
1325
1326 as = spi_master_get_devdata(master);
1327
1328 /*
1329 * Scratch buffer is used for throwaway rx and tx data.
1330 * It's coherent to minimize dcache pollution.
1331 */
1332 as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
1333 &as->buffer_dma, GFP_KERNEL);
1334 if (!as->buffer)
1335 goto out_free;
1336
1337 spin_lock_init(&as->lock);
1338
1339 as->pdev = pdev;
1340 as->regs = devm_ioremap_resource(&pdev->dev, regs);
1341 if (IS_ERR(as->regs)) {
1342 ret = PTR_ERR(as->regs);
1343 goto out_free_buffer;
1344 }
1345 as->phybase = regs->start;
1346 as->irq = irq;
1347 as->clk = clk;
1348
1349 init_completion(&as->xfer_completion);
1350
1351 atmel_get_caps(as);
1352
1353 as->use_cs_gpios = true;
1354 if (atmel_spi_is_v2(as) &&
1355 !of_get_property(pdev->dev.of_node, "cs-gpios", NULL)) {
1356 as->use_cs_gpios = false;
1357 master->num_chipselect = 4;
1358 }
1359
1360 as->use_dma = false;
1361 as->use_pdc = false;
1362 if (as->caps.has_dma_support) {
1363 ret = atmel_spi_configure_dma(as);
1364 if (ret == 0)
1365 as->use_dma = true;
1366 else if (ret == -EPROBE_DEFER)
1367 return ret;
1368 } else {
1369 as->use_pdc = true;
1370 }
1371
1372 if (as->caps.has_dma_support && !as->use_dma)
1373 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1374
1375 if (as->use_pdc) {
1376 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1377 0, dev_name(&pdev->dev), master);
1378 } else {
1379 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1380 0, dev_name(&pdev->dev), master);
1381 }
1382 if (ret)
1383 goto out_unmap_regs;
1384
1385 /* Initialize the hardware */
1386 ret = clk_prepare_enable(clk);
1387 if (ret)
1388 goto out_free_irq;
1389 spi_writel(as, CR, SPI_BIT(SWRST));
1390 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1391 if (as->caps.has_wdrbt) {
1392 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1393 | SPI_BIT(MSTR));
1394 } else {
1395 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1396 }
1397
1398 if (as->use_pdc)
1399 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1400 spi_writel(as, CR, SPI_BIT(SPIEN));
1401
1402 /* go! */
1403 dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
1404 (unsigned long)regs->start, irq);
1405
1406 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1407 pm_runtime_use_autosuspend(&pdev->dev);
1408 pm_runtime_set_active(&pdev->dev);
1409 pm_runtime_enable(&pdev->dev);
1410
1411 ret = devm_spi_register_master(&pdev->dev, master);
1412 if (ret)
1413 goto out_free_dma;
1414
1415 return 0;
1416
1417 out_free_dma:
1418 pm_runtime_disable(&pdev->dev);
1419 pm_runtime_set_suspended(&pdev->dev);
1420
1421 if (as->use_dma)
1422 atmel_spi_release_dma(as);
1423
1424 spi_writel(as, CR, SPI_BIT(SWRST));
1425 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1426 clk_disable_unprepare(clk);
1427 out_free_irq:
1428 out_unmap_regs:
1429 out_free_buffer:
1430 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1431 as->buffer_dma);
1432 out_free:
1433 spi_master_put(master);
1434 return ret;
1435 }
1436
1437 static int atmel_spi_remove(struct platform_device *pdev)
1438 {
1439 struct spi_master *master = platform_get_drvdata(pdev);
1440 struct atmel_spi *as = spi_master_get_devdata(master);
1441
1442 pm_runtime_get_sync(&pdev->dev);
1443
1444 /* reset the hardware and block queue progress */
1445 spin_lock_irq(&as->lock);
1446 if (as->use_dma) {
1447 atmel_spi_stop_dma(as);
1448 atmel_spi_release_dma(as);
1449 }
1450
1451 spi_writel(as, CR, SPI_BIT(SWRST));
1452 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1453 spi_readl(as, SR);
1454 spin_unlock_irq(&as->lock);
1455
1456 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1457 as->buffer_dma);
1458
1459 clk_disable_unprepare(as->clk);
1460
1461 pm_runtime_put_noidle(&pdev->dev);
1462 pm_runtime_disable(&pdev->dev);
1463
1464 return 0;
1465 }
1466
1467 #ifdef CONFIG_PM
1468 static int atmel_spi_runtime_suspend(struct device *dev)
1469 {
1470 struct spi_master *master = dev_get_drvdata(dev);
1471 struct atmel_spi *as = spi_master_get_devdata(master);
1472
1473 clk_disable_unprepare(as->clk);
1474 pinctrl_pm_select_sleep_state(dev);
1475
1476 return 0;
1477 }
1478
1479 static int atmel_spi_runtime_resume(struct device *dev)
1480 {
1481 struct spi_master *master = dev_get_drvdata(dev);
1482 struct atmel_spi *as = spi_master_get_devdata(master);
1483
1484 pinctrl_pm_select_default_state(dev);
1485
1486 return clk_prepare_enable(as->clk);
1487 }
1488
1489 static int atmel_spi_suspend(struct device *dev)
1490 {
1491 struct spi_master *master = dev_get_drvdata(dev);
1492 int ret;
1493
1494 /* Stop the queue running */
1495 ret = spi_master_suspend(master);
1496 if (ret) {
1497 dev_warn(dev, "cannot suspend master\n");
1498 return ret;
1499 }
1500
1501 if (!pm_runtime_suspended(dev))
1502 atmel_spi_runtime_suspend(dev);
1503
1504 return 0;
1505 }
1506
1507 static int atmel_spi_resume(struct device *dev)
1508 {
1509 struct spi_master *master = dev_get_drvdata(dev);
1510 int ret;
1511
1512 if (!pm_runtime_suspended(dev)) {
1513 ret = atmel_spi_runtime_resume(dev);
1514 if (ret)
1515 return ret;
1516 }
1517
1518 /* Start the queue running */
1519 ret = spi_master_resume(master);
1520 if (ret)
1521 dev_err(dev, "problem starting queue (%d)\n", ret);
1522
1523 return ret;
1524 }
1525
1526 static const struct dev_pm_ops atmel_spi_pm_ops = {
1527 SET_SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume)
1528 SET_RUNTIME_PM_OPS(atmel_spi_runtime_suspend,
1529 atmel_spi_runtime_resume, NULL)
1530 };
1531 #define ATMEL_SPI_PM_OPS (&atmel_spi_pm_ops)
1532 #else
1533 #define ATMEL_SPI_PM_OPS NULL
1534 #endif
1535
1536 #if defined(CONFIG_OF)
1537 static const struct of_device_id atmel_spi_dt_ids[] = {
1538 { .compatible = "atmel,at91rm9200-spi" },
1539 { /* sentinel */ }
1540 };
1541
1542 MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1543 #endif
1544
1545 static struct platform_driver atmel_spi_driver = {
1546 .driver = {
1547 .name = "atmel_spi",
1548 .pm = ATMEL_SPI_PM_OPS,
1549 .of_match_table = of_match_ptr(atmel_spi_dt_ids),
1550 },
1551 .probe = atmel_spi_probe,
1552 .remove = atmel_spi_remove,
1553 };
1554 module_platform_driver(atmel_spi_driver);
1555
1556 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1557 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1558 MODULE_LICENSE("GPL");
1559 MODULE_ALIAS("platform:atmel_spi");
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