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amd-iommu: don't free dma adresses below 512MB with CONFIG_IOMMU_STRESS
[linux-2.6/btrfs-unstable.git] / arch / x86 / kernel / amd_iommu.c
blob04ff5ec4ac0ed7f897111e876a0593556fdfcb2e
1 /*
2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
30 #include <asm/gart.h>
31 #include <asm/amd_iommu_types.h>
32 #include <asm/amd_iommu.h>
33
34 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
35
36 #define EXIT_LOOP_COUNT 10000000
37
38 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
39
40 /* A list of preallocated protection domains */
41 static LIST_HEAD(iommu_pd_list);
42 static DEFINE_SPINLOCK(iommu_pd_list_lock);
43
44 #ifdef CONFIG_IOMMU_API
45 static struct iommu_ops amd_iommu_ops;
46 #endif
47
48 /*
49 * general struct to manage commands send to an IOMMU
50 */
51 struct iommu_cmd {
52 u32 data[4];
53 };
54
55 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
56 struct unity_map_entry *e);
57 static struct dma_ops_domain *find_protection_domain(u16 devid);
58 static u64* alloc_pte(struct protection_domain *dom,
59 unsigned long address, u64
60 **pte_page, gfp_t gfp);
61 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
62 unsigned long start_page,
63 unsigned int pages);
64
65 #ifdef CONFIG_AMD_IOMMU_STATS
66
67 /*
68 * Initialization code for statistics collection
69 */
70
71 DECLARE_STATS_COUNTER(compl_wait);
72 DECLARE_STATS_COUNTER(cnt_map_single);
73 DECLARE_STATS_COUNTER(cnt_unmap_single);
74 DECLARE_STATS_COUNTER(cnt_map_sg);
75 DECLARE_STATS_COUNTER(cnt_unmap_sg);
76 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
77 DECLARE_STATS_COUNTER(cnt_free_coherent);
78 DECLARE_STATS_COUNTER(cross_page);
79 DECLARE_STATS_COUNTER(domain_flush_single);
80 DECLARE_STATS_COUNTER(domain_flush_all);
81 DECLARE_STATS_COUNTER(alloced_io_mem);
82 DECLARE_STATS_COUNTER(total_map_requests);
83
84 static struct dentry *stats_dir;
85 static struct dentry *de_isolate;
86 static struct dentry *de_fflush;
87
88 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
89 {
90 if (stats_dir == NULL)
91 return;
92
93 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
94 &cnt->value);
95 }
96
97 static void amd_iommu_stats_init(void)
98 {
99 stats_dir = debugfs_create_dir("amd-iommu", NULL);
100 if (stats_dir == NULL)
101 return;
102
103 de_isolate = debugfs_create_bool("isolation", 0444, stats_dir,
104 (u32 *)&amd_iommu_isolate);
105
106 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
107 (u32 *)&amd_iommu_unmap_flush);
108
109 amd_iommu_stats_add(&compl_wait);
110 amd_iommu_stats_add(&cnt_map_single);
111 amd_iommu_stats_add(&cnt_unmap_single);
112 amd_iommu_stats_add(&cnt_map_sg);
113 amd_iommu_stats_add(&cnt_unmap_sg);
114 amd_iommu_stats_add(&cnt_alloc_coherent);
115 amd_iommu_stats_add(&cnt_free_coherent);
116 amd_iommu_stats_add(&cross_page);
117 amd_iommu_stats_add(&domain_flush_single);
118 amd_iommu_stats_add(&domain_flush_all);
119 amd_iommu_stats_add(&alloced_io_mem);
120 amd_iommu_stats_add(&total_map_requests);
121 }
122
123 #endif
124
125 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
126 static int iommu_has_npcache(struct amd_iommu *iommu)
127 {
128 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
129 }
130
131 /****************************************************************************
132 *
133 * Interrupt handling functions
134 *
135 ****************************************************************************/
136
137 static void iommu_print_event(void *__evt)
138 {
139 u32 *event = __evt;
140 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
141 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
142 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
143 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
144 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
145
146 printk(KERN_ERR "AMD IOMMU: Event logged [");
147
148 switch (type) {
149 case EVENT_TYPE_ILL_DEV:
150 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
151 "address=0x%016llx flags=0x%04x]\n",
152 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
153 address, flags);
154 break;
155 case EVENT_TYPE_IO_FAULT:
156 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
157 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
158 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
159 domid, address, flags);
160 break;
161 case EVENT_TYPE_DEV_TAB_ERR:
162 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
163 "address=0x%016llx flags=0x%04x]\n",
164 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
165 address, flags);
166 break;
167 case EVENT_TYPE_PAGE_TAB_ERR:
168 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
169 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
170 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
171 domid, address, flags);
172 break;
173 case EVENT_TYPE_ILL_CMD:
174 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
175 break;
176 case EVENT_TYPE_CMD_HARD_ERR:
177 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
178 "flags=0x%04x]\n", address, flags);
179 break;
180 case EVENT_TYPE_IOTLB_INV_TO:
181 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
182 "address=0x%016llx]\n",
183 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
184 address);
185 break;
186 case EVENT_TYPE_INV_DEV_REQ:
187 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
188 "address=0x%016llx flags=0x%04x]\n",
189 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
190 address, flags);
191 break;
192 default:
193 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
194 }
195 }
196
197 static void iommu_poll_events(struct amd_iommu *iommu)
198 {
199 u32 head, tail;
200 unsigned long flags;
201
202 spin_lock_irqsave(&iommu->lock, flags);
203
204 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
205 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
206
207 while (head != tail) {
208 iommu_print_event(iommu->evt_buf + head);
209 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
210 }
211
212 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
213
214 spin_unlock_irqrestore(&iommu->lock, flags);
215 }
216
217 irqreturn_t amd_iommu_int_handler(int irq, void *data)
218 {
219 struct amd_iommu *iommu;
220
221 list_for_each_entry(iommu, &amd_iommu_list, list)
222 iommu_poll_events(iommu);
223
224 return IRQ_HANDLED;
225 }
226
227 /****************************************************************************
228 *
229 * IOMMU command queuing functions
230 *
231 ****************************************************************************/
232
233 /*
234 * Writes the command to the IOMMUs command buffer and informs the
235 * hardware about the new command. Must be called with iommu->lock held.
236 */
237 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
238 {
239 u32 tail, head;
240 u8 *target;
241
242 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
243 target = iommu->cmd_buf + tail;
244 memcpy_toio(target, cmd, sizeof(*cmd));
245 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
246 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
247 if (tail == head)
248 return -ENOMEM;
249 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
250
251 return 0;
252 }
253
254 /*
255 * General queuing function for commands. Takes iommu->lock and calls
256 * __iommu_queue_command().
257 */
258 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
259 {
260 unsigned long flags;
261 int ret;
262
263 spin_lock_irqsave(&iommu->lock, flags);
264 ret = __iommu_queue_command(iommu, cmd);
265 if (!ret)
266 iommu->need_sync = true;
267 spin_unlock_irqrestore(&iommu->lock, flags);
268
269 return ret;
270 }
271
272 /*
273 * This function waits until an IOMMU has completed a completion
274 * wait command
275 */
276 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
277 {
278 int ready = 0;
279 unsigned status = 0;
280 unsigned long i = 0;
281
282 INC_STATS_COUNTER(compl_wait);
283
284 while (!ready && (i < EXIT_LOOP_COUNT)) {
285 ++i;
286 /* wait for the bit to become one */
287 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
288 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
289 }
290
291 /* set bit back to zero */
292 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
293 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
294
295 if (unlikely(i == EXIT_LOOP_COUNT))
296 panic("AMD IOMMU: Completion wait loop failed\n");
297 }
298
299 /*
300 * This function queues a completion wait command into the command
301 * buffer of an IOMMU
302 */
303 static int __iommu_completion_wait(struct amd_iommu *iommu)
304 {
305 struct iommu_cmd cmd;
306
307 memset(&cmd, 0, sizeof(cmd));
308 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
309 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
310
311 return __iommu_queue_command(iommu, &cmd);
312 }
313
314 /*
315 * This function is called whenever we need to ensure that the IOMMU has
316 * completed execution of all commands we sent. It sends a
317 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
318 * us about that by writing a value to a physical address we pass with
319 * the command.
320 */
321 static int iommu_completion_wait(struct amd_iommu *iommu)
322 {
323 int ret = 0;
324 unsigned long flags;
325
326 spin_lock_irqsave(&iommu->lock, flags);
327
328 if (!iommu->need_sync)
329 goto out;
330
331 ret = __iommu_completion_wait(iommu);
332
333 iommu->need_sync = false;
334
335 if (ret)
336 goto out;
337
338 __iommu_wait_for_completion(iommu);
339
340 out:
341 spin_unlock_irqrestore(&iommu->lock, flags);
342
343 return 0;
344 }
345
346 /*
347 * Command send function for invalidating a device table entry
348 */
349 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
350 {
351 struct iommu_cmd cmd;
352 int ret;
353
354 BUG_ON(iommu == NULL);
355
356 memset(&cmd, 0, sizeof(cmd));
357 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
358 cmd.data[0] = devid;
359
360 ret = iommu_queue_command(iommu, &cmd);
361
362 return ret;
363 }
364
365 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
366 u16 domid, int pde, int s)
367 {
368 memset(cmd, 0, sizeof(*cmd));
369 address &= PAGE_MASK;
370 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
371 cmd->data[1] |= domid;
372 cmd->data[2] = lower_32_bits(address);
373 cmd->data[3] = upper_32_bits(address);
374 if (s) /* size bit - we flush more than one 4kb page */
375 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
376 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
377 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
378 }
379
380 /*
381 * Generic command send function for invalidaing TLB entries
382 */
383 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
384 u64 address, u16 domid, int pde, int s)
385 {
386 struct iommu_cmd cmd;
387 int ret;
388
389 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
390
391 ret = iommu_queue_command(iommu, &cmd);
392
393 return ret;
394 }
395
396 /*
397 * TLB invalidation function which is called from the mapping functions.
398 * It invalidates a single PTE if the range to flush is within a single
399 * page. Otherwise it flushes the whole TLB of the IOMMU.
400 */
401 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
402 u64 address, size_t size)
403 {
404 int s = 0;
405 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
406
407 address &= PAGE_MASK;
408
409 if (pages > 1) {
410 /*
411 * If we have to flush more than one page, flush all
412 * TLB entries for this domain
413 */
414 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
415 s = 1;
416 }
417
418 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
419
420 return 0;
421 }
422
423 /* Flush the whole IO/TLB for a given protection domain */
424 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
425 {
426 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
427
428 INC_STATS_COUNTER(domain_flush_single);
429
430 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
431 }
432
433 /*
434 * This function is used to flush the IO/TLB for a given protection domain
435 * on every IOMMU in the system
436 */
437 static void iommu_flush_domain(u16 domid)
438 {
439 unsigned long flags;
440 struct amd_iommu *iommu;
441 struct iommu_cmd cmd;
442
443 INC_STATS_COUNTER(domain_flush_all);
444
445 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
446 domid, 1, 1);
447
448 list_for_each_entry(iommu, &amd_iommu_list, list) {
449 spin_lock_irqsave(&iommu->lock, flags);
450 __iommu_queue_command(iommu, &cmd);
451 __iommu_completion_wait(iommu);
452 __iommu_wait_for_completion(iommu);
453 spin_unlock_irqrestore(&iommu->lock, flags);
454 }
455 }
456
457 /****************************************************************************
458 *
459 * The functions below are used the create the page table mappings for
460 * unity mapped regions.
461 *
462 ****************************************************************************/
463
464 /*
465 * Generic mapping functions. It maps a physical address into a DMA
466 * address space. It allocates the page table pages if necessary.
467 * In the future it can be extended to a generic mapping function
468 * supporting all features of AMD IOMMU page tables like level skipping
469 * and full 64 bit address spaces.
470 */
471 static int iommu_map_page(struct protection_domain *dom,
472 unsigned long bus_addr,
473 unsigned long phys_addr,
474 int prot)
475 {
476 u64 __pte, *pte;
477
478 bus_addr = PAGE_ALIGN(bus_addr);
479 phys_addr = PAGE_ALIGN(phys_addr);
480
481 /* only support 512GB address spaces for now */
482 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
483 return -EINVAL;
484
485 pte = alloc_pte(dom, bus_addr, NULL, GFP_KERNEL);
486
487 if (IOMMU_PTE_PRESENT(*pte))
488 return -EBUSY;
489
490 __pte = phys_addr | IOMMU_PTE_P;
491 if (prot & IOMMU_PROT_IR)
492 __pte |= IOMMU_PTE_IR;
493 if (prot & IOMMU_PROT_IW)
494 __pte |= IOMMU_PTE_IW;
495
496 *pte = __pte;
497
498 return 0;
499 }
500
501 static void iommu_unmap_page(struct protection_domain *dom,
502 unsigned long bus_addr)
503 {
504 u64 *pte;
505
506 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
507
508 if (!IOMMU_PTE_PRESENT(*pte))
509 return;
510
511 pte = IOMMU_PTE_PAGE(*pte);
512 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
513
514 if (!IOMMU_PTE_PRESENT(*pte))
515 return;
516
517 pte = IOMMU_PTE_PAGE(*pte);
518 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
519
520 *pte = 0;
521 }
522
523 /*
524 * This function checks if a specific unity mapping entry is needed for
525 * this specific IOMMU.
526 */
527 static int iommu_for_unity_map(struct amd_iommu *iommu,
528 struct unity_map_entry *entry)
529 {
530 u16 bdf, i;
531
532 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
533 bdf = amd_iommu_alias_table[i];
534 if (amd_iommu_rlookup_table[bdf] == iommu)
535 return 1;
536 }
537
538 return 0;
539 }
540
541 /*
542 * Init the unity mappings for a specific IOMMU in the system
543 *
544 * Basically iterates over all unity mapping entries and applies them to
545 * the default domain DMA of that IOMMU if necessary.
546 */
547 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
548 {
549 struct unity_map_entry *entry;
550 int ret;
551
552 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
553 if (!iommu_for_unity_map(iommu, entry))
554 continue;
555 ret = dma_ops_unity_map(iommu->default_dom, entry);
556 if (ret)
557 return ret;
558 }
559
560 return 0;
561 }
562
563 /*
564 * This function actually applies the mapping to the page table of the
565 * dma_ops domain.
566 */
567 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
568 struct unity_map_entry *e)
569 {
570 u64 addr;
571 int ret;
572
573 for (addr = e->address_start; addr < e->address_end;
574 addr += PAGE_SIZE) {
575 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
576 if (ret)
577 return ret;
578 /*
579 * if unity mapping is in aperture range mark the page
580 * as allocated in the aperture
581 */
582 if (addr < dma_dom->aperture_size)
583 __set_bit(addr >> PAGE_SHIFT,
584 dma_dom->aperture[0]->bitmap);
585 }
586
587 return 0;
588 }
589
590 /*
591 * Inits the unity mappings required for a specific device
592 */
593 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
594 u16 devid)
595 {
596 struct unity_map_entry *e;
597 int ret;
598
599 list_for_each_entry(e, &amd_iommu_unity_map, list) {
600 if (!(devid >= e->devid_start && devid <= e->devid_end))
601 continue;
602 ret = dma_ops_unity_map(dma_dom, e);
603 if (ret)
604 return ret;
605 }
606
607 return 0;
608 }
609
610 /****************************************************************************
611 *
612 * The next functions belong to the address allocator for the dma_ops
613 * interface functions. They work like the allocators in the other IOMMU
614 * drivers. Its basically a bitmap which marks the allocated pages in
615 * the aperture. Maybe it could be enhanced in the future to a more
616 * efficient allocator.
617 *
618 ****************************************************************************/
619
620 /*
621 * The address allocator core functions.
622 *
623 * called with domain->lock held
624 */
625
626 /*
627 * This function checks if there is a PTE for a given dma address. If
628 * there is one, it returns the pointer to it.
629 */
630 static u64* fetch_pte(struct protection_domain *domain,
631 unsigned long address)
632 {
633 u64 *pte;
634
635 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(address)];
636
637 if (!IOMMU_PTE_PRESENT(*pte))
638 return NULL;
639
640 pte = IOMMU_PTE_PAGE(*pte);
641 pte = &pte[IOMMU_PTE_L1_INDEX(address)];
642
643 if (!IOMMU_PTE_PRESENT(*pte))
644 return NULL;
645
646 pte = IOMMU_PTE_PAGE(*pte);
647 pte = &pte[IOMMU_PTE_L0_INDEX(address)];
648
649 return pte;
650 }
651
652 /*
653 * This function is used to add a new aperture range to an existing
654 * aperture in case of dma_ops domain allocation or address allocation
655 * failure.
656 */
657 static int alloc_new_range(struct amd_iommu *iommu,
658 struct dma_ops_domain *dma_dom,
659 bool populate, gfp_t gfp)
660 {
661 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
662 int i;
663
664 #ifdef CONFIG_IOMMU_STRESS
665 populate = false;
666 #endif
667
668 if (index >= APERTURE_MAX_RANGES)
669 return -ENOMEM;
670
671 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
672 if (!dma_dom->aperture[index])
673 return -ENOMEM;
674
675 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
676 if (!dma_dom->aperture[index]->bitmap)
677 goto out_free;
678
679 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
680
681 if (populate) {
682 unsigned long address = dma_dom->aperture_size;
683 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
684 u64 *pte, *pte_page;
685
686 for (i = 0; i < num_ptes; ++i) {
687 pte = alloc_pte(&dma_dom->domain, address,
688 &pte_page, gfp);
689 if (!pte)
690 goto out_free;
691
692 dma_dom->aperture[index]->pte_pages[i] = pte_page;
693
694 address += APERTURE_RANGE_SIZE / 64;
695 }
696 }
697
698 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
699
700 /* Intialize the exclusion range if necessary */
701 if (iommu->exclusion_start &&
702 iommu->exclusion_start >= dma_dom->aperture[index]->offset &&
703 iommu->exclusion_start < dma_dom->aperture_size) {
704 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
705 int pages = iommu_num_pages(iommu->exclusion_start,
706 iommu->exclusion_length,
707 PAGE_SIZE);
708 dma_ops_reserve_addresses(dma_dom, startpage, pages);
709 }
710
711 /*
712 * Check for areas already mapped as present in the new aperture
713 * range and mark those pages as reserved in the allocator. Such
714 * mappings may already exist as a result of requested unity
715 * mappings for devices.
716 */
717 for (i = dma_dom->aperture[index]->offset;
718 i < dma_dom->aperture_size;
719 i += PAGE_SIZE) {
720 u64 *pte = fetch_pte(&dma_dom->domain, i);
721 if (!pte || !IOMMU_PTE_PRESENT(*pte))
722 continue;
723
724 dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
725 }
726
727 return 0;
728
729 out_free:
730 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
731
732 kfree(dma_dom->aperture[index]);
733 dma_dom->aperture[index] = NULL;
734
735 return -ENOMEM;
736 }
737
738 static unsigned long dma_ops_area_alloc(struct device *dev,
739 struct dma_ops_domain *dom,
740 unsigned int pages,
741 unsigned long align_mask,
742 u64 dma_mask,
743 unsigned long start)
744 {
745 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
746 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
747 int i = start >> APERTURE_RANGE_SHIFT;
748 unsigned long boundary_size;
749 unsigned long address = -1;
750 unsigned long limit;
751
752 next_bit >>= PAGE_SHIFT;
753
754 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
755 PAGE_SIZE) >> PAGE_SHIFT;
756
757 for (;i < max_index; ++i) {
758 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
759
760 if (dom->aperture[i]->offset >= dma_mask)
761 break;
762
763 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
764 dma_mask >> PAGE_SHIFT);
765
766 address = iommu_area_alloc(dom->aperture[i]->bitmap,
767 limit, next_bit, pages, 0,
768 boundary_size, align_mask);
769 if (address != -1) {
770 address = dom->aperture[i]->offset +
771 (address << PAGE_SHIFT);
772 dom->next_address = address + (pages << PAGE_SHIFT);
773 break;
774 }
775
776 next_bit = 0;
777 }
778
779 return address;
780 }
781
782 static unsigned long dma_ops_alloc_addresses(struct device *dev,
783 struct dma_ops_domain *dom,
784 unsigned int pages,
785 unsigned long align_mask,
786 u64 dma_mask)
787 {
788 unsigned long address;
789
790 #ifdef CONFIG_IOMMU_STRESS
791 dom->next_address = 0;
792 dom->need_flush = true;
793 #endif
794
795 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
796 dma_mask, dom->next_address);
797
798 if (address == -1) {
799 dom->next_address = 0;
800 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
801 dma_mask, 0);
802 dom->need_flush = true;
803 }
804
805 if (unlikely(address == -1))
806 address = bad_dma_address;
807
808 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
809
810 return address;
811 }
812
813 /*
814 * The address free function.
815 *
816 * called with domain->lock held
817 */
818 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
819 unsigned long address,
820 unsigned int pages)
821 {
822 unsigned i = address >> APERTURE_RANGE_SHIFT;
823 struct aperture_range *range = dom->aperture[i];
824
825 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
826
827 #ifdef CONFIG_IOMMU_STRESS
828 if (i < 4)
829 return;
830 #endif
831
832 if (address >= dom->next_address)
833 dom->need_flush = true;
834
835 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
836
837 iommu_area_free(range->bitmap, address, pages);
838
839 }
840
841 /****************************************************************************
842 *
843 * The next functions belong to the domain allocation. A domain is
844 * allocated for every IOMMU as the default domain. If device isolation
845 * is enabled, every device get its own domain. The most important thing
846 * about domains is the page table mapping the DMA address space they
847 * contain.
848 *
849 ****************************************************************************/
850
851 static u16 domain_id_alloc(void)
852 {
853 unsigned long flags;
854 int id;
855
856 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
857 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
858 BUG_ON(id == 0);
859 if (id > 0 && id < MAX_DOMAIN_ID)
860 __set_bit(id, amd_iommu_pd_alloc_bitmap);
861 else
862 id = 0;
863 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
864
865 return id;
866 }
867
868 static void domain_id_free(int id)
869 {
870 unsigned long flags;
871
872 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
873 if (id > 0 && id < MAX_DOMAIN_ID)
874 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
875 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
876 }
877
878 /*
879 * Used to reserve address ranges in the aperture (e.g. for exclusion
880 * ranges.
881 */
882 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
883 unsigned long start_page,
884 unsigned int pages)
885 {
886 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
887
888 if (start_page + pages > last_page)
889 pages = last_page - start_page;
890
891 for (i = start_page; i < start_page + pages; ++i) {
892 int index = i / APERTURE_RANGE_PAGES;
893 int page = i % APERTURE_RANGE_PAGES;
894 __set_bit(page, dom->aperture[index]->bitmap);
895 }
896 }
897
898 static void free_pagetable(struct protection_domain *domain)
899 {
900 int i, j;
901 u64 *p1, *p2, *p3;
902
903 p1 = domain->pt_root;
904
905 if (!p1)
906 return;
907
908 for (i = 0; i < 512; ++i) {
909 if (!IOMMU_PTE_PRESENT(p1[i]))
910 continue;
911
912 p2 = IOMMU_PTE_PAGE(p1[i]);
913 for (j = 0; j < 512; ++j) {
914 if (!IOMMU_PTE_PRESENT(p2[j]))
915 continue;
916 p3 = IOMMU_PTE_PAGE(p2[j]);
917 free_page((unsigned long)p3);
918 }
919
920 free_page((unsigned long)p2);
921 }
922
923 free_page((unsigned long)p1);
924
925 domain->pt_root = NULL;
926 }
927
928 /*
929 * Free a domain, only used if something went wrong in the
930 * allocation path and we need to free an already allocated page table
931 */
932 static void dma_ops_domain_free(struct dma_ops_domain *dom)
933 {
934 int i;
935
936 if (!dom)
937 return;
938
939 free_pagetable(&dom->domain);
940
941 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
942 if (!dom->aperture[i])
943 continue;
944 free_page((unsigned long)dom->aperture[i]->bitmap);
945 kfree(dom->aperture[i]);
946 }
947
948 kfree(dom);
949 }
950
951 /*
952 * Allocates a new protection domain usable for the dma_ops functions.
953 * It also intializes the page table and the address allocator data
954 * structures required for the dma_ops interface
955 */
956 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu)
957 {
958 struct dma_ops_domain *dma_dom;
959
960 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
961 if (!dma_dom)
962 return NULL;
963
964 spin_lock_init(&dma_dom->domain.lock);
965
966 dma_dom->domain.id = domain_id_alloc();
967 if (dma_dom->domain.id == 0)
968 goto free_dma_dom;
969 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
970 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
971 dma_dom->domain.flags = PD_DMA_OPS_MASK;
972 dma_dom->domain.priv = dma_dom;
973 if (!dma_dom->domain.pt_root)
974 goto free_dma_dom;
975
976 dma_dom->need_flush = false;
977 dma_dom->target_dev = 0xffff;
978
979 if (alloc_new_range(iommu, dma_dom, true, GFP_KERNEL))
980 goto free_dma_dom;
981
982 /*
983 * mark the first page as allocated so we never return 0 as
984 * a valid dma-address. So we can use 0 as error value
985 */
986 dma_dom->aperture[0]->bitmap[0] = 1;
987 dma_dom->next_address = 0;
988
989
990 return dma_dom;
991
992 free_dma_dom:
993 dma_ops_domain_free(dma_dom);
994
995 return NULL;
996 }
997
998 /*
999 * little helper function to check whether a given protection domain is a
1000 * dma_ops domain
1001 */
1002 static bool dma_ops_domain(struct protection_domain *domain)
1003 {
1004 return domain->flags & PD_DMA_OPS_MASK;
1005 }
1006
1007 /*
1008 * Find out the protection domain structure for a given PCI device. This
1009 * will give us the pointer to the page table root for example.
1010 */
1011 static struct protection_domain *domain_for_device(u16 devid)
1012 {
1013 struct protection_domain *dom;
1014 unsigned long flags;
1015
1016 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
1017 dom = amd_iommu_pd_table[devid];
1018 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1019
1020 return dom;
1021 }
1022
1023 /*
1024 * If a device is not yet associated with a domain, this function does
1025 * assigns it visible for the hardware
1026 */
1027 static void attach_device(struct amd_iommu *iommu,
1028 struct protection_domain *domain,
1029 u16 devid)
1030 {
1031 unsigned long flags;
1032 u64 pte_root = virt_to_phys(domain->pt_root);
1033
1034 domain->dev_cnt += 1;
1035
1036 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1037 << DEV_ENTRY_MODE_SHIFT;
1038 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1039
1040 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1041 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
1042 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
1043 amd_iommu_dev_table[devid].data[2] = domain->id;
1044
1045 amd_iommu_pd_table[devid] = domain;
1046 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1047
1048 iommu_queue_inv_dev_entry(iommu, devid);
1049 }
1050
1051 /*
1052 * Removes a device from a protection domain (unlocked)
1053 */
1054 static void __detach_device(struct protection_domain *domain, u16 devid)
1055 {
1056
1057 /* lock domain */
1058 spin_lock(&domain->lock);
1059
1060 /* remove domain from the lookup table */
1061 amd_iommu_pd_table[devid] = NULL;
1062
1063 /* remove entry from the device table seen by the hardware */
1064 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1065 amd_iommu_dev_table[devid].data[1] = 0;
1066 amd_iommu_dev_table[devid].data[2] = 0;
1067
1068 /* decrease reference counter */
1069 domain->dev_cnt -= 1;
1070
1071 /* ready */
1072 spin_unlock(&domain->lock);
1073 }
1074
1075 /*
1076 * Removes a device from a protection domain (with devtable_lock held)
1077 */
1078 static void detach_device(struct protection_domain *domain, u16 devid)
1079 {
1080 unsigned long flags;
1081
1082 /* lock device table */
1083 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1084 __detach_device(domain, devid);
1085 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1086 }
1087
1088 static int device_change_notifier(struct notifier_block *nb,
1089 unsigned long action, void *data)
1090 {
1091 struct device *dev = data;
1092 struct pci_dev *pdev = to_pci_dev(dev);
1093 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
1094 struct protection_domain *domain;
1095 struct dma_ops_domain *dma_domain;
1096 struct amd_iommu *iommu;
1097 unsigned long flags;
1098
1099 if (devid > amd_iommu_last_bdf)
1100 goto out;
1101
1102 devid = amd_iommu_alias_table[devid];
1103
1104 iommu = amd_iommu_rlookup_table[devid];
1105 if (iommu == NULL)
1106 goto out;
1107
1108 domain = domain_for_device(devid);
1109
1110 if (domain && !dma_ops_domain(domain))
1111 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
1112 "to a non-dma-ops domain\n", dev_name(dev));
1113
1114 switch (action) {
1115 case BUS_NOTIFY_BOUND_DRIVER:
1116 if (domain)
1117 goto out;
1118 dma_domain = find_protection_domain(devid);
1119 if (!dma_domain)
1120 dma_domain = iommu->default_dom;
1121 attach_device(iommu, &dma_domain->domain, devid);
1122 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1123 "device %s\n", dma_domain->domain.id, dev_name(dev));
1124 break;
1125 case BUS_NOTIFY_UNBIND_DRIVER:
1126 if (!domain)
1127 goto out;
1128 detach_device(domain, devid);
1129 break;
1130 case BUS_NOTIFY_ADD_DEVICE:
1131 /* allocate a protection domain if a device is added */
1132 dma_domain = find_protection_domain(devid);
1133 if (dma_domain)
1134 goto out;
1135 dma_domain = dma_ops_domain_alloc(iommu);
1136 if (!dma_domain)
1137 goto out;
1138 dma_domain->target_dev = devid;
1139
1140 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1141 list_add_tail(&dma_domain->list, &iommu_pd_list);
1142 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1143
1144 break;
1145 default:
1146 goto out;
1147 }
1148
1149 iommu_queue_inv_dev_entry(iommu, devid);
1150 iommu_completion_wait(iommu);
1151
1152 out:
1153 return 0;
1154 }
1155
1156 struct notifier_block device_nb = {
1157 .notifier_call = device_change_notifier,
1158 };
1159
1160 /*****************************************************************************
1161 *
1162 * The next functions belong to the dma_ops mapping/unmapping code.
1163 *
1164 *****************************************************************************/
1165
1166 /*
1167 * This function checks if the driver got a valid device from the caller to
1168 * avoid dereferencing invalid pointers.
1169 */
1170 static bool check_device(struct device *dev)
1171 {
1172 if (!dev || !dev->dma_mask)
1173 return false;
1174
1175 return true;
1176 }
1177
1178 /*
1179 * In this function the list of preallocated protection domains is traversed to
1180 * find the domain for a specific device
1181 */
1182 static struct dma_ops_domain *find_protection_domain(u16 devid)
1183 {
1184 struct dma_ops_domain *entry, *ret = NULL;
1185 unsigned long flags;
1186
1187 if (list_empty(&iommu_pd_list))
1188 return NULL;
1189
1190 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1191
1192 list_for_each_entry(entry, &iommu_pd_list, list) {
1193 if (entry->target_dev == devid) {
1194 ret = entry;
1195 break;
1196 }
1197 }
1198
1199 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1200
1201 return ret;
1202 }
1203
1204 /*
1205 * In the dma_ops path we only have the struct device. This function
1206 * finds the corresponding IOMMU, the protection domain and the
1207 * requestor id for a given device.
1208 * If the device is not yet associated with a domain this is also done
1209 * in this function.
1210 */
1211 static int get_device_resources(struct device *dev,
1212 struct amd_iommu **iommu,
1213 struct protection_domain **domain,
1214 u16 *bdf)
1215 {
1216 struct dma_ops_domain *dma_dom;
1217 struct pci_dev *pcidev;
1218 u16 _bdf;
1219
1220 *iommu = NULL;
1221 *domain = NULL;
1222 *bdf = 0xffff;
1223
1224 if (dev->bus != &pci_bus_type)
1225 return 0;
1226
1227 pcidev = to_pci_dev(dev);
1228 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1229
1230 /* device not translated by any IOMMU in the system? */
1231 if (_bdf > amd_iommu_last_bdf)
1232 return 0;
1233
1234 *bdf = amd_iommu_alias_table[_bdf];
1235
1236 *iommu = amd_iommu_rlookup_table[*bdf];
1237 if (*iommu == NULL)
1238 return 0;
1239 *domain = domain_for_device(*bdf);
1240 if (*domain == NULL) {
1241 dma_dom = find_protection_domain(*bdf);
1242 if (!dma_dom)
1243 dma_dom = (*iommu)->default_dom;
1244 *domain = &dma_dom->domain;
1245 attach_device(*iommu, *domain, *bdf);
1246 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1247 "device %s\n", (*domain)->id, dev_name(dev));
1248 }
1249
1250 if (domain_for_device(_bdf) == NULL)
1251 attach_device(*iommu, *domain, _bdf);
1252
1253 return 1;
1254 }
1255
1256 /*
1257 * If the pte_page is not yet allocated this function is called
1258 */
1259 static u64* alloc_pte(struct protection_domain *dom,
1260 unsigned long address, u64 **pte_page, gfp_t gfp)
1261 {
1262 u64 *pte, *page;
1263
1264 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(address)];
1265
1266 if (!IOMMU_PTE_PRESENT(*pte)) {
1267 page = (u64 *)get_zeroed_page(gfp);
1268 if (!page)
1269 return NULL;
1270 *pte = IOMMU_L2_PDE(virt_to_phys(page));
1271 }
1272
1273 pte = IOMMU_PTE_PAGE(*pte);
1274 pte = &pte[IOMMU_PTE_L1_INDEX(address)];
1275
1276 if (!IOMMU_PTE_PRESENT(*pte)) {
1277 page = (u64 *)get_zeroed_page(gfp);
1278 if (!page)
1279 return NULL;
1280 *pte = IOMMU_L1_PDE(virt_to_phys(page));
1281 }
1282
1283 pte = IOMMU_PTE_PAGE(*pte);
1284
1285 if (pte_page)
1286 *pte_page = pte;
1287
1288 pte = &pte[IOMMU_PTE_L0_INDEX(address)];
1289
1290 return pte;
1291 }
1292
1293 /*
1294 * This function fetches the PTE for a given address in the aperture
1295 */
1296 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1297 unsigned long address)
1298 {
1299 struct aperture_range *aperture;
1300 u64 *pte, *pte_page;
1301
1302 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1303 if (!aperture)
1304 return NULL;
1305
1306 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1307 if (!pte) {
1308 pte = alloc_pte(&dom->domain, address, &pte_page, GFP_ATOMIC);
1309 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1310 } else
1311 pte += IOMMU_PTE_L0_INDEX(address);
1312
1313 return pte;
1314 }
1315
1316 /*
1317 * This is the generic map function. It maps one 4kb page at paddr to
1318 * the given address in the DMA address space for the domain.
1319 */
1320 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1321 struct dma_ops_domain *dom,
1322 unsigned long address,
1323 phys_addr_t paddr,
1324 int direction)
1325 {
1326 u64 *pte, __pte;
1327
1328 WARN_ON(address > dom->aperture_size);
1329
1330 paddr &= PAGE_MASK;
1331
1332 pte = dma_ops_get_pte(dom, address);
1333 if (!pte)
1334 return bad_dma_address;
1335
1336 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1337
1338 if (direction == DMA_TO_DEVICE)
1339 __pte |= IOMMU_PTE_IR;
1340 else if (direction == DMA_FROM_DEVICE)
1341 __pte |= IOMMU_PTE_IW;
1342 else if (direction == DMA_BIDIRECTIONAL)
1343 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1344
1345 WARN_ON(*pte);
1346
1347 *pte = __pte;
1348
1349 return (dma_addr_t)address;
1350 }
1351
1352 /*
1353 * The generic unmapping function for on page in the DMA address space.
1354 */
1355 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1356 struct dma_ops_domain *dom,
1357 unsigned long address)
1358 {
1359 struct aperture_range *aperture;
1360 u64 *pte;
1361
1362 if (address >= dom->aperture_size)
1363 return;
1364
1365 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1366 if (!aperture)
1367 return;
1368
1369 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1370 if (!pte)
1371 return;
1372
1373 pte += IOMMU_PTE_L0_INDEX(address);
1374
1375 WARN_ON(!*pte);
1376
1377 *pte = 0ULL;
1378 }
1379
1380 /*
1381 * This function contains common code for mapping of a physically
1382 * contiguous memory region into DMA address space. It is used by all
1383 * mapping functions provided with this IOMMU driver.
1384 * Must be called with the domain lock held.
1385 */
1386 static dma_addr_t __map_single(struct device *dev,
1387 struct amd_iommu *iommu,
1388 struct dma_ops_domain *dma_dom,
1389 phys_addr_t paddr,
1390 size_t size,
1391 int dir,
1392 bool align,
1393 u64 dma_mask)
1394 {
1395 dma_addr_t offset = paddr & ~PAGE_MASK;
1396 dma_addr_t address, start, ret;
1397 unsigned int pages;
1398 unsigned long align_mask = 0;
1399 int i;
1400
1401 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1402 paddr &= PAGE_MASK;
1403
1404 INC_STATS_COUNTER(total_map_requests);
1405
1406 if (pages > 1)
1407 INC_STATS_COUNTER(cross_page);
1408
1409 if (align)
1410 align_mask = (1UL << get_order(size)) - 1;
1411
1412 retry:
1413 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1414 dma_mask);
1415 if (unlikely(address == bad_dma_address)) {
1416 /*
1417 * setting next_address here will let the address
1418 * allocator only scan the new allocated range in the
1419 * first run. This is a small optimization.
1420 */
1421 dma_dom->next_address = dma_dom->aperture_size;
1422
1423 if (alloc_new_range(iommu, dma_dom, false, GFP_ATOMIC))
1424 goto out;
1425
1426 /*
1427 * aperture was sucessfully enlarged by 128 MB, try
1428 * allocation again
1429 */
1430 goto retry;
1431 }
1432
1433 start = address;
1434 for (i = 0; i < pages; ++i) {
1435 ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1436 if (ret == bad_dma_address)
1437 goto out_unmap;
1438
1439 paddr += PAGE_SIZE;
1440 start += PAGE_SIZE;
1441 }
1442 address += offset;
1443
1444 ADD_STATS_COUNTER(alloced_io_mem, size);
1445
1446 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1447 iommu_flush_tlb(iommu, dma_dom->domain.id);
1448 dma_dom->need_flush = false;
1449 } else if (unlikely(iommu_has_npcache(iommu)))
1450 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1451
1452 out:
1453 return address;
1454
1455 out_unmap:
1456
1457 for (--i; i >= 0; --i) {
1458 start -= PAGE_SIZE;
1459 dma_ops_domain_unmap(iommu, dma_dom, start);
1460 }
1461
1462 dma_ops_free_addresses(dma_dom, address, pages);
1463
1464 return bad_dma_address;
1465 }
1466
1467 /*
1468 * Does the reverse of the __map_single function. Must be called with
1469 * the domain lock held too
1470 */
1471 static void __unmap_single(struct amd_iommu *iommu,
1472 struct dma_ops_domain *dma_dom,
1473 dma_addr_t dma_addr,
1474 size_t size,
1475 int dir)
1476 {
1477 dma_addr_t i, start;
1478 unsigned int pages;
1479
1480 if ((dma_addr == bad_dma_address) ||
1481 (dma_addr + size > dma_dom->aperture_size))
1482 return;
1483
1484 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1485 dma_addr &= PAGE_MASK;
1486 start = dma_addr;
1487
1488 for (i = 0; i < pages; ++i) {
1489 dma_ops_domain_unmap(iommu, dma_dom, start);
1490 start += PAGE_SIZE;
1491 }
1492
1493 SUB_STATS_COUNTER(alloced_io_mem, size);
1494
1495 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1496
1497 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1498 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1499 dma_dom->need_flush = false;
1500 }
1501 }
1502
1503 /*
1504 * The exported map_single function for dma_ops.
1505 */
1506 static dma_addr_t map_page(struct device *dev, struct page *page,
1507 unsigned long offset, size_t size,
1508 enum dma_data_direction dir,
1509 struct dma_attrs *attrs)
1510 {
1511 unsigned long flags;
1512 struct amd_iommu *iommu;
1513 struct protection_domain *domain;
1514 u16 devid;
1515 dma_addr_t addr;
1516 u64 dma_mask;
1517 phys_addr_t paddr = page_to_phys(page) + offset;
1518
1519 INC_STATS_COUNTER(cnt_map_single);
1520
1521 if (!check_device(dev))
1522 return bad_dma_address;
1523
1524 dma_mask = *dev->dma_mask;
1525
1526 get_device_resources(dev, &iommu, &domain, &devid);
1527
1528 if (iommu == NULL || domain == NULL)
1529 /* device not handled by any AMD IOMMU */
1530 return (dma_addr_t)paddr;
1531
1532 if (!dma_ops_domain(domain))
1533 return bad_dma_address;
1534
1535 spin_lock_irqsave(&domain->lock, flags);
1536 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1537 dma_mask);
1538 if (addr == bad_dma_address)
1539 goto out;
1540
1541 iommu_completion_wait(iommu);
1542
1543 out:
1544 spin_unlock_irqrestore(&domain->lock, flags);
1545
1546 return addr;
1547 }
1548
1549 /*
1550 * The exported unmap_single function for dma_ops.
1551 */
1552 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
1553 enum dma_data_direction dir, struct dma_attrs *attrs)
1554 {
1555 unsigned long flags;
1556 struct amd_iommu *iommu;
1557 struct protection_domain *domain;
1558 u16 devid;
1559
1560 INC_STATS_COUNTER(cnt_unmap_single);
1561
1562 if (!check_device(dev) ||
1563 !get_device_resources(dev, &iommu, &domain, &devid))
1564 /* device not handled by any AMD IOMMU */
1565 return;
1566
1567 if (!dma_ops_domain(domain))
1568 return;
1569
1570 spin_lock_irqsave(&domain->lock, flags);
1571
1572 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1573
1574 iommu_completion_wait(iommu);
1575
1576 spin_unlock_irqrestore(&domain->lock, flags);
1577 }
1578
1579 /*
1580 * This is a special map_sg function which is used if we should map a
1581 * device which is not handled by an AMD IOMMU in the system.
1582 */
1583 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1584 int nelems, int dir)
1585 {
1586 struct scatterlist *s;
1587 int i;
1588
1589 for_each_sg(sglist, s, nelems, i) {
1590 s->dma_address = (dma_addr_t)sg_phys(s);
1591 s->dma_length = s->length;
1592 }
1593
1594 return nelems;
1595 }
1596
1597 /*
1598 * The exported map_sg function for dma_ops (handles scatter-gather
1599 * lists).
1600 */
1601 static int map_sg(struct device *dev, struct scatterlist *sglist,
1602 int nelems, enum dma_data_direction dir,
1603 struct dma_attrs *attrs)
1604 {
1605 unsigned long flags;
1606 struct amd_iommu *iommu;
1607 struct protection_domain *domain;
1608 u16 devid;
1609 int i;
1610 struct scatterlist *s;
1611 phys_addr_t paddr;
1612 int mapped_elems = 0;
1613 u64 dma_mask;
1614
1615 INC_STATS_COUNTER(cnt_map_sg);
1616
1617 if (!check_device(dev))
1618 return 0;
1619
1620 dma_mask = *dev->dma_mask;
1621
1622 get_device_resources(dev, &iommu, &domain, &devid);
1623
1624 if (!iommu || !domain)
1625 return map_sg_no_iommu(dev, sglist, nelems, dir);
1626
1627 if (!dma_ops_domain(domain))
1628 return 0;
1629
1630 spin_lock_irqsave(&domain->lock, flags);
1631
1632 for_each_sg(sglist, s, nelems, i) {
1633 paddr = sg_phys(s);
1634
1635 s->dma_address = __map_single(dev, iommu, domain->priv,
1636 paddr, s->length, dir, false,
1637 dma_mask);
1638
1639 if (s->dma_address) {
1640 s->dma_length = s->length;
1641 mapped_elems++;
1642 } else
1643 goto unmap;
1644 }
1645
1646 iommu_completion_wait(iommu);
1647
1648 out:
1649 spin_unlock_irqrestore(&domain->lock, flags);
1650
1651 return mapped_elems;
1652 unmap:
1653 for_each_sg(sglist, s, mapped_elems, i) {
1654 if (s->dma_address)
1655 __unmap_single(iommu, domain->priv, s->dma_address,
1656 s->dma_length, dir);
1657 s->dma_address = s->dma_length = 0;
1658 }
1659
1660 mapped_elems = 0;
1661
1662 goto out;
1663 }
1664
1665 /*
1666 * The exported map_sg function for dma_ops (handles scatter-gather
1667 * lists).
1668 */
1669 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1670 int nelems, enum dma_data_direction dir,
1671 struct dma_attrs *attrs)
1672 {
1673 unsigned long flags;
1674 struct amd_iommu *iommu;
1675 struct protection_domain *domain;
1676 struct scatterlist *s;
1677 u16 devid;
1678 int i;
1679
1680 INC_STATS_COUNTER(cnt_unmap_sg);
1681
1682 if (!check_device(dev) ||
1683 !get_device_resources(dev, &iommu, &domain, &devid))
1684 return;
1685
1686 if (!dma_ops_domain(domain))
1687 return;
1688
1689 spin_lock_irqsave(&domain->lock, flags);
1690
1691 for_each_sg(sglist, s, nelems, i) {
1692 __unmap_single(iommu, domain->priv, s->dma_address,
1693 s->dma_length, dir);
1694 s->dma_address = s->dma_length = 0;
1695 }
1696
1697 iommu_completion_wait(iommu);
1698
1699 spin_unlock_irqrestore(&domain->lock, flags);
1700 }
1701
1702 /*
1703 * The exported alloc_coherent function for dma_ops.
1704 */
1705 static void *alloc_coherent(struct device *dev, size_t size,
1706 dma_addr_t *dma_addr, gfp_t flag)
1707 {
1708 unsigned long flags;
1709 void *virt_addr;
1710 struct amd_iommu *iommu;
1711 struct protection_domain *domain;
1712 u16 devid;
1713 phys_addr_t paddr;
1714 u64 dma_mask = dev->coherent_dma_mask;
1715
1716 INC_STATS_COUNTER(cnt_alloc_coherent);
1717
1718 if (!check_device(dev))
1719 return NULL;
1720
1721 if (!get_device_resources(dev, &iommu, &domain, &devid))
1722 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1723
1724 flag |= __GFP_ZERO;
1725 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1726 if (!virt_addr)
1727 return 0;
1728
1729 paddr = virt_to_phys(virt_addr);
1730
1731 if (!iommu || !domain) {
1732 *dma_addr = (dma_addr_t)paddr;
1733 return virt_addr;
1734 }
1735
1736 if (!dma_ops_domain(domain))
1737 goto out_free;
1738
1739 if (!dma_mask)
1740 dma_mask = *dev->dma_mask;
1741
1742 spin_lock_irqsave(&domain->lock, flags);
1743
1744 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1745 size, DMA_BIDIRECTIONAL, true, dma_mask);
1746
1747 if (*dma_addr == bad_dma_address)
1748 goto out_free;
1749
1750 iommu_completion_wait(iommu);
1751
1752 spin_unlock_irqrestore(&domain->lock, flags);
1753
1754 return virt_addr;
1755
1756 out_free:
1757
1758 free_pages((unsigned long)virt_addr, get_order(size));
1759
1760 return NULL;
1761 }
1762
1763 /*
1764 * The exported free_coherent function for dma_ops.
1765 */
1766 static void free_coherent(struct device *dev, size_t size,
1767 void *virt_addr, dma_addr_t dma_addr)
1768 {
1769 unsigned long flags;
1770 struct amd_iommu *iommu;
1771 struct protection_domain *domain;
1772 u16 devid;
1773
1774 INC_STATS_COUNTER(cnt_free_coherent);
1775
1776 if (!check_device(dev))
1777 return;
1778
1779 get_device_resources(dev, &iommu, &domain, &devid);
1780
1781 if (!iommu || !domain)
1782 goto free_mem;
1783
1784 if (!dma_ops_domain(domain))
1785 goto free_mem;
1786
1787 spin_lock_irqsave(&domain->lock, flags);
1788
1789 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1790
1791 iommu_completion_wait(iommu);
1792
1793 spin_unlock_irqrestore(&domain->lock, flags);
1794
1795 free_mem:
1796 free_pages((unsigned long)virt_addr, get_order(size));
1797 }
1798
1799 /*
1800 * This function is called by the DMA layer to find out if we can handle a
1801 * particular device. It is part of the dma_ops.
1802 */
1803 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1804 {
1805 u16 bdf;
1806 struct pci_dev *pcidev;
1807
1808 /* No device or no PCI device */
1809 if (!dev || dev->bus != &pci_bus_type)
1810 return 0;
1811
1812 pcidev = to_pci_dev(dev);
1813
1814 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1815
1816 /* Out of our scope? */
1817 if (bdf > amd_iommu_last_bdf)
1818 return 0;
1819
1820 return 1;
1821 }
1822
1823 /*
1824 * The function for pre-allocating protection domains.
1825 *
1826 * If the driver core informs the DMA layer if a driver grabs a device
1827 * we don't need to preallocate the protection domains anymore.
1828 * For now we have to.
1829 */
1830 static void prealloc_protection_domains(void)
1831 {
1832 struct pci_dev *dev = NULL;
1833 struct dma_ops_domain *dma_dom;
1834 struct amd_iommu *iommu;
1835 u16 devid;
1836
1837 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1838 devid = calc_devid(dev->bus->number, dev->devfn);
1839 if (devid > amd_iommu_last_bdf)
1840 continue;
1841 devid = amd_iommu_alias_table[devid];
1842 if (domain_for_device(devid))
1843 continue;
1844 iommu = amd_iommu_rlookup_table[devid];
1845 if (!iommu)
1846 continue;
1847 dma_dom = dma_ops_domain_alloc(iommu);
1848 if (!dma_dom)
1849 continue;
1850 init_unity_mappings_for_device(dma_dom, devid);
1851 dma_dom->target_dev = devid;
1852
1853 list_add_tail(&dma_dom->list, &iommu_pd_list);
1854 }
1855 }
1856
1857 static struct dma_map_ops amd_iommu_dma_ops = {
1858 .alloc_coherent = alloc_coherent,
1859 .free_coherent = free_coherent,
1860 .map_page = map_page,
1861 .unmap_page = unmap_page,
1862 .map_sg = map_sg,
1863 .unmap_sg = unmap_sg,
1864 .dma_supported = amd_iommu_dma_supported,
1865 };
1866
1867 /*
1868 * The function which clues the AMD IOMMU driver into dma_ops.
1869 */
1870 int __init amd_iommu_init_dma_ops(void)
1871 {
1872 struct amd_iommu *iommu;
1873 int ret;
1874
1875 /*
1876 * first allocate a default protection domain for every IOMMU we
1877 * found in the system. Devices not assigned to any other
1878 * protection domain will be assigned to the default one.
1879 */
1880 list_for_each_entry(iommu, &amd_iommu_list, list) {
1881 iommu->default_dom = dma_ops_domain_alloc(iommu);
1882 if (iommu->default_dom == NULL)
1883 return -ENOMEM;
1884 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
1885 ret = iommu_init_unity_mappings(iommu);
1886 if (ret)
1887 goto free_domains;
1888 }
1889
1890 /*
1891 * If device isolation is enabled, pre-allocate the protection
1892 * domains for each device.
1893 */
1894 if (amd_iommu_isolate)
1895 prealloc_protection_domains();
1896
1897 iommu_detected = 1;
1898 force_iommu = 1;
1899 bad_dma_address = 0;
1900 #ifdef CONFIG_GART_IOMMU
1901 gart_iommu_aperture_disabled = 1;
1902 gart_iommu_aperture = 0;
1903 #endif
1904
1905 /* Make the driver finally visible to the drivers */
1906 dma_ops = &amd_iommu_dma_ops;
1907
1908 register_iommu(&amd_iommu_ops);
1909
1910 bus_register_notifier(&pci_bus_type, &device_nb);
1911
1912 amd_iommu_stats_init();
1913
1914 return 0;
1915
1916 free_domains:
1917
1918 list_for_each_entry(iommu, &amd_iommu_list, list) {
1919 if (iommu->default_dom)
1920 dma_ops_domain_free(iommu->default_dom);
1921 }
1922
1923 return ret;
1924 }
1925
1926 /*****************************************************************************
1927 *
1928 * The following functions belong to the exported interface of AMD IOMMU
1929 *
1930 * This interface allows access to lower level functions of the IOMMU
1931 * like protection domain handling and assignement of devices to domains
1932 * which is not possible with the dma_ops interface.
1933 *
1934 *****************************************************************************/
1935
1936 static void cleanup_domain(struct protection_domain *domain)
1937 {
1938 unsigned long flags;
1939 u16 devid;
1940
1941 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1942
1943 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1944 if (amd_iommu_pd_table[devid] == domain)
1945 __detach_device(domain, devid);
1946
1947 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1948 }
1949
1950 static int amd_iommu_domain_init(struct iommu_domain *dom)
1951 {
1952 struct protection_domain *domain;
1953
1954 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
1955 if (!domain)
1956 return -ENOMEM;
1957
1958 spin_lock_init(&domain->lock);
1959 domain->mode = PAGE_MODE_3_LEVEL;
1960 domain->id = domain_id_alloc();
1961 if (!domain->id)
1962 goto out_free;
1963 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1964 if (!domain->pt_root)
1965 goto out_free;
1966
1967 dom->priv = domain;
1968
1969 return 0;
1970
1971 out_free:
1972 kfree(domain);
1973
1974 return -ENOMEM;
1975 }
1976
1977 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
1978 {
1979 struct protection_domain *domain = dom->priv;
1980
1981 if (!domain)
1982 return;
1983
1984 if (domain->dev_cnt > 0)
1985 cleanup_domain(domain);
1986
1987 BUG_ON(domain->dev_cnt != 0);
1988
1989 free_pagetable(domain);
1990
1991 domain_id_free(domain->id);
1992
1993 kfree(domain);
1994
1995 dom->priv = NULL;
1996 }
1997
1998 static void amd_iommu_detach_device(struct iommu_domain *dom,
1999 struct device *dev)
2000 {
2001 struct protection_domain *domain = dom->priv;
2002 struct amd_iommu *iommu;
2003 struct pci_dev *pdev;
2004 u16 devid;
2005
2006 if (dev->bus != &pci_bus_type)
2007 return;
2008
2009 pdev = to_pci_dev(dev);
2010
2011 devid = calc_devid(pdev->bus->number, pdev->devfn);
2012
2013 if (devid > 0)
2014 detach_device(domain, devid);
2015
2016 iommu = amd_iommu_rlookup_table[devid];
2017 if (!iommu)
2018 return;
2019
2020 iommu_queue_inv_dev_entry(iommu, devid);
2021 iommu_completion_wait(iommu);
2022 }
2023
2024 static int amd_iommu_attach_device(struct iommu_domain *dom,
2025 struct device *dev)
2026 {
2027 struct protection_domain *domain = dom->priv;
2028 struct protection_domain *old_domain;
2029 struct amd_iommu *iommu;
2030 struct pci_dev *pdev;
2031 u16 devid;
2032
2033 if (dev->bus != &pci_bus_type)
2034 return -EINVAL;
2035
2036 pdev = to_pci_dev(dev);
2037
2038 devid = calc_devid(pdev->bus->number, pdev->devfn);
2039
2040 if (devid >= amd_iommu_last_bdf ||
2041 devid != amd_iommu_alias_table[devid])
2042 return -EINVAL;
2043
2044 iommu = amd_iommu_rlookup_table[devid];
2045 if (!iommu)
2046 return -EINVAL;
2047
2048 old_domain = domain_for_device(devid);
2049 if (old_domain)
2050 return -EBUSY;
2051
2052 attach_device(iommu, domain, devid);
2053
2054 iommu_completion_wait(iommu);
2055
2056 return 0;
2057 }
2058
2059 static int amd_iommu_map_range(struct iommu_domain *dom,
2060 unsigned long iova, phys_addr_t paddr,
2061 size_t size, int iommu_prot)
2062 {
2063 struct protection_domain *domain = dom->priv;
2064 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
2065 int prot = 0;
2066 int ret;
2067
2068 if (iommu_prot & IOMMU_READ)
2069 prot |= IOMMU_PROT_IR;
2070 if (iommu_prot & IOMMU_WRITE)
2071 prot |= IOMMU_PROT_IW;
2072
2073 iova &= PAGE_MASK;
2074 paddr &= PAGE_MASK;
2075
2076 for (i = 0; i < npages; ++i) {
2077 ret = iommu_map_page(domain, iova, paddr, prot);
2078 if (ret)
2079 return ret;
2080
2081 iova += PAGE_SIZE;
2082 paddr += PAGE_SIZE;
2083 }
2084
2085 return 0;
2086 }
2087
2088 static void amd_iommu_unmap_range(struct iommu_domain *dom,
2089 unsigned long iova, size_t size)
2090 {
2091
2092 struct protection_domain *domain = dom->priv;
2093 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
2094
2095 iova &= PAGE_MASK;
2096
2097 for (i = 0; i < npages; ++i) {
2098 iommu_unmap_page(domain, iova);
2099 iova += PAGE_SIZE;
2100 }
2101
2102 iommu_flush_domain(domain->id);
2103 }
2104
2105 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2106 unsigned long iova)
2107 {
2108 struct protection_domain *domain = dom->priv;
2109 unsigned long offset = iova & ~PAGE_MASK;
2110 phys_addr_t paddr;
2111 u64 *pte;
2112
2113 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)];
2114
2115 if (!IOMMU_PTE_PRESENT(*pte))
2116 return 0;
2117
2118 pte = IOMMU_PTE_PAGE(*pte);
2119 pte = &pte[IOMMU_PTE_L1_INDEX(iova)];
2120
2121 if (!IOMMU_PTE_PRESENT(*pte))
2122 return 0;
2123
2124 pte = IOMMU_PTE_PAGE(*pte);
2125 pte = &pte[IOMMU_PTE_L0_INDEX(iova)];
2126
2127 if (!IOMMU_PTE_PRESENT(*pte))
2128 return 0;
2129
2130 paddr = *pte & IOMMU_PAGE_MASK;
2131 paddr |= offset;
2132
2133 return paddr;
2134 }
2135
2136 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2137 unsigned long cap)
2138 {
2139 return 0;
2140 }
2141
2142 static struct iommu_ops amd_iommu_ops = {
2143 .domain_init = amd_iommu_domain_init,
2144 .domain_destroy = amd_iommu_domain_destroy,
2145 .attach_dev = amd_iommu_attach_device,
2146 .detach_dev = amd_iommu_detach_device,
2147 .map = amd_iommu_map_range,
2148 .unmap = amd_iommu_unmap_range,
2149 .iova_to_phys = amd_iommu_iova_to_phys,
2150 .domain_has_cap = amd_iommu_domain_has_cap,
2151 };
2152
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