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usb: musb: tusb6010: Handle DMA TX completion in DMA callback as well
[linux-2.6/btrfs-unstable.git] / drivers / usb / musb / tusb6010_omap.c
blob1c4592d753bf8b90ac5b0115909a6a6ca032502c
1 /*
2 * TUSB6010 USB 2.0 OTG Dual Role controller OMAP DMA interface
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/errno.h>
14 #include <linux/usb.h>
15 #include <linux/platform_device.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/slab.h>
18 #include <linux/omap-dma.h>
19
20 #include "musb_core.h"
21 #include "tusb6010.h"
22
23 #define to_chdat(c) ((struct tusb_omap_dma_ch *)(c)->private_data)
24
25 #define MAX_DMAREQ 5 /* REVISIT: Really 6, but req5 not OK */
26
27 #define OMAP24XX_DMA_EXT_DMAREQ0 2
28 #define OMAP24XX_DMA_EXT_DMAREQ1 3
29 #define OMAP242X_DMA_EXT_DMAREQ2 14
30 #define OMAP242X_DMA_EXT_DMAREQ3 15
31 #define OMAP242X_DMA_EXT_DMAREQ4 16
32 #define OMAP242X_DMA_EXT_DMAREQ5 64
33
34 struct tusb_dma_data {
35 int ch;
36 s8 dmareq;
37 s8 sync_dev;
38 };
39
40 struct tusb_omap_dma_ch {
41 struct musb *musb;
42 void __iomem *tbase;
43 unsigned long phys_offset;
44 int epnum;
45 u8 tx;
46 struct musb_hw_ep *hw_ep;
47
48 struct tusb_dma_data *dma_data;
49
50 struct tusb_omap_dma *tusb_dma;
51
52 dma_addr_t dma_addr;
53
54 u32 len;
55 u16 packet_sz;
56 u16 transfer_packet_sz;
57 u32 transfer_len;
58 u32 completed_len;
59 };
60
61 struct tusb_omap_dma {
62 struct dma_controller controller;
63 void __iomem *tbase;
64
65 struct tusb_dma_data dma_pool[MAX_DMAREQ];
66 unsigned multichannel:1;
67 };
68
69 /*
70 * Allocate dmareq0 to the current channel unless it's already taken
71 */
72 static inline int tusb_omap_use_shared_dmareq(struct tusb_omap_dma_ch *chdat)
73 {
74 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
75
76 if (reg != 0) {
77 dev_dbg(chdat->musb->controller, "ep%i dmareq0 is busy for ep%i\n",
78 chdat->epnum, reg & 0xf);
79 return -EAGAIN;
80 }
81
82 if (chdat->tx)
83 reg = (1 << 4) | chdat->epnum;
84 else
85 reg = chdat->epnum;
86
87 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
88
89 return 0;
90 }
91
92 static inline void tusb_omap_free_shared_dmareq(struct tusb_omap_dma_ch *chdat)
93 {
94 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
95
96 if ((reg & 0xf) != chdat->epnum) {
97 printk(KERN_ERR "ep%i trying to release dmareq0 for ep%i\n",
98 chdat->epnum, reg & 0xf);
99 return;
100 }
101 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, 0);
102 }
103
104 /*
105 * See also musb_dma_completion in plat_uds.c and musb_g_[tx|rx]() in
106 * musb_gadget.c.
107 */
108 static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
109 {
110 struct dma_channel *channel = (struct dma_channel *)data;
111 struct tusb_omap_dma_ch *chdat = to_chdat(channel);
112 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
113 struct musb *musb = chdat->musb;
114 struct device *dev = musb->controller;
115 struct musb_hw_ep *hw_ep = chdat->hw_ep;
116 void __iomem *ep_conf = hw_ep->conf;
117 void __iomem *mbase = musb->mregs;
118 unsigned long remaining, flags, pio;
119 int ch;
120
121 spin_lock_irqsave(&musb->lock, flags);
122
123 ch = chdat->dma_data->ch;
124
125 if (ch_status != OMAP_DMA_BLOCK_IRQ)
126 printk(KERN_ERR "TUSB DMA error status: %i\n", ch_status);
127
128 dev_dbg(musb->controller, "ep%i %s dma callback ch: %i status: %x\n",
129 chdat->epnum, chdat->tx ? "tx" : "rx",
130 ch, ch_status);
131
132 if (chdat->tx)
133 remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET);
134 else
135 remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET);
136
137 remaining = TUSB_EP_CONFIG_XFR_SIZE(remaining);
138
139 /* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */
140 if (unlikely(remaining > chdat->transfer_len)) {
141 dev_dbg(musb->controller, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n",
142 chdat->tx ? "tx" : "rx", ch, remaining);
143 remaining = 0;
144 }
145
146 channel->actual_len = chdat->transfer_len - remaining;
147 pio = chdat->len - channel->actual_len;
148
149 dev_dbg(musb->controller, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len);
150
151 /* Transfer remaining 1 - 31 bytes */
152 if (pio > 0 && pio < 32) {
153 u8 *buf;
154
155 dev_dbg(musb->controller, "Using PIO for remaining %lu bytes\n", pio);
156 buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len;
157 if (chdat->tx) {
158 dma_unmap_single(dev, chdat->dma_addr,
159 chdat->transfer_len,
160 DMA_TO_DEVICE);
161 musb_write_fifo(hw_ep, pio, buf);
162 } else {
163 dma_unmap_single(dev, chdat->dma_addr,
164 chdat->transfer_len,
165 DMA_FROM_DEVICE);
166 musb_read_fifo(hw_ep, pio, buf);
167 }
168 channel->actual_len += pio;
169 }
170
171 if (!tusb_dma->multichannel)
172 tusb_omap_free_shared_dmareq(chdat);
173
174 channel->status = MUSB_DMA_STATUS_FREE;
175
176 musb_dma_completion(musb, chdat->epnum, chdat->tx);
177
178 /* We must terminate short tx transfers manually by setting TXPKTRDY.
179 * REVISIT: This same problem may occur with other MUSB dma as well.
180 * Easy to test with g_ether by pinging the MUSB board with ping -s54.
181 */
182 if ((chdat->transfer_len < chdat->packet_sz)
183 || (chdat->transfer_len % chdat->packet_sz != 0)) {
184 u16 csr;
185
186 if (chdat->tx) {
187 dev_dbg(musb->controller, "terminating short tx packet\n");
188 musb_ep_select(mbase, chdat->epnum);
189 csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
190 csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY
191 | MUSB_TXCSR_P_WZC_BITS;
192 musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
193 }
194 }
195
196 spin_unlock_irqrestore(&musb->lock, flags);
197 }
198
199 static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
200 u8 rndis_mode, dma_addr_t dma_addr, u32 len)
201 {
202 struct tusb_omap_dma_ch *chdat = to_chdat(channel);
203 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
204 struct musb *musb = chdat->musb;
205 struct device *dev = musb->controller;
206 struct musb_hw_ep *hw_ep = chdat->hw_ep;
207 void __iomem *mbase = musb->mregs;
208 void __iomem *ep_conf = hw_ep->conf;
209 dma_addr_t fifo = hw_ep->fifo_sync;
210 struct omap_dma_channel_params dma_params;
211 u32 dma_remaining;
212 int src_burst, dst_burst;
213 u16 csr;
214 u32 psize;
215 struct tusb_dma_data *dma_data;
216
217 if (unlikely(dma_addr & 0x1) || (len < 32) || (len > packet_sz))
218 return false;
219
220 /*
221 * HW issue #10: Async dma will eventually corrupt the XFR_SIZE
222 * register which will cause missed DMA interrupt. We could try to
223 * use a timer for the callback, but it is unsafe as the XFR_SIZE
224 * register is corrupt, and we won't know if the DMA worked.
225 */
226 if (dma_addr & 0x2)
227 return false;
228
229 /*
230 * Because of HW issue #10, it seems like mixing sync DMA and async
231 * PIO access can confuse the DMA. Make sure XFR_SIZE is reset before
232 * using the channel for DMA.
233 */
234 if (chdat->tx)
235 dma_remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET);
236 else
237 dma_remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET);
238
239 dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining);
240 if (dma_remaining) {
241 dev_dbg(musb->controller, "Busy %s dma ch%i, not using: %08x\n",
242 chdat->tx ? "tx" : "rx",
243 chdat->dma_data ? chdat->dma_data->ch : -1,
244 dma_remaining);
245 return false;
246 }
247
248 chdat->transfer_len = len & ~0x1f;
249
250 if (len < packet_sz)
251 chdat->transfer_packet_sz = chdat->transfer_len;
252 else
253 chdat->transfer_packet_sz = packet_sz;
254
255 dma_data = chdat->dma_data;
256 if (!tusb_dma->multichannel) {
257 if (tusb_omap_use_shared_dmareq(chdat) != 0) {
258 dev_dbg(musb->controller, "could not get dma for ep%i\n", chdat->epnum);
259 return false;
260 }
261 if (dma_data->ch < 0) {
262 /* REVISIT: This should get blocked earlier, happens
263 * with MSC ErrorRecoveryTest
264 */
265 WARN_ON(1);
266 return false;
267 }
268 }
269
270 omap_set_dma_callback(dma_data->ch, tusb_omap_dma_cb, channel);
271
272 chdat->packet_sz = packet_sz;
273 chdat->len = len;
274 channel->actual_len = 0;
275 chdat->dma_addr = dma_addr;
276 channel->status = MUSB_DMA_STATUS_BUSY;
277
278 /* Since we're recycling dma areas, we need to clean or invalidate */
279 if (chdat->tx)
280 dma_map_single(dev, phys_to_virt(dma_addr), len,
281 DMA_TO_DEVICE);
282 else
283 dma_map_single(dev, phys_to_virt(dma_addr), len,
284 DMA_FROM_DEVICE);
285
286 /* Use 16-bit transfer if dma_addr is not 32-bit aligned */
287 if ((dma_addr & 0x3) == 0) {
288 dma_params.data_type = OMAP_DMA_DATA_TYPE_S32;
289 dma_params.elem_count = 8; /* Elements in frame */
290 } else {
291 dma_params.data_type = OMAP_DMA_DATA_TYPE_S16;
292 dma_params.elem_count = 16; /* Elements in frame */
293 fifo = hw_ep->fifo_async;
294 }
295
296 dma_params.frame_count = chdat->transfer_len / 32; /* Burst sz frame */
297
298 dev_dbg(musb->controller, "ep%i %s dma ch%i dma: %pad len: %u(%u) packet_sz: %i(%i)\n",
299 chdat->epnum, chdat->tx ? "tx" : "rx",
300 dma_data->ch, &dma_addr, chdat->transfer_len, len,
301 chdat->transfer_packet_sz, packet_sz);
302
303 /*
304 * Prepare omap DMA for transfer
305 */
306 if (chdat->tx) {
307 dma_params.src_amode = OMAP_DMA_AMODE_POST_INC;
308 dma_params.src_start = (unsigned long)dma_addr;
309 dma_params.src_ei = 0;
310 dma_params.src_fi = 0;
311
312 dma_params.dst_amode = OMAP_DMA_AMODE_DOUBLE_IDX;
313 dma_params.dst_start = (unsigned long)fifo;
314 dma_params.dst_ei = 1;
315 dma_params.dst_fi = -31; /* Loop 32 byte window */
316
317 dma_params.trigger = dma_data->sync_dev;
318 dma_params.sync_mode = OMAP_DMA_SYNC_FRAME;
319 dma_params.src_or_dst_synch = 0; /* Dest sync */
320
321 src_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 read */
322 dst_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 write */
323 } else {
324 dma_params.src_amode = OMAP_DMA_AMODE_DOUBLE_IDX;
325 dma_params.src_start = (unsigned long)fifo;
326 dma_params.src_ei = 1;
327 dma_params.src_fi = -31; /* Loop 32 byte window */
328
329 dma_params.dst_amode = OMAP_DMA_AMODE_POST_INC;
330 dma_params.dst_start = (unsigned long)dma_addr;
331 dma_params.dst_ei = 0;
332 dma_params.dst_fi = 0;
333
334 dma_params.trigger = dma_data->sync_dev;
335 dma_params.sync_mode = OMAP_DMA_SYNC_FRAME;
336 dma_params.src_or_dst_synch = 1; /* Source sync */
337
338 src_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 read */
339 dst_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 write */
340 }
341
342 dev_dbg(musb->controller, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n",
343 chdat->epnum, chdat->tx ? "tx" : "rx",
344 (dma_params.data_type == OMAP_DMA_DATA_TYPE_S32) ? 32 : 16,
345 ((dma_addr & 0x3) == 0) ? "sync" : "async",
346 dma_params.src_start, dma_params.dst_start);
347
348 omap_set_dma_params(dma_data->ch, &dma_params);
349 omap_set_dma_src_burst_mode(dma_data->ch, src_burst);
350 omap_set_dma_dest_burst_mode(dma_data->ch, dst_burst);
351 omap_set_dma_write_mode(dma_data->ch, OMAP_DMA_WRITE_LAST_NON_POSTED);
352
353 /*
354 * Prepare MUSB for DMA transfer
355 */
356 musb_ep_select(mbase, chdat->epnum);
357 if (chdat->tx) {
358 csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
359 csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB
360 | MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE);
361 csr &= ~MUSB_TXCSR_P_UNDERRUN;
362 musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
363 } else {
364 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
365 csr |= MUSB_RXCSR_DMAENAB;
366 csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE);
367 musb_writew(hw_ep->regs, MUSB_RXCSR,
368 csr | MUSB_RXCSR_P_WZC_BITS);
369 }
370
371 /*
372 * Start DMA transfer
373 */
374 omap_start_dma(dma_data->ch);
375
376 if (chdat->tx) {
377 /* Send transfer_packet_sz packets at a time */
378 psize = musb_readl(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET);
379 psize &= ~0x7ff;
380 psize |= chdat->transfer_packet_sz;
381 musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, psize);
382
383 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
384 TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
385 } else {
386 /* Receive transfer_packet_sz packets at a time */
387 psize = musb_readl(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET);
388 psize &= ~(0x7ff << 16);
389 psize |= (chdat->transfer_packet_sz << 16);
390 musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, psize);
391
392 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
393 TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
394 }
395
396 return true;
397 }
398
399 static int tusb_omap_dma_abort(struct dma_channel *channel)
400 {
401 struct tusb_omap_dma_ch *chdat = to_chdat(channel);
402
403 if (chdat->dma_data)
404 omap_stop_dma(chdat->dma_data->ch);
405
406 channel->status = MUSB_DMA_STATUS_FREE;
407
408 return 0;
409 }
410
411 static inline int tusb_omap_dma_allocate_dmareq(struct tusb_omap_dma_ch *chdat)
412 {
413 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
414 int i, dmareq_nr = -1;
415
416 for (i = 0; i < MAX_DMAREQ; i++) {
417 int cur = (reg & (0xf << (i * 5))) >> (i * 5);
418 if (cur == 0) {
419 dmareq_nr = i;
420 break;
421 }
422 }
423
424 if (dmareq_nr == -1)
425 return -EAGAIN;
426
427 reg |= (chdat->epnum << (dmareq_nr * 5));
428 if (chdat->tx)
429 reg |= ((1 << 4) << (dmareq_nr * 5));
430 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
431
432 chdat->dma_data = &chdat->tusb_dma->dma_pool[dmareq_nr];
433
434 return 0;
435 }
436
437 static inline void tusb_omap_dma_free_dmareq(struct tusb_omap_dma_ch *chdat)
438 {
439 u32 reg;
440
441 if (!chdat || !chdat->dma_data || chdat->dma_data->dmareq < 0)
442 return;
443
444 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
445 reg &= ~(0x1f << (chdat->dma_data->dmareq * 5));
446 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
447
448 chdat->dma_data = NULL;
449 }
450
451 static struct dma_channel *dma_channel_pool[MAX_DMAREQ];
452
453 static struct dma_channel *
454 tusb_omap_dma_allocate(struct dma_controller *c,
455 struct musb_hw_ep *hw_ep,
456 u8 tx)
457 {
458 int ret, i;
459 struct tusb_omap_dma *tusb_dma;
460 struct musb *musb;
461 struct dma_channel *channel = NULL;
462 struct tusb_omap_dma_ch *chdat = NULL;
463 struct tusb_dma_data *dma_data = NULL;
464
465 tusb_dma = container_of(c, struct tusb_omap_dma, controller);
466 musb = tusb_dma->controller.musb;
467
468 /* REVISIT: Why does dmareq5 not work? */
469 if (hw_ep->epnum == 0) {
470 dev_dbg(musb->controller, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx");
471 return NULL;
472 }
473
474 for (i = 0; i < MAX_DMAREQ; i++) {
475 struct dma_channel *ch = dma_channel_pool[i];
476 if (ch->status == MUSB_DMA_STATUS_UNKNOWN) {
477 ch->status = MUSB_DMA_STATUS_FREE;
478 channel = ch;
479 chdat = ch->private_data;
480 break;
481 }
482 }
483
484 if (!channel)
485 return NULL;
486
487 chdat->musb = tusb_dma->controller.musb;
488 chdat->tbase = tusb_dma->tbase;
489 chdat->hw_ep = hw_ep;
490 chdat->epnum = hw_ep->epnum;
491 chdat->completed_len = 0;
492 chdat->tusb_dma = tusb_dma;
493 if (tx)
494 chdat->tx = 1;
495 else
496 chdat->tx = 0;
497
498 channel->max_len = 0x7fffffff;
499 channel->desired_mode = 0;
500 channel->actual_len = 0;
501
502 if (!chdat->dma_data) {
503 if (tusb_dma->multichannel) {
504 ret = tusb_omap_dma_allocate_dmareq(chdat);
505 if (ret != 0)
506 goto free_dmareq;
507 } else {
508 chdat->dma_data = &tusb_dma->dma_pool[0];
509 }
510 }
511
512 dma_data = chdat->dma_data;
513
514 dev_dbg(musb->controller, "ep%i %s dma: %s dma%i dmareq%i sync%i\n",
515 chdat->epnum,
516 chdat->tx ? "tx" : "rx",
517 tusb_dma->multichannel ? "shared" : "dedicated",
518 dma_data->ch, dma_data->dmareq, dma_data->sync_dev);
519
520 return channel;
521
522 free_dmareq:
523 tusb_omap_dma_free_dmareq(chdat);
524
525 dev_dbg(musb->controller, "ep%i: Could not get a DMA channel\n", chdat->epnum);
526 channel->status = MUSB_DMA_STATUS_UNKNOWN;
527
528 return NULL;
529 }
530
531 static void tusb_omap_dma_release(struct dma_channel *channel)
532 {
533 struct tusb_omap_dma_ch *chdat = to_chdat(channel);
534 struct musb *musb = chdat->musb;
535
536 dev_dbg(musb->controller, "ep%i ch%i\n", chdat->epnum,
537 chdat->dma_data->ch);
538
539 channel->status = MUSB_DMA_STATUS_UNKNOWN;
540
541 omap_stop_dma(chdat->dma_data->ch);
542 tusb_omap_dma_free_dmareq(chdat);
543
544 channel = NULL;
545 }
546
547 void tusb_dma_controller_destroy(struct dma_controller *c)
548 {
549 struct tusb_omap_dma *tusb_dma;
550 int i;
551
552 tusb_dma = container_of(c, struct tusb_omap_dma, controller);
553 for (i = 0; i < MAX_DMAREQ; i++) {
554 struct dma_channel *ch = dma_channel_pool[i];
555 if (ch) {
556 kfree(ch->private_data);
557 kfree(ch);
558 }
559
560 /* Free up the DMA channels */
561 if (tusb_dma && tusb_dma->dma_pool[i].ch >= 0)
562 omap_free_dma(tusb_dma->dma_pool[i].ch);
563 }
564
565 kfree(tusb_dma);
566 }
567 EXPORT_SYMBOL_GPL(tusb_dma_controller_destroy);
568
569 static int tusb_omap_allocate_dma_pool(struct tusb_omap_dma *tusb_dma)
570 {
571 int i;
572 int ret = 0;
573 const int sync_dev[6] = {
574 OMAP24XX_DMA_EXT_DMAREQ0,
575 OMAP24XX_DMA_EXT_DMAREQ1,
576 OMAP242X_DMA_EXT_DMAREQ2,
577 OMAP242X_DMA_EXT_DMAREQ3,
578 OMAP242X_DMA_EXT_DMAREQ4,
579 OMAP242X_DMA_EXT_DMAREQ5,
580 };
581
582 for (i = 0; i < MAX_DMAREQ; i++) {
583 struct tusb_dma_data *dma_data = &tusb_dma->dma_pool[i];
584
585 /*
586 * Request DMA channels:
587 * - one channel in case of non multichannel mode
588 * - MAX_DMAREQ number of channels in multichannel mode
589 */
590 if (i == 0 || tusb_dma->multichannel) {
591 char ch_name[8];
592
593 sprintf(ch_name, "dmareq%d", i);
594 dma_data->sync_dev = sync_dev[i];
595 dma_data->ch = -1;
596 /* callback data is ngoing to be set later */
597 ret = omap_request_dma(dma_data->sync_dev, ch_name,
598 tusb_omap_dma_cb, NULL, &dma_data->ch);
599 if (ret != 0) {
600 dev_err(tusb_dma->controller.musb->controller,
601 "Failed to request %s\n", ch_name);
602 goto dma_error;
603 }
604
605 dma_data->dmareq = i;
606 } else {
607 dma_data->dmareq = -1;
608 dma_data->sync_dev = -1;
609 dma_data->ch = -1;
610 }
611 }
612
613 return 0;
614
615 dma_error:
616 for (; i >= 0; i--) {
617 struct tusb_dma_data *dma_data = &tusb_dma->dma_pool[i];
618
619 if (dma_data->ch >= 0)
620 omap_free_dma(dma_data->ch);
621 }
622
623 return ret;
624 }
625
626 struct dma_controller *
627 tusb_dma_controller_create(struct musb *musb, void __iomem *base)
628 {
629 void __iomem *tbase = musb->ctrl_base;
630 struct tusb_omap_dma *tusb_dma;
631 int i;
632
633 /* REVISIT: Get dmareq lines used from board-*.c */
634
635 musb_writel(musb->ctrl_base, TUSB_DMA_INT_MASK, 0x7fffffff);
636 musb_writel(musb->ctrl_base, TUSB_DMA_EP_MAP, 0);
637
638 musb_writel(tbase, TUSB_DMA_REQ_CONF,
639 TUSB_DMA_REQ_CONF_BURST_SIZE(2)
640 | TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f)
641 | TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
642
643 tusb_dma = kzalloc(sizeof(struct tusb_omap_dma), GFP_KERNEL);
644 if (!tusb_dma)
645 goto out;
646
647 tusb_dma->controller.musb = musb;
648 tusb_dma->tbase = musb->ctrl_base;
649
650 tusb_dma->controller.channel_alloc = tusb_omap_dma_allocate;
651 tusb_dma->controller.channel_release = tusb_omap_dma_release;
652 tusb_dma->controller.channel_program = tusb_omap_dma_program;
653 tusb_dma->controller.channel_abort = tusb_omap_dma_abort;
654
655 if (musb->tusb_revision >= TUSB_REV_30)
656 tusb_dma->multichannel = 1;
657
658 for (i = 0; i < MAX_DMAREQ; i++) {
659 struct dma_channel *ch;
660 struct tusb_omap_dma_ch *chdat;
661
662 ch = kzalloc(sizeof(struct dma_channel), GFP_KERNEL);
663 if (!ch)
664 goto cleanup;
665
666 dma_channel_pool[i] = ch;
667
668 chdat = kzalloc(sizeof(struct tusb_omap_dma_ch), GFP_KERNEL);
669 if (!chdat)
670 goto cleanup;
671
672 ch->status = MUSB_DMA_STATUS_UNKNOWN;
673 ch->private_data = chdat;
674 }
675
676 if (tusb_omap_allocate_dma_pool(tusb_dma))
677 goto cleanup;
678
679 return &tusb_dma->controller;
680
681 cleanup:
682 musb_dma_controller_destroy(&tusb_dma->controller);
683 out:
684 return NULL;
685 }
686 EXPORT_SYMBOL_GPL(tusb_dma_controller_create);
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