drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24
  25 #include "pp_debug.h"
  26 #include "smumgr.h"
  27 #include "smu_ucode_xfer_vi.h"
  28 #include "smu/smu_7_1_3_d.h"
  29 #include "smu/smu_7_1_3_sh_mask.h"
  30 #include "ppatomctrl.h"
  31 #include "cgs_common.h"
  32 #include "smu7_ppsmc.h"
  33 #include "smu7_smumgr.h"
  34
  35 #define SMU7_SMC_SIZE 0x20000
  36
  37 static int smu7_set_smc_sram_address(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t limit)
  38 {
  39         PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL);
  40         PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL);
  41
  42         cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, smc_addr);
  43         PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); /* on ci, SMC_IND_ACCESS_CNTL is different */
  44         return 0;
  45 }
  46
  47
  48 int smu7_copy_bytes_from_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit)
  49 {
  50         uint32_t data;
  51         uint32_t addr;
  52         uint8_t *dest_byte;
  53         uint8_t i, data_byte[4] = {0};
  54         uint32_t *pdata = (uint32_t *)&data_byte;
  55
  56         PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -EINVAL);
  57         PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -EINVAL);
  58
  59         addr = smc_start_address;
  60
  61         while (byte_count >= 4) {
  62                 smu7_read_smc_sram_dword(hwmgr, addr, &data, limit);
  63
  64                 *dest = PP_SMC_TO_HOST_UL(data);
  65
  66                 dest += 1;
  67                 byte_count -= 4;
  68                 addr += 4;
  69         }
  70
  71         if (byte_count) {
  72                 smu7_read_smc_sram_dword(hwmgr, addr, &data, limit);
  73                 *pdata = PP_SMC_TO_HOST_UL(data);
  74         /* Cast dest into byte type in dest_byte.  This way, we don't overflow if the allocated memory is not 4-byte aligned. */
  75                 dest_byte = (uint8_t *)dest;
  76                 for (i = 0; i < byte_count; i++)
  77                         dest_byte[i] = data_byte[i];
  78         }
  79
  80         return 0;
  81 }
  82
  83
  84 int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
  85                                 const uint8_t *src, uint32_t byte_count, uint32_t limit)
  86 {
  87         int result;
  88         uint32_t data = 0;
  89         uint32_t original_data;
  90         uint32_t addr = 0;
  91         uint32_t extra_shift;
  92
  93         PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -EINVAL);
  94         PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -EINVAL);
  95
  96         addr = smc_start_address;
  97
  98         while (byte_count >= 4) {
  99         /* Bytes are written into the SMC addres space with the MSB first. */
 100                 data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
 101
 102                 result = smu7_set_smc_sram_address(hwmgr, addr, limit);
 103
 104                 if (0 != result)
 105                         return result;
 106
 107                 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, data);
 108
 109                 src += 4;
 110                 byte_count -= 4;
 111                 addr += 4;
 112         }
 113
 114         if (0 != byte_count) {
 115
 116                 data = 0;
 117
 118                 result = smu7_set_smc_sram_address(hwmgr, addr, limit);
 119
 120                 if (0 != result)
 121                         return result;
 122
 123
 124                 original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11);
 125
 126                 extra_shift = 8 * (4 - byte_count);
 127
 128                 while (byte_count > 0) {
 129                         /* Bytes are written into the SMC addres space with the MSB first. */
 130                         data = (0x100 * data) + *src++;
 131                         byte_count--;
 132                 }
 133
 134                 data <<= extra_shift;
 135
 136                 data |= (original_data & ~((~0UL) << extra_shift));
 137
 138                 result = smu7_set_smc_sram_address(hwmgr, addr, limit);
 139
 140                 if (0 != result)
 141                         return result;
 142
 143                 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, data);
 144         }
 145
 146         return 0;
 147 }
 148
 149
 150 int smu7_program_jump_on_start(struct pp_hwmgr *hwmgr)
 151 {
 152         static const unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 };
 153
 154         smu7_copy_bytes_to_smc(hwmgr, 0x0, data, 4, sizeof(data)+1);
 155
 156         return 0;
 157 }
 158
 159 bool smu7_is_smc_ram_running(struct pp_hwmgr *hwmgr)
 160 {
 161         return ((0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
 162         && (0x20100 <= cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMC_PC_C)));
 163 }
 164
 165 int smu7_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
 166 {
 167         int ret;
 168
 169         if (!smu7_is_smc_ram_running(hwmgr))
 170                 return -EINVAL;
 171
 172
 173         PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
 174
 175         ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);
 176
 177         if (ret != 1)
 178                 pr_info("\n failed to send pre message %x ret is %d \n",  msg, ret);
 179
 180         cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
 181
 182         PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
 183
 184         ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);
 185
 186         if (ret != 1)
 187                 pr_info("\n failed to send message %x ret is %d \n",  msg, ret);
 188
 189         return 0;
 190 }
 191
 192 int smu7_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg)
 193 {
 194         cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
 195
 196         return 0;
 197 }
 198
 199 int smu7_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter)
 200 {
 201         if (!smu7_is_smc_ram_running(hwmgr)) {
 202                 return -EINVAL;
 203         }
 204
 205         PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
 206
 207         cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter);
 208
 209         return smu7_send_msg_to_smc(hwmgr, msg);
 210 }
 211
 212 int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter)
 213 {
 214         cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter);
 215
 216         return smu7_send_msg_to_smc_without_waiting(hwmgr, msg);
 217 }
 218
 219 int smu7_send_msg_to_smc_offset(struct pp_hwmgr *hwmgr)
 220 {
 221         cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, 0x20000);
 222
 223         cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
 224
 225         PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
 226
 227         if (1 != PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP))
 228                 pr_info("Failed to send Message.\n");
 229
 230         return 0;
 231 }
 232
 233 int smu7_wait_for_smc_inactive(struct pp_hwmgr *hwmgr)
 234 {
 235         if (!smu7_is_smc_ram_running(hwmgr))
 236                 return -EINVAL;
 237
 238         PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0);
 239         return 0;
 240 }
 241
 242
 243 enum cgs_ucode_id smu7_convert_fw_type_to_cgs(uint32_t fw_type)
 244 {
 245         enum cgs_ucode_id result = CGS_UCODE_ID_MAXIMUM;
 246
 247         switch (fw_type) {
 248         case UCODE_ID_SMU:
 249                 result = CGS_UCODE_ID_SMU;
 250                 break;
 251         case UCODE_ID_SMU_SK:
 252                 result = CGS_UCODE_ID_SMU_SK;
 253                 break;
 254         case UCODE_ID_SDMA0:
 255                 result = CGS_UCODE_ID_SDMA0;
 256                 break;
 257         case UCODE_ID_SDMA1:
 258                 result = CGS_UCODE_ID_SDMA1;
 259                 break;
 260         case UCODE_ID_CP_CE:
 261                 result = CGS_UCODE_ID_CP_CE;
 262                 break;
 263         case UCODE_ID_CP_PFP:
 264                 result = CGS_UCODE_ID_CP_PFP;
 265                 break;
 266         case UCODE_ID_CP_ME:
 267                 result = CGS_UCODE_ID_CP_ME;
 268                 break;
 269         case UCODE_ID_CP_MEC:
 270                 result = CGS_UCODE_ID_CP_MEC;
 271                 break;
 272         case UCODE_ID_CP_MEC_JT1:
 273                 result = CGS_UCODE_ID_CP_MEC_JT1;
 274                 break;
 275         case UCODE_ID_CP_MEC_JT2:
 276                 result = CGS_UCODE_ID_CP_MEC_JT2;
 277                 break;
 278         case UCODE_ID_RLC_G:
 279                 result = CGS_UCODE_ID_RLC_G;
 280                 break;
 281         case UCODE_ID_MEC_STORAGE:
 282                 result = CGS_UCODE_ID_STORAGE;
 283                 break;
 284         default:
 285                 break;
 286         }
 287
 288         return result;
 289 }
 290
 291
 292 int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t *value, uint32_t limit)
 293 {
 294         int result;
 295
 296         result = smu7_set_smc_sram_address(hwmgr, smc_addr, limit);
 297
 298         if (result)
 299                 return result;
 300
 301         *value = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11);
 302         return 0;
 303 }
 304
 305 int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t value, uint32_t limit)
 306 {
 307         int result;
 308
 309         result = smu7_set_smc_sram_address(hwmgr, smc_addr, limit);
 310
 311         if (result)
 312                 return result;
 313
 314         cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, value);
 315
 316         return 0;
 317 }
 318
 319 /* Convert the firmware type to SMU type mask. For MEC, we need to check all MEC related type */
 320
 321 static uint32_t smu7_get_mask_for_firmware_type(uint32_t fw_type)
 322 {
 323         uint32_t result = 0;
 324
 325         switch (fw_type) {
 326         case UCODE_ID_SDMA0:
 327                 result = UCODE_ID_SDMA0_MASK;
 328                 break;
 329         case UCODE_ID_SDMA1:
 330                 result = UCODE_ID_SDMA1_MASK;
 331                 break;
 332         case UCODE_ID_CP_CE:
 333                 result = UCODE_ID_CP_CE_MASK;
 334                 break;
 335         case UCODE_ID_CP_PFP:
 336                 result = UCODE_ID_CP_PFP_MASK;
 337                 break;
 338         case UCODE_ID_CP_ME:
 339                 result = UCODE_ID_CP_ME_MASK;
 340                 break;
 341         case UCODE_ID_CP_MEC:
 342         case UCODE_ID_CP_MEC_JT1:
 343         case UCODE_ID_CP_MEC_JT2:
 344                 result = UCODE_ID_CP_MEC_MASK;
 345                 break;
 346         case UCODE_ID_RLC_G:
 347                 result = UCODE_ID_RLC_G_MASK;
 348                 break;
 349         default:
 350                 pr_info("UCode type is out of range! \n");
 351                 result = 0;
 352         }
 353
 354         return result;
 355 }
 356
 357 static int smu7_populate_single_firmware_entry(struct pp_hwmgr *hwmgr,
 358                                                 uint32_t fw_type,
 359                                                 struct SMU_Entry *entry)
 360 {
 361         int result = 0;
 362         struct cgs_firmware_info info = {0};
 363
 364         result = cgs_get_firmware_info(hwmgr->device,
 365                                 smu7_convert_fw_type_to_cgs(fw_type),
 366                                 &info);
 367
 368         if (!result) {
 369                 entry->version = info.fw_version;
 370                 entry->id = (uint16_t)fw_type;
 371                 entry->image_addr_high = smu_upper_32_bits(info.mc_addr);
 372                 entry->image_addr_low = smu_lower_32_bits(info.mc_addr);
 373                 entry->meta_data_addr_high = 0;
 374                 entry->meta_data_addr_low = 0;
 375
 376                 /* digest need be excluded out */
 377                 if (cgs_is_virtualization_enabled(hwmgr->device))
 378                         info.image_size -= 20;
 379                 entry->data_size_byte = info.image_size;
 380                 entry->num_register_entries = 0;
 381         }
 382
 383         if ((fw_type == UCODE_ID_RLC_G)
 384                 || (fw_type == UCODE_ID_CP_MEC))
 385                 entry->flags = 1;
 386         else
 387                 entry->flags = 0;
 388
 389         return 0;
 390 }
 391
 392 int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
 393 {
 394         struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
 395         uint32_t fw_to_load;
 396         int result = 0;
 397         struct SMU_DRAMData_TOC *toc;
 398
 399         if (!hwmgr->reload_fw) {
 400                 pr_info("skip reloading...\n");
 401                 return 0;
 402         }
 403
 404         if (smu_data->soft_regs_start)
 405                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 406                                         smu_data->soft_regs_start + smum_get_offsetof(hwmgr,
 407                                         SMU_SoftRegisters, UcodeLoadStatus),
 408                                         0x0);
 409
 410         if (hwmgr->chip_id > CHIP_TOPAZ) { /* add support for Topaz */
 411                 if (!cgs_is_virtualization_enabled(hwmgr->device)) {
 412                         smu7_send_msg_to_smc_with_parameter(hwmgr,
 413                                                 PPSMC_MSG_SMU_DRAM_ADDR_HI,
 414                                                 smu_data->smu_buffer.mc_addr_high);
 415                         smu7_send_msg_to_smc_with_parameter(hwmgr,
 416                                                 PPSMC_MSG_SMU_DRAM_ADDR_LO,
 417                                                 smu_data->smu_buffer.mc_addr_low);
 418                 }
 419                 fw_to_load = UCODE_ID_RLC_G_MASK
 420                            + UCODE_ID_SDMA0_MASK
 421                            + UCODE_ID_SDMA1_MASK
 422                            + UCODE_ID_CP_CE_MASK
 423                            + UCODE_ID_CP_ME_MASK
 424                            + UCODE_ID_CP_PFP_MASK
 425                            + UCODE_ID_CP_MEC_MASK;
 426         } else {
 427                 fw_to_load = UCODE_ID_RLC_G_MASK
 428                            + UCODE_ID_SDMA0_MASK
 429                            + UCODE_ID_SDMA1_MASK
 430                            + UCODE_ID_CP_CE_MASK
 431                            + UCODE_ID_CP_ME_MASK
 432                            + UCODE_ID_CP_PFP_MASK
 433                            + UCODE_ID_CP_MEC_MASK
 434                            + UCODE_ID_CP_MEC_JT1_MASK
 435                            + UCODE_ID_CP_MEC_JT2_MASK;
 436         }
 437
 438         toc = (struct SMU_DRAMData_TOC *)smu_data->header;
 439         toc->num_entries = 0;
 440         toc->structure_version = 1;
 441
 442         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
 443                                 UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]),
 444                                 "Failed to Get Firmware Entry.", return -EINVAL);
 445         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
 446                                 UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]),
 447                                 "Failed to Get Firmware Entry.", return -EINVAL);
 448         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
 449                                 UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]),
 450                                 "Failed to Get Firmware Entry.", return -EINVAL);
 451         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
 452                                 UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]),
 453                                 "Failed to Get Firmware Entry.", return -EINVAL);
 454         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
 455                                 UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]),
 456                                 "Failed to Get Firmware Entry.", return -EINVAL);
 457         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
 458                                 UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]),
 459                                 "Failed to Get Firmware Entry.", return -EINVAL);
 460         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
 461                                 UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]),
 462                                 "Failed to Get Firmware Entry.", return -EINVAL);
 463         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
 464                                 UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]),
 465                                 "Failed to Get Firmware Entry.", return -EINVAL);
 466         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
 467                                 UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]),
 468                                 "Failed to Get Firmware Entry.", return -EINVAL);
 469         if (cgs_is_virtualization_enabled(hwmgr->device))
 470                 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
 471                                 UCODE_ID_MEC_STORAGE, &toc->entry[toc->num_entries++]),
 472                                 "Failed to Get Firmware Entry.", return -EINVAL);
 473
 474         smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high);
 475         smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low);
 476
 477         if (smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_LoadUcodes, fw_to_load))
 478                 pr_err("Fail to Request SMU Load uCode");
 479
 480         return result;
 481 }
 482
 483 /* Check if the FW has been loaded, SMU will not return if loading has not finished. */
 484 int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type)
 485 {
 486         struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
 487         uint32_t fw_mask = smu7_get_mask_for_firmware_type(fw_type);
 488         uint32_t ret;
 489
 490         ret = phm_wait_on_indirect_register(hwmgr, mmSMC_IND_INDEX_11,
 491                                         smu_data->soft_regs_start + smum_get_offsetof(hwmgr,
 492                                         SMU_SoftRegisters, UcodeLoadStatus),
 493                                         fw_mask, fw_mask);
 494         return ret;
 495 }
 496
 497 int smu7_reload_firmware(struct pp_hwmgr *hwmgr)
 498 {
 499         return hwmgr->smumgr_funcs->start_smu(hwmgr);
 500 }
 501
 502 static int smu7_upload_smc_firmware_data(struct pp_hwmgr *hwmgr, uint32_t length, uint32_t *src, uint32_t limit)
 503 {
 504         uint32_t byte_count = length;
 505
 506         PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL);
 507
 508         cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, 0x20000);
 509         PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1);
 510
 511         for (; byte_count >= 4; byte_count -= 4)
 512                 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, *src++);
 513
 514         PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);
 515
 516         PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be divisible by 4.", return -EINVAL);
 517
 518         return 0;
 519 }
 520
 521
 522 int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr)
 523 {
 524         int result = 0;
 525         struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
 526
 527         struct cgs_firmware_info info = {0};
 528
 529         if (smu_data->security_hard_key == 1)
 530                 cgs_get_firmware_info(hwmgr->device,
 531                         smu7_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
 532         else
 533                 cgs_get_firmware_info(hwmgr->device,
 534                         smu7_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info);
 535
 536         hwmgr->is_kicker = info.is_kicker;
 537
 538         result = smu7_upload_smc_firmware_data(hwmgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZE);
 539
 540         return result;
 541 }
 542
 543 int smu7_init(struct pp_hwmgr *hwmgr)
 544 {
 545         struct smu7_smumgr *smu_data;
 546         uint8_t *internal_buf;
 547         uint64_t mc_addr = 0;
 548
 549         /* Allocate memory for backend private data */
 550         smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
 551         smu_data->header_buffer.data_size =
 552                         ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
 553
 554 /* Allocate FW image data structure and header buffer and
 555  * send the header buffer address to SMU */
 556         smu_allocate_memory(hwmgr->device,
 557                 smu_data->header_buffer.data_size,
 558                 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
 559                 PAGE_SIZE,
 560                 &mc_addr,
 561                 &smu_data->header_buffer.kaddr,
 562                 &smu_data->header_buffer.handle);
 563
 564         smu_data->header = smu_data->header_buffer.kaddr;
 565         smu_data->header_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
 566         smu_data->header_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
 567
 568         PP_ASSERT_WITH_CODE((NULL != smu_data->header),
 569                 "Out of memory.",
 570                 kfree(hwmgr->smu_backend);
 571                 cgs_free_gpu_mem(hwmgr->device,
 572                 (cgs_handle_t)smu_data->header_buffer.handle);
 573                 return -EINVAL);
 574
 575         if (cgs_is_virtualization_enabled(hwmgr->device))
 576                 return 0;
 577
 578         smu_data->smu_buffer.data_size = 200*4096;
 579         smu_allocate_memory(hwmgr->device,
 580                 smu_data->smu_buffer.data_size,
 581                 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
 582                 PAGE_SIZE,
 583                 &mc_addr,
 584                 &smu_data->smu_buffer.kaddr,
 585                 &smu_data->smu_buffer.handle);
 586
 587         internal_buf = smu_data->smu_buffer.kaddr;
 588         smu_data->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
 589         smu_data->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
 590
 591         PP_ASSERT_WITH_CODE((NULL != internal_buf),
 592                 "Out of memory.",
 593                 kfree(hwmgr->smu_backend);
 594                 cgs_free_gpu_mem(hwmgr->device,
 595                 (cgs_handle_t)smu_data->smu_buffer.handle);
 596                 return -EINVAL);
 597
 598         if (smum_is_hw_avfs_present(hwmgr))
 599                 smu_data->avfs.avfs_btc_status = AVFS_BTC_BOOT;
 600         else
 601                 smu_data->avfs.avfs_btc_status = AVFS_BTC_NOTSUPPORTED;
 602
 603         return 0;
 604 }
 605
 606
 607 int smu7_smu_fini(struct pp_hwmgr *hwmgr)
 608 {
 609         kfree(hwmgr->smu_backend);
 610         hwmgr->smu_backend = NULL;
 611         cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU);
 612         return 0;
 613 }