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rtl8xxxu: Implement 8723bu power on sequence
[linux-2.6/btrfs-unstable.git] / drivers / net / wireless / realtek / rtl8xxxu / rtl8xxxu.c
blob1f30b3bb5daf7ce8e3449a83f51200c2bc972f79
1 /*
2 * RTL8XXXU mac80211 USB driver
3 *
4 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
5 *
6 * Portions, notably calibration code:
7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
8 *
9 * This driver was written as a replacement for the vendor provided
10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
11 * their programming interface, I have started adding support for
12 * additional 8xxx chips like the 8192cu, 8188cus, etc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of version 2 of the GNU General Public License as
16 * published by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * more details.
22 */
23
24 #include <linux/init.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/errno.h>
28 #include <linux/slab.h>
29 #include <linux/module.h>
30 #include <linux/spinlock.h>
31 #include <linux/list.h>
32 #include <linux/usb.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/wireless.h>
37 #include <linux/firmware.h>
38 #include <linux/moduleparam.h>
39 #include <net/mac80211.h>
40 #include "rtl8xxxu.h"
41 #include "rtl8xxxu_regs.h"
42
43 #define DRIVER_NAME "rtl8xxxu"
44
45 static int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
46 static bool rtl8xxxu_ht40_2g;
47
48 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
49 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
50 MODULE_LICENSE("GPL");
51 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
52 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
53 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
54 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
55 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
56 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
57 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
58 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
59 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
60
61 module_param_named(debug, rtl8xxxu_debug, int, 0600);
62 MODULE_PARM_DESC(debug, "Set debug mask");
63 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
64 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
65
66 #define USB_VENDOR_ID_REALTEK 0x0bda
67 /* Minimum IEEE80211_MAX_FRAME_LEN */
68 #define RTL_RX_BUFFER_SIZE IEEE80211_MAX_FRAME_LEN
69 #define RTL8XXXU_RX_URBS 32
70 #define RTL8XXXU_RX_URB_PENDING_WATER 8
71 #define RTL8XXXU_TX_URBS 64
72 #define RTL8XXXU_TX_URB_LOW_WATER 25
73 #define RTL8XXXU_TX_URB_HIGH_WATER 32
74
75 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
76 struct rtl8xxxu_rx_urb *rx_urb);
77
78 static struct ieee80211_rate rtl8xxxu_rates[] = {
79 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
80 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
81 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
82 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
83 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
84 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
85 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
86 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
87 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
88 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
89 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
90 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
91 };
92
93 static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
94 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412,
95 .hw_value = 1, .max_power = 30 },
96 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417,
97 .hw_value = 2, .max_power = 30 },
98 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422,
99 .hw_value = 3, .max_power = 30 },
100 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427,
101 .hw_value = 4, .max_power = 30 },
102 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432,
103 .hw_value = 5, .max_power = 30 },
104 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437,
105 .hw_value = 6, .max_power = 30 },
106 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442,
107 .hw_value = 7, .max_power = 30 },
108 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447,
109 .hw_value = 8, .max_power = 30 },
110 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452,
111 .hw_value = 9, .max_power = 30 },
112 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457,
113 .hw_value = 10, .max_power = 30 },
114 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462,
115 .hw_value = 11, .max_power = 30 },
116 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467,
117 .hw_value = 12, .max_power = 30 },
118 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472,
119 .hw_value = 13, .max_power = 30 },
120 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484,
121 .hw_value = 14, .max_power = 30 }
122 };
123
124 static struct ieee80211_supported_band rtl8xxxu_supported_band = {
125 .channels = rtl8xxxu_channels_2g,
126 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
127 .bitrates = rtl8xxxu_rates,
128 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
129 };
130
131 static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
132 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
133 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
134 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
135 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
136 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
137 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
138 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
139 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
140 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
141 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
142 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
143 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
144 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
145 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
146 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
147 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
148 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
149 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
150 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
151 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
152 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
153 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
154 };
155
156 static struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = {
157 {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
158 {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
159 {0x430, 0x00}, {0x431, 0x00},
160 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
161 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
162 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
163 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
164 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
165 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
166 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
167 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
168 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
169 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
170 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
171 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
172 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
173 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
174 {0x516, 0x0a}, {0x525, 0x4f},
175 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50},
176 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
177 {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff},
178 {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff},
179 {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
180 {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00},
181 {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
182 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
183 {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04},
184 {0xffff, 0xff},
185 };
186
187 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
188 {0x800, 0x80040000}, {0x804, 0x00000003},
189 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
190 {0x810, 0x10001331}, {0x814, 0x020c3d10},
191 {0x818, 0x02200385}, {0x81c, 0x00000000},
192 {0x820, 0x01000100}, {0x824, 0x00390004},
193 {0x828, 0x00000000}, {0x82c, 0x00000000},
194 {0x830, 0x00000000}, {0x834, 0x00000000},
195 {0x838, 0x00000000}, {0x83c, 0x00000000},
196 {0x840, 0x00010000}, {0x844, 0x00000000},
197 {0x848, 0x00000000}, {0x84c, 0x00000000},
198 {0x850, 0x00000000}, {0x854, 0x00000000},
199 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
200 {0x860, 0x66f60110}, {0x864, 0x061f0130},
201 {0x868, 0x00000000}, {0x86c, 0x32323200},
202 {0x870, 0x07000760}, {0x874, 0x22004000},
203 {0x878, 0x00000808}, {0x87c, 0x00000000},
204 {0x880, 0xc0083070}, {0x884, 0x000004d5},
205 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
206 {0x890, 0x00000800}, {0x894, 0xfffffffe},
207 {0x898, 0x40302010}, {0x89c, 0x00706050},
208 {0x900, 0x00000000}, {0x904, 0x00000023},
209 {0x908, 0x00000000}, {0x90c, 0x81121111},
210 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
211 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
212 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
213 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
214 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
215 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
216 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
217 {0xa78, 0x00000900},
218 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
219 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
220 {0xc10, 0x08800000}, {0xc14, 0x40000100},
221 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
222 {0xc20, 0x00000000}, {0xc24, 0x00000000},
223 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
224 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
225 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
226 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
227 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
228 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
229 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
230 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
231 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
232 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
233 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
234 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
235 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
236 {0xc90, 0x00121820}, {0xc94, 0x00000000},
237 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
238 {0xca0, 0x00000000}, {0xca4, 0x00000080},
239 {0xca8, 0x00000000}, {0xcac, 0x00000000},
240 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
241 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
242 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
243 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
244 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
245 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
246 {0xce0, 0x00222222}, {0xce4, 0x00000000},
247 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
248 {0xd00, 0x00080740}, {0xd04, 0x00020401},
249 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
250 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
251 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
252 {0xd30, 0x00000000}, {0xd34, 0x80608000},
253 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
254 {0xd40, 0x00000000}, {0xd44, 0x00000000},
255 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
256 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
257 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
258 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
259 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
260 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
261 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
262 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
263 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
264 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
265 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
266 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
267 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
268 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
269 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
270 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
271 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
272 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
273 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
274 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
275 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
276 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
277 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
278 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
279 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
280 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
281 {0xf00, 0x00000300},
282 {0xffff, 0xffffffff},
283 };
284
285 static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = {
286 {0x800, 0x80040000}, {0x804, 0x00000003},
287 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
288 {0x810, 0x10001331}, {0x814, 0x020c3d10},
289 {0x818, 0x02200385}, {0x81c, 0x00000000},
290 {0x820, 0x01000100}, {0x824, 0x00190204},
291 {0x828, 0x00000000}, {0x82c, 0x00000000},
292 {0x830, 0x00000000}, {0x834, 0x00000000},
293 {0x838, 0x00000000}, {0x83c, 0x00000000},
294 {0x840, 0x00010000}, {0x844, 0x00000000},
295 {0x848, 0x00000000}, {0x84c, 0x00000000},
296 {0x850, 0x00000000}, {0x854, 0x00000000},
297 {0x858, 0x569a11a9}, {0x85c, 0x01000014},
298 {0x860, 0x66f60110}, {0x864, 0x061f0649},
299 {0x868, 0x00000000}, {0x86c, 0x27272700},
300 {0x870, 0x07000760}, {0x874, 0x25004000},
301 {0x878, 0x00000808}, {0x87c, 0x00000000},
302 {0x880, 0xb0000c1c}, {0x884, 0x00000001},
303 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
304 {0x890, 0x00000800}, {0x894, 0xfffffffe},
305 {0x898, 0x40302010}, {0x89c, 0x00706050},
306 {0x900, 0x00000000}, {0x904, 0x00000023},
307 {0x908, 0x00000000}, {0x90c, 0x81121111},
308 {0x910, 0x00000002}, {0x914, 0x00000201},
309 {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
310 {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
311 {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
312 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
313 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
314 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
315 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
316 {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
317 {0xa80, 0x21806490}, {0xb2c, 0x00000000},
318 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
319 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
320 {0xc10, 0x08800000}, {0xc14, 0x40000100},
321 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
322 {0xc20, 0x00000000}, {0xc24, 0x00000000},
323 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
324 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
325 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
326 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
327 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
328 {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
329 {0xc58, 0x00013149}, {0xc5c, 0x00250492},
330 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
331 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
332 {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
333 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
334 {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
335 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
336 {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
337 {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
338 {0xca0, 0x00000000}, {0xca4, 0x000300a0},
339 {0xca8, 0x00000000}, {0xcac, 0x00000000},
340 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
341 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
342 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
343 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
344 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
345 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
346 {0xce0, 0x00222222}, {0xce4, 0x00000000},
347 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
348 {0xd00, 0x00000740}, {0xd04, 0x40020401},
349 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
350 {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
351 {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
352 {0xd30, 0x00000000}, {0xd34, 0x80608000},
353 {0xd38, 0x00000000}, {0xd3c, 0x00127353},
354 {0xd40, 0x00000000}, {0xd44, 0x00000000},
355 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
356 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
357 {0xd58, 0x00000282}, {0xd5c, 0x30032064},
358 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
359 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
360 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
361 {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
362 {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
363 {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
364 {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
365 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
366 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
367 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
368 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
369 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
370 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
371 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
372 {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
373 {0xe70, 0x00c00096}, {0xe74, 0x01000056},
374 {0xe78, 0x01000014}, {0xe7c, 0x01000056},
375 {0xe80, 0x01000014}, {0xe84, 0x00c00096},
376 {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
377 {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
378 {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
379 {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
380 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
381 {0xf00, 0x00000300},
382 {0x820, 0x01000100}, {0x800, 0x83040000},
383 {0xffff, 0xffffffff},
384 };
385
386 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
387 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
388 {0x800, 0x80040002}, {0x804, 0x00000003},
389 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
390 {0x810, 0x10000330}, {0x814, 0x020c3d10},
391 {0x818, 0x02200385}, {0x81c, 0x00000000},
392 {0x820, 0x01000100}, {0x824, 0x00390004},
393 {0x828, 0x01000100}, {0x82c, 0x00390004},
394 {0x830, 0x27272727}, {0x834, 0x27272727},
395 {0x838, 0x27272727}, {0x83c, 0x27272727},
396 {0x840, 0x00010000}, {0x844, 0x00010000},
397 {0x848, 0x27272727}, {0x84c, 0x27272727},
398 {0x850, 0x00000000}, {0x854, 0x00000000},
399 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
400 {0x860, 0x66e60230}, {0x864, 0x061f0130},
401 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
402 {0x870, 0x07000700}, {0x874, 0x22184000},
403 {0x878, 0x08080808}, {0x87c, 0x00000000},
404 {0x880, 0xc0083070}, {0x884, 0x000004d5},
405 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
406 {0x890, 0x00000800}, {0x894, 0xfffffffe},
407 {0x898, 0x40302010}, {0x89c, 0x00706050},
408 {0x900, 0x00000000}, {0x904, 0x00000023},
409 {0x908, 0x00000000}, {0x90c, 0x81121313},
410 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
411 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
412 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
413 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
414 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
415 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
416 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
417 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
418 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
419 {0xc10, 0x08800000}, {0xc14, 0x40000100},
420 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
421 {0xc20, 0x00000000}, {0xc24, 0x00000000},
422 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
423 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
424 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
425 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
426 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
427 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
428 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
429 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
430 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
431 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
432 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
433 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
434 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
435 {0xc90, 0x00121820}, {0xc94, 0x00000000},
436 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
437 {0xca0, 0x00000000}, {0xca4, 0x00000080},
438 {0xca8, 0x00000000}, {0xcac, 0x00000000},
439 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
440 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
441 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
442 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
443 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
444 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
445 {0xce0, 0x00222222}, {0xce4, 0x00000000},
446 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
447 {0xd00, 0x00080740}, {0xd04, 0x00020403},
448 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
449 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
450 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
451 {0xd30, 0x00000000}, {0xd34, 0x80608000},
452 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
453 {0xd40, 0x00000000}, {0xd44, 0x00000000},
454 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
455 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
456 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
457 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
458 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
459 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
460 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
461 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
462 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
463 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
464 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
465 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
466 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
467 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
468 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
469 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
470 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
471 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
472 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
473 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
474 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
475 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
476 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
477 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
478 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
479 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
480 {0xf00, 0x00000300},
481 {0xffff, 0xffffffff},
482 };
483
484 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
485 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
486 {0x040, 0x000c0004}, {0x800, 0x80040000},
487 {0x804, 0x00000001}, {0x808, 0x0000fc00},
488 {0x80c, 0x0000000a}, {0x810, 0x10005388},
489 {0x814, 0x020c3d10}, {0x818, 0x02200385},
490 {0x81c, 0x00000000}, {0x820, 0x01000100},
491 {0x824, 0x00390204}, {0x828, 0x00000000},
492 {0x82c, 0x00000000}, {0x830, 0x00000000},
493 {0x834, 0x00000000}, {0x838, 0x00000000},
494 {0x83c, 0x00000000}, {0x840, 0x00010000},
495 {0x844, 0x00000000}, {0x848, 0x00000000},
496 {0x84c, 0x00000000}, {0x850, 0x00000000},
497 {0x854, 0x00000000}, {0x858, 0x569a569a},
498 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
499 {0x864, 0x061f0130}, {0x868, 0x00000000},
500 {0x86c, 0x20202000}, {0x870, 0x03000300},
501 {0x874, 0x22004000}, {0x878, 0x00000808},
502 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
503 {0x884, 0x000004d5}, {0x888, 0x00000000},
504 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
505 {0x894, 0xfffffffe}, {0x898, 0x40302010},
506 {0x89c, 0x00706050}, {0x900, 0x00000000},
507 {0x904, 0x00000023}, {0x908, 0x00000000},
508 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
509 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
510 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
511 {0xa14, 0x11144028}, {0xa18, 0x00881117},
512 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
513 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
514 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
515 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
516 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
517 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
518 {0xc14, 0x40000100}, {0xc18, 0x08800000},
519 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
520 {0xc24, 0x00000000}, {0xc28, 0x00000000},
521 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
522 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
523 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
524 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
525 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
526 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
527 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
528 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
529 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
530 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
531 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
532 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
533 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
534 {0xc94, 0x00000000}, {0xc98, 0x00121820},
535 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
536 {0xca4, 0x00000080}, {0xca8, 0x00000000},
537 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
538 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
539 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
540 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
541 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
542 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
543 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
544 {0xce4, 0x00000000}, {0xce8, 0x37644302},
545 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
546 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
547 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
548 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
549 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
550 {0xd34, 0x80608000}, {0xd38, 0x00000000},
551 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
552 {0xd44, 0x00000000}, {0xd48, 0x00000000},
553 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
554 {0xd54, 0x00000000}, {0xd58, 0x00000000},
555 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
556 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
557 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
558 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
559 {0xe00, 0x24242424}, {0xe04, 0x24242424},
560 {0xe08, 0x03902024}, {0xe10, 0x24242424},
561 {0xe14, 0x24242424}, {0xe18, 0x24242424},
562 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
563 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
564 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
565 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
566 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
567 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
568 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
569 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
570 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
571 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
572 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
573 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
574 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
575 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
576 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
577 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
578 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
579 {0xf00, 0x00000300},
580 {0xffff, 0xffffffff},
581 };
582
583 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
584 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
585 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
586 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
587 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
588 {0xc78, 0x78080001}, {0xc78, 0x77090001},
589 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
590 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
591 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
592 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
593 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
594 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
595 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
596 {0xc78, 0x68180001}, {0xc78, 0x67190001},
597 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
598 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
599 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
600 {0xc78, 0x60200001}, {0xc78, 0x49210001},
601 {0xc78, 0x48220001}, {0xc78, 0x47230001},
602 {0xc78, 0x46240001}, {0xc78, 0x45250001},
603 {0xc78, 0x44260001}, {0xc78, 0x43270001},
604 {0xc78, 0x42280001}, {0xc78, 0x41290001},
605 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
606 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
607 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
608 {0xc78, 0x21300001}, {0xc78, 0x20310001},
609 {0xc78, 0x06320001}, {0xc78, 0x05330001},
610 {0xc78, 0x04340001}, {0xc78, 0x03350001},
611 {0xc78, 0x02360001}, {0xc78, 0x01370001},
612 {0xc78, 0x00380001}, {0xc78, 0x00390001},
613 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
614 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
615 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
616 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
617 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
618 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
619 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
620 {0xc78, 0x78480001}, {0xc78, 0x77490001},
621 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
622 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
623 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
624 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
625 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
626 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
627 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
628 {0xc78, 0x68580001}, {0xc78, 0x67590001},
629 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
630 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
631 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
632 {0xc78, 0x60600001}, {0xc78, 0x49610001},
633 {0xc78, 0x48620001}, {0xc78, 0x47630001},
634 {0xc78, 0x46640001}, {0xc78, 0x45650001},
635 {0xc78, 0x44660001}, {0xc78, 0x43670001},
636 {0xc78, 0x42680001}, {0xc78, 0x41690001},
637 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
638 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
639 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
640 {0xc78, 0x21700001}, {0xc78, 0x20710001},
641 {0xc78, 0x06720001}, {0xc78, 0x05730001},
642 {0xc78, 0x04740001}, {0xc78, 0x03750001},
643 {0xc78, 0x02760001}, {0xc78, 0x01770001},
644 {0xc78, 0x00780001}, {0xc78, 0x00790001},
645 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
646 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
647 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
648 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
649 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
650 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
651 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
652 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
653 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
654 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
655 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
656 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
657 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
658 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
659 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
660 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
661 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
662 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
663 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
664 {0xffff, 0xffffffff}
665 };
666
667 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
668 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
669 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
670 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
671 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
672 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
673 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
674 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
675 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
676 {0xc78, 0x73100001}, {0xc78, 0x72110001},
677 {0xc78, 0x71120001}, {0xc78, 0x70130001},
678 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
679 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
680 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
681 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
682 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
683 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
684 {0xc78, 0x63200001}, {0xc78, 0x62210001},
685 {0xc78, 0x61220001}, {0xc78, 0x60230001},
686 {0xc78, 0x46240001}, {0xc78, 0x45250001},
687 {0xc78, 0x44260001}, {0xc78, 0x43270001},
688 {0xc78, 0x42280001}, {0xc78, 0x41290001},
689 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
690 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
691 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
692 {0xc78, 0x21300001}, {0xc78, 0x20310001},
693 {0xc78, 0x06320001}, {0xc78, 0x05330001},
694 {0xc78, 0x04340001}, {0xc78, 0x03350001},
695 {0xc78, 0x02360001}, {0xc78, 0x01370001},
696 {0xc78, 0x00380001}, {0xc78, 0x00390001},
697 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
698 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
699 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
700 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
701 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
702 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
703 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
704 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
705 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
706 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
707 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
708 {0xc78, 0x73500001}, {0xc78, 0x72510001},
709 {0xc78, 0x71520001}, {0xc78, 0x70530001},
710 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
711 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
712 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
713 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
714 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
715 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
716 {0xc78, 0x63600001}, {0xc78, 0x62610001},
717 {0xc78, 0x61620001}, {0xc78, 0x60630001},
718 {0xc78, 0x46640001}, {0xc78, 0x45650001},
719 {0xc78, 0x44660001}, {0xc78, 0x43670001},
720 {0xc78, 0x42680001}, {0xc78, 0x41690001},
721 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
722 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
723 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
724 {0xc78, 0x21700001}, {0xc78, 0x20710001},
725 {0xc78, 0x06720001}, {0xc78, 0x05730001},
726 {0xc78, 0x04740001}, {0xc78, 0x03750001},
727 {0xc78, 0x02760001}, {0xc78, 0x01770001},
728 {0xc78, 0x00780001}, {0xc78, 0x00790001},
729 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
730 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
731 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
732 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
733 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
734 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
735 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
736 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
737 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
738 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
739 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
740 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
741 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
742 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
743 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
744 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
745 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
746 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
747 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
748 {0xffff, 0xffffffff}
749 };
750
751 static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = {
752 {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
753 {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
754 {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
755 {0xc78, 0xf7060001}, {0xc78, 0xf6070001},
756 {0xc78, 0xf5080001}, {0xc78, 0xf4090001},
757 {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001},
758 {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001},
759 {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001},
760 {0xc78, 0xed100001}, {0xc78, 0xec110001},
761 {0xc78, 0xeb120001}, {0xc78, 0xea130001},
762 {0xc78, 0xe9140001}, {0xc78, 0xe8150001},
763 {0xc78, 0xe7160001}, {0xc78, 0xe6170001},
764 {0xc78, 0xe5180001}, {0xc78, 0xe4190001},
765 {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001},
766 {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001},
767 {0xc78, 0x671e0001}, {0xc78, 0x661f0001},
768 {0xc78, 0x65200001}, {0xc78, 0x64210001},
769 {0xc78, 0x63220001}, {0xc78, 0x4a230001},
770 {0xc78, 0x49240001}, {0xc78, 0x48250001},
771 {0xc78, 0x47260001}, {0xc78, 0x46270001},
772 {0xc78, 0x45280001}, {0xc78, 0x44290001},
773 {0xc78, 0x432a0001}, {0xc78, 0x422b0001},
774 {0xc78, 0x292c0001}, {0xc78, 0x282d0001},
775 {0xc78, 0x272e0001}, {0xc78, 0x262f0001},
776 {0xc78, 0x0a300001}, {0xc78, 0x09310001},
777 {0xc78, 0x08320001}, {0xc78, 0x07330001},
778 {0xc78, 0x06340001}, {0xc78, 0x05350001},
779 {0xc78, 0x04360001}, {0xc78, 0x03370001},
780 {0xc78, 0x02380001}, {0xc78, 0x01390001},
781 {0xc78, 0x013a0001}, {0xc78, 0x013b0001},
782 {0xc78, 0x013c0001}, {0xc78, 0x013d0001},
783 {0xc78, 0x013e0001}, {0xc78, 0x013f0001},
784 {0xc78, 0xfc400001}, {0xc78, 0xfb410001},
785 {0xc78, 0xfa420001}, {0xc78, 0xf9430001},
786 {0xc78, 0xf8440001}, {0xc78, 0xf7450001},
787 {0xc78, 0xf6460001}, {0xc78, 0xf5470001},
788 {0xc78, 0xf4480001}, {0xc78, 0xf3490001},
789 {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001},
790 {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001},
791 {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001},
792 {0xc78, 0xec500001}, {0xc78, 0xeb510001},
793 {0xc78, 0xea520001}, {0xc78, 0xe9530001},
794 {0xc78, 0xe8540001}, {0xc78, 0xe7550001},
795 {0xc78, 0xe6560001}, {0xc78, 0xe5570001},
796 {0xc78, 0xe4580001}, {0xc78, 0xe3590001},
797 {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001},
798 {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001},
799 {0xc78, 0x675e0001}, {0xc78, 0x665f0001},
800 {0xc78, 0x65600001}, {0xc78, 0x64610001},
801 {0xc78, 0x63620001}, {0xc78, 0x62630001},
802 {0xc78, 0x61640001}, {0xc78, 0x48650001},
803 {0xc78, 0x47660001}, {0xc78, 0x46670001},
804 {0xc78, 0x45680001}, {0xc78, 0x44690001},
805 {0xc78, 0x436a0001}, {0xc78, 0x426b0001},
806 {0xc78, 0x286c0001}, {0xc78, 0x276d0001},
807 {0xc78, 0x266e0001}, {0xc78, 0x256f0001},
808 {0xc78, 0x24700001}, {0xc78, 0x09710001},
809 {0xc78, 0x08720001}, {0xc78, 0x07730001},
810 {0xc78, 0x06740001}, {0xc78, 0x05750001},
811 {0xc78, 0x04760001}, {0xc78, 0x03770001},
812 {0xc78, 0x02780001}, {0xc78, 0x01790001},
813 {0xc78, 0x017a0001}, {0xc78, 0x017b0001},
814 {0xc78, 0x017c0001}, {0xc78, 0x017d0001},
815 {0xc78, 0x017e0001}, {0xc78, 0x017f0001},
816 {0xc50, 0x69553422},
817 {0xc50, 0x69553420},
818 {0x824, 0x00390204},
819 {0xffff, 0xffffffff}
820 };
821
822 static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
823 {0x00, 0x00030159}, {0x01, 0x00031284},
824 {0x02, 0x00098000}, {0x03, 0x00039c63},
825 {0x04, 0x000210e7}, {0x09, 0x0002044f},
826 {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
827 {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
828 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
829 {0x19, 0x00000000}, {0x1a, 0x00030355},
830 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
831 {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
832 {0x1f, 0x00000000}, {0x20, 0x0000b614},
833 {0x21, 0x0006c000}, {0x22, 0x00000000},
834 {0x23, 0x00001558}, {0x24, 0x00000060},
835 {0x25, 0x00000483}, {0x26, 0x0004f000},
836 {0x27, 0x000ec7d9}, {0x28, 0x00057730},
837 {0x29, 0x00004783}, {0x2a, 0x00000001},
838 {0x2b, 0x00021334}, {0x2a, 0x00000000},
839 {0x2b, 0x00000054}, {0x2a, 0x00000001},
840 {0x2b, 0x00000808}, {0x2b, 0x00053333},
841 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
842 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
843 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
844 {0x2b, 0x00000808}, {0x2b, 0x00063333},
845 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
846 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
847 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
848 {0x2b, 0x00000808}, {0x2b, 0x00073333},
849 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
850 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
851 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
852 {0x2b, 0x00000709}, {0x2b, 0x00063333},
853 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
854 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
855 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
856 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
857 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
858 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
859 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
860 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
861 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
862 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
863 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
864 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
865 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
866 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
867 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
868 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
869 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
870 {0x10, 0x0002000f}, {0x11, 0x000203f9},
871 {0x10, 0x0003000f}, {0x11, 0x000ff500},
872 {0x10, 0x00000000}, {0x11, 0x00000000},
873 {0x10, 0x0008000f}, {0x11, 0x0003f100},
874 {0x10, 0x0009000f}, {0x11, 0x00023100},
875 {0x12, 0x00032000}, {0x12, 0x00071000},
876 {0x12, 0x000b0000}, {0x12, 0x000fc000},
877 {0x13, 0x000287b3}, {0x13, 0x000244b7},
878 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
879 {0x13, 0x00018493}, {0x13, 0x0001429b},
880 {0x13, 0x00010299}, {0x13, 0x0000c29c},
881 {0x13, 0x000081a0}, {0x13, 0x000040ac},
882 {0x13, 0x00000020}, {0x14, 0x0001944c},
883 {0x14, 0x00059444}, {0x14, 0x0009944c},
884 {0x14, 0x000d9444}, {0x15, 0x0000f474},
885 {0x15, 0x0004f477}, {0x15, 0x0008f455},
886 {0x15, 0x000cf455}, {0x16, 0x00000339},
887 {0x16, 0x00040339}, {0x16, 0x00080339},
888 {0x16, 0x000c0366}, {0x00, 0x00010159},
889 {0x18, 0x0000f401}, {0xfe, 0x00000000},
890 {0xfe, 0x00000000}, {0x1f, 0x00000003},
891 {0xfe, 0x00000000}, {0xfe, 0x00000000},
892 {0x1e, 0x00000247}, {0x1f, 0x00000000},
893 {0x00, 0x00030159},
894 {0xff, 0xffffffff}
895 };
896
897 static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = {
898 {0x00, 0x00010000}, {0xb0, 0x000dffe0},
899 {0xfe, 0x00000000}, {0xfe, 0x00000000},
900 {0xfe, 0x00000000}, {0xb1, 0x00000018},
901 {0xfe, 0x00000000}, {0xfe, 0x00000000},
902 {0xfe, 0x00000000}, {0xb2, 0x00084c00},
903 {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
904 {0xb7, 0x00000010}, {0xb8, 0x0000907f},
905 {0x5c, 0x00000002}, {0x7c, 0x00000002},
906 {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
907 {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
908 {0x1e, 0x00000000}, {0xdf, 0x00000780},
909 {0x50, 0x00067435},
910 /*
911 * The 8723bu vendor driver indicates that bit 8 should be set in
912 * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
913 * they never actually check the package type - and just default
914 * to not setting it.
915 */
916 {0x51, 0x0006b04e},
917 {0x52, 0x000007d2}, {0x53, 0x00000000},
918 {0x54, 0x00050400}, {0x55, 0x0004026e},
919 {0xdd, 0x0000004c}, {0x70, 0x00067435},
920 /*
921 * 0x71 has same package type condition as for register 0x51
922 */
923 {0x71, 0x0006b04e},
924 {0x72, 0x000007d2}, {0x73, 0x00000000},
925 {0x74, 0x00050400}, {0x75, 0x0004026e},
926 {0xef, 0x00000100}, {0x34, 0x0000add7},
927 {0x35, 0x00005c00}, {0x34, 0x00009dd4},
928 {0x35, 0x00005000}, {0x34, 0x00008dd1},
929 {0x35, 0x00004400}, {0x34, 0x00007dce},
930 {0x35, 0x00003800}, {0x34, 0x00006cd1},
931 {0x35, 0x00004400}, {0x34, 0x00005cce},
932 {0x35, 0x00003800}, {0x34, 0x000048ce},
933 {0x35, 0x00004400}, {0x34, 0x000034ce},
934 {0x35, 0x00003800}, {0x34, 0x00002451},
935 {0x35, 0x00004400}, {0x34, 0x0000144e},
936 {0x35, 0x00003800}, {0x34, 0x00000051},
937 {0x35, 0x00004400}, {0xef, 0x00000000},
938 {0xef, 0x00000100}, {0xed, 0x00000010},
939 {0x44, 0x0000add7}, {0x44, 0x00009dd4},
940 {0x44, 0x00008dd1}, {0x44, 0x00007dce},
941 {0x44, 0x00006cc1}, {0x44, 0x00005cce},
942 {0x44, 0x000044d1}, {0x44, 0x000034ce},
943 {0x44, 0x00002451}, {0x44, 0x0000144e},
944 {0x44, 0x00000051}, {0xef, 0x00000000},
945 {0xed, 0x00000000}, {0x7f, 0x00020080},
946 {0xef, 0x00002000}, {0x3b, 0x000380ef},
947 {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
948 {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
949 {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
950 {0x3b, 0x00000900}, {0xef, 0x00000000},
951 {0xed, 0x00000001}, {0x40, 0x000380ef},
952 {0x40, 0x000302fe}, {0x40, 0x00028ce6},
953 {0x40, 0x000200bc}, {0x40, 0x000188a5},
954 {0x40, 0x00010fbc}, {0x40, 0x00008f71},
955 {0x40, 0x00000900}, {0xed, 0x00000000},
956 {0x82, 0x00080000}, {0x83, 0x00008000},
957 {0x84, 0x00048d80}, {0x85, 0x00068000},
958 {0xa2, 0x00080000}, {0xa3, 0x00008000},
959 {0xa4, 0x00048d80}, {0xa5, 0x00068000},
960 {0xed, 0x00000002}, {0xef, 0x00000002},
961 {0x56, 0x00000032}, {0x76, 0x00000032},
962 {0x01, 0x00000780},
963 {0xff, 0xffffffff}
964 };
965
966 static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
967 {0x00, 0x00030159}, {0x01, 0x00031284},
968 {0x02, 0x00098000}, {0x03, 0x00018c63},
969 {0x04, 0x000210e7}, {0x09, 0x0002044f},
970 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
971 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
972 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
973 {0x19, 0x00000000}, {0x1a, 0x00010255},
974 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
975 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
976 {0x1f, 0x00080001}, {0x20, 0x0000b614},
977 {0x21, 0x0006c000}, {0x22, 0x00000000},
978 {0x23, 0x00001558}, {0x24, 0x00000060},
979 {0x25, 0x00000483}, {0x26, 0x0004f000},
980 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
981 {0x29, 0x00004783}, {0x2a, 0x00000001},
982 {0x2b, 0x00021334}, {0x2a, 0x00000000},
983 {0x2b, 0x00000054}, {0x2a, 0x00000001},
984 {0x2b, 0x00000808}, {0x2b, 0x00053333},
985 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
986 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
987 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
988 {0x2b, 0x00000808}, {0x2b, 0x00063333},
989 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
990 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
991 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
992 {0x2b, 0x00000808}, {0x2b, 0x00073333},
993 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
994 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
995 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
996 {0x2b, 0x00000709}, {0x2b, 0x00063333},
997 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
998 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
999 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1000 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1001 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1002 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1003 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1004 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1005 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1006 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1007 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1008 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1009 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1010 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1011 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1012 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1013 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1014 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1015 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1016 {0x10, 0x00000000}, {0x11, 0x00000000},
1017 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1018 {0x10, 0x0009000f}, {0x11, 0x00023100},
1019 {0x12, 0x00032000}, {0x12, 0x00071000},
1020 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1021 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1022 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1023 {0x13, 0x00018493}, {0x13, 0x0001429b},
1024 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1025 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1026 {0x13, 0x00000020}, {0x14, 0x0001944c},
1027 {0x14, 0x00059444}, {0x14, 0x0009944c},
1028 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1029 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1030 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1031 {0x16, 0x000a0330}, {0x16, 0x00060330},
1032 {0x16, 0x00020330}, {0x00, 0x00010159},
1033 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1034 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1035 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1036 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1037 {0x00, 0x00030159},
1038 {0xff, 0xffffffff}
1039 };
1040
1041 static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
1042 {0x00, 0x00030159}, {0x01, 0x00031284},
1043 {0x02, 0x00098000}, {0x03, 0x00018c63},
1044 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1045 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1046 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1047 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1048 {0x12, 0x00032000}, {0x12, 0x00071000},
1049 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1050 {0x13, 0x000287af}, {0x13, 0x000244b7},
1051 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1052 {0x13, 0x00018493}, {0x13, 0x00014297},
1053 {0x13, 0x00010295}, {0x13, 0x0000c298},
1054 {0x13, 0x0000819c}, {0x13, 0x000040a8},
1055 {0x13, 0x0000001c}, {0x14, 0x0001944c},
1056 {0x14, 0x00059444}, {0x14, 0x0009944c},
1057 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1058 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1059 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1060 {0x16, 0x000a0330}, {0x16, 0x00060330},
1061 {0x16, 0x00020330},
1062 {0xff, 0xffffffff}
1063 };
1064
1065 static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
1066 {0x00, 0x00030159}, {0x01, 0x00031284},
1067 {0x02, 0x00098000}, {0x03, 0x00018c63},
1068 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1069 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1070 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1071 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1072 {0x19, 0x00000000}, {0x1a, 0x00010255},
1073 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1074 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1075 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1076 {0x21, 0x0006c000}, {0x22, 0x00000000},
1077 {0x23, 0x00001558}, {0x24, 0x00000060},
1078 {0x25, 0x00000483}, {0x26, 0x0004f000},
1079 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1080 {0x29, 0x00004783}, {0x2a, 0x00000001},
1081 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1082 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1083 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1084 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1085 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1086 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1087 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1088 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1089 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1090 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1091 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1092 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1093 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1094 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1095 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1096 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1097 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1098 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1099 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1100 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1101 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1102 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1103 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1104 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1105 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1106 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1107 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1108 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1109 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1110 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1111 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1112 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1113 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1114 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1115 {0x10, 0x00000000}, {0x11, 0x00000000},
1116 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1117 {0x10, 0x0009000f}, {0x11, 0x00023100},
1118 {0x12, 0x00032000}, {0x12, 0x00071000},
1119 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1120 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1121 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1122 {0x13, 0x00018493}, {0x13, 0x0001429b},
1123 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1124 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1125 {0x13, 0x00000020}, {0x14, 0x0001944c},
1126 {0x14, 0x00059444}, {0x14, 0x0009944c},
1127 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1128 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1129 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1130 {0x16, 0x000a0330}, {0x16, 0x00060330},
1131 {0x16, 0x00020330}, {0x00, 0x00010159},
1132 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1133 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1134 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1135 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1136 {0x00, 0x00030159},
1137 {0xff, 0xffffffff}
1138 };
1139
1140 static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
1141 {0x00, 0x00030159}, {0x01, 0x00031284},
1142 {0x02, 0x00098000}, {0x03, 0x00018c63},
1143 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1144 {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
1145 {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
1146 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1147 {0x19, 0x00000000}, {0x1a, 0x00000255},
1148 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1149 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1150 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1151 {0x21, 0x0006c000}, {0x22, 0x0000083c},
1152 {0x23, 0x00001558}, {0x24, 0x00000060},
1153 {0x25, 0x00000483}, {0x26, 0x0004f000},
1154 {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
1155 {0x29, 0x00004783}, {0x2a, 0x00000001},
1156 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1157 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1158 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1159 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1160 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1161 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1162 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1163 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1164 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1165 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1166 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1167 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1168 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1169 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1170 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1171 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1172 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1173 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1174 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1175 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1176 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1177 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1178 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1179 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1180 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1181 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1182 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1183 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1184 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1185 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1186 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1187 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1188 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1189 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1190 {0x10, 0x00000000}, {0x11, 0x00000000},
1191 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1192 {0x10, 0x0009000f}, {0x11, 0x00023100},
1193 {0x12, 0x000d8000}, {0x12, 0x00090000},
1194 {0x12, 0x00051000}, {0x12, 0x00012000},
1195 {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
1196 {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
1197 {0x13, 0x000183a4}, {0x13, 0x00014398},
1198 {0x13, 0x000101a4}, {0x13, 0x0000c198},
1199 {0x13, 0x000080a4}, {0x13, 0x00004098},
1200 {0x13, 0x00000000}, {0x14, 0x0001944c},
1201 {0x14, 0x00059444}, {0x14, 0x0009944c},
1202 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1203 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1204 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1205 {0x16, 0x000a0330}, {0x16, 0x00060330},
1206 {0x16, 0x00020330}, {0x00, 0x00010159},
1207 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1208 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1209 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1210 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1211 {0x00, 0x00030159},
1212 {0xff, 0xffffffff}
1213 };
1214
1215 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
1216 { /* RF_A */
1217 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
1218 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
1219 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
1220 .hspiread = REG_HSPI_XA_READBACK,
1221 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
1222 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
1223 },
1224 { /* RF_B */
1225 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
1226 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
1227 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
1228 .hspiread = REG_HSPI_XB_READBACK,
1229 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
1230 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
1231 },
1232 };
1233
1234 static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
1235 REG_OFDM0_XA_RX_IQ_IMBALANCE,
1236 REG_OFDM0_XB_RX_IQ_IMBALANCE,
1237 REG_OFDM0_ENERGY_CCA_THRES,
1238 REG_OFDM0_AGCR_SSI_TABLE,
1239 REG_OFDM0_XA_TX_IQ_IMBALANCE,
1240 REG_OFDM0_XB_TX_IQ_IMBALANCE,
1241 REG_OFDM0_XC_TX_AFE,
1242 REG_OFDM0_XD_TX_AFE,
1243 REG_OFDM0_RX_IQ_EXT_ANTA
1244 };
1245
1246 static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
1247 {
1248 struct usb_device *udev = priv->udev;
1249 int len;
1250 u8 data;
1251
1252 mutex_lock(&priv->usb_buf_mutex);
1253 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1254 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1255 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1256 RTW_USB_CONTROL_MSG_TIMEOUT);
1257 data = priv->usb_buf.val8;
1258 mutex_unlock(&priv->usb_buf_mutex);
1259
1260 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1261 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",
1262 __func__, addr, data, len);
1263 return data;
1264 }
1265
1266 static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
1267 {
1268 struct usb_device *udev = priv->udev;
1269 int len;
1270 u16 data;
1271
1272 mutex_lock(&priv->usb_buf_mutex);
1273 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1274 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1275 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1276 RTW_USB_CONTROL_MSG_TIMEOUT);
1277 data = le16_to_cpu(priv->usb_buf.val16);
1278 mutex_unlock(&priv->usb_buf_mutex);
1279
1280 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1281 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",
1282 __func__, addr, data, len);
1283 return data;
1284 }
1285
1286 static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1287 {
1288 struct usb_device *udev = priv->udev;
1289 int len;
1290 u32 data;
1291
1292 mutex_lock(&priv->usb_buf_mutex);
1293 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1294 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1295 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1296 RTW_USB_CONTROL_MSG_TIMEOUT);
1297 data = le32_to_cpu(priv->usb_buf.val32);
1298 mutex_unlock(&priv->usb_buf_mutex);
1299
1300 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1301 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",
1302 __func__, addr, data, len);
1303 return data;
1304 }
1305
1306 static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1307 {
1308 struct usb_device *udev = priv->udev;
1309 int ret;
1310
1311 mutex_lock(&priv->usb_buf_mutex);
1312 priv->usb_buf.val8 = val;
1313 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1314 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1315 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1316 RTW_USB_CONTROL_MSG_TIMEOUT);
1317
1318 mutex_unlock(&priv->usb_buf_mutex);
1319
1320 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1321 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1322 __func__, addr, val);
1323 return ret;
1324 }
1325
1326 static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1327 {
1328 struct usb_device *udev = priv->udev;
1329 int ret;
1330
1331 mutex_lock(&priv->usb_buf_mutex);
1332 priv->usb_buf.val16 = cpu_to_le16(val);
1333 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1334 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1335 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1336 RTW_USB_CONTROL_MSG_TIMEOUT);
1337 mutex_unlock(&priv->usb_buf_mutex);
1338
1339 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1340 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1341 __func__, addr, val);
1342 return ret;
1343 }
1344
1345 static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1346 {
1347 struct usb_device *udev = priv->udev;
1348 int ret;
1349
1350 mutex_lock(&priv->usb_buf_mutex);
1351 priv->usb_buf.val32 = cpu_to_le32(val);
1352 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1353 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1354 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1355 RTW_USB_CONTROL_MSG_TIMEOUT);
1356 mutex_unlock(&priv->usb_buf_mutex);
1357
1358 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1359 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1360 __func__, addr, val);
1361 return ret;
1362 }
1363
1364 static int
1365 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1366 {
1367 struct usb_device *udev = priv->udev;
1368 int blocksize = priv->fops->writeN_block_size;
1369 int ret, i, count, remainder;
1370
1371 count = len / blocksize;
1372 remainder = len % blocksize;
1373
1374 for (i = 0; i < count; i++) {
1375 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1376 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1377 addr, 0, buf, blocksize,
1378 RTW_USB_CONTROL_MSG_TIMEOUT);
1379 if (ret != blocksize)
1380 goto write_error;
1381
1382 addr += blocksize;
1383 buf += blocksize;
1384 }
1385
1386 if (remainder) {
1387 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1388 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1389 addr, 0, buf, remainder,
1390 RTW_USB_CONTROL_MSG_TIMEOUT);
1391 if (ret != remainder)
1392 goto write_error;
1393 }
1394
1395 return len;
1396
1397 write_error:
1398 dev_info(&udev->dev,
1399 "%s: Failed to write block at addr: %04x size: %04x\n",
1400 __func__, addr, blocksize);
1401 return -EAGAIN;
1402 }
1403
1404 static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1405 enum rtl8xxxu_rfpath path, u8 reg)
1406 {
1407 u32 hssia, val32, retval;
1408
1409 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1410 if (path != RF_A)
1411 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1412 else
1413 val32 = hssia;
1414
1415 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1416 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1417 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1418 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1419 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1420
1421 udelay(10);
1422
1423 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1424 udelay(100);
1425
1426 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1427 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1428 udelay(10);
1429
1430 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1431 if (val32 & FPGA0_HSSI_PARM1_PI)
1432 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1433 else
1434 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1435
1436 retval &= 0xfffff;
1437
1438 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1439 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1440 __func__, reg, retval);
1441 return retval;
1442 }
1443
1444 /*
1445 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
1446 * have write issues in high temperature conditions. We may have to
1447 * retry writing them.
1448 */
1449 static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1450 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1451 {
1452 int ret, retval;
1453 u32 dataaddr;
1454
1455 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1456 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1457 __func__, reg, data);
1458
1459 data &= FPGA0_LSSI_PARM_DATA_MASK;
1460 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1461
1462 /* Use XB for path B */
1463 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1464 if (ret != sizeof(dataaddr))
1465 retval = -EIO;
1466 else
1467 retval = 0;
1468
1469 udelay(1);
1470
1471 return retval;
1472 }
1473
1474 static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv,
1475 struct h2c_cmd *h2c, int len)
1476 {
1477 struct device *dev = &priv->udev->dev;
1478 int mbox_nr, retry, retval = 0;
1479 int mbox_reg, mbox_ext_reg;
1480 u8 val8;
1481
1482 mutex_lock(&priv->h2c_mutex);
1483
1484 mbox_nr = priv->next_mbox;
1485 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1486 mbox_ext_reg = priv->fops->mbox_ext_reg +
1487 (mbox_nr * priv->fops->mbox_ext_width);
1488
1489 /*
1490 * MBOX ready?
1491 */
1492 retry = 100;
1493 do {
1494 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1495 if (!(val8 & BIT(mbox_nr)))
1496 break;
1497 } while (retry--);
1498
1499 if (!retry) {
1500 dev_info(dev, "%s: Mailbox busy\n", __func__);
1501 retval = -EBUSY;
1502 goto error;
1503 }
1504
1505 /*
1506 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1507 */
1508 if (len > sizeof(u32)) {
1509 if (priv->fops->mbox_ext_width == 4) {
1510 rtl8xxxu_write32(priv, mbox_ext_reg,
1511 le32_to_cpu(h2c->raw_wide.ext));
1512 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1513 dev_info(dev, "H2C_EXT %08x\n",
1514 le32_to_cpu(h2c->raw_wide.ext));
1515 } else {
1516 rtl8xxxu_write16(priv, mbox_ext_reg,
1517 le16_to_cpu(h2c->raw.ext));
1518 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1519 dev_info(dev, "H2C_EXT %04x\n",
1520 le16_to_cpu(h2c->raw.ext));
1521 }
1522 }
1523 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1524 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1525 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1526
1527 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1528
1529 error:
1530 mutex_unlock(&priv->h2c_mutex);
1531 return retval;
1532 }
1533
1534 static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data)
1535 {
1536 struct h2c_cmd h2c;
1537 int reqnum = 0;
1538
1539 memset(&h2c, 0, sizeof(struct h2c_cmd));
1540 h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
1541 h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
1542 h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
1543 h2c.bt_mp_oper.data = data;
1544 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
1545
1546 reqnum++;
1547 memset(&h2c, 0, sizeof(struct h2c_cmd));
1548 h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
1549 h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
1550 h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
1551 h2c.bt_mp_oper.addr = reg;
1552 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
1553 }
1554
1555 static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
1556 {
1557 u8 val8;
1558 u32 val32;
1559
1560 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1561 val8 |= BIT(0) | BIT(3);
1562 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1563
1564 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1565 val32 &= ~(BIT(4) | BIT(5));
1566 val32 |= BIT(3);
1567 if (priv->rf_paths == 2) {
1568 val32 &= ~(BIT(20) | BIT(21));
1569 val32 |= BIT(19);
1570 }
1571 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1572
1573 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1574 val32 &= ~OFDM_RF_PATH_TX_MASK;
1575 if (priv->tx_paths == 2)
1576 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1577 else if (priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c)
1578 val32 |= OFDM_RF_PATH_TX_B;
1579 else
1580 val32 |= OFDM_RF_PATH_TX_A;
1581 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1582
1583 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1584 val32 &= ~FPGA_RF_MODE_JAPAN;
1585 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1586
1587 if (priv->rf_paths == 2)
1588 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1589 else
1590 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1591
1592 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1593 if (priv->rf_paths == 2)
1594 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1595
1596 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1597 }
1598
1599 static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
1600 {
1601 u8 sps0;
1602 u32 val32;
1603
1604 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1605
1606 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1607
1608 /* RF RX code for preamble power saving */
1609 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1610 val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1611 if (priv->rf_paths == 2)
1612 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1613 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1614
1615 /* Disable TX for four paths */
1616 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1617 val32 &= ~OFDM_RF_PATH_TX_MASK;
1618 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1619
1620 /* Enable power saving */
1621 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1622 val32 |= FPGA_RF_MODE_JAPAN;
1623 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1624
1625 /* AFE control register to power down bits [30:22] */
1626 if (priv->rf_paths == 2)
1627 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1628 else
1629 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1630
1631 /* Power down RF module */
1632 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1633 if (priv->rf_paths == 2)
1634 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1635
1636 sps0 &= ~(BIT(0) | BIT(3));
1637 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1638 }
1639
1640
1641 static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1642 {
1643 u8 val8;
1644
1645 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1646 val8 &= ~BIT(6);
1647 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1648
1649 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1650 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1651 val8 &= ~BIT(0);
1652 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1653 }
1654
1655
1656 /*
1657 * The rtl8723a has 3 channel groups for it's efuse settings. It only
1658 * supports the 2.4GHz band, so channels 1 - 14:
1659 * group 0: channels 1 - 3
1660 * group 1: channels 4 - 9
1661 * group 2: channels 10 - 14
1662 *
1663 * Note: We index from 0 in the code
1664 */
1665 static int rtl8723a_channel_to_group(int channel)
1666 {
1667 int group;
1668
1669 if (channel < 4)
1670 group = 0;
1671 else if (channel < 10)
1672 group = 1;
1673 else
1674 group = 2;
1675
1676 return group;
1677 }
1678
1679 static void rtl8723au_config_channel(struct ieee80211_hw *hw)
1680 {
1681 struct rtl8xxxu_priv *priv = hw->priv;
1682 u32 val32, rsr;
1683 u8 val8, opmode;
1684 bool ht = true;
1685 int sec_ch_above, channel;
1686 int i;
1687
1688 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1689 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1690 channel = hw->conf.chandef.chan->hw_value;
1691
1692 switch (hw->conf.chandef.width) {
1693 case NL80211_CHAN_WIDTH_20_NOHT:
1694 ht = false;
1695 case NL80211_CHAN_WIDTH_20:
1696 opmode |= BW_OPMODE_20MHZ;
1697 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1698
1699 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1700 val32 &= ~FPGA_RF_MODE;
1701 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1702
1703 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1704 val32 &= ~FPGA_RF_MODE;
1705 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1706
1707 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1708 val32 |= FPGA0_ANALOG2_20MHZ;
1709 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1710 break;
1711 case NL80211_CHAN_WIDTH_40:
1712 if (hw->conf.chandef.center_freq1 >
1713 hw->conf.chandef.chan->center_freq) {
1714 sec_ch_above = 1;
1715 channel += 2;
1716 } else {
1717 sec_ch_above = 0;
1718 channel -= 2;
1719 }
1720
1721 opmode &= ~BW_OPMODE_20MHZ;
1722 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1723 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1724 if (sec_ch_above)
1725 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1726 else
1727 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1728 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1729
1730 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1731 val32 |= FPGA_RF_MODE;
1732 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1733
1734 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1735 val32 |= FPGA_RF_MODE;
1736 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1737
1738 /*
1739 * Set Control channel to upper or lower. These settings
1740 * are required only for 40MHz
1741 */
1742 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1743 val32 &= ~CCK0_SIDEBAND;
1744 if (!sec_ch_above)
1745 val32 |= CCK0_SIDEBAND;
1746 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1747
1748 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1749 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1750 if (sec_ch_above)
1751 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1752 else
1753 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1754 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1755
1756 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1757 val32 &= ~FPGA0_ANALOG2_20MHZ;
1758 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1759
1760 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1761 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1762 if (sec_ch_above)
1763 val32 |= FPGA0_PS_UPPER_CHANNEL;
1764 else
1765 val32 |= FPGA0_PS_LOWER_CHANNEL;
1766 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1767 break;
1768
1769 default:
1770 break;
1771 }
1772
1773 for (i = RF_A; i < priv->rf_paths; i++) {
1774 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1775 val32 &= ~MODE_AG_CHANNEL_MASK;
1776 val32 |= channel;
1777 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1778 }
1779
1780 if (ht)
1781 val8 = 0x0e;
1782 else
1783 val8 = 0x0a;
1784
1785 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1786 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1787
1788 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1789 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1790
1791 for (i = RF_A; i < priv->rf_paths; i++) {
1792 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1793 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1794 val32 &= ~MODE_AG_CHANNEL_20MHZ;
1795 else
1796 val32 |= MODE_AG_CHANNEL_20MHZ;
1797 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1798 }
1799 }
1800
1801 static void rtl8723bu_config_channel(struct ieee80211_hw *hw)
1802 {
1803 struct rtl8xxxu_priv *priv = hw->priv;
1804 u32 val32, rsr;
1805 u8 val8, subchannel;
1806 u16 rf_mode_bw;
1807 bool ht = true;
1808 int sec_ch_above, channel;
1809 int i;
1810
1811 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);
1812 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK;
1813 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1814 channel = hw->conf.chandef.chan->hw_value;
1815
1816 /* Hack */
1817 subchannel = 0;
1818
1819 switch (hw->conf.chandef.width) {
1820 case NL80211_CHAN_WIDTH_20_NOHT:
1821 ht = false;
1822 case NL80211_CHAN_WIDTH_20:
1823 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20;
1824 subchannel = 0;
1825
1826 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1827 val32 &= ~FPGA_RF_MODE;
1828 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1829
1830 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1831 val32 &= ~FPGA_RF_MODE;
1832 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1833
1834 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
1835 val32 &= ~(BIT(30) | BIT(31));
1836 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
1837
1838 break;
1839 case NL80211_CHAN_WIDTH_40:
1840 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40;
1841
1842 if (hw->conf.chandef.center_freq1 >
1843 hw->conf.chandef.chan->center_freq) {
1844 sec_ch_above = 1;
1845 channel += 2;
1846 } else {
1847 sec_ch_above = 0;
1848 channel -= 2;
1849 }
1850
1851 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1852 val32 |= FPGA_RF_MODE;
1853 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1854
1855 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1856 val32 |= FPGA_RF_MODE;
1857 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1858
1859 /*
1860 * Set Control channel to upper or lower. These settings
1861 * are required only for 40MHz
1862 */
1863 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1864 val32 &= ~CCK0_SIDEBAND;
1865 if (!sec_ch_above)
1866 val32 |= CCK0_SIDEBAND;
1867 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1868
1869 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1870 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1871 if (sec_ch_above)
1872 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1873 else
1874 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1875 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1876
1877 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1878 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1879 if (sec_ch_above)
1880 val32 |= FPGA0_PS_UPPER_CHANNEL;
1881 else
1882 val32 |= FPGA0_PS_LOWER_CHANNEL;
1883 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1884 break;
1885 case NL80211_CHAN_WIDTH_80:
1886 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80;
1887 break;
1888 default:
1889 break;
1890 }
1891
1892 for (i = RF_A; i < priv->rf_paths; i++) {
1893 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1894 val32 &= ~MODE_AG_CHANNEL_MASK;
1895 val32 |= channel;
1896 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1897 }
1898
1899 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw);
1900 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);
1901
1902 if (ht)
1903 val8 = 0x0e;
1904 else
1905 val8 = 0x0a;
1906
1907 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1908 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1909
1910 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1911 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1912
1913 for (i = RF_A; i < priv->rf_paths; i++) {
1914 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1915 val32 &= ~MODE_AG_BW_MASK;
1916 switch(hw->conf.chandef.width) {
1917 case NL80211_CHAN_WIDTH_80:
1918 val32 |= MODE_AG_BW_80MHZ_8723B;
1919 break;
1920 case NL80211_CHAN_WIDTH_40:
1921 val32 |= MODE_AG_BW_40MHZ_8723B;
1922 break;
1923 default:
1924 val32 |= MODE_AG_BW_20MHZ_8723B;
1925 break;
1926 }
1927 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1928 }
1929 }
1930
1931 static void
1932 rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1933 {
1934 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1935 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1936 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1937 u8 val8;
1938 int group, i;
1939
1940 group = rtl8723a_channel_to_group(channel);
1941
1942 cck[0] = priv->cck_tx_power_index_A[group];
1943 cck[1] = priv->cck_tx_power_index_B[group];
1944
1945 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1946 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1947
1948 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1949 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1950
1951 mcsbase[0] = ofdm[0];
1952 mcsbase[1] = ofdm[1];
1953 if (!ht40) {
1954 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1955 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1956 }
1957
1958 if (priv->tx_paths > 1) {
1959 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1960 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;
1961 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1962 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;
1963 }
1964
1965 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1966 dev_info(&priv->udev->dev,
1967 "%s: Setting TX power CCK A: %02x, "
1968 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1969 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1970
1971 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1972 if (cck[i] > RF6052_MAX_TX_PWR)
1973 cck[i] = RF6052_MAX_TX_PWR;
1974 if (ofdm[i] > RF6052_MAX_TX_PWR)
1975 ofdm[i] = RF6052_MAX_TX_PWR;
1976 }
1977
1978 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1979 val32 &= 0xffff00ff;
1980 val32 |= (cck[0] << 8);
1981 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1982
1983 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1984 val32 &= 0xff;
1985 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1986 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1987
1988 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1989 val32 &= 0xffffff00;
1990 val32 |= cck[1];
1991 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1992
1993 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1994 val32 &= 0xff;
1995 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1996 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1997
1998 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1999 ofdmbase[0] << 16 | ofdmbase[0] << 24;
2000 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
2001 ofdmbase[1] << 16 | ofdmbase[1] << 24;
2002 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
2003 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
2004
2005 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
2006 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
2007
2008 mcs_a = mcsbase[0] | mcsbase[0] << 8 |
2009 mcsbase[0] << 16 | mcsbase[0] << 24;
2010 mcs_b = mcsbase[1] | mcsbase[1] << 8 |
2011 mcsbase[1] << 16 | mcsbase[1] << 24;
2012
2013 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
2014 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
2015
2016 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
2017 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
2018
2019 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
2020 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
2021
2022 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
2023 for (i = 0; i < 3; i++) {
2024 if (i != 2)
2025 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
2026 else
2027 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
2028 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
2029 }
2030 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
2031 for (i = 0; i < 3; i++) {
2032 if (i != 2)
2033 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
2034 else
2035 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
2036 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
2037 }
2038 }
2039
2040 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
2041 enum nl80211_iftype linktype)
2042 {
2043 u8 val8;
2044
2045 val8 = rtl8xxxu_read8(priv, REG_MSR);
2046 val8 &= ~MSR_LINKTYPE_MASK;
2047
2048 switch (linktype) {
2049 case NL80211_IFTYPE_UNSPECIFIED:
2050 val8 |= MSR_LINKTYPE_NONE;
2051 break;
2052 case NL80211_IFTYPE_ADHOC:
2053 val8 |= MSR_LINKTYPE_ADHOC;
2054 break;
2055 case NL80211_IFTYPE_STATION:
2056 val8 |= MSR_LINKTYPE_STATION;
2057 break;
2058 case NL80211_IFTYPE_AP:
2059 val8 |= MSR_LINKTYPE_AP;
2060 break;
2061 default:
2062 goto out;
2063 }
2064
2065 rtl8xxxu_write8(priv, REG_MSR, val8);
2066 out:
2067 return;
2068 }
2069
2070 static void
2071 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
2072 {
2073 u16 val16;
2074
2075 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
2076 RETRY_LIMIT_SHORT_MASK) |
2077 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
2078 RETRY_LIMIT_LONG_MASK);
2079
2080 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
2081 }
2082
2083 static void
2084 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
2085 {
2086 u16 val16;
2087
2088 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
2089 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
2090
2091 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
2092 }
2093
2094 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
2095 {
2096 struct device *dev = &priv->udev->dev;
2097 char *cut;
2098
2099 switch (priv->chip_cut) {
2100 case 0:
2101 cut = "A";
2102 break;
2103 case 1:
2104 cut = "B";
2105 break;
2106 case 2:
2107 cut = "C";
2108 break;
2109 case 3:
2110 cut = "D";
2111 break;
2112 case 4:
2113 cut = "E";
2114 break;
2115 default:
2116 cut = "unknown";
2117 }
2118
2119 dev_info(dev,
2120 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
2121 priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
2122 priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
2123 priv->has_bluetooth, priv->has_gps, priv->hi_pa);
2124
2125 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
2126 }
2127
2128 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
2129 {
2130 struct device *dev = &priv->udev->dev;
2131 u32 val32, bonding;
2132 u16 val16;
2133
2134 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
2135 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
2136 SYS_CFG_CHIP_VERSION_SHIFT;
2137 if (val32 & SYS_CFG_TRP_VAUX_EN) {
2138 dev_info(dev, "Unsupported test chip\n");
2139 return -ENOTSUPP;
2140 }
2141
2142 if (val32 & SYS_CFG_BT_FUNC) {
2143 if (priv->chip_cut >= 3) {
2144 sprintf(priv->chip_name, "8723BU");
2145 priv->rtlchip = 0x8723b;
2146 } else {
2147 sprintf(priv->chip_name, "8723AU");
2148 priv->usb_interrupts = 1;
2149 priv->rtlchip = 0x8723a;
2150 }
2151
2152 priv->rf_paths = 1;
2153 priv->rx_paths = 1;
2154 priv->tx_paths = 1;
2155
2156 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
2157 if (val32 & MULTI_WIFI_FUNC_EN)
2158 priv->has_wifi = 1;
2159 if (val32 & MULTI_BT_FUNC_EN)
2160 priv->has_bluetooth = 1;
2161 if (val32 & MULTI_GPS_FUNC_EN)
2162 priv->has_gps = 1;
2163 priv->is_multi_func = 1;
2164 } else if (val32 & SYS_CFG_TYPE_ID) {
2165 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
2166 bonding &= HPON_FSM_BONDING_MASK;
2167 if (priv->chip_cut >= 3) {
2168 if (bonding == HPON_FSM_BONDING_1T2R) {
2169 sprintf(priv->chip_name, "8191EU");
2170 priv->rf_paths = 2;
2171 priv->rx_paths = 2;
2172 priv->tx_paths = 1;
2173 priv->rtlchip = 0x8191e;
2174 } else {
2175 sprintf(priv->chip_name, "8192EU");
2176 priv->rf_paths = 2;
2177 priv->rx_paths = 2;
2178 priv->tx_paths = 2;
2179 priv->rtlchip = 0x8192e;
2180 }
2181 } else if (bonding == HPON_FSM_BONDING_1T2R) {
2182 sprintf(priv->chip_name, "8191CU");
2183 priv->rf_paths = 2;
2184 priv->rx_paths = 2;
2185 priv->tx_paths = 1;
2186 priv->usb_interrupts = 1;
2187 priv->rtlchip = 0x8191c;
2188 } else {
2189 sprintf(priv->chip_name, "8192CU");
2190 priv->rf_paths = 2;
2191 priv->rx_paths = 2;
2192 priv->tx_paths = 2;
2193 priv->usb_interrupts = 1;
2194 priv->rtlchip = 0x8192c;
2195 }
2196 priv->has_wifi = 1;
2197 } else {
2198 sprintf(priv->chip_name, "8188CU");
2199 priv->rf_paths = 1;
2200 priv->rx_paths = 1;
2201 priv->tx_paths = 1;
2202 priv->rtlchip = 0x8188c;
2203 priv->usb_interrupts = 1;
2204 priv->has_wifi = 1;
2205 }
2206
2207 switch (priv->rtlchip) {
2208 case 0x8188e:
2209 case 0x8192e:
2210 case 0x8723b:
2211 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
2212 case SYS_CFG_VENDOR_ID_TSMC:
2213 sprintf(priv->chip_vendor, "TSMC");
2214 break;
2215 case SYS_CFG_VENDOR_ID_SMIC:
2216 sprintf(priv->chip_vendor, "SMIC");
2217 priv->vendor_smic = 1;
2218 break;
2219 case SYS_CFG_VENDOR_ID_UMC:
2220 sprintf(priv->chip_vendor, "UMC");
2221 priv->vendor_umc = 1;
2222 break;
2223 default:
2224 sprintf(priv->chip_vendor, "unknown");
2225 }
2226 break;
2227 default:
2228 if (val32 & SYS_CFG_VENDOR_ID) {
2229 sprintf(priv->chip_vendor, "UMC");
2230 priv->vendor_umc = 1;
2231 } else {
2232 sprintf(priv->chip_vendor, "TSMC");
2233 }
2234 }
2235
2236 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
2237 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
2238
2239 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
2240 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
2241 priv->ep_tx_high_queue = 1;
2242 priv->ep_tx_count++;
2243 }
2244
2245 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
2246 priv->ep_tx_normal_queue = 1;
2247 priv->ep_tx_count++;
2248 }
2249
2250 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
2251 priv->ep_tx_low_queue = 1;
2252 priv->ep_tx_count++;
2253 }
2254
2255 /*
2256 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
2257 */
2258 if (!priv->ep_tx_count) {
2259 switch (priv->nr_out_eps) {
2260 case 4:
2261 case 3:
2262 priv->ep_tx_low_queue = 1;
2263 priv->ep_tx_count++;
2264 case 2:
2265 priv->ep_tx_normal_queue = 1;
2266 priv->ep_tx_count++;
2267 case 1:
2268 priv->ep_tx_high_queue = 1;
2269 priv->ep_tx_count++;
2270 break;
2271 default:
2272 dev_info(dev, "Unsupported USB TX end-points\n");
2273 return -ENOTSUPP;
2274 }
2275 }
2276
2277 return 0;
2278 }
2279
2280 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
2281 {
2282 struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723;
2283
2284 if (efuse->rtl_id != cpu_to_le16(0x8129))
2285 return -EINVAL;
2286
2287 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2288
2289 memcpy(priv->cck_tx_power_index_A,
2290 efuse->cck_tx_power_index_A,
2291 sizeof(priv->cck_tx_power_index_A));
2292 memcpy(priv->cck_tx_power_index_B,
2293 efuse->cck_tx_power_index_B,
2294 sizeof(priv->cck_tx_power_index_B));
2295
2296 memcpy(priv->ht40_1s_tx_power_index_A,
2297 efuse->ht40_1s_tx_power_index_A,
2298 sizeof(priv->ht40_1s_tx_power_index_A));
2299 memcpy(priv->ht40_1s_tx_power_index_B,
2300 efuse->ht40_1s_tx_power_index_B,
2301 sizeof(priv->ht40_1s_tx_power_index_B));
2302
2303 memcpy(priv->ht20_tx_power_index_diff,
2304 efuse->ht20_tx_power_index_diff,
2305 sizeof(priv->ht20_tx_power_index_diff));
2306 memcpy(priv->ofdm_tx_power_index_diff,
2307 efuse->ofdm_tx_power_index_diff,
2308 sizeof(priv->ofdm_tx_power_index_diff));
2309
2310 memcpy(priv->ht40_max_power_offset,
2311 efuse->ht40_max_power_offset,
2312 sizeof(priv->ht40_max_power_offset));
2313 memcpy(priv->ht20_max_power_offset,
2314 efuse->ht20_max_power_offset,
2315 sizeof(priv->ht20_max_power_offset));
2316
2317 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2318 efuse->vendor_name);
2319 dev_info(&priv->udev->dev, "Product: %.41s\n",
2320 efuse->device_name);
2321 return 0;
2322 }
2323
2324 static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv)
2325 {
2326 struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu;
2327
2328 if (efuse->rtl_id != cpu_to_le16(0x8129))
2329 return -EINVAL;
2330
2331 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2332
2333 memcpy(priv->cck_tx_power_index_A, efuse->cck_tx_power_index_A,
2334 sizeof(priv->cck_tx_power_index_A));
2335 memcpy(priv->cck_tx_power_index_B, efuse->cck_tx_power_index_B,
2336 sizeof(priv->cck_tx_power_index_B));
2337
2338 memcpy(priv->ht40_1s_tx_power_index_A, efuse->ht40_1s_tx_power_index_A,
2339 sizeof(priv->ht40_1s_tx_power_index_A));
2340 memcpy(priv->ht40_1s_tx_power_index_B, efuse->ht40_1s_tx_power_index_B,
2341 sizeof(priv->ht40_1s_tx_power_index_B));
2342
2343 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2344 dev_info(&priv->udev->dev, "Product: %.41s\n", efuse->device_name);
2345
2346 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2347 int i;
2348 unsigned char *raw = priv->efuse_wifi.raw;
2349
2350 dev_info(&priv->udev->dev,
2351 "%s: dumping efuse (0x%02zx bytes):\n",
2352 __func__, sizeof(struct rtl8723bu_efuse));
2353 for (i = 0; i < sizeof(struct rtl8723bu_efuse); i += 8) {
2354 dev_info(&priv->udev->dev, "%02x: "
2355 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2356 raw[i], raw[i + 1], raw[i + 2],
2357 raw[i + 3], raw[i + 4], raw[i + 5],
2358 raw[i + 6], raw[i + 7]);
2359 }
2360 }
2361
2362 return 0;
2363 }
2364
2365 #ifdef CONFIG_RTL8XXXU_UNTESTED
2366
2367 static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
2368 {
2369 struct rtl8192cu_efuse *efuse = &priv->efuse_wifi.efuse8192;
2370 int i;
2371
2372 if (efuse->rtl_id != cpu_to_le16(0x8129))
2373 return -EINVAL;
2374
2375 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2376
2377 memcpy(priv->cck_tx_power_index_A,
2378 efuse->cck_tx_power_index_A,
2379 sizeof(priv->cck_tx_power_index_A));
2380 memcpy(priv->cck_tx_power_index_B,
2381 efuse->cck_tx_power_index_B,
2382 sizeof(priv->cck_tx_power_index_B));
2383
2384 memcpy(priv->ht40_1s_tx_power_index_A,
2385 efuse->ht40_1s_tx_power_index_A,
2386 sizeof(priv->ht40_1s_tx_power_index_A));
2387 memcpy(priv->ht40_1s_tx_power_index_B,
2388 efuse->ht40_1s_tx_power_index_B,
2389 sizeof(priv->ht40_1s_tx_power_index_B));
2390 memcpy(priv->ht40_2s_tx_power_index_diff,
2391 efuse->ht40_2s_tx_power_index_diff,
2392 sizeof(priv->ht40_2s_tx_power_index_diff));
2393
2394 memcpy(priv->ht20_tx_power_index_diff,
2395 efuse->ht20_tx_power_index_diff,
2396 sizeof(priv->ht20_tx_power_index_diff));
2397 memcpy(priv->ofdm_tx_power_index_diff,
2398 efuse->ofdm_tx_power_index_diff,
2399 sizeof(priv->ofdm_tx_power_index_diff));
2400
2401 memcpy(priv->ht40_max_power_offset,
2402 efuse->ht40_max_power_offset,
2403 sizeof(priv->ht40_max_power_offset));
2404 memcpy(priv->ht20_max_power_offset,
2405 efuse->ht20_max_power_offset,
2406 sizeof(priv->ht20_max_power_offset));
2407
2408 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2409 efuse->vendor_name);
2410 dev_info(&priv->udev->dev, "Product: %.20s\n",
2411 efuse->device_name);
2412
2413 if (efuse->rf_regulatory & 0x20) {
2414 sprintf(priv->chip_name, "8188RU");
2415 priv->hi_pa = 1;
2416 }
2417
2418 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2419 unsigned char *raw = priv->efuse_wifi.raw;
2420
2421 dev_info(&priv->udev->dev,
2422 "%s: dumping efuse (0x%02zx bytes):\n",
2423 __func__, sizeof(struct rtl8192cu_efuse));
2424 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
2425 dev_info(&priv->udev->dev, "%02x: "
2426 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2427 raw[i], raw[i + 1], raw[i + 2],
2428 raw[i + 3], raw[i + 4], raw[i + 5],
2429 raw[i + 6], raw[i + 7]);
2430 }
2431 }
2432 return 0;
2433 }
2434
2435 #endif
2436
2437 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)
2438 {
2439 struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu;
2440 int i;
2441
2442 if (efuse->rtl_id != cpu_to_le16(0x8129))
2443 return -EINVAL;
2444
2445 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2446
2447 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2448 dev_info(&priv->udev->dev, "Product: %.11s\n", efuse->device_name);
2449 dev_info(&priv->udev->dev, "Serial: %.11s\n", efuse->serial);
2450
2451 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2452 unsigned char *raw = priv->efuse_wifi.raw;
2453
2454 dev_info(&priv->udev->dev,
2455 "%s: dumping efuse (0x%02zx bytes):\n",
2456 __func__, sizeof(struct rtl8192eu_efuse));
2457 for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8) {
2458 dev_info(&priv->udev->dev, "%02x: "
2459 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2460 raw[i], raw[i + 1], raw[i + 2],
2461 raw[i + 3], raw[i + 4], raw[i + 5],
2462 raw[i + 6], raw[i + 7]);
2463 }
2464 }
2465 return 0;
2466 }
2467
2468 static int
2469 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
2470 {
2471 int i;
2472 u8 val8;
2473 u32 val32;
2474
2475 /* Write Address */
2476 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
2477 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
2478 val8 &= 0xfc;
2479 val8 |= (offset >> 8) & 0x03;
2480 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
2481
2482 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
2483 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
2484
2485 /* Poll for data read */
2486 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2487 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
2488 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2489 if (val32 & BIT(31))
2490 break;
2491 }
2492
2493 if (i == RTL8XXXU_MAX_REG_POLL)
2494 return -EIO;
2495
2496 udelay(50);
2497 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2498
2499 *data = val32 & 0xff;
2500 return 0;
2501 }
2502
2503 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
2504 {
2505 struct device *dev = &priv->udev->dev;
2506 int i, ret = 0;
2507 u8 val8, word_mask, header, extheader;
2508 u16 val16, efuse_addr, offset;
2509 u32 val32;
2510
2511 val16 = rtl8xxxu_read16(priv, REG_9346CR);
2512 if (val16 & EEPROM_ENABLE)
2513 priv->has_eeprom = 1;
2514 if (val16 & EEPROM_BOOT)
2515 priv->boot_eeprom = 1;
2516
2517 if (priv->is_multi_func) {
2518 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
2519 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
2520 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
2521 }
2522
2523 dev_dbg(dev, "Booting from %s\n",
2524 priv->boot_eeprom ? "EEPROM" : "EFUSE");
2525
2526 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
2527
2528 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
2529 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
2530 if (!(val16 & SYS_ISO_PWC_EV12V)) {
2531 val16 |= SYS_ISO_PWC_EV12V;
2532 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
2533 }
2534 /* Reset: 0x0000[28], default valid */
2535 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2536 if (!(val16 & SYS_FUNC_ELDR)) {
2537 val16 |= SYS_FUNC_ELDR;
2538 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2539 }
2540
2541 /*
2542 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
2543 */
2544 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
2545 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
2546 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
2547 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
2548 }
2549
2550 /* Default value is 0xff */
2551 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
2552
2553 efuse_addr = 0;
2554 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
2555 u16 map_addr;
2556
2557 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
2558 if (ret || header == 0xff)
2559 goto exit;
2560
2561 if ((header & 0x1f) == 0x0f) { /* extended header */
2562 offset = (header & 0xe0) >> 5;
2563
2564 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
2565 &extheader);
2566 if (ret)
2567 goto exit;
2568 /* All words disabled */
2569 if ((extheader & 0x0f) == 0x0f)
2570 continue;
2571
2572 offset |= ((extheader & 0xf0) >> 1);
2573 word_mask = extheader & 0x0f;
2574 } else {
2575 offset = (header >> 4) & 0x0f;
2576 word_mask = header & 0x0f;
2577 }
2578
2579 /* Get word enable value from PG header */
2580
2581 /* We have 8 bits to indicate validity */
2582 map_addr = offset * 8;
2583 if (map_addr >= EFUSE_MAP_LEN) {
2584 dev_warn(dev, "%s: Illegal map_addr (%04x), "
2585 "efuse corrupt!\n",
2586 __func__, map_addr);
2587 ret = -EINVAL;
2588 goto exit;
2589 }
2590 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2591 /* Check word enable condition in the section */
2592 if (word_mask & BIT(i)) {
2593 map_addr += 2;
2594 continue;
2595 }
2596
2597 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2598 if (ret)
2599 goto exit;
2600 priv->efuse_wifi.raw[map_addr++] = val8;
2601
2602 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2603 if (ret)
2604 goto exit;
2605 priv->efuse_wifi.raw[map_addr++] = val8;
2606 }
2607 }
2608
2609 exit:
2610 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
2611
2612 return ret;
2613 }
2614
2615 static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
2616 {
2617 u8 val8;
2618 u16 sys_func;
2619
2620 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2621 val8 &= ~BIT(0);
2622 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2623 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2624 sys_func &= ~SYS_FUNC_CPU_ENABLE;
2625 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2626 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2627 val8 |= BIT(0);
2628 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2629 sys_func |= SYS_FUNC_CPU_ENABLE;
2630 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2631 }
2632
2633 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
2634 {
2635 struct device *dev = &priv->udev->dev;
2636 int ret = 0, i;
2637 u32 val32;
2638
2639 /* Poll checksum report */
2640 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2641 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2642 if (val32 & MCU_FW_DL_CSUM_REPORT)
2643 break;
2644 }
2645
2646 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2647 dev_warn(dev, "Firmware checksum poll timed out\n");
2648 ret = -EAGAIN;
2649 goto exit;
2650 }
2651
2652 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2653 val32 |= MCU_FW_DL_READY;
2654 val32 &= ~MCU_WINT_INIT_READY;
2655 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2656
2657 /*
2658 * Reset the 8051 in order for the firmware to start running,
2659 * otherwise it won't come up on the 8192eu
2660 */
2661 rtl8xxxu_reset_8051(priv);
2662
2663 /* Wait for firmware to become ready */
2664 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2665 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2666 if (val32 & MCU_WINT_INIT_READY)
2667 break;
2668
2669 udelay(100);
2670 }
2671
2672 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2673 dev_warn(dev, "Firmware failed to start\n");
2674 ret = -EAGAIN;
2675 goto exit;
2676 }
2677
2678 exit:
2679 return ret;
2680 }
2681
2682 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2683 {
2684 int pages, remainder, i, ret;
2685 u8 val8;
2686 u16 val16;
2687 u32 val32;
2688 u8 *fwptr;
2689
2690 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2691 val8 |= 4;
2692 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2693
2694 /* 8051 enable */
2695 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2696 val16 |= SYS_FUNC_CPU_ENABLE;
2697 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2698
2699 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2700 if (val8 & MCU_FW_RAM_SEL) {
2701 pr_info("do the RAM reset\n");
2702 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
2703 rtl8xxxu_reset_8051(priv);
2704 }
2705
2706 /* MCU firmware download enable */
2707 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2708 val8 |= MCU_FW_DL_ENABLE;
2709 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2710
2711 /* 8051 reset */
2712 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2713 val32 &= ~BIT(19);
2714 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2715
2716 /* Reset firmware download checksum */
2717 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2718 val8 |= MCU_FW_DL_CSUM_REPORT;
2719 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2720
2721 pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2722 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2723
2724 fwptr = priv->fw_data->data;
2725
2726 for (i = 0; i < pages; i++) {
2727 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2728 val8 |= i;
2729 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2730
2731 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2732 fwptr, RTL_FW_PAGE_SIZE);
2733 if (ret != RTL_FW_PAGE_SIZE) {
2734 ret = -EAGAIN;
2735 goto fw_abort;
2736 }
2737
2738 fwptr += RTL_FW_PAGE_SIZE;
2739 }
2740
2741 if (remainder) {
2742 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2743 val8 |= i;
2744 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2745 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2746 fwptr, remainder);
2747 if (ret != remainder) {
2748 ret = -EAGAIN;
2749 goto fw_abort;
2750 }
2751 }
2752
2753 ret = 0;
2754 fw_abort:
2755 /* MCU firmware download disable */
2756 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
2757 val16 &= ~MCU_FW_DL_ENABLE;
2758 rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
2759
2760 return ret;
2761 }
2762
2763 static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2764 {
2765 struct device *dev = &priv->udev->dev;
2766 const struct firmware *fw;
2767 int ret = 0;
2768 u16 signature;
2769
2770 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2771 if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2772 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2773 ret = -EAGAIN;
2774 goto exit;
2775 }
2776 if (!fw) {
2777 dev_warn(dev, "Firmware data not available\n");
2778 ret = -EINVAL;
2779 goto exit;
2780 }
2781
2782 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
2783 if (!priv->fw_data) {
2784 ret = -ENOMEM;
2785 goto exit;
2786 }
2787 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2788
2789 signature = le16_to_cpu(priv->fw_data->signature);
2790 switch (signature & 0xfff0) {
2791 case 0x92e0:
2792 case 0x92c0:
2793 case 0x88c0:
2794 case 0x5300:
2795 case 0x2300:
2796 break;
2797 default:
2798 ret = -EINVAL;
2799 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2800 __func__, signature);
2801 }
2802
2803 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2804 le16_to_cpu(priv->fw_data->major_version),
2805 priv->fw_data->minor_version, signature);
2806
2807 exit:
2808 release_firmware(fw);
2809 return ret;
2810 }
2811
2812 static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
2813 {
2814 char *fw_name;
2815 int ret;
2816
2817 switch (priv->chip_cut) {
2818 case 0:
2819 fw_name = "rtlwifi/rtl8723aufw_A.bin";
2820 break;
2821 case 1:
2822 if (priv->enable_bluetooth)
2823 fw_name = "rtlwifi/rtl8723aufw_B.bin";
2824 else
2825 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
2826
2827 break;
2828 default:
2829 return -EINVAL;
2830 }
2831
2832 ret = rtl8xxxu_load_firmware(priv, fw_name);
2833 return ret;
2834 }
2835
2836 static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv)
2837 {
2838 char *fw_name;
2839 int ret;
2840
2841 if (priv->enable_bluetooth)
2842 fw_name = "rtlwifi/rtl8723bu_bt.bin";
2843 else
2844 fw_name = "rtlwifi/rtl8723bu_nic.bin";
2845
2846 ret = rtl8xxxu_load_firmware(priv, fw_name);
2847 return ret;
2848 }
2849
2850 #ifdef CONFIG_RTL8XXXU_UNTESTED
2851
2852 static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
2853 {
2854 char *fw_name;
2855 int ret;
2856
2857 if (!priv->vendor_umc)
2858 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
2859 else if (priv->chip_cut || priv->rtlchip == 0x8192c)
2860 fw_name = "rtlwifi/rtl8192cufw_B.bin";
2861 else
2862 fw_name = "rtlwifi/rtl8192cufw_A.bin";
2863
2864 ret = rtl8xxxu_load_firmware(priv, fw_name);
2865
2866 return ret;
2867 }
2868
2869 #endif
2870
2871 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)
2872 {
2873 char *fw_name;
2874 int ret;
2875
2876 fw_name = "rtlwifi/rtl8192eu_nic.bin";
2877
2878 ret = rtl8xxxu_load_firmware(priv, fw_name);
2879
2880 return ret;
2881 }
2882
2883 static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2884 {
2885 u16 val16;
2886 int i = 100;
2887
2888 /* Inform 8051 to perform reset */
2889 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2890
2891 for (i = 100; i > 0; i--) {
2892 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2893
2894 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2895 dev_dbg(&priv->udev->dev,
2896 "%s: Firmware self reset success!\n", __func__);
2897 break;
2898 }
2899 udelay(50);
2900 }
2901
2902 if (!i) {
2903 /* Force firmware reset */
2904 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2905 val16 &= ~SYS_FUNC_CPU_ENABLE;
2906 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2907 }
2908 }
2909
2910 static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv)
2911 {
2912 u32 val32;
2913
2914 val32 = rtl8xxxu_read32(priv, 0x64);
2915 val32 &= ~(BIT(20) | BIT(24));
2916 rtl8xxxu_write32(priv, 0x64, val32);
2917
2918 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
2919 val32 &= ~BIT(4);
2920 val32 |= BIT(3);
2921 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
2922
2923 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
2924 val32 &= ~BIT(23);
2925 val32 |= BIT(24);
2926 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
2927
2928 val32 = rtl8xxxu_read32(priv, 0x0944);
2929 val32 |= (BIT(0) | BIT(1));
2930 rtl8xxxu_write32(priv, 0x0944, val32);
2931
2932 val32 = rtl8xxxu_read32(priv, 0x0930);
2933 val32 &= 0xffffff00;
2934 val32 |= 0x77;
2935 rtl8xxxu_write32(priv, 0x0930, val32);
2936 }
2937
2938 static int
2939 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv, struct rtl8xxxu_reg8val *array)
2940 {
2941 int i, ret;
2942 u16 reg;
2943 u8 val;
2944
2945 for (i = 0; ; i++) {
2946 reg = array[i].reg;
2947 val = array[i].val;
2948
2949 if (reg == 0xffff && val == 0xff)
2950 break;
2951
2952 ret = rtl8xxxu_write8(priv, reg, val);
2953 if (ret != 1) {
2954 dev_warn(&priv->udev->dev,
2955 "Failed to initialize MAC\n");
2956 return -EAGAIN;
2957 }
2958 }
2959
2960 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2961
2962 return 0;
2963 }
2964
2965 static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2966 struct rtl8xxxu_reg32val *array)
2967 {
2968 int i, ret;
2969 u16 reg;
2970 u32 val;
2971
2972 for (i = 0; ; i++) {
2973 reg = array[i].reg;
2974 val = array[i].val;
2975
2976 if (reg == 0xffff && val == 0xffffffff)
2977 break;
2978
2979 ret = rtl8xxxu_write32(priv, reg, val);
2980 if (ret != sizeof(val)) {
2981 dev_warn(&priv->udev->dev,
2982 "Failed to initialize PHY\n");
2983 return -EAGAIN;
2984 }
2985 udelay(1);
2986 }
2987
2988 return 0;
2989 }
2990
2991 /*
2992 * Most of this is black magic retrieved from the old rtl8723au driver
2993 */
2994 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2995 {
2996 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
2997 u16 val16;
2998 u32 val32;
2999
3000 /*
3001 * Todo: The vendor driver maintains a table of PHY register
3002 * addresses, which is initialized here. Do we need this?
3003 */
3004
3005 if (priv->rtlchip == 0x8723b) {
3006 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
3007 } else {
3008 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
3009 udelay(2);
3010 val8 |= AFE_PLL_320_ENABLE;
3011 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
3012 udelay(2);
3013
3014 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
3015 udelay(2);
3016 }
3017
3018 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3019 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
3020 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3021
3022 if (priv->rtlchip != 0x8723b) {
3023 /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
3024 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
3025 val32 &= ~AFE_XTAL_RF_GATE;
3026 if (priv->has_bluetooth)
3027 val32 &= ~AFE_XTAL_BT_GATE;
3028 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
3029 }
3030
3031 /* 6. 0x1f[7:0] = 0x07 */
3032 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
3033 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
3034
3035 if (priv->hi_pa)
3036 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
3037 else if (priv->tx_paths == 2)
3038 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
3039 else if (priv->rtlchip == 0x8723b)
3040 rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table);
3041 else
3042 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
3043
3044
3045 if (priv->rtlchip == 0x8188c && priv->hi_pa &&
3046 priv->vendor_umc && priv->chip_cut == 1)
3047 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
3048
3049 if (priv->tx_paths == 1 && priv->rx_paths == 2) {
3050 /*
3051 * For 1T2R boards, patch the registers.
3052 *
3053 * It looks like 8191/2 1T2R boards use path B for TX
3054 */
3055 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
3056 val32 &= ~(BIT(0) | BIT(1));
3057 val32 |= BIT(1);
3058 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
3059
3060 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
3061 val32 &= ~0x300033;
3062 val32 |= 0x200022;
3063 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
3064
3065 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
3066 val32 &= 0xff000000;
3067 val32 |= 0x45000000;
3068 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
3069
3070 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
3071 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
3072 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
3073 OFDM_RF_PATH_TX_B);
3074 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
3075
3076 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
3077 val32 &= ~(BIT(4) | BIT(5));
3078 val32 |= BIT(4);
3079 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
3080
3081 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
3082 val32 &= ~(BIT(27) | BIT(26));
3083 val32 |= BIT(27);
3084 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
3085
3086 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
3087 val32 &= ~(BIT(27) | BIT(26));
3088 val32 |= BIT(27);
3089 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
3090
3091 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
3092 val32 &= ~(BIT(27) | BIT(26));
3093 val32 |= BIT(27);
3094 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
3095
3096 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
3097 val32 &= ~(BIT(27) | BIT(26));
3098 val32 |= BIT(27);
3099 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
3100
3101 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
3102 val32 &= ~(BIT(27) | BIT(26));
3103 val32 |= BIT(27);
3104 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
3105 }
3106
3107 if (priv->rtlchip == 0x8723b)
3108 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table);
3109 else if (priv->hi_pa)
3110 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
3111 else
3112 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
3113
3114 if ((priv->rtlchip == 0x8723a || priv->rtlchip == 0x8723b) &&
3115 priv->efuse_wifi.efuse8723.version >= 0x01) {
3116 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
3117
3118 val8 = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
3119 val32 &= 0xff000fff;
3120 val32 |= ((val8 | (val8 << 6)) << 12);
3121
3122 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
3123 }
3124
3125 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
3126 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
3127 ldohci12 = 0x57;
3128 lpldo = 1;
3129 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
3130
3131 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
3132
3133 return 0;
3134 }
3135
3136 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
3137 struct rtl8xxxu_rfregval *array,
3138 enum rtl8xxxu_rfpath path)
3139 {
3140 int i, ret;
3141 u8 reg;
3142 u32 val;
3143
3144 for (i = 0; ; i++) {
3145 reg = array[i].reg;
3146 val = array[i].val;
3147
3148 if (reg == 0xff && val == 0xffffffff)
3149 break;
3150
3151 switch (reg) {
3152 case 0xfe:
3153 msleep(50);
3154 continue;
3155 case 0xfd:
3156 mdelay(5);
3157 continue;
3158 case 0xfc:
3159 mdelay(1);
3160 continue;
3161 case 0xfb:
3162 udelay(50);
3163 continue;
3164 case 0xfa:
3165 udelay(5);
3166 continue;
3167 case 0xf9:
3168 udelay(1);
3169 continue;
3170 }
3171
3172 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
3173 if (ret) {
3174 dev_warn(&priv->udev->dev,
3175 "Failed to initialize RF\n");
3176 return -EAGAIN;
3177 }
3178 udelay(1);
3179 }
3180
3181 return 0;
3182 }
3183
3184 static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
3185 struct rtl8xxxu_rfregval *table,
3186 enum rtl8xxxu_rfpath path)
3187 {
3188 u32 val32;
3189 u16 val16, rfsi_rfenv;
3190 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
3191
3192 switch (path) {
3193 case RF_A:
3194 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
3195 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
3196 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
3197 break;
3198 case RF_B:
3199 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
3200 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
3201 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
3202 break;
3203 default:
3204 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
3205 __func__, path + 'A');
3206 return -EINVAL;
3207 }
3208 /* For path B, use XB */
3209 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
3210 rfsi_rfenv &= FPGA0_RF_RFENV;
3211
3212 /*
3213 * These two we might be able to optimize into one
3214 */
3215 val32 = rtl8xxxu_read32(priv, reg_int_oe);
3216 val32 |= BIT(20); /* 0x10 << 16 */
3217 rtl8xxxu_write32(priv, reg_int_oe, val32);
3218 udelay(1);
3219
3220 val32 = rtl8xxxu_read32(priv, reg_int_oe);
3221 val32 |= BIT(4);
3222 rtl8xxxu_write32(priv, reg_int_oe, val32);
3223 udelay(1);
3224
3225 /*
3226 * These two we might be able to optimize into one
3227 */
3228 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3229 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
3230 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3231 udelay(1);
3232
3233 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3234 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
3235 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3236 udelay(1);
3237
3238 rtl8xxxu_init_rf_regs(priv, table, path);
3239
3240 /* For path B, use XB */
3241 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
3242 val16 &= ~FPGA0_RF_RFENV;
3243 val16 |= rfsi_rfenv;
3244 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
3245
3246 return 0;
3247 }
3248
3249 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
3250 {
3251 int ret = -EBUSY;
3252 int count = 0;
3253 u32 value;
3254
3255 value = LLT_OP_WRITE | address << 8 | data;
3256
3257 rtl8xxxu_write32(priv, REG_LLT_INIT, value);
3258
3259 do {
3260 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
3261 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
3262 ret = 0;
3263 break;
3264 }
3265 } while (count++ < 20);
3266
3267 return ret;
3268 }
3269
3270 static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3271 {
3272 int ret;
3273 int i;
3274
3275 for (i = 0; i < last_tx_page; i++) {
3276 ret = rtl8xxxu_llt_write(priv, i, i + 1);
3277 if (ret)
3278 goto exit;
3279 }
3280
3281 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
3282 if (ret)
3283 goto exit;
3284
3285 /* Mark remaining pages as a ring buffer */
3286 for (i = last_tx_page + 1; i < 0xff; i++) {
3287 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
3288 if (ret)
3289 goto exit;
3290 }
3291
3292 /* Let last entry point to the start entry of ring buffer */
3293 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
3294 if (ret)
3295 goto exit;
3296
3297 exit:
3298 return ret;
3299 }
3300
3301 static int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3302 {
3303 u32 val32;
3304 int ret = 0;
3305 int i;
3306
3307 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3308 val32 |= AUTO_LLT_INIT_LLT;
3309 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
3310
3311 for (i = 500; i; i--) {
3312 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3313 if (!(val32 & AUTO_LLT_INIT_LLT))
3314 break;
3315 usleep_range(2, 4);
3316 }
3317
3318 if (!i) {
3319 ret = -EBUSY;
3320 dev_warn(&priv->udev->dev, "LLT table init failed\n");
3321 }
3322
3323 return ret;
3324 }
3325
3326 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
3327 {
3328 u16 val16, hi, lo;
3329 u16 hiq, mgq, bkq, beq, viq, voq;
3330 int hip, mgp, bkp, bep, vip, vop;
3331 int ret = 0;
3332
3333 switch (priv->ep_tx_count) {
3334 case 1:
3335 if (priv->ep_tx_high_queue) {
3336 hi = TRXDMA_QUEUE_HIGH;
3337 } else if (priv->ep_tx_low_queue) {
3338 hi = TRXDMA_QUEUE_LOW;
3339 } else if (priv->ep_tx_normal_queue) {
3340 hi = TRXDMA_QUEUE_NORMAL;
3341 } else {
3342 hi = 0;
3343 ret = -EINVAL;
3344 }
3345
3346 hiq = hi;
3347 mgq = hi;
3348 bkq = hi;
3349 beq = hi;
3350 viq = hi;
3351 voq = hi;
3352
3353 hip = 0;
3354 mgp = 0;
3355 bkp = 0;
3356 bep = 0;
3357 vip = 0;
3358 vop = 0;
3359 break;
3360 case 2:
3361 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
3362 hi = TRXDMA_QUEUE_HIGH;
3363 lo = TRXDMA_QUEUE_LOW;
3364 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
3365 hi = TRXDMA_QUEUE_NORMAL;
3366 lo = TRXDMA_QUEUE_LOW;
3367 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
3368 hi = TRXDMA_QUEUE_HIGH;
3369 lo = TRXDMA_QUEUE_NORMAL;
3370 } else {
3371 ret = -EINVAL;
3372 hi = 0;
3373 lo = 0;
3374 }
3375
3376 hiq = hi;
3377 mgq = hi;
3378 bkq = lo;
3379 beq = lo;
3380 viq = hi;
3381 voq = hi;
3382
3383 hip = 0;
3384 mgp = 0;
3385 bkp = 1;
3386 bep = 1;
3387 vip = 0;
3388 vop = 0;
3389 break;
3390 case 3:
3391 beq = TRXDMA_QUEUE_LOW;
3392 bkq = TRXDMA_QUEUE_LOW;
3393 viq = TRXDMA_QUEUE_NORMAL;
3394 voq = TRXDMA_QUEUE_HIGH;
3395 mgq = TRXDMA_QUEUE_HIGH;
3396 hiq = TRXDMA_QUEUE_HIGH;
3397
3398 hip = hiq ^ 3;
3399 mgp = mgq ^ 3;
3400 bkp = bkq ^ 3;
3401 bep = beq ^ 3;
3402 vip = viq ^ 3;
3403 vop = viq ^ 3;
3404 break;
3405 default:
3406 ret = -EINVAL;
3407 }
3408
3409 /*
3410 * None of the vendor drivers are configuring the beacon
3411 * queue here .... why?
3412 */
3413 if (!ret) {
3414 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
3415 val16 &= 0x7;
3416 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
3417 (viq << TRXDMA_CTRL_VIQ_SHIFT) |
3418 (beq << TRXDMA_CTRL_BEQ_SHIFT) |
3419 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
3420 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
3421 (hiq << TRXDMA_CTRL_HIQ_SHIFT);
3422 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
3423
3424 priv->pipe_out[TXDESC_QUEUE_VO] =
3425 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
3426 priv->pipe_out[TXDESC_QUEUE_VI] =
3427 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
3428 priv->pipe_out[TXDESC_QUEUE_BE] =
3429 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
3430 priv->pipe_out[TXDESC_QUEUE_BK] =
3431 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
3432 priv->pipe_out[TXDESC_QUEUE_BEACON] =
3433 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3434 priv->pipe_out[TXDESC_QUEUE_MGNT] =
3435 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
3436 priv->pipe_out[TXDESC_QUEUE_HIGH] =
3437 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
3438 priv->pipe_out[TXDESC_QUEUE_CMD] =
3439 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3440 }
3441
3442 return ret;
3443 }
3444
3445 static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
3446 bool iqk_ok, int result[][8],
3447 int candidate, bool tx_only)
3448 {
3449 u32 oldval, x, tx0_a, reg;
3450 int y, tx0_c;
3451 u32 val32;
3452
3453 if (!iqk_ok)
3454 return;
3455
3456 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3457 oldval = val32 >> 22;
3458
3459 x = result[candidate][0];
3460 if ((x & 0x00000200) != 0)
3461 x = x | 0xfffffc00;
3462 tx0_a = (x * oldval) >> 8;
3463
3464 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3465 val32 &= ~0x3ff;
3466 val32 |= tx0_a;
3467 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3468
3469 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3470 val32 &= ~BIT(31);
3471 if ((x * oldval >> 7) & 0x1)
3472 val32 |= BIT(31);
3473 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3474
3475 y = result[candidate][1];
3476 if ((y & 0x00000200) != 0)
3477 y = y | 0xfffffc00;
3478 tx0_c = (y * oldval) >> 8;
3479
3480 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
3481 val32 &= ~0xf0000000;
3482 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
3483 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
3484
3485 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3486 val32 &= ~0x003f0000;
3487 val32 |= ((tx0_c & 0x3f) << 16);
3488 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3489
3490 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3491 val32 &= ~BIT(29);
3492 if ((y * oldval >> 7) & 0x1)
3493 val32 |= BIT(29);
3494 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3495
3496 if (tx_only) {
3497 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3498 return;
3499 }
3500
3501 reg = result[candidate][2];
3502
3503 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3504 val32 &= ~0x3ff;
3505 val32 |= (reg & 0x3ff);
3506 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3507
3508 reg = result[candidate][3] & 0x3F;
3509
3510 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3511 val32 &= ~0xfc00;
3512 val32 |= ((reg << 10) & 0xfc00);
3513 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3514
3515 reg = (result[candidate][3] >> 6) & 0xF;
3516
3517 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
3518 val32 &= ~0xf0000000;
3519 val32 |= (reg << 28);
3520 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
3521 }
3522
3523 static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
3524 bool iqk_ok, int result[][8],
3525 int candidate, bool tx_only)
3526 {
3527 u32 oldval, x, tx1_a, reg;
3528 int y, tx1_c;
3529 u32 val32;
3530
3531 if (!iqk_ok)
3532 return;
3533
3534 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3535 oldval = val32 >> 22;
3536
3537 x = result[candidate][4];
3538 if ((x & 0x00000200) != 0)
3539 x = x | 0xfffffc00;
3540 tx1_a = (x * oldval) >> 8;
3541
3542 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3543 val32 &= ~0x3ff;
3544 val32 |= tx1_a;
3545 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3546
3547 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3548 val32 &= ~BIT(27);
3549 if ((x * oldval >> 7) & 0x1)
3550 val32 |= BIT(27);
3551 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3552
3553 y = result[candidate][5];
3554 if ((y & 0x00000200) != 0)
3555 y = y | 0xfffffc00;
3556 tx1_c = (y * oldval) >> 8;
3557
3558 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
3559 val32 &= ~0xf0000000;
3560 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
3561 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
3562
3563 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3564 val32 &= ~0x003f0000;
3565 val32 |= ((tx1_c & 0x3f) << 16);
3566 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3567
3568 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3569 val32 &= ~BIT(25);
3570 if ((y * oldval >> 7) & 0x1)
3571 val32 |= BIT(25);
3572 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3573
3574 if (tx_only) {
3575 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3576 return;
3577 }
3578
3579 reg = result[candidate][6];
3580
3581 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3582 val32 &= ~0x3ff;
3583 val32 |= (reg & 0x3ff);
3584 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3585
3586 reg = result[candidate][7] & 0x3f;
3587
3588 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3589 val32 &= ~0xfc00;
3590 val32 |= ((reg << 10) & 0xfc00);
3591 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3592
3593 reg = (result[candidate][7] >> 6) & 0xf;
3594
3595 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
3596 val32 &= ~0x0000f000;
3597 val32 |= (reg << 12);
3598 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
3599 }
3600
3601 #define MAX_TOLERANCE 5
3602
3603 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
3604 int result[][8], int c1, int c2)
3605 {
3606 u32 i, j, diff, simubitmap, bound = 0;
3607 int candidate[2] = {-1, -1}; /* for path A and path B */
3608 bool retval = true;
3609
3610 if (priv->tx_paths > 1)
3611 bound = 8;
3612 else
3613 bound = 4;
3614
3615 simubitmap = 0;
3616
3617 for (i = 0; i < bound; i++) {
3618 diff = (result[c1][i] > result[c2][i]) ?
3619 (result[c1][i] - result[c2][i]) :
3620 (result[c2][i] - result[c1][i]);
3621 if (diff > MAX_TOLERANCE) {
3622 if ((i == 2 || i == 6) && !simubitmap) {
3623 if (result[c1][i] + result[c1][i + 1] == 0)
3624 candidate[(i / 4)] = c2;
3625 else if (result[c2][i] + result[c2][i + 1] == 0)
3626 candidate[(i / 4)] = c1;
3627 else
3628 simubitmap = simubitmap | (1 << i);
3629 } else {
3630 simubitmap = simubitmap | (1 << i);
3631 }
3632 }
3633 }
3634
3635 if (simubitmap == 0) {
3636 for (i = 0; i < (bound / 4); i++) {
3637 if (candidate[i] >= 0) {
3638 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3639 result[3][j] = result[candidate[i]][j];
3640 retval = false;
3641 }
3642 }
3643 return retval;
3644 } else if (!(simubitmap & 0x0f)) {
3645 /* path A OK */
3646 for (i = 0; i < 4; i++)
3647 result[3][i] = result[c1][i];
3648 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
3649 /* path B OK */
3650 for (i = 4; i < 8; i++)
3651 result[3][i] = result[c1][i];
3652 }
3653
3654 return false;
3655 }
3656
3657 static bool rtl8723bu_simularity_compare(struct rtl8xxxu_priv *priv,
3658 int result[][8], int c1, int c2)
3659 {
3660 u32 i, j, diff, simubitmap, bound = 0;
3661 int candidate[2] = {-1, -1}; /* for path A and path B */
3662 int tmp1, tmp2;
3663 bool retval = true;
3664
3665 if (priv->tx_paths > 1)
3666 bound = 8;
3667 else
3668 bound = 4;
3669
3670 simubitmap = 0;
3671
3672 for (i = 0; i < bound; i++) {
3673 if (i & 1) {
3674 if ((result[c1][i] & 0x00000200))
3675 tmp1 = result[c1][i] | 0xfffffc00;
3676 else
3677 tmp1 = result[c1][i];
3678
3679 if ((result[c2][i]& 0x00000200))
3680 tmp2 = result[c2][i] | 0xfffffc00;
3681 else
3682 tmp2 = result[c2][i];
3683 } else {
3684 tmp1 = result[c1][i];
3685 tmp2 = result[c2][i];
3686 }
3687
3688 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
3689
3690 if (diff > MAX_TOLERANCE) {
3691 if ((i == 2 || i == 6) && !simubitmap) {
3692 if (result[c1][i] + result[c1][i + 1] == 0)
3693 candidate[(i / 4)] = c2;
3694 else if (result[c2][i] + result[c2][i + 1] == 0)
3695 candidate[(i / 4)] = c1;
3696 else
3697 simubitmap = simubitmap | (1 << i);
3698 } else {
3699 simubitmap = simubitmap | (1 << i);
3700 }
3701 }
3702 }
3703
3704 if (simubitmap == 0) {
3705 for (i = 0; i < (bound / 4); i++) {
3706 if (candidate[i] >= 0) {
3707 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3708 result[3][j] = result[candidate[i]][j];
3709 retval = false;
3710 }
3711 }
3712 return retval;
3713 } else {
3714 if (!(simubitmap & 0x03)) {
3715 /* path A TX OK */
3716 for (i = 0; i < 2; i++)
3717 result[3][i] = result[c1][i];
3718 }
3719
3720 if (!(simubitmap & 0x0c)) {
3721 /* path A RX OK */
3722 for (i = 2; i < 4; i++)
3723 result[3][i] = result[c1][i];
3724 }
3725
3726 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
3727 /* path B RX OK */
3728 for (i = 4; i < 6; i++)
3729 result[3][i] = result[c1][i];
3730 }
3731
3732 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
3733 /* path B RX OK */
3734 for (i = 6; i < 8; i++)
3735 result[3][i] = result[c1][i];
3736 }
3737 }
3738
3739 return false;
3740 }
3741
3742 static void
3743 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
3744 {
3745 int i;
3746
3747 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3748 backup[i] = rtl8xxxu_read8(priv, reg[i]);
3749
3750 backup[i] = rtl8xxxu_read32(priv, reg[i]);
3751 }
3752
3753 static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
3754 const u32 *reg, u32 *backup)
3755 {
3756 int i;
3757
3758 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3759 rtl8xxxu_write8(priv, reg[i], backup[i]);
3760
3761 rtl8xxxu_write32(priv, reg[i], backup[i]);
3762 }
3763
3764 static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3765 u32 *backup, int count)
3766 {
3767 int i;
3768
3769 for (i = 0; i < count; i++)
3770 backup[i] = rtl8xxxu_read32(priv, regs[i]);
3771 }
3772
3773 static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3774 u32 *backup, int count)
3775 {
3776 int i;
3777
3778 for (i = 0; i < count; i++)
3779 rtl8xxxu_write32(priv, regs[i], backup[i]);
3780 }
3781
3782
3783 static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
3784 bool path_a_on)
3785 {
3786 u32 path_on;
3787 int i;
3788
3789 if (priv->tx_paths == 1) {
3790 path_on = priv->fops->adda_1t_path_on;
3791 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init);
3792 } else {
3793 path_on = path_a_on ? priv->fops->adda_2t_path_on_a :
3794 priv->fops->adda_2t_path_on_b;
3795
3796 rtl8xxxu_write32(priv, regs[0], path_on);
3797 }
3798
3799 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3800 rtl8xxxu_write32(priv, regs[i], path_on);
3801 }
3802
3803 static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3804 const u32 *regs, u32 *backup)
3805 {
3806 int i = 0;
3807
3808 rtl8xxxu_write8(priv, regs[i], 0x3f);
3809
3810 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3811 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3812
3813 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3814 }
3815
3816 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3817 {
3818 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3819 int result = 0;
3820
3821 /* path-A IQK setting */
3822 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3823 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3824 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3825
3826 val32 = (priv->rf_paths > 1) ? 0x28160202 :
3827 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3828 0x28160502;
3829 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3830
3831 /* path-B IQK setting */
3832 if (priv->rf_paths > 1) {
3833 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3834 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3835 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3836 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3837 }
3838
3839 /* LO calibration setting */
3840 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3841
3842 /* One shot, path A LOK & IQK */
3843 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3844 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3845
3846 mdelay(1);
3847
3848 /* Check failed */
3849 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3850 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3851 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3852 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3853
3854 if (!(reg_eac & BIT(28)) &&
3855 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3856 ((reg_e9c & 0x03ff0000) != 0x00420000))
3857 result |= 0x01;
3858 else /* If TX not OK, ignore RX */
3859 goto out;
3860
3861 /* If TX is OK, check whether RX is OK */
3862 if (!(reg_eac & BIT(27)) &&
3863 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3864 ((reg_eac & 0x03ff0000) != 0x00360000))
3865 result |= 0x02;
3866 else
3867 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3868 __func__);
3869 out:
3870 return result;
3871 }
3872
3873 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3874 {
3875 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3876 int result = 0;
3877
3878 /* One shot, path B LOK & IQK */
3879 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3880 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3881
3882 mdelay(1);
3883
3884 /* Check failed */
3885 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3886 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3887 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3888 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3889 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3890
3891 if (!(reg_eac & BIT(31)) &&
3892 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3893 ((reg_ebc & 0x03ff0000) != 0x00420000))
3894 result |= 0x01;
3895 else
3896 goto out;
3897
3898 if (!(reg_eac & BIT(30)) &&
3899 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3900 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3901 result |= 0x02;
3902 else
3903 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3904 __func__);
3905 out:
3906 return result;
3907 }
3908
3909 static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv)
3910 {
3911 u32 reg_eac, reg_e94, reg_e9c, path_sel, val32;
3912 int result = 0;
3913
3914 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
3915
3916 /*
3917 * Leave IQK mode
3918 */
3919 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
3920 val32 &= 0x000000ff;
3921 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
3922
3923 /*
3924 * Enable path A PA in TX IQK mode
3925 */
3926 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
3927 val32 |= 0x80000;
3928 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
3929 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000);
3930 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f);
3931 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87);
3932
3933 /*
3934 * Tx IQK setting
3935 */
3936 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3937 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3938
3939 /* path-A IQK setting */
3940 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
3941 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
3942 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
3943 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
3944
3945 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea);
3946 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
3947 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
3948 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
3949
3950 /* LO calibration setting */
3951 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
3952
3953 /*
3954 * Enter IQK mode
3955 */
3956 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
3957 val32 &= 0x000000ff;
3958 val32 |= 0x80800000;
3959 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
3960
3961 /*
3962 * The vendor driver indicates the USB module is always using
3963 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
3964 */
3965 if (priv->rf_paths > 1)
3966 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
3967 else
3968 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
3969
3970 /*
3971 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
3972 * No trace of this in the 8192eu or 8188eu vendor drivers.
3973 */
3974 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
3975
3976 /* One shot, path A LOK & IQK */
3977 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3978 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3979
3980 mdelay(1);
3981
3982 /* Restore Ant Path */
3983 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
3984 #ifdef RTL8723BU_BT
3985 /* GNT_BT = 1 */
3986 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
3987 #endif
3988
3989 /*
3990 * Leave IQK mode
3991 */
3992 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
3993 val32 &= 0x000000ff;
3994 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
3995
3996 /* Check failed */
3997 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3998 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3999 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4000
4001 val32 = (reg_e9c >> 16) & 0x3ff;
4002 if (val32 & 0x200)
4003 val32 = 0x400 - val32;
4004
4005 if (!(reg_eac & BIT(28)) &&
4006 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4007 ((reg_e9c & 0x03ff0000) != 0x00420000) &&
4008 ((reg_e94 & 0x03ff0000) < 0x01100000) &&
4009 ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
4010 val32 < 0xf)
4011 result |= 0x01;
4012 else /* If TX not OK, ignore RX */
4013 goto out;
4014
4015 out:
4016 return result;
4017 }
4018
4019 static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
4020 {
4021 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32;
4022 int result = 0;
4023
4024 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4025
4026 /*
4027 * Leave IQK mode
4028 */
4029 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4030 val32 &= 0x000000ff;
4031 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4032
4033 /*
4034 * Enable path A PA in TX IQK mode
4035 */
4036 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4037 val32 |= 0x80000;
4038 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4039 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4040 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4041 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
4042
4043 /*
4044 * Tx IQK setting
4045 */
4046 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4047 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4048
4049 /* path-A IQK setting */
4050 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
4051 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
4052 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4053 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4054
4055 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0);
4056 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
4057 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4058 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4059
4060 /* LO calibration setting */
4061 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
4062
4063 /*
4064 * Enter IQK mode
4065 */
4066 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4067 val32 &= 0x000000ff;
4068 val32 |= 0x80800000;
4069 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4070
4071 /*
4072 * The vendor driver indicates the USB module is always using
4073 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4074 */
4075 if (priv->rf_paths > 1)
4076 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4077 else
4078 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4079
4080 /*
4081 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4082 * No trace of this in the 8192eu or 8188eu vendor drivers.
4083 */
4084 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4085
4086 /* One shot, path A LOK & IQK */
4087 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4088 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4089
4090 mdelay(1);
4091
4092 /* Restore Ant Path */
4093 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4094 #ifdef RTL8723BU_BT
4095 /* GNT_BT = 1 */
4096 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4097 #endif
4098
4099 /*
4100 * Leave IQK mode
4101 */
4102 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4103 val32 &= 0x000000ff;
4104 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4105
4106 /* Check failed */
4107 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4108 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4109 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4110
4111 val32 = (reg_e9c >> 16) & 0x3ff;
4112 if (val32 & 0x200)
4113 val32 = 0x400 - val32;
4114
4115 if (!(reg_eac & BIT(28)) &&
4116 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4117 ((reg_e9c & 0x03ff0000) != 0x00420000) &&
4118 ((reg_e94 & 0x03ff0000) < 0x01100000) &&
4119 ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
4120 val32 < 0xf)
4121 result |= 0x01;
4122 else /* If TX not OK, ignore RX */
4123 goto out;
4124
4125 val32 = 0x80007c00 | (reg_e94 &0x3ff0000) |
4126 ((reg_e9c & 0x3ff0000) >> 16);
4127 rtl8xxxu_write32(priv, REG_TX_IQK, val32);
4128
4129 /*
4130 * Modify RX IQK mode
4131 */
4132 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4133 val32 &= 0x000000ff;
4134 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4135 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4136 val32 |= 0x80000;
4137 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4138 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4139 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4140 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77);
4141
4142 /*
4143 * PA, PAD setting
4144 */
4145 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0xf80);
4146 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f);
4147
4148 /*
4149 * RX IQK setting
4150 */
4151 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4152
4153 /* path-A IQK setting */
4154 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
4155 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
4156 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4157 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4158
4159 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000);
4160 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f);
4161 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4162 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4163
4164 /* LO calibration setting */
4165 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1);
4166
4167 /*
4168 * Enter IQK mode
4169 */
4170 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4171 val32 &= 0x000000ff;
4172 val32 |= 0x80800000;
4173 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4174
4175 if (priv->rf_paths > 1)
4176 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4177 else
4178 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4179
4180 /*
4181 * Disable BT
4182 */
4183 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4184
4185 /* One shot, path A LOK & IQK */
4186 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4187 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4188
4189 mdelay(1);
4190
4191 /* Restore Ant Path */
4192 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4193 #ifdef RTL8723BU_BT
4194 /* GNT_BT = 1 */
4195 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4196 #endif
4197
4198 /*
4199 * Leave IQK mode
4200 */
4201 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4202 val32 &= 0x000000ff;
4203 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4204
4205 /* Check failed */
4206 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4207 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
4208
4209 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x780);
4210
4211 val32 = (reg_eac >> 16) & 0x3ff;
4212 if (val32 & 0x200)
4213 val32 = 0x400 - val32;
4214
4215 if (!(reg_eac & BIT(27)) &&
4216 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
4217 ((reg_eac & 0x03ff0000) != 0x00360000) &&
4218 ((reg_ea4 & 0x03ff0000) < 0x01100000) &&
4219 ((reg_ea4 & 0x03ff0000) > 0x00f00000) &&
4220 val32 < 0xf)
4221 result |= 0x02;
4222 else /* If TX not OK, ignore RX */
4223 goto out;
4224 out:
4225 return result;
4226 }
4227
4228 #ifdef RTL8723BU_PATH_B
4229 static int rtl8723bu_iqk_path_b(struct rtl8xxxu_priv *priv)
4230 {
4231 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, path_sel;
4232 int result = 0;
4233
4234 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4235
4236 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4237 val32 &= 0x000000ff;
4238 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4239
4240 /* One shot, path B LOK & IQK */
4241 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
4242 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
4243
4244 mdelay(1);
4245
4246 /* Check failed */
4247 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4248 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4249 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4250 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4251 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4252
4253 if (!(reg_eac & BIT(31)) &&
4254 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
4255 ((reg_ebc & 0x03ff0000) != 0x00420000))
4256 result |= 0x01;
4257 else
4258 goto out;
4259
4260 if (!(reg_eac & BIT(30)) &&
4261 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
4262 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
4263 result |= 0x02;
4264 else
4265 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
4266 __func__);
4267 out:
4268 return result;
4269 }
4270 #endif
4271
4272 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
4273 int result[][8], int t)
4274 {
4275 struct device *dev = &priv->udev->dev;
4276 u32 i, val32;
4277 int path_a_ok, path_b_ok;
4278 int retry = 2;
4279 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
4280 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
4281 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
4282 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
4283 REG_TX_OFDM_BBON, REG_TX_TO_RX,
4284 REG_TX_TO_TX, REG_RX_CCK,
4285 REG_RX_OFDM, REG_RX_WAIT_RIFS,
4286 REG_RX_TO_RX, REG_STANDBY,
4287 REG_SLEEP, REG_PMPD_ANAEN
4288 };
4289 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
4290 REG_TXPAUSE, REG_BEACON_CTRL,
4291 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
4292 };
4293 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
4294 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
4295 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
4296 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
4297 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
4298 };
4299
4300 /*
4301 * Note: IQ calibration must be performed after loading
4302 * PHY_REG.txt , and radio_a, radio_b.txt
4303 */
4304
4305 if (t == 0) {
4306 /* Save ADDA parameters, turn Path A ADDA on */
4307 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
4308 RTL8XXXU_ADDA_REGS);
4309 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4310 rtl8xxxu_save_regs(priv, iqk_bb_regs,
4311 priv->bb_backup, RTL8XXXU_BB_REGS);
4312 }
4313
4314 rtl8xxxu_path_adda_on(priv, adda_regs, true);
4315
4316 if (t == 0) {
4317 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
4318 if (val32 & FPGA0_HSSI_PARM1_PI)
4319 priv->pi_enabled = 1;
4320 }
4321
4322 if (!priv->pi_enabled) {
4323 /* Switch BB to PI mode to do IQ Calibration. */
4324 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
4325 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
4326 }
4327
4328 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4329 val32 &= ~FPGA_RF_MODE_CCK;
4330 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4331
4332 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
4333 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
4334 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
4335
4336 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
4337 val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
4338 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4339
4340 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
4341 val32 &= ~BIT(10);
4342 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
4343 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
4344 val32 &= ~BIT(10);
4345 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
4346
4347 if (priv->tx_paths > 1) {
4348 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
4349 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
4350 }
4351
4352 /* MAC settings */
4353 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
4354
4355 /* Page B init */
4356 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
4357
4358 if (priv->tx_paths > 1)
4359 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
4360
4361 /* IQ calibration setting */
4362 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
4363 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4364 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4365
4366 for (i = 0; i < retry; i++) {
4367 path_a_ok = rtl8xxxu_iqk_path_a(priv);
4368 if (path_a_ok == 0x03) {
4369 val32 = rtl8xxxu_read32(priv,
4370 REG_TX_POWER_BEFORE_IQK_A);
4371 result[t][0] = (val32 >> 16) & 0x3ff;
4372 val32 = rtl8xxxu_read32(priv,
4373 REG_TX_POWER_AFTER_IQK_A);
4374 result[t][1] = (val32 >> 16) & 0x3ff;
4375 val32 = rtl8xxxu_read32(priv,
4376 REG_RX_POWER_BEFORE_IQK_A_2);
4377 result[t][2] = (val32 >> 16) & 0x3ff;
4378 val32 = rtl8xxxu_read32(priv,
4379 REG_RX_POWER_AFTER_IQK_A_2);
4380 result[t][3] = (val32 >> 16) & 0x3ff;
4381 break;
4382 } else if (i == (retry - 1) && path_a_ok == 0x01) {
4383 /* TX IQK OK */
4384 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
4385 __func__);
4386
4387 val32 = rtl8xxxu_read32(priv,
4388 REG_TX_POWER_BEFORE_IQK_A);
4389 result[t][0] = (val32 >> 16) & 0x3ff;
4390 val32 = rtl8xxxu_read32(priv,
4391 REG_TX_POWER_AFTER_IQK_A);
4392 result[t][1] = (val32 >> 16) & 0x3ff;
4393 }
4394 }
4395
4396 if (!path_a_ok)
4397 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
4398
4399 if (priv->tx_paths > 1) {
4400 /*
4401 * Path A into standby
4402 */
4403 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
4404 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
4405 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
4406
4407 /* Turn Path B ADDA on */
4408 rtl8xxxu_path_adda_on(priv, adda_regs, false);
4409
4410 for (i = 0; i < retry; i++) {
4411 path_b_ok = rtl8xxxu_iqk_path_b(priv);
4412 if (path_b_ok == 0x03) {
4413 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4414 result[t][4] = (val32 >> 16) & 0x3ff;
4415 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4416 result[t][5] = (val32 >> 16) & 0x3ff;
4417 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4418 result[t][6] = (val32 >> 16) & 0x3ff;
4419 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4420 result[t][7] = (val32 >> 16) & 0x3ff;
4421 break;
4422 } else if (i == (retry - 1) && path_b_ok == 0x01) {
4423 /* TX IQK OK */
4424 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4425 result[t][4] = (val32 >> 16) & 0x3ff;
4426 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4427 result[t][5] = (val32 >> 16) & 0x3ff;
4428 }
4429 }
4430
4431 if (!path_b_ok)
4432 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
4433 }
4434
4435 /* Back to BB mode, load original value */
4436 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
4437
4438 if (t) {
4439 if (!priv->pi_enabled) {
4440 /*
4441 * Switch back BB to SI mode after finishing
4442 * IQ Calibration
4443 */
4444 val32 = 0x01000000;
4445 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
4446 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
4447 }
4448
4449 /* Reload ADDA power saving parameters */
4450 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
4451 RTL8XXXU_ADDA_REGS);
4452
4453 /* Reload MAC parameters */
4454 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4455
4456 /* Reload BB parameters */
4457 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
4458 priv->bb_backup, RTL8XXXU_BB_REGS);
4459
4460 /* Restore RX initial gain */
4461 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
4462
4463 if (priv->tx_paths > 1) {
4464 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
4465 0x00032ed3);
4466 }
4467
4468 /* Load 0xe30 IQC default value */
4469 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
4470 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
4471 }
4472 }
4473
4474 static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
4475 int result[][8], int t)
4476 {
4477 struct device *dev = &priv->udev->dev;
4478 u32 i, val32;
4479 int path_a_ok /*, path_b_ok */;
4480 int retry = 2;
4481 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
4482 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
4483 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
4484 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
4485 REG_TX_OFDM_BBON, REG_TX_TO_RX,
4486 REG_TX_TO_TX, REG_RX_CCK,
4487 REG_RX_OFDM, REG_RX_WAIT_RIFS,
4488 REG_RX_TO_RX, REG_STANDBY,
4489 REG_SLEEP, REG_PMPD_ANAEN
4490 };
4491 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
4492 REG_TXPAUSE, REG_BEACON_CTRL,
4493 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
4494 };
4495 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
4496 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
4497 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
4498 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
4499 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
4500 };
4501 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;
4502 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;
4503
4504 /*
4505 * Note: IQ calibration must be performed after loading
4506 * PHY_REG.txt , and radio_a, radio_b.txt
4507 */
4508
4509 if (t == 0) {
4510 /* Save ADDA parameters, turn Path A ADDA on */
4511 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
4512 RTL8XXXU_ADDA_REGS);
4513 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4514 rtl8xxxu_save_regs(priv, iqk_bb_regs,
4515 priv->bb_backup, RTL8XXXU_BB_REGS);
4516 }
4517
4518 rtl8xxxu_path_adda_on(priv, adda_regs, true);
4519
4520 /* MAC settings */
4521 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
4522
4523 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
4524 val32 |= 0x0f000000;
4525 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
4526
4527 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
4528 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
4529 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
4530
4531 #ifdef RTL8723BU_PATH_B
4532 /* Set RF mode to standby Path B */
4533 if (priv->tx_paths > 1)
4534 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x10000);
4535 #endif
4536
4537 #if 0
4538 /* Page B init */
4539 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x0f600000);
4540
4541 if (priv->tx_paths > 1)
4542 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x0f600000);
4543 #endif
4544
4545 /*
4546 * RX IQ calibration setting for 8723B D cut large current issue
4547 * when leaving IPS
4548 */
4549 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4550 val32 &= 0x000000ff;
4551 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4552
4553 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4554 val32 |= 0x80000;
4555 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4556
4557 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4558 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4559 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
4560
4561 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
4562 val32 |= 0x20;
4563 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
4564
4565 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd);
4566
4567 for (i = 0; i < retry; i++) {
4568 path_a_ok = rtl8723bu_iqk_path_a(priv);
4569 if (path_a_ok == 0x01) {
4570 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4571 val32 &= 0x000000ff;
4572 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4573
4574 #if 0 /* Only needed in restore case, we may need this when going to suspend */
4575 priv->RFCalibrateInfo.TxLOK[RF_A] =
4576 rtl8xxxu_read_rfreg(priv, RF_A,
4577 RF6052_REG_TXM_IDAC);
4578 #endif
4579
4580 val32 = rtl8xxxu_read32(priv,
4581 REG_TX_POWER_BEFORE_IQK_A);
4582 result[t][0] = (val32 >> 16) & 0x3ff;
4583 val32 = rtl8xxxu_read32(priv,
4584 REG_TX_POWER_AFTER_IQK_A);
4585 result[t][1] = (val32 >> 16) & 0x3ff;
4586
4587 break;
4588 }
4589 }
4590
4591 if (!path_a_ok)
4592 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
4593
4594 for (i = 0; i < retry; i++) {
4595 path_a_ok = rtl8723bu_rx_iqk_path_a(priv);
4596 if (path_a_ok == 0x03) {
4597 val32 = rtl8xxxu_read32(priv,
4598 REG_RX_POWER_BEFORE_IQK_A_2);
4599 result[t][2] = (val32 >> 16) & 0x3ff;
4600 val32 = rtl8xxxu_read32(priv,
4601 REG_RX_POWER_AFTER_IQK_A_2);
4602 result[t][3] = (val32 >> 16) & 0x3ff;
4603
4604 break;
4605 }
4606 }
4607
4608 if (!path_a_ok)
4609 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
4610
4611 if (priv->tx_paths > 1) {
4612 #if 1
4613 dev_warn(dev, "%s: Path B not supported\n", __func__);
4614 #else
4615
4616 /*
4617 * Path A into standby
4618 */
4619 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4620 val32 &= 0x000000ff;
4621 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4622 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);
4623
4624 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4625 val32 &= 0x000000ff;
4626 val32 |= 0x80800000;
4627 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4628
4629 /* Turn Path B ADDA on */
4630 rtl8xxxu_path_adda_on(priv, adda_regs, false);
4631
4632 for (i = 0; i < retry; i++) {
4633 path_b_ok = rtl8xxxu_iqk_path_b(priv);
4634 if (path_b_ok == 0x03) {
4635 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4636 result[t][4] = (val32 >> 16) & 0x3ff;
4637 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4638 result[t][5] = (val32 >> 16) & 0x3ff;
4639 break;
4640 }
4641 }
4642
4643 if (!path_b_ok)
4644 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
4645
4646 for (i = 0; i < retry; i++) {
4647 path_b_ok = rtl8723bu_rx_iqk_path_b(priv);
4648 if (path_a_ok == 0x03) {
4649 val32 = rtl8xxxu_read32(priv,
4650 REG_RX_POWER_BEFORE_IQK_B_2);
4651 result[t][6] = (val32 >> 16) & 0x3ff;
4652 val32 = rtl8xxxu_read32(priv,
4653 REG_RX_POWER_AFTER_IQK_B_2);
4654 result[t][7] = (val32 >> 16) & 0x3ff;
4655 break;
4656 }
4657 }
4658
4659 if (!path_b_ok)
4660 dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);
4661 #endif
4662 }
4663
4664 /* Back to BB mode, load original value */
4665 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4666 val32 &= 0x000000ff;
4667 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4668
4669 if (t) {
4670 /* Reload ADDA power saving parameters */
4671 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
4672 RTL8XXXU_ADDA_REGS);
4673
4674 /* Reload MAC parameters */
4675 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4676
4677 /* Reload BB parameters */
4678 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
4679 priv->bb_backup, RTL8XXXU_BB_REGS);
4680
4681 /* Restore RX initial gain */
4682 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
4683 val32 &= 0xffffff00;
4684 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);
4685 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);
4686
4687 if (priv->tx_paths > 1) {
4688 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
4689 val32 &= 0xffffff00;
4690 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
4691 val32 | 0x50);
4692 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
4693 val32 | xb_agc);
4694 }
4695
4696 /* Load 0xe30 IQC default value */
4697 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
4698 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
4699 }
4700 }
4701
4702 static void rtl8xxxu_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start)
4703 {
4704 struct h2c_cmd h2c;
4705
4706 if (priv->fops->mbox_ext_width < 4)
4707 return;
4708
4709 memset(&h2c, 0, sizeof(struct h2c_cmd));
4710 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION;
4711 h2c.bt_wlan_calibration.data = start;
4712
4713 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration));
4714 }
4715
4716 static void rtl8723au_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
4717 {
4718 struct device *dev = &priv->udev->dev;
4719 int result[4][8]; /* last is final result */
4720 int i, candidate;
4721 bool path_a_ok, path_b_ok;
4722 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
4723 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4724 s32 reg_tmp = 0;
4725 bool simu;
4726
4727 rtl8xxxu_prepare_calibrate(priv, 1);
4728
4729 memset(result, 0, sizeof(result));
4730 candidate = -1;
4731
4732 path_a_ok = false;
4733 path_b_ok = false;
4734
4735 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4736
4737 for (i = 0; i < 3; i++) {
4738 rtl8xxxu_phy_iqcalibrate(priv, result, i);
4739
4740 if (i == 1) {
4741 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
4742 if (simu) {
4743 candidate = 0;
4744 break;
4745 }
4746 }
4747
4748 if (i == 2) {
4749 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
4750 if (simu) {
4751 candidate = 0;
4752 break;
4753 }
4754
4755 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
4756 if (simu) {
4757 candidate = 1;
4758 } else {
4759 for (i = 0; i < 8; i++)
4760 reg_tmp += result[3][i];
4761
4762 if (reg_tmp)
4763 candidate = 3;
4764 else
4765 candidate = -1;
4766 }
4767 }
4768 }
4769
4770 for (i = 0; i < 4; i++) {
4771 reg_e94 = result[i][0];
4772 reg_e9c = result[i][1];
4773 reg_ea4 = result[i][2];
4774 reg_eac = result[i][3];
4775 reg_eb4 = result[i][4];
4776 reg_ebc = result[i][5];
4777 reg_ec4 = result[i][6];
4778 reg_ecc = result[i][7];
4779 }
4780
4781 if (candidate >= 0) {
4782 reg_e94 = result[candidate][0];
4783 priv->rege94 = reg_e94;
4784 reg_e9c = result[candidate][1];
4785 priv->rege9c = reg_e9c;
4786 reg_ea4 = result[candidate][2];
4787 reg_eac = result[candidate][3];
4788 reg_eb4 = result[candidate][4];
4789 priv->regeb4 = reg_eb4;
4790 reg_ebc = result[candidate][5];
4791 priv->regebc = reg_ebc;
4792 reg_ec4 = result[candidate][6];
4793 reg_ecc = result[candidate][7];
4794 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
4795 dev_dbg(dev,
4796 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
4797 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
4798 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
4799 path_a_ok = true;
4800 path_b_ok = true;
4801 } else {
4802 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
4803 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
4804 }
4805
4806 if (reg_e94 && candidate >= 0)
4807 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
4808 candidate, (reg_ea4 == 0));
4809
4810 if (priv->tx_paths > 1 && reg_eb4)
4811 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
4812 candidate, (reg_ec4 == 0));
4813
4814 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
4815 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
4816
4817 rtl8xxxu_prepare_calibrate(priv, 0);
4818 }
4819
4820 static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
4821 {
4822 struct device *dev = &priv->udev->dev;
4823 int result[4][8]; /* last is final result */
4824 int i, candidate;
4825 bool path_a_ok, path_b_ok;
4826 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
4827 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4828 u32 val32, bt_control;
4829 s32 reg_tmp = 0;
4830 bool simu;
4831
4832 rtl8xxxu_prepare_calibrate(priv, 1);
4833
4834 memset(result, 0, sizeof(result));
4835 candidate = -1;
4836
4837 path_a_ok = false;
4838 path_b_ok = false;
4839
4840 bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU);
4841
4842 for (i = 0; i < 3; i++) {
4843 rtl8723bu_phy_iqcalibrate(priv, result, i);
4844
4845 if (i == 1) {
4846 simu = rtl8723bu_simularity_compare(priv, result, 0, 1);
4847 if (simu) {
4848 candidate = 0;
4849 break;
4850 }
4851 }
4852
4853 if (i == 2) {
4854 simu = rtl8723bu_simularity_compare(priv, result, 0, 2);
4855 if (simu) {
4856 candidate = 0;
4857 break;
4858 }
4859
4860 simu = rtl8723bu_simularity_compare(priv, result, 1, 2);
4861 if (simu) {
4862 candidate = 1;
4863 } else {
4864 for (i = 0; i < 8; i++)
4865 reg_tmp += result[3][i];
4866
4867 if (reg_tmp)
4868 candidate = 3;
4869 else
4870 candidate = -1;
4871 }
4872 }
4873 }
4874
4875 for (i = 0; i < 4; i++) {
4876 reg_e94 = result[i][0];
4877 reg_e9c = result[i][1];
4878 reg_ea4 = result[i][2];
4879 reg_eac = result[i][3];
4880 reg_eb4 = result[i][4];
4881 reg_ebc = result[i][5];
4882 reg_ec4 = result[i][6];
4883 reg_ecc = result[i][7];
4884 }
4885
4886 if (candidate >= 0) {
4887 reg_e94 = result[candidate][0];
4888 priv->rege94 = reg_e94;
4889 reg_e9c = result[candidate][1];
4890 priv->rege9c = reg_e9c;
4891 reg_ea4 = result[candidate][2];
4892 reg_eac = result[candidate][3];
4893 reg_eb4 = result[candidate][4];
4894 priv->regeb4 = reg_eb4;
4895 reg_ebc = result[candidate][5];
4896 priv->regebc = reg_ebc;
4897 reg_ec4 = result[candidate][6];
4898 reg_ecc = result[candidate][7];
4899 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
4900 dev_dbg(dev,
4901 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
4902 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
4903 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
4904 path_a_ok = true;
4905 path_b_ok = true;
4906 } else {
4907 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
4908 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
4909 }
4910
4911 if (reg_e94 && candidate >= 0)
4912 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
4913 candidate, (reg_ea4 == 0));
4914
4915 if (priv->tx_paths > 1 && reg_eb4)
4916 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
4917 candidate, (reg_ec4 == 0));
4918
4919 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
4920 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
4921
4922 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control);
4923
4924 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4925 val32 |= 0x80000;
4926 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4927 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000);
4928 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4929 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177);
4930 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
4931 val32 |= 0x20;
4932 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
4933 rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd);
4934
4935 if (priv->rf_paths > 1) {
4936 dev_dbg(dev, "%s: beware 2T not yet supported\n", __func__);
4937 #ifdef RTL8723BU_PATH_B
4938 if (RF_Path == 0x0) //S1
4939 ODM_SetIQCbyRFpath(pDM_Odm, 0);
4940 else //S0
4941 ODM_SetIQCbyRFpath(pDM_Odm, 1);
4942 #endif
4943 }
4944 rtl8xxxu_prepare_calibrate(priv, 0);
4945 }
4946
4947 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
4948 {
4949 u32 val32;
4950 u32 rf_amode, rf_bmode = 0, lstf;
4951
4952 /* Check continuous TX and Packet TX */
4953 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
4954
4955 if (lstf & OFDM_LSTF_MASK) {
4956 /* Disable all continuous TX */
4957 val32 = lstf & ~OFDM_LSTF_MASK;
4958 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
4959
4960 /* Read original RF mode Path A */
4961 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
4962
4963 /* Set RF mode to standby Path A */
4964 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
4965 (rf_amode & 0x8ffff) | 0x10000);
4966
4967 /* Path-B */
4968 if (priv->tx_paths > 1) {
4969 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
4970 RF6052_REG_AC);
4971
4972 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
4973 (rf_bmode & 0x8ffff) | 0x10000);
4974 }
4975 } else {
4976 /* Deal with Packet TX case */
4977 /* block all queues */
4978 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
4979 }
4980
4981 /* Start LC calibration */
4982 if (priv->fops->has_s0s1)
4983 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0);
4984 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
4985 val32 |= 0x08000;
4986 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
4987
4988 msleep(100);
4989
4990 if (priv->fops->has_s0s1)
4991 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0);
4992
4993 /* Restore original parameters */
4994 if (lstf & OFDM_LSTF_MASK) {
4995 /* Path-A */
4996 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
4997 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
4998
4999 /* Path-B */
5000 if (priv->tx_paths > 1)
5001 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
5002 rf_bmode);
5003 } else /* Deal with Packet TX case */
5004 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
5005 }
5006
5007 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
5008 {
5009 int i;
5010 u16 reg;
5011
5012 reg = REG_MACID;
5013
5014 for (i = 0; i < ETH_ALEN; i++)
5015 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
5016
5017 return 0;
5018 }
5019
5020 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
5021 {
5022 int i;
5023 u16 reg;
5024
5025 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
5026
5027 reg = REG_BSSID;
5028
5029 for (i = 0; i < ETH_ALEN; i++)
5030 rtl8xxxu_write8(priv, reg + i, bssid[i]);
5031
5032 return 0;
5033 }
5034
5035 static void
5036 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
5037 {
5038 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
5039 u8 max_agg = 0xf;
5040 int i;
5041
5042 ampdu_factor = 1 << (ampdu_factor + 2);
5043 if (ampdu_factor > max_agg)
5044 ampdu_factor = max_agg;
5045
5046 for (i = 0; i < 4; i++) {
5047 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
5048 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
5049
5050 if ((vals[i] & 0x0f) > ampdu_factor)
5051 vals[i] = (vals[i] & 0xf0) | ampdu_factor;
5052
5053 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
5054 }
5055 }
5056
5057 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
5058 {
5059 u8 val8;
5060
5061 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
5062 val8 &= 0xf8;
5063 val8 |= density;
5064 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
5065 }
5066
5067 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
5068 {
5069 u8 val8;
5070 int count, ret;
5071
5072 /* Start of rtl8723AU_card_enable_flow */
5073 /* Act to Cardemu sequence*/
5074 /* Turn off RF */
5075 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
5076
5077 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
5078 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
5079 val8 &= ~LEDCFG2_DPDT_SELECT;
5080 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
5081
5082 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
5083 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5084 val8 |= BIT(1);
5085 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5086
5087 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5088 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5089 if ((val8 & BIT(1)) == 0)
5090 break;
5091 udelay(10);
5092 }
5093
5094 if (!count) {
5095 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
5096 __func__);
5097 ret = -EBUSY;
5098 goto exit;
5099 }
5100
5101 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
5102 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5103 val8 |= SYS_ISO_ANALOG_IPS;
5104 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5105
5106 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
5107 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5108 val8 &= ~LDOA15_ENABLE;
5109 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5110
5111 exit:
5112 return ret;
5113 }
5114
5115 static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
5116 {
5117 u8 val8;
5118 u8 val32;
5119 int count, ret;
5120
5121 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5122
5123 /*
5124 * Poll - wait for RX packet to complete
5125 */
5126 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5127 val32 = rtl8xxxu_read32(priv, 0x5f8);
5128 if (!val32)
5129 break;
5130 udelay(10);
5131 }
5132
5133 if (!count) {
5134 dev_warn(&priv->udev->dev,
5135 "%s: RX poll timed out (0x05f8)\n", __func__);
5136 ret = -EBUSY;
5137 goto exit;
5138 }
5139
5140 /* Disable CCK and OFDM, clock gated */
5141 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
5142 val8 &= ~SYS_FUNC_BBRSTB;
5143 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
5144
5145 udelay(2);
5146
5147 /* Reset baseband */
5148 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
5149 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
5150 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
5151
5152 /* Reset MAC TRX */
5153 val8 = rtl8xxxu_read8(priv, REG_CR);
5154 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
5155 rtl8xxxu_write8(priv, REG_CR, val8);
5156
5157 /* Reset MAC TRX */
5158 val8 = rtl8xxxu_read8(priv, REG_CR + 1);
5159 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
5160 rtl8xxxu_write8(priv, REG_CR + 1, val8);
5161
5162 /* Respond TX OK to scheduler */
5163 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
5164 val8 |= DUAL_TSF_TX_OK;
5165 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
5166
5167 exit:
5168 return ret;
5169 }
5170
5171 static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv *priv)
5172 {
5173 u8 val8;
5174
5175 /* Clear suspend enable and power down enable*/
5176 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5177 val8 &= ~(BIT(3) | BIT(7));
5178 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5179
5180 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
5181 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
5182 val8 &= ~BIT(0);
5183 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
5184
5185 /* 0x04[12:11] = 11 enable WL suspend*/
5186 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5187 val8 &= ~(BIT(3) | BIT(4));
5188 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5189 }
5190
5191 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv)
5192 {
5193 u8 val8;
5194
5195 /* Clear suspend enable and power down enable*/
5196 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5197 val8 &= ~(BIT(3) | BIT(4));
5198 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5199 }
5200
5201 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv)
5202 {
5203 u8 val8;
5204 u32 val32;
5205 int count, ret = 0;
5206
5207 /* disable HWPDN 0x04[15]=0*/
5208 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5209 val8 &= ~BIT(7);
5210 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5211
5212 /* disable SW LPS 0x04[10]= 0 */
5213 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5214 val8 &= ~BIT(2);
5215 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5216
5217 /* disable WL suspend*/
5218 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5219 val8 &= ~(BIT(3) | BIT(4));
5220 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5221
5222 /* wait till 0x04[17] = 1 power ready*/
5223 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5224 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5225 if (val32 & BIT(17))
5226 break;
5227
5228 udelay(10);
5229 }
5230
5231 if (!count) {
5232 ret = -EBUSY;
5233 goto exit;
5234 }
5235
5236 /* We should be able to optimize the following three entries into one */
5237
5238 /* release WLON reset 0x04[16]= 1*/
5239 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5240 val8 |= BIT(0);
5241 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5242
5243 /* set, then poll until 0 */
5244 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5245 val32 |= APS_FSMCO_MAC_ENABLE;
5246 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5247
5248 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5249 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5250 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5251 ret = 0;
5252 break;
5253 }
5254 udelay(10);
5255 }
5256
5257 if (!count) {
5258 ret = -EBUSY;
5259 goto exit;
5260 }
5261
5262 exit:
5263 return ret;
5264 }
5265
5266 static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv)
5267 {
5268 u8 val8;
5269 u32 val32;
5270 int count, ret = 0;
5271
5272 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
5273 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5274 val8 |= LDOA15_ENABLE;
5275 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5276
5277 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5278 val8 = rtl8xxxu_read8(priv, 0x0067);
5279 val8 &= ~BIT(4);
5280 rtl8xxxu_write8(priv, 0x0067, val8);
5281
5282 mdelay(1);
5283
5284 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5285 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5286 val8 &= ~SYS_ISO_ANALOG_IPS;
5287 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5288
5289 /* disable SW LPS 0x04[10]= 0 */
5290 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5291 val8 &= ~BIT(2);
5292 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5293
5294 /* wait till 0x04[17] = 1 power ready*/
5295 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5296 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5297 if (val32 & BIT(17))
5298 break;
5299
5300 udelay(10);
5301 }
5302
5303 if (!count) {
5304 ret = -EBUSY;
5305 goto exit;
5306 }
5307
5308 /* We should be able to optimize the following three entries into one */
5309
5310 /* release WLON reset 0x04[16]= 1*/
5311 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5312 val8 |= BIT(0);
5313 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5314
5315 /* disable HWPDN 0x04[15]= 0*/
5316 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5317 val8 &= ~BIT(7);
5318 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5319
5320 /* disable WL suspend*/
5321 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5322 val8 &= ~(BIT(3) | BIT(4));
5323 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5324
5325 /* set, then poll until 0 */
5326 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5327 val32 |= APS_FSMCO_MAC_ENABLE;
5328 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5329
5330 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5331 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5332 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5333 ret = 0;
5334 break;
5335 }
5336 udelay(10);
5337 }
5338
5339 if (!count) {
5340 ret = -EBUSY;
5341 goto exit;
5342 }
5343
5344 /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
5345 /*
5346 * Note: Vendor driver actually clears this bit, despite the
5347 * documentation claims it's being set!
5348 */
5349 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
5350 val8 |= LEDCFG2_DPDT_SELECT;
5351 val8 &= ~LEDCFG2_DPDT_SELECT;
5352 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
5353
5354 exit:
5355 return ret;
5356 }
5357
5358 static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv)
5359 {
5360 u8 val8;
5361 u32 val32;
5362 int count, ret = 0;
5363
5364 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */
5365 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5366 val8 |= LDOA15_ENABLE;
5367 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5368
5369 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5370 val8 = rtl8xxxu_read8(priv, 0x0067);
5371 val8 &= ~BIT(4);
5372 rtl8xxxu_write8(priv, 0x0067, val8);
5373
5374 mdelay(1);
5375
5376 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5377 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5378 val8 &= ~SYS_ISO_ANALOG_IPS;
5379 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5380
5381 /* Disable SW LPS 0x04[10]= 0 */
5382 val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
5383 val32 &= ~APS_FSMCO_SW_LPS;
5384 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5385
5386 /* Wait until 0x04[17] = 1 power ready */
5387 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5388 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5389 if (val32 & BIT(17))
5390 break;
5391
5392 udelay(10);
5393 }
5394
5395 if (!count) {
5396 ret = -EBUSY;
5397 goto exit;
5398 }
5399
5400 /* We should be able to optimize the following three entries into one */
5401
5402 /* Release WLON reset 0x04[16]= 1*/
5403 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5404 val32 |= APS_FSMCO_WLON_RESET;
5405 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5406
5407 /* Disable HWPDN 0x04[15]= 0*/
5408 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5409 val32 &= ~APS_FSMCO_HW_POWERDOWN;
5410 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5411
5412 /* Disable WL suspend*/
5413 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5414 val32 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE);
5415 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5416
5417 /* Set, then poll until 0 */
5418 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5419 val32 |= APS_FSMCO_MAC_ENABLE;
5420 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5421
5422 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5423 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5424 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5425 ret = 0;
5426 break;
5427 }
5428 udelay(10);
5429 }
5430
5431 if (!count) {
5432 ret = -EBUSY;
5433 goto exit;
5434 }
5435
5436 /* Enable WL control XTAL setting */
5437 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
5438 val8 |= AFE_MISC_WL_XTAL_CTRL;
5439 rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
5440
5441 /* Enable falling edge triggering interrupt */
5442 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1);
5443 val8 |= BIT(1);
5444 rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8);
5445
5446 /* Enable GPIO9 interrupt mode */
5447 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1);
5448 val8 |= BIT(1);
5449 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8);
5450
5451 /* Enable GPIO9 input mode */
5452 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2);
5453 val8 &= ~BIT(1);
5454 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8);
5455
5456 /* Enable HSISR GPIO[C:0] interrupt */
5457 val8 = rtl8xxxu_read8(priv, REG_HSIMR);
5458 val8 |= BIT(0);
5459 rtl8xxxu_write8(priv, REG_HSIMR, val8);
5460
5461 /* Enable HSISR GPIO9 interrupt */
5462 val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2);
5463 val8 |= BIT(1);
5464 rtl8xxxu_write8(priv, REG_HSIMR + 2, val8);
5465
5466 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL);
5467 val8 |= MULTI_WIFI_HW_ROF_EN;
5468 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8);
5469
5470 /* For GPIO9 internal pull high setting BIT(14) */
5471 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1);
5472 val8 |= BIT(6);
5473 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8);
5474
5475 exit:
5476 return ret;
5477 }
5478
5479 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
5480 {
5481 u8 val8;
5482
5483 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
5484 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
5485
5486 /* 0x04[12:11] = 01 enable WL suspend */
5487 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5488 val8 &= ~BIT(4);
5489 val8 |= BIT(3);
5490 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5491
5492 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5493 val8 |= BIT(7);
5494 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5495
5496 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
5497 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
5498 val8 |= BIT(0);
5499 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
5500
5501 return 0;
5502 }
5503
5504 static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
5505 {
5506 u8 val8;
5507 u16 val16;
5508 u32 val32;
5509 int ret;
5510
5511 /*
5512 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5513 */
5514 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
5515
5516 rtl8723a_disabled_to_emu(priv);
5517
5518 ret = rtl8723a_emu_to_active(priv);
5519 if (ret)
5520 goto exit;
5521
5522 /*
5523 * 0x0004[19] = 1, reset 8051
5524 */
5525 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5526 val8 |= BIT(3);
5527 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5528
5529 /*
5530 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5531 * Set CR bit10 to enable 32k calibration.
5532 */
5533 val16 = rtl8xxxu_read16(priv, REG_CR);
5534 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5535 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5536 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5537 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5538 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5539 rtl8xxxu_write16(priv, REG_CR, val16);
5540
5541 /* For EFuse PG */
5542 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
5543 val32 &= ~(BIT(28) | BIT(29) | BIT(30));
5544 val32 |= (0x06 << 28);
5545 rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
5546 exit:
5547 return ret;
5548 }
5549
5550 static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv)
5551 {
5552 u8 val8;
5553 u16 val16;
5554 u32 val32;
5555 int ret;
5556
5557 rtl8723a_disabled_to_emu(priv);
5558
5559 ret = rtl8723b_emu_to_active(priv);
5560 if (ret)
5561 goto exit;
5562
5563 /*
5564 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5565 * Set CR bit10 to enable 32k calibration.
5566 */
5567 val16 = rtl8xxxu_read16(priv, REG_CR);
5568 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5569 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5570 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5571 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5572 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5573 rtl8xxxu_write16(priv, REG_CR, val16);
5574
5575 /*
5576 * BT coexist power on settings. This is identical for 1 and 2
5577 * antenna parts.
5578 */
5579 rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20);
5580
5581 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
5582 val16 |= SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN;
5583 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
5584
5585 rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18);
5586 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
5587 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
5588 /* Antenna inverse */
5589 rtl8xxxu_write8(priv, 0xfe08, 0x01);
5590
5591 val16 = rtl8xxxu_read16(priv, REG_PWR_DATA);
5592 val16 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
5593 rtl8xxxu_write16(priv, REG_PWR_DATA, val16);
5594
5595 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
5596 val32 |= LEDCFG0_DPDT_SELECT;
5597 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
5598
5599 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
5600 val8 &= ~PAD_CTRL1_SW_DPDT_SEL_DATA;
5601 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
5602 exit:
5603 return ret;
5604 }
5605
5606 #ifdef CONFIG_RTL8XXXU_UNTESTED
5607
5608 static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
5609 {
5610 u8 val8;
5611 u16 val16;
5612 u32 val32;
5613 int i;
5614
5615 for (i = 100; i; i--) {
5616 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
5617 if (val8 & APS_FSMCO_PFM_ALDN)
5618 break;
5619 }
5620
5621 if (!i) {
5622 pr_info("%s: Poll failed\n", __func__);
5623 return -ENODEV;
5624 }
5625
5626 /*
5627 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5628 */
5629 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
5630 rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
5631 udelay(100);
5632
5633 val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
5634 if (!(val8 & LDOV12D_ENABLE)) {
5635 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
5636 val8 |= LDOV12D_ENABLE;
5637 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
5638
5639 udelay(100);
5640
5641 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5642 val8 &= ~SYS_ISO_MD2PP;
5643 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5644 }
5645
5646 /*
5647 * Auto enable WLAN
5648 */
5649 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
5650 val16 |= APS_FSMCO_MAC_ENABLE;
5651 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
5652
5653 for (i = 1000; i; i--) {
5654 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
5655 if (!(val16 & APS_FSMCO_MAC_ENABLE))
5656 break;
5657 }
5658 if (!i) {
5659 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
5660 return -EBUSY;
5661 }
5662
5663 /*
5664 * Enable radio, GPIO, LED
5665 */
5666 val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
5667 APS_FSMCO_PFM_ALDN;
5668 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
5669
5670 /*
5671 * Release RF digital isolation
5672 */
5673 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
5674 val16 &= ~SYS_ISO_DIOR;
5675 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
5676
5677 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
5678 val8 &= ~APSD_CTRL_OFF;
5679 rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
5680 for (i = 200; i; i--) {
5681 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
5682 if (!(val8 & APSD_CTRL_OFF_STATUS))
5683 break;
5684 }
5685
5686 if (!i) {
5687 pr_info("%s: APSD_CTRL poll failed\n", __func__);
5688 return -EBUSY;
5689 }
5690
5691 /*
5692 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5693 */
5694 val16 = rtl8xxxu_read16(priv, REG_CR);
5695 val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5696 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
5697 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
5698 rtl8xxxu_write16(priv, REG_CR, val16);
5699
5700 /*
5701 * Workaround for 8188RU LNA power leakage problem.
5702 */
5703 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
5704 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
5705 val32 &= ~BIT(1);
5706 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
5707 }
5708 return 0;
5709 }
5710
5711 #endif
5712
5713 static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)
5714 {
5715 u16 val16;
5716 u32 val32;
5717 int ret;
5718
5719 ret = 0;
5720
5721 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
5722 if (val32 & SYS_CFG_SPS_LDO_SEL) {
5723 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3);
5724 } else {
5725 /*
5726 * Raise 1.2V voltage
5727 */
5728 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL);
5729 val32 &= 0xff0fffff;
5730 val32 |= 0x00500000;
5731 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32);
5732 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);
5733 }
5734
5735 rtl8192e_disabled_to_emu(priv);
5736
5737 ret = rtl8192e_emu_to_active(priv);
5738 if (ret)
5739 goto exit;
5740
5741 rtl8xxxu_write16(priv, REG_CR, 0x0000);
5742
5743 /*
5744 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5745 * Set CR bit10 to enable 32k calibration.
5746 */
5747 val16 = rtl8xxxu_read16(priv, REG_CR);
5748 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5749 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5750 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5751 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5752 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5753 rtl8xxxu_write16(priv, REG_CR, val16);
5754
5755 exit:
5756 return ret;
5757 }
5758
5759 static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
5760 {
5761 u8 val8;
5762 u16 val16;
5763 u32 val32;
5764
5765 /*
5766 * Workaround for 8188RU LNA power leakage problem.
5767 */
5768 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
5769 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
5770 val32 |= BIT(1);
5771 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
5772 }
5773
5774 rtl8xxxu_active_to_lps(priv);
5775
5776 /* Turn off RF */
5777 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
5778
5779 /* Reset Firmware if running in RAM */
5780 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
5781 rtl8xxxu_firmware_self_reset(priv);
5782
5783 /* Reset MCU */
5784 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
5785 val16 &= ~SYS_FUNC_CPU_ENABLE;
5786 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
5787
5788 /* Reset MCU ready status */
5789 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
5790
5791 rtl8xxxu_active_to_emu(priv);
5792 rtl8xxxu_emu_to_disabled(priv);
5793
5794 /* Reset MCU IO Wrapper */
5795 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
5796 val8 &= ~BIT(0);
5797 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
5798
5799 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
5800 val8 |= BIT(0);
5801 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
5802
5803 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
5804 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
5805 }
5806
5807 static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
5808 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5)
5809 {
5810 struct h2c_cmd h2c;
5811
5812 memset(&h2c, 0, sizeof(struct h2c_cmd));
5813 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA;
5814 h2c.b_type_dma.data1 = arg1;
5815 h2c.b_type_dma.data2 = arg2;
5816 h2c.b_type_dma.data3 = arg3;
5817 h2c.b_type_dma.data4 = arg4;
5818 h2c.b_type_dma.data5 = arg5;
5819 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma));
5820 }
5821
5822 static void rtl8723bu_init_bt(struct rtl8xxxu_priv *priv)
5823 {
5824 struct h2c_cmd h2c;
5825 u32 val32;
5826 u8 val8;
5827
5828 /*
5829 * No indication anywhere as to what 0x0790 does. The 2 antenna
5830 * vendor code preserves bits 6-7 here.
5831 */
5832 rtl8xxxu_write8(priv, 0x0790, 0x05);
5833 /*
5834 * 0x0778 seems to be related to enabling the number of antennas
5835 * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it
5836 * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01
5837 */
5838 rtl8xxxu_write8(priv, 0x0778, 0x01);
5839
5840 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
5841 val8 |= BIT(5);
5842 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
5843
5844 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780);
5845
5846 rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */
5847
5848 /*
5849 * Set BT grant to low
5850 */
5851 memset(&h2c, 0, sizeof(struct h2c_cmd));
5852 h2c.bt_grant.cmd = H2C_8723B_BT_GRANT;
5853 h2c.bt_grant.data = 0;
5854 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant));
5855
5856 /*
5857 * WLAN action by PTA
5858 */
5859 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x0c);
5860
5861 /*
5862 * BT select S0/S1 controlled by WiFi
5863 */
5864 val8 = rtl8xxxu_read8(priv, 0x0067);
5865 val8 |= BIT(5);
5866 rtl8xxxu_write8(priv, 0x0067, val8);
5867
5868 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
5869 val32 |= BIT(11);
5870 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
5871
5872 /*
5873 * Bits 6/7 are marked in/out ... but for what?
5874 */
5875 rtl8xxxu_write8(priv, 0x0974, 0xff);
5876
5877 val32 = rtl8xxxu_read32(priv, 0x0944);
5878 val32 |= (BIT(0) | BIT(1));
5879 rtl8xxxu_write32(priv, 0x0944, val32);
5880
5881 rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77);
5882
5883 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
5884 val32 &= ~BIT(24);
5885 val32 |= BIT(23);
5886 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
5887
5888 /*
5889 * Fix external switch Main->S1, Aux->S0
5890 */
5891 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
5892 val8 &= ~BIT(0);
5893 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
5894
5895 memset(&h2c, 0, sizeof(struct h2c_cmd));
5896 h2c.ant_sel_rsv.cmd = H2C_8723B_ANT_SEL_RSV;
5897 h2c.ant_sel_rsv.ant_inverse = 1;
5898 h2c.ant_sel_rsv.int_switch_type = 0;
5899 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv));
5900
5901 /*
5902 * 0x280, 0x00, 0x200, 0x80 - not clear
5903 */
5904 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
5905
5906 /*
5907 * Software control, antenna at WiFi side
5908 */
5909 rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00);
5910
5911 memset(&h2c, 0, sizeof(struct h2c_cmd));
5912 h2c.bt_info.cmd = H2C_8723B_BT_INFO;
5913 h2c.bt_info.data = BIT(0);
5914 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info));
5915
5916 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
5917 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a);
5918 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5919 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE4, 0x00000003);
5920
5921 memset(&h2c, 0, sizeof(struct h2c_cmd));
5922 h2c.ignore_wlan.cmd = H2C_8723B_BT_IGNORE_WLANACT;
5923 h2c.ignore_wlan.data = 0;
5924 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan));
5925 }
5926
5927 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
5928 {
5929 struct rtl8xxxu_priv *priv = hw->priv;
5930 struct device *dev = &priv->udev->dev;
5931 struct rtl8xxxu_rfregval *rftable;
5932 bool macpower;
5933 int ret;
5934 u8 val8;
5935 u16 val16;
5936 u32 val32;
5937
5938 /* Check if MAC is already powered on */
5939 val8 = rtl8xxxu_read8(priv, REG_CR);
5940
5941 /*
5942 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
5943 * initialized. First MAC returns 0xea, second MAC returns 0x00
5944 */
5945 if (val8 == 0xea)
5946 macpower = false;
5947 else
5948 macpower = true;
5949
5950 ret = priv->fops->power_on(priv);
5951 if (ret < 0) {
5952 dev_warn(dev, "%s: Failed power on\n", __func__);
5953 goto exit;
5954 }
5955
5956 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
5957 if (!macpower) {
5958 if (priv->ep_tx_normal_queue)
5959 val8 = TX_PAGE_NUM_NORM_PQ;
5960 else
5961 val8 = 0;
5962
5963 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
5964
5965 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;
5966
5967 if (priv->ep_tx_high_queue)
5968 val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
5969 if (priv->ep_tx_low_queue)
5970 val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
5971
5972 rtl8xxxu_write32(priv, REG_RQPN, val32);
5973
5974 /*
5975 * Set TX buffer boundary
5976 */
5977 val8 = TX_TOTAL_PAGE_NUM + 1;
5978 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
5979 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
5980 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
5981 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
5982 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
5983 }
5984
5985 ret = rtl8xxxu_download_firmware(priv);
5986 dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
5987 if (ret)
5988 goto exit;
5989 ret = rtl8xxxu_start_firmware(priv);
5990 dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
5991 if (ret)
5992 goto exit;
5993
5994 ret = rtl8xxxu_init_queue_priority(priv);
5995 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
5996 if (ret)
5997 goto exit;
5998
5999 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
6000 if (!macpower) {
6001 ret = priv->fops->llt_init(priv, TX_TOTAL_PAGE_NUM);
6002 if (ret) {
6003 dev_warn(dev, "%s: LLT table init failed\n", __func__);
6004 goto exit;
6005 }
6006 }
6007
6008 /* Fix USB interface interference issue */
6009 if (priv->rtlchip == 0x8723a) {
6010 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
6011 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
6012 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6013 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
6014 } else {
6015 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
6016 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
6017 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
6018 }
6019
6020 /* Solve too many protocol error on USB bus */
6021 /* Can't do this for 8188/8192 UMC A cut parts */
6022 if (priv->rtlchip == 0x8723a ||
6023 ((priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c ||
6024 priv->rtlchip == 0x8188c) &&
6025 (priv->chip_cut || !priv->vendor_umc))) {
6026 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
6027 rtl8xxxu_write8(priv, 0xfe41, 0x94);
6028 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6029
6030 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
6031 rtl8xxxu_write8(priv, 0xfe41, 0x19);
6032 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6033
6034 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
6035 rtl8xxxu_write8(priv, 0xfe41, 0x91);
6036 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6037
6038 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
6039 rtl8xxxu_write8(priv, 0xfe41, 0x81);
6040 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6041 }
6042
6043 if (priv->rtlchip == 0x8192e || priv->rtlchip == 0x8723b) {
6044 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
6045 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
6046 }
6047
6048 if (priv->fops->phy_init_antenna_selection)
6049 priv->fops->phy_init_antenna_selection(priv);
6050
6051 if (priv->rtlchip == 0x8723b)
6052 ret = rtl8xxxu_init_mac(priv, rtl8723b_mac_init_table);
6053 else
6054 ret = rtl8xxxu_init_mac(priv, rtl8723a_mac_init_table);
6055
6056 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
6057 if (ret)
6058 goto exit;
6059
6060 ret = rtl8xxxu_init_phy_bb(priv);
6061 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
6062 if (ret)
6063 goto exit;
6064
6065 switch(priv->rtlchip) {
6066 case 0x8723a:
6067 rftable = rtl8723au_radioa_1t_init_table;
6068 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6069 break;
6070 case 0x8723b:
6071 rftable = rtl8723bu_radioa_1t_init_table;
6072 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6073 break;
6074 case 0x8188c:
6075 if (priv->hi_pa)
6076 rftable = rtl8188ru_radioa_1t_highpa_table;
6077 else
6078 rftable = rtl8192cu_radioa_1t_init_table;
6079 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6080 break;
6081 case 0x8191c:
6082 rftable = rtl8192cu_radioa_1t_init_table;
6083 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6084 break;
6085 case 0x8192c:
6086 rftable = rtl8192cu_radioa_2t_init_table;
6087 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6088 if (ret)
6089 break;
6090 rftable = rtl8192cu_radiob_2t_init_table;
6091 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
6092 break;
6093 default:
6094 ret = -EINVAL;
6095 }
6096
6097 if (ret)
6098 goto exit;
6099
6100 /* Reduce 80M spur */
6101 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
6102 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
6103 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
6104 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
6105
6106 /* RFSW Control - clear bit 14 ?? */
6107 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
6108 /* 0x07000760 */
6109 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
6110 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
6111 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
6112 FPGA0_RF_BD_CTRL_SHIFT);
6113 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
6114 /* 0x860[6:5]= 00 - why? - this sets antenna B */
6115 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
6116
6117 priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
6118 RF6052_REG_MODE_AG);
6119
6120 /*
6121 * Set RX page boundary
6122 */
6123 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff);
6124 /*
6125 * Transfer page size is always 128
6126 */
6127 val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) |
6128 (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT);
6129 rtl8xxxu_write8(priv, REG_PBP, val8);
6130
6131 /*
6132 * Unit in 8 bytes, not obvious what it is used for
6133 */
6134 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
6135
6136 /*
6137 * Enable all interrupts - not obvious USB needs to do this
6138 */
6139 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
6140 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
6141
6142 rtl8xxxu_set_mac(priv);
6143 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
6144
6145 /*
6146 * Configure initial WMAC settings
6147 */
6148 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
6149 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
6150 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
6151 rtl8xxxu_write32(priv, REG_RCR, val32);
6152
6153 /*
6154 * Accept all multicast
6155 */
6156 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
6157 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
6158
6159 /*
6160 * Init adaptive controls
6161 */
6162 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6163 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
6164 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
6165 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6166
6167 /* CCK = 0x0a, OFDM = 0x10 */
6168 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
6169 rtl8xxxu_set_retry(priv, 0x30, 0x30);
6170 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
6171
6172 /*
6173 * Init EDCA
6174 */
6175 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
6176
6177 /* Set CCK SIFS */
6178 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
6179
6180 /* Set OFDM SIFS */
6181 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
6182
6183 /* TXOP */
6184 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
6185 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
6186 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
6187 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
6188
6189 /* Set data auto rate fallback retry count */
6190 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
6191 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
6192 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
6193 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
6194
6195 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
6196 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
6197 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
6198
6199 /* Set ACK timeout */
6200 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
6201
6202 /*
6203 * Initialize beacon parameters
6204 */
6205 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
6206 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
6207 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
6208 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
6209 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
6210 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
6211
6212 /*
6213 * Enable CCK and OFDM block
6214 */
6215 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
6216 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
6217 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
6218
6219 /*
6220 * Invalidate all CAM entries - bit 30 is undocumented
6221 */
6222 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
6223
6224 /*
6225 * Start out with default power levels for channel 6, 20MHz
6226 */
6227 rtl8723a_set_tx_power(priv, 1, false);
6228
6229 /* Let the 8051 take control of antenna setting */
6230 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
6231 val8 |= LEDCFG2_DPDT_SELECT;
6232 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
6233
6234 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
6235
6236 /* Disable BAR - not sure if this has any effect on USB */
6237 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
6238
6239 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
6240
6241 rtl8723a_phy_lc_calibrate(priv);
6242
6243 priv->fops->phy_iq_calibrate(priv);
6244
6245 /*
6246 * This should enable thermal meter
6247 */
6248 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
6249
6250 /* Init BT hw config. */
6251 if (priv->fops->init_bt)
6252 priv->fops->init_bt(priv);
6253
6254 /* Set NAV_UPPER to 30000us */
6255 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
6256 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
6257
6258 if (priv->rtlchip == 0x8723a) {
6259 /*
6260 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
6261 * but we need to find root cause.
6262 * This is 8723au only.
6263 */
6264 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
6265 if ((val32 & 0xff000000) != 0x83000000) {
6266 val32 |= FPGA_RF_MODE_CCK;
6267 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
6268 }
6269 }
6270
6271 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
6272 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
6273 /* ack for xmit mgmt frames. */
6274 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
6275
6276 exit:
6277 return ret;
6278 }
6279
6280 static void rtl8xxxu_disable_device(struct ieee80211_hw *hw)
6281 {
6282 struct rtl8xxxu_priv *priv = hw->priv;
6283
6284 rtl8xxxu_power_off(priv);
6285 }
6286
6287 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
6288 struct ieee80211_key_conf *key, const u8 *mac)
6289 {
6290 u32 cmd, val32, addr, ctrl;
6291 int j, i, tmp_debug;
6292
6293 tmp_debug = rtl8xxxu_debug;
6294 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
6295 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
6296
6297 /*
6298 * This is a bit of a hack - the lower bits of the cipher
6299 * suite selector happens to match the cipher index in the CAM
6300 */
6301 addr = key->keyidx << CAM_CMD_KEY_SHIFT;
6302 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
6303
6304 for (j = 5; j >= 0; j--) {
6305 switch (j) {
6306 case 0:
6307 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
6308 break;
6309 case 1:
6310 val32 = mac[2] | (mac[3] << 8) |
6311 (mac[4] << 16) | (mac[5] << 24);
6312 break;
6313 default:
6314 i = (j - 2) << 2;
6315 val32 = key->key[i] | (key->key[i + 1] << 8) |
6316 key->key[i + 2] << 16 | key->key[i + 3] << 24;
6317 break;
6318 }
6319
6320 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
6321 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
6322 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
6323 udelay(100);
6324 }
6325
6326 rtl8xxxu_debug = tmp_debug;
6327 }
6328
6329 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
6330 struct ieee80211_vif *vif, const u8 *mac)
6331 {
6332 struct rtl8xxxu_priv *priv = hw->priv;
6333 u8 val8;
6334
6335 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6336 val8 |= BEACON_DISABLE_TSF_UPDATE;
6337 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6338 }
6339
6340 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
6341 struct ieee80211_vif *vif)
6342 {
6343 struct rtl8xxxu_priv *priv = hw->priv;
6344 u8 val8;
6345
6346 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6347 val8 &= ~BEACON_DISABLE_TSF_UPDATE;
6348 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6349 }
6350
6351 static void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
6352 u32 ramask, int sgi)
6353 {
6354 struct h2c_cmd h2c;
6355
6356 h2c.ramask.cmd = H2C_SET_RATE_MASK;
6357 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
6358 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
6359
6360 h2c.ramask.arg = 0x80;
6361 if (sgi)
6362 h2c.ramask.arg |= 0x20;
6363
6364 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
6365 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));
6366 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));
6367 }
6368
6369 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
6370 {
6371 u32 val32;
6372 u8 rate_idx = 0;
6373
6374 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
6375
6376 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6377 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
6378 val32 |= rate_cfg;
6379 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6380
6381 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
6382
6383 while (rate_cfg) {
6384 rate_cfg = (rate_cfg >> 1);
6385 rate_idx++;
6386 }
6387 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
6388 }
6389
6390 static void
6391 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6392 struct ieee80211_bss_conf *bss_conf, u32 changed)
6393 {
6394 struct rtl8xxxu_priv *priv = hw->priv;
6395 struct device *dev = &priv->udev->dev;
6396 struct ieee80211_sta *sta;
6397 u32 val32;
6398 u8 val8;
6399
6400 if (changed & BSS_CHANGED_ASSOC) {
6401 struct h2c_cmd h2c;
6402
6403 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
6404
6405 memset(&h2c, 0, sizeof(struct h2c_cmd));
6406 rtl8xxxu_set_linktype(priv, vif->type);
6407
6408 if (bss_conf->assoc) {
6409 u32 ramask;
6410 int sgi = 0;
6411
6412 rcu_read_lock();
6413 sta = ieee80211_find_sta(vif, bss_conf->bssid);
6414 if (!sta) {
6415 dev_info(dev, "%s: ASSOC no sta found\n",
6416 __func__);
6417 rcu_read_unlock();
6418 goto error;
6419 }
6420
6421 if (sta->ht_cap.ht_supported)
6422 dev_info(dev, "%s: HT supported\n", __func__);
6423 if (sta->vht_cap.vht_supported)
6424 dev_info(dev, "%s: VHT supported\n", __func__);
6425
6426 /* TODO: Set bits 28-31 for rate adaptive id */
6427 ramask = (sta->supp_rates[0] & 0xfff) |
6428 sta->ht_cap.mcs.rx_mask[0] << 12 |
6429 sta->ht_cap.mcs.rx_mask[1] << 20;
6430 if (sta->ht_cap.cap &
6431 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
6432 sgi = 1;
6433 rcu_read_unlock();
6434
6435 rtl8xxxu_update_rate_mask(priv, ramask, sgi);
6436
6437 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
6438
6439 rtl8723a_stop_tx_beacon(priv);
6440
6441 /* joinbss sequence */
6442 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
6443 0xc000 | bss_conf->aid);
6444
6445 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
6446 } else {
6447 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6448 val8 |= BEACON_DISABLE_TSF_UPDATE;
6449 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6450
6451 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
6452 }
6453 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
6454 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));
6455 }
6456
6457 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
6458 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
6459 bss_conf->use_short_preamble);
6460 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6461 if (bss_conf->use_short_preamble)
6462 val32 |= RSR_ACK_SHORT_PREAMBLE;
6463 else
6464 val32 &= ~RSR_ACK_SHORT_PREAMBLE;
6465 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6466 }
6467
6468 if (changed & BSS_CHANGED_ERP_SLOT) {
6469 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
6470 bss_conf->use_short_slot);
6471
6472 if (bss_conf->use_short_slot)
6473 val8 = 9;
6474 else
6475 val8 = 20;
6476 rtl8xxxu_write8(priv, REG_SLOT, val8);
6477 }
6478
6479 if (changed & BSS_CHANGED_BSSID) {
6480 dev_dbg(dev, "Changed BSSID!\n");
6481 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
6482 }
6483
6484 if (changed & BSS_CHANGED_BASIC_RATES) {
6485 dev_dbg(dev, "Changed BASIC_RATES!\n");
6486 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
6487 }
6488 error:
6489 return;
6490 }
6491
6492 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
6493 {
6494 u32 rtlqueue;
6495
6496 switch (queue) {
6497 case IEEE80211_AC_VO:
6498 rtlqueue = TXDESC_QUEUE_VO;
6499 break;
6500 case IEEE80211_AC_VI:
6501 rtlqueue = TXDESC_QUEUE_VI;
6502 break;
6503 case IEEE80211_AC_BE:
6504 rtlqueue = TXDESC_QUEUE_BE;
6505 break;
6506 case IEEE80211_AC_BK:
6507 rtlqueue = TXDESC_QUEUE_BK;
6508 break;
6509 default:
6510 rtlqueue = TXDESC_QUEUE_BE;
6511 }
6512
6513 return rtlqueue;
6514 }
6515
6516 static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
6517 {
6518 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
6519 u32 queue;
6520
6521 if (ieee80211_is_mgmt(hdr->frame_control))
6522 queue = TXDESC_QUEUE_MGNT;
6523 else
6524 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
6525
6526 return queue;
6527 }
6528
6529 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_tx_desc *tx_desc)
6530 {
6531 __le16 *ptr = (__le16 *)tx_desc;
6532 u16 csum = 0;
6533 int i;
6534
6535 /*
6536 * Clear csum field before calculation, as the csum field is
6537 * in the middle of the struct.
6538 */
6539 tx_desc->csum = cpu_to_le16(0);
6540
6541 for (i = 0; i < (sizeof(struct rtl8xxxu_tx_desc) / sizeof(u16)); i++)
6542 csum = csum ^ le16_to_cpu(ptr[i]);
6543
6544 tx_desc->csum |= cpu_to_le16(csum);
6545 }
6546
6547 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
6548 {
6549 struct rtl8xxxu_tx_urb *tx_urb, *tmp;
6550 unsigned long flags;
6551
6552 spin_lock_irqsave(&priv->tx_urb_lock, flags);
6553 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
6554 list_del(&tx_urb->list);
6555 priv->tx_urb_free_count--;
6556 usb_free_urb(&tx_urb->urb);
6557 }
6558 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6559 }
6560
6561 static struct rtl8xxxu_tx_urb *
6562 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
6563 {
6564 struct rtl8xxxu_tx_urb *tx_urb;
6565 unsigned long flags;
6566
6567 spin_lock_irqsave(&priv->tx_urb_lock, flags);
6568 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
6569 struct rtl8xxxu_tx_urb, list);
6570 if (tx_urb) {
6571 list_del(&tx_urb->list);
6572 priv->tx_urb_free_count--;
6573 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
6574 !priv->tx_stopped) {
6575 priv->tx_stopped = true;
6576 ieee80211_stop_queues(priv->hw);
6577 }
6578 }
6579
6580 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6581
6582 return tx_urb;
6583 }
6584
6585 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
6586 struct rtl8xxxu_tx_urb *tx_urb)
6587 {
6588 unsigned long flags;
6589
6590 INIT_LIST_HEAD(&tx_urb->list);
6591
6592 spin_lock_irqsave(&priv->tx_urb_lock, flags);
6593
6594 list_add(&tx_urb->list, &priv->tx_urb_free_list);
6595 priv->tx_urb_free_count++;
6596 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
6597 priv->tx_stopped) {
6598 priv->tx_stopped = false;
6599 ieee80211_wake_queues(priv->hw);
6600 }
6601
6602 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6603 }
6604
6605 static void rtl8xxxu_tx_complete(struct urb *urb)
6606 {
6607 struct sk_buff *skb = (struct sk_buff *)urb->context;
6608 struct ieee80211_tx_info *tx_info;
6609 struct ieee80211_hw *hw;
6610 struct rtl8xxxu_tx_urb *tx_urb =
6611 container_of(urb, struct rtl8xxxu_tx_urb, urb);
6612
6613 tx_info = IEEE80211_SKB_CB(skb);
6614 hw = tx_info->rate_driver_data[0];
6615
6616 skb_pull(skb, sizeof(struct rtl8xxxu_tx_desc));
6617
6618 ieee80211_tx_info_clear_status(tx_info);
6619 tx_info->status.rates[0].idx = -1;
6620 tx_info->status.rates[0].count = 0;
6621
6622 if (!urb->status)
6623 tx_info->flags |= IEEE80211_TX_STAT_ACK;
6624
6625 ieee80211_tx_status_irqsafe(hw, skb);
6626
6627 rtl8xxxu_free_tx_urb(hw->priv, tx_urb);
6628 }
6629
6630 static void rtl8xxxu_dump_action(struct device *dev,
6631 struct ieee80211_hdr *hdr)
6632 {
6633 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
6634 u16 cap, timeout;
6635
6636 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
6637 return;
6638
6639 switch (mgmt->u.action.u.addba_resp.action_code) {
6640 case WLAN_ACTION_ADDBA_RESP:
6641 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
6642 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
6643 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
6644 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
6645 "status %02x\n",
6646 timeout,
6647 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
6648 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
6649 (cap >> 1) & 0x1,
6650 le16_to_cpu(mgmt->u.action.u.addba_resp.status));
6651 break;
6652 case WLAN_ACTION_ADDBA_REQ:
6653 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
6654 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
6655 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
6656 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
6657 timeout,
6658 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
6659 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
6660 (cap >> 1) & 0x1);
6661 break;
6662 default:
6663 dev_info(dev, "action frame %02x\n",
6664 mgmt->u.action.u.addba_resp.action_code);
6665 break;
6666 }
6667 }
6668
6669 static void rtl8xxxu_tx(struct ieee80211_hw *hw,
6670 struct ieee80211_tx_control *control,
6671 struct sk_buff *skb)
6672 {
6673 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
6674 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
6675 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
6676 struct rtl8xxxu_priv *priv = hw->priv;
6677 struct rtl8xxxu_tx_desc *tx_desc;
6678 struct rtl8xxxu_tx_urb *tx_urb;
6679 struct ieee80211_sta *sta = NULL;
6680 struct ieee80211_vif *vif = tx_info->control.vif;
6681 struct device *dev = &priv->udev->dev;
6682 u32 queue, rate;
6683 u16 pktlen = skb->len;
6684 u16 seq_number;
6685 u16 rate_flag = tx_info->control.rates[0].flags;
6686 int ret;
6687
6688 if (skb_headroom(skb) < sizeof(struct rtl8xxxu_tx_desc)) {
6689 dev_warn(dev,
6690 "%s: Not enough headroom (%i) for tx descriptor\n",
6691 __func__, skb_headroom(skb));
6692 goto error;
6693 }
6694
6695 if (unlikely(skb->len > (65535 - sizeof(struct rtl8xxxu_tx_desc)))) {
6696 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
6697 __func__, skb->len);
6698 goto error;
6699 }
6700
6701 tx_urb = rtl8xxxu_alloc_tx_urb(priv);
6702 if (!tx_urb) {
6703 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
6704 goto error;
6705 }
6706
6707 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
6708 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
6709 __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
6710
6711 if (ieee80211_is_action(hdr->frame_control))
6712 rtl8xxxu_dump_action(dev, hdr);
6713
6714 tx_info->rate_driver_data[0] = hw;
6715
6716 if (control && control->sta)
6717 sta = control->sta;
6718
6719 tx_desc = (struct rtl8xxxu_tx_desc *)
6720 skb_push(skb, sizeof(struct rtl8xxxu_tx_desc));
6721
6722 memset(tx_desc, 0, sizeof(struct rtl8xxxu_tx_desc));
6723 tx_desc->pkt_size = cpu_to_le16(pktlen);
6724 tx_desc->pkt_offset = sizeof(struct rtl8xxxu_tx_desc);
6725
6726 tx_desc->txdw0 =
6727 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
6728 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
6729 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
6730 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
6731
6732 queue = rtl8xxxu_queue_select(hw, skb);
6733 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
6734
6735 if (tx_info->control.hw_key) {
6736 switch (tx_info->control.hw_key->cipher) {
6737 case WLAN_CIPHER_SUITE_WEP40:
6738 case WLAN_CIPHER_SUITE_WEP104:
6739 case WLAN_CIPHER_SUITE_TKIP:
6740 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
6741 break;
6742 case WLAN_CIPHER_SUITE_CCMP:
6743 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
6744 break;
6745 default:
6746 break;
6747 }
6748 }
6749
6750 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
6751 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT);
6752
6753 if (rate_flag & IEEE80211_TX_RC_MCS)
6754 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
6755 else
6756 rate = tx_rate->hw_value;
6757 tx_desc->txdw5 = cpu_to_le32(rate);
6758
6759 if (ieee80211_is_data(hdr->frame_control))
6760 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
6761
6762 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
6763 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
6764 if (sta->ht_cap.ht_supported) {
6765 u32 ampdu, val32;
6766
6767 ampdu = (u32)sta->ht_cap.ampdu_density;
6768 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
6769 tx_desc->txdw2 |= cpu_to_le32(val32);
6770 tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_ENABLE);
6771 } else
6772 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
6773 } else
6774 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
6775
6776 if (ieee80211_is_data_qos(hdr->frame_control))
6777 tx_desc->txdw4 |= cpu_to_le32(TXDESC_QOS);
6778 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
6779 (sta && vif && vif->bss_conf.use_short_preamble))
6780 tx_desc->txdw4 |= cpu_to_le32(TXDESC_SHORT_PREAMBLE);
6781 if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
6782 (ieee80211_is_data_qos(hdr->frame_control) &&
6783 sta && sta->ht_cap.cap &
6784 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
6785 tx_desc->txdw5 |= cpu_to_le32(TXDESC_SHORT_GI);
6786 }
6787 if (ieee80211_is_mgmt(hdr->frame_control)) {
6788 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
6789 tx_desc->txdw4 |= cpu_to_le32(TXDESC_USE_DRIVER_RATE);
6790 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC_RETRY_LIMIT_SHIFT);
6791 tx_desc->txdw5 |= cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE);
6792 }
6793
6794 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
6795 /* Use RTS rate 24M - does the mac80211 tell us which to use? */
6796 tx_desc->txdw4 |= cpu_to_le32(DESC_RATE_24M);
6797 tx_desc->txdw4 |= cpu_to_le32(TXDESC_RTS_CTS_ENABLE);
6798 tx_desc->txdw4 |= cpu_to_le32(TXDESC_HW_RTS_ENABLE);
6799 }
6800
6801 rtl8xxxu_calc_tx_desc_csum(tx_desc);
6802
6803 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
6804 skb->data, skb->len, rtl8xxxu_tx_complete, skb);
6805
6806 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
6807 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
6808 if (ret) {
6809 usb_unanchor_urb(&tx_urb->urb);
6810 rtl8xxxu_free_tx_urb(priv, tx_urb);
6811 goto error;
6812 }
6813 return;
6814 error:
6815 dev_kfree_skb(skb);
6816 }
6817
6818 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
6819 struct ieee80211_rx_status *rx_status,
6820 struct rtl8xxxu_rx_desc *rx_desc,
6821 struct rtl8723au_phy_stats *phy_stats)
6822 {
6823 if (phy_stats->sgi_en)
6824 rx_status->flag |= RX_FLAG_SHORT_GI;
6825
6826 if (rx_desc->rxmcs < DESC_RATE_6M) {
6827 /*
6828 * Handle PHY stats for CCK rates
6829 */
6830 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
6831
6832 switch (cck_agc_rpt & 0xc0) {
6833 case 0xc0:
6834 rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
6835 break;
6836 case 0x80:
6837 rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
6838 break;
6839 case 0x40:
6840 rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
6841 break;
6842 case 0x00:
6843 rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
6844 break;
6845 }
6846 } else {
6847 rx_status->signal =
6848 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
6849 }
6850 }
6851
6852 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
6853 {
6854 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
6855 unsigned long flags;
6856
6857 spin_lock_irqsave(&priv->rx_urb_lock, flags);
6858
6859 list_for_each_entry_safe(rx_urb, tmp,
6860 &priv->rx_urb_pending_list, list) {
6861 list_del(&rx_urb->list);
6862 priv->rx_urb_pending_count--;
6863 usb_free_urb(&rx_urb->urb);
6864 }
6865
6866 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
6867 }
6868
6869 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
6870 struct rtl8xxxu_rx_urb *rx_urb)
6871 {
6872 struct sk_buff *skb;
6873 unsigned long flags;
6874 int pending = 0;
6875
6876 spin_lock_irqsave(&priv->rx_urb_lock, flags);
6877
6878 if (!priv->shutdown) {
6879 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
6880 priv->rx_urb_pending_count++;
6881 pending = priv->rx_urb_pending_count;
6882 } else {
6883 skb = (struct sk_buff *)rx_urb->urb.context;
6884 dev_kfree_skb(skb);
6885 usb_free_urb(&rx_urb->urb);
6886 }
6887
6888 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
6889
6890 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
6891 schedule_work(&priv->rx_urb_wq);
6892 }
6893
6894 static void rtl8xxxu_rx_urb_work(struct work_struct *work)
6895 {
6896 struct rtl8xxxu_priv *priv;
6897 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
6898 struct list_head local;
6899 struct sk_buff *skb;
6900 unsigned long flags;
6901 int ret;
6902
6903 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
6904 INIT_LIST_HEAD(&local);
6905
6906 spin_lock_irqsave(&priv->rx_urb_lock, flags);
6907
6908 list_splice_init(&priv->rx_urb_pending_list, &local);
6909 priv->rx_urb_pending_count = 0;
6910
6911 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
6912
6913 list_for_each_entry_safe(rx_urb, tmp, &local, list) {
6914 list_del_init(&rx_urb->list);
6915 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
6916 /*
6917 * If out of memory or temporary error, put it back on the
6918 * queue and try again. Otherwise the device is dead/gone
6919 * and we should drop it.
6920 */
6921 switch (ret) {
6922 case 0:
6923 break;
6924 case -ENOMEM:
6925 case -EAGAIN:
6926 rtl8xxxu_queue_rx_urb(priv, rx_urb);
6927 break;
6928 default:
6929 pr_info("failed to requeue urb %i\n", ret);
6930 skb = (struct sk_buff *)rx_urb->urb.context;
6931 dev_kfree_skb(skb);
6932 usb_free_urb(&rx_urb->urb);
6933 }
6934 }
6935 }
6936
6937 static int rtl8723au_parse_rx_desc(struct rtl8xxxu_priv *priv,
6938 struct sk_buff *skb,
6939 struct ieee80211_rx_status *rx_status)
6940 {
6941 struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data;
6942 struct rtl8723au_phy_stats *phy_stats;
6943 int drvinfo_sz, desc_shift;
6944
6945 skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc));
6946
6947 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
6948
6949 drvinfo_sz = rx_desc->drvinfo_sz * 8;
6950 desc_shift = rx_desc->shift;
6951 skb_pull(skb, drvinfo_sz + desc_shift);
6952
6953 if (rx_desc->phy_stats)
6954 rtl8xxxu_rx_parse_phystats(priv, rx_status, rx_desc, phy_stats);
6955
6956 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
6957 rx_status->flag |= RX_FLAG_MACTIME_START;
6958
6959 if (!rx_desc->swdec)
6960 rx_status->flag |= RX_FLAG_DECRYPTED;
6961 if (rx_desc->crc32)
6962 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
6963 if (rx_desc->bw)
6964 rx_status->flag |= RX_FLAG_40MHZ;
6965
6966 if (rx_desc->rxht) {
6967 rx_status->flag |= RX_FLAG_HT;
6968 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
6969 } else {
6970 rx_status->rate_idx = rx_desc->rxmcs;
6971 }
6972
6973 return RX_TYPE_DATA_PKT;
6974 }
6975
6976 static int rtl8723bu_parse_rx_desc(struct rtl8xxxu_priv *priv,
6977 struct sk_buff *skb,
6978 struct ieee80211_rx_status *rx_status)
6979 {
6980 struct rtl8723bu_rx_desc *rx_desc =
6981 (struct rtl8723bu_rx_desc *)skb->data;
6982 struct rtl8723au_phy_stats *phy_stats;
6983 int drvinfo_sz, desc_shift;
6984 int rx_type;
6985
6986 skb_pull(skb, sizeof(struct rtl8723bu_rx_desc));
6987
6988 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
6989
6990 drvinfo_sz = rx_desc->drvinfo_sz * 8;
6991 desc_shift = rx_desc->shift;
6992 skb_pull(skb, drvinfo_sz + desc_shift);
6993
6994 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
6995 rx_status->flag |= RX_FLAG_MACTIME_START;
6996
6997 if (!rx_desc->swdec)
6998 rx_status->flag |= RX_FLAG_DECRYPTED;
6999 if (rx_desc->crc32)
7000 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7001 if (rx_desc->bw)
7002 rx_status->flag |= RX_FLAG_40MHZ;
7003
7004 if (rx_desc->rxmcs >= DESC_RATE_MCS0) {
7005 rx_status->flag |= RX_FLAG_HT;
7006 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
7007 } else {
7008 rx_status->rate_idx = rx_desc->rxmcs;
7009 }
7010
7011 if (rx_desc->rpt_sel) {
7012 struct device *dev = &priv->udev->dev;
7013 dev_dbg(dev, "%s: C2H packet\n", __func__);
7014 rx_type = RX_TYPE_C2H;
7015 } else {
7016 rx_type = RX_TYPE_DATA_PKT;
7017 }
7018
7019 return rx_type;
7020 }
7021
7022 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv,
7023 struct sk_buff *skb)
7024 {
7025 struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data;
7026 struct device *dev = &priv->udev->dev;
7027 int len;
7028
7029 len = skb->len - 2;
7030
7031 dev_info(dev, "C2H ID %02x seq %02x, len %02x source %02x\n",
7032 c2h->id, c2h->seq, len, c2h->bt_info.response_source);
7033
7034 switch(c2h->id) {
7035 case C2H_8723B_BT_INFO:
7036 if (c2h->bt_info.response_source >
7037 BT_INFO_SRC_8723B_BT_ACTIVE_SEND)
7038 dev_info(dev, "C2H_BT_INFO WiFi only firmware\n");
7039 else
7040 dev_info(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n");
7041
7042 if (c2h->bt_info.bt_has_reset)
7043 dev_info(dev, "BT has been reset\n");
7044 if (c2h->bt_info.tx_rx_mask)
7045 dev_info(dev, "BT TRx mask\n");
7046
7047 break;
7048 case C2H_8723B_BT_MP_INFO:
7049 dev_info(dev, "C2H_MP_INFO ext ID %02x, status %02x\n",
7050 c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status);
7051 break;
7052 default:
7053 pr_info("%s: Unhandled C2H event %02x\n", __func__, c2h->id);
7054 break;
7055 }
7056 }
7057
7058 static void rtl8xxxu_rx_complete(struct urb *urb)
7059 {
7060 struct rtl8xxxu_rx_urb *rx_urb =
7061 container_of(urb, struct rtl8xxxu_rx_urb, urb);
7062 struct ieee80211_hw *hw = rx_urb->hw;
7063 struct rtl8xxxu_priv *priv = hw->priv;
7064 struct sk_buff *skb = (struct sk_buff *)urb->context;
7065 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
7066 struct device *dev = &priv->udev->dev;
7067 __le32 *_rx_desc_le = (__le32 *)skb->data;
7068 u32 *_rx_desc = (u32 *)skb->data;
7069 int rx_type, i;
7070
7071 for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++)
7072 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
7073
7074 skb_put(skb, urb->actual_length);
7075
7076 if (urb->status == 0) {
7077 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
7078
7079 rx_type = priv->fops->parse_rx_desc(priv, skb, rx_status);
7080
7081 rx_status->freq = hw->conf.chandef.chan->center_freq;
7082 rx_status->band = hw->conf.chandef.chan->band;
7083
7084 if (rx_type == RX_TYPE_DATA_PKT)
7085 ieee80211_rx_irqsafe(hw, skb);
7086 else {
7087 rtl8723bu_handle_c2h(priv, skb);
7088 dev_kfree_skb(skb);
7089 }
7090
7091 skb = NULL;
7092 rx_urb->urb.context = NULL;
7093 rtl8xxxu_queue_rx_urb(priv, rx_urb);
7094 } else {
7095 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
7096 goto cleanup;
7097 }
7098 return;
7099
7100 cleanup:
7101 usb_free_urb(urb);
7102 dev_kfree_skb(skb);
7103 return;
7104 }
7105
7106 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
7107 struct rtl8xxxu_rx_urb *rx_urb)
7108 {
7109 struct sk_buff *skb;
7110 int skb_size;
7111 int ret;
7112
7113 skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE;
7114 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
7115 if (!skb)
7116 return -ENOMEM;
7117
7118 memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc));
7119 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
7120 skb_size, rtl8xxxu_rx_complete, skb);
7121 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
7122 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
7123 if (ret)
7124 usb_unanchor_urb(&rx_urb->urb);
7125 return ret;
7126 }
7127
7128 static void rtl8xxxu_int_complete(struct urb *urb)
7129 {
7130 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
7131 struct device *dev = &priv->udev->dev;
7132 int ret;
7133
7134 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
7135 if (urb->status == 0) {
7136 usb_anchor_urb(urb, &priv->int_anchor);
7137 ret = usb_submit_urb(urb, GFP_ATOMIC);
7138 if (ret)
7139 usb_unanchor_urb(urb);
7140 } else {
7141 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
7142 }
7143 }
7144
7145
7146 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
7147 {
7148 struct rtl8xxxu_priv *priv = hw->priv;
7149 struct urb *urb;
7150 u32 val32;
7151 int ret;
7152
7153 urb = usb_alloc_urb(0, GFP_KERNEL);
7154 if (!urb)
7155 return -ENOMEM;
7156
7157 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
7158 priv->int_buf, USB_INTR_CONTENT_LENGTH,
7159 rtl8xxxu_int_complete, priv, 1);
7160 usb_anchor_urb(urb, &priv->int_anchor);
7161 ret = usb_submit_urb(urb, GFP_KERNEL);
7162 if (ret) {
7163 usb_unanchor_urb(urb);
7164 goto error;
7165 }
7166
7167 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
7168 val32 |= USB_HIMR_CPWM;
7169 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
7170
7171 error:
7172 return ret;
7173 }
7174
7175 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
7176 struct ieee80211_vif *vif)
7177 {
7178 struct rtl8xxxu_priv *priv = hw->priv;
7179 int ret;
7180 u8 val8;
7181
7182 switch (vif->type) {
7183 case NL80211_IFTYPE_STATION:
7184 rtl8723a_stop_tx_beacon(priv);
7185
7186 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
7187 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
7188 BEACON_DISABLE_TSF_UPDATE;
7189 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
7190 ret = 0;
7191 break;
7192 default:
7193 ret = -EOPNOTSUPP;
7194 }
7195
7196 rtl8xxxu_set_linktype(priv, vif->type);
7197
7198 return ret;
7199 }
7200
7201 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
7202 struct ieee80211_vif *vif)
7203 {
7204 struct rtl8xxxu_priv *priv = hw->priv;
7205
7206 dev_dbg(&priv->udev->dev, "%s\n", __func__);
7207 }
7208
7209 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
7210 {
7211 struct rtl8xxxu_priv *priv = hw->priv;
7212 struct device *dev = &priv->udev->dev;
7213 u16 val16;
7214 int ret = 0, channel;
7215 bool ht40;
7216
7217 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
7218 dev_info(dev,
7219 "%s: channel: %i (changed %08x chandef.width %02x)\n",
7220 __func__, hw->conf.chandef.chan->hw_value,
7221 changed, hw->conf.chandef.width);
7222
7223 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
7224 val16 = ((hw->conf.long_frame_max_tx_count <<
7225 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
7226 ((hw->conf.short_frame_max_tx_count <<
7227 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
7228 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
7229 }
7230
7231 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
7232 switch (hw->conf.chandef.width) {
7233 case NL80211_CHAN_WIDTH_20_NOHT:
7234 case NL80211_CHAN_WIDTH_20:
7235 ht40 = false;
7236 break;
7237 case NL80211_CHAN_WIDTH_40:
7238 ht40 = true;
7239 break;
7240 default:
7241 ret = -ENOTSUPP;
7242 goto exit;
7243 }
7244
7245 channel = hw->conf.chandef.chan->hw_value;
7246
7247 rtl8723a_set_tx_power(priv, channel, ht40);
7248
7249 rtl8723au_config_channel(hw);
7250 }
7251
7252 exit:
7253 return ret;
7254 }
7255
7256 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
7257 struct ieee80211_vif *vif, u16 queue,
7258 const struct ieee80211_tx_queue_params *param)
7259 {
7260 struct rtl8xxxu_priv *priv = hw->priv;
7261 struct device *dev = &priv->udev->dev;
7262 u32 val32;
7263 u8 aifs, acm_ctrl, acm_bit;
7264
7265 aifs = param->aifs;
7266
7267 val32 = aifs |
7268 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
7269 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
7270 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
7271
7272 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
7273 dev_dbg(dev,
7274 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
7275 __func__, queue, val32, param->acm, acm_ctrl);
7276
7277 switch (queue) {
7278 case IEEE80211_AC_VO:
7279 acm_bit = ACM_HW_CTRL_VO;
7280 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
7281 break;
7282 case IEEE80211_AC_VI:
7283 acm_bit = ACM_HW_CTRL_VI;
7284 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
7285 break;
7286 case IEEE80211_AC_BE:
7287 acm_bit = ACM_HW_CTRL_BE;
7288 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
7289 break;
7290 case IEEE80211_AC_BK:
7291 acm_bit = ACM_HW_CTRL_BK;
7292 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
7293 break;
7294 default:
7295 acm_bit = 0;
7296 break;
7297 }
7298
7299 if (param->acm)
7300 acm_ctrl |= acm_bit;
7301 else
7302 acm_ctrl &= ~acm_bit;
7303 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
7304
7305 return 0;
7306 }
7307
7308 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
7309 unsigned int changed_flags,
7310 unsigned int *total_flags, u64 multicast)
7311 {
7312 struct rtl8xxxu_priv *priv = hw->priv;
7313 u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
7314
7315 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
7316 __func__, changed_flags, *total_flags);
7317
7318 /*
7319 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
7320 */
7321
7322 if (*total_flags & FIF_FCSFAIL)
7323 rcr |= RCR_ACCEPT_CRC32;
7324 else
7325 rcr &= ~RCR_ACCEPT_CRC32;
7326
7327 /*
7328 * FIF_PLCPFAIL not supported?
7329 */
7330
7331 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
7332 rcr &= ~RCR_CHECK_BSSID_BEACON;
7333 else
7334 rcr |= RCR_CHECK_BSSID_BEACON;
7335
7336 if (*total_flags & FIF_CONTROL)
7337 rcr |= RCR_ACCEPT_CTRL_FRAME;
7338 else
7339 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
7340
7341 if (*total_flags & FIF_OTHER_BSS) {
7342 rcr |= RCR_ACCEPT_AP;
7343 rcr &= ~RCR_CHECK_BSSID_MATCH;
7344 } else {
7345 rcr &= ~RCR_ACCEPT_AP;
7346 rcr |= RCR_CHECK_BSSID_MATCH;
7347 }
7348
7349 if (*total_flags & FIF_PSPOLL)
7350 rcr |= RCR_ACCEPT_PM;
7351 else
7352 rcr &= ~RCR_ACCEPT_PM;
7353
7354 /*
7355 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
7356 */
7357
7358 rtl8xxxu_write32(priv, REG_RCR, rcr);
7359
7360 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
7361 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
7362 FIF_PROBE_REQ);
7363 }
7364
7365 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
7366 {
7367 if (rts > 2347)
7368 return -EINVAL;
7369
7370 return 0;
7371 }
7372
7373 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
7374 struct ieee80211_vif *vif,
7375 struct ieee80211_sta *sta,
7376 struct ieee80211_key_conf *key)
7377 {
7378 struct rtl8xxxu_priv *priv = hw->priv;
7379 struct device *dev = &priv->udev->dev;
7380 u8 mac_addr[ETH_ALEN];
7381 u8 val8;
7382 u16 val16;
7383 u32 val32;
7384 int retval = -EOPNOTSUPP;
7385
7386 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
7387 __func__, cmd, key->cipher, key->keyidx);
7388
7389 if (vif->type != NL80211_IFTYPE_STATION)
7390 return -EOPNOTSUPP;
7391
7392 if (key->keyidx > 3)
7393 return -EOPNOTSUPP;
7394
7395 switch (key->cipher) {
7396 case WLAN_CIPHER_SUITE_WEP40:
7397 case WLAN_CIPHER_SUITE_WEP104:
7398
7399 break;
7400 case WLAN_CIPHER_SUITE_CCMP:
7401 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
7402 break;
7403 case WLAN_CIPHER_SUITE_TKIP:
7404 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
7405 default:
7406 return -EOPNOTSUPP;
7407 }
7408
7409 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
7410 dev_dbg(dev, "%s: pairwise key\n", __func__);
7411 ether_addr_copy(mac_addr, sta->addr);
7412 } else {
7413 dev_dbg(dev, "%s: group key\n", __func__);
7414 eth_broadcast_addr(mac_addr);
7415 }
7416
7417 val16 = rtl8xxxu_read16(priv, REG_CR);
7418 val16 |= CR_SECURITY_ENABLE;
7419 rtl8xxxu_write16(priv, REG_CR, val16);
7420
7421 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
7422 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
7423 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
7424 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
7425
7426 switch (cmd) {
7427 case SET_KEY:
7428 key->hw_key_idx = key->keyidx;
7429 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7430 rtl8xxxu_cam_write(priv, key, mac_addr);
7431 retval = 0;
7432 break;
7433 case DISABLE_KEY:
7434 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
7435 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
7436 key->keyidx << CAM_CMD_KEY_SHIFT;
7437 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
7438 retval = 0;
7439 break;
7440 default:
7441 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
7442 }
7443
7444 return retval;
7445 }
7446
7447 static int
7448 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7449 struct ieee80211_ampdu_params *params)
7450 {
7451 struct rtl8xxxu_priv *priv = hw->priv;
7452 struct device *dev = &priv->udev->dev;
7453 u8 ampdu_factor, ampdu_density;
7454 struct ieee80211_sta *sta = params->sta;
7455 enum ieee80211_ampdu_mlme_action action = params->action;
7456
7457 switch (action) {
7458 case IEEE80211_AMPDU_TX_START:
7459 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
7460 ampdu_factor = sta->ht_cap.ampdu_factor;
7461 ampdu_density = sta->ht_cap.ampdu_density;
7462 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
7463 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
7464 dev_dbg(dev,
7465 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
7466 ampdu_factor, ampdu_density);
7467 break;
7468 case IEEE80211_AMPDU_TX_STOP_FLUSH:
7469 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
7470 rtl8xxxu_set_ampdu_factor(priv, 0);
7471 rtl8xxxu_set_ampdu_min_space(priv, 0);
7472 break;
7473 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
7474 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
7475 __func__);
7476 rtl8xxxu_set_ampdu_factor(priv, 0);
7477 rtl8xxxu_set_ampdu_min_space(priv, 0);
7478 break;
7479 case IEEE80211_AMPDU_RX_START:
7480 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
7481 break;
7482 case IEEE80211_AMPDU_RX_STOP:
7483 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
7484 break;
7485 default:
7486 break;
7487 }
7488 return 0;
7489 }
7490
7491 static int rtl8xxxu_start(struct ieee80211_hw *hw)
7492 {
7493 struct rtl8xxxu_priv *priv = hw->priv;
7494 struct rtl8xxxu_rx_urb *rx_urb;
7495 struct rtl8xxxu_tx_urb *tx_urb;
7496 unsigned long flags;
7497 int ret, i;
7498
7499 ret = 0;
7500
7501 init_usb_anchor(&priv->rx_anchor);
7502 init_usb_anchor(&priv->tx_anchor);
7503 init_usb_anchor(&priv->int_anchor);
7504
7505 rtl8723a_enable_rf(priv);
7506 if (priv->usb_interrupts) {
7507 ret = rtl8xxxu_submit_int_urb(hw);
7508 if (ret)
7509 goto exit;
7510 }
7511
7512 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
7513 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
7514 if (!tx_urb) {
7515 if (!i)
7516 ret = -ENOMEM;
7517
7518 goto error_out;
7519 }
7520 usb_init_urb(&tx_urb->urb);
7521 INIT_LIST_HEAD(&tx_urb->list);
7522 tx_urb->hw = hw;
7523 list_add(&tx_urb->list, &priv->tx_urb_free_list);
7524 priv->tx_urb_free_count++;
7525 }
7526
7527 priv->tx_stopped = false;
7528
7529 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7530 priv->shutdown = false;
7531 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7532
7533 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
7534 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
7535 if (!rx_urb) {
7536 if (!i)
7537 ret = -ENOMEM;
7538
7539 goto error_out;
7540 }
7541 usb_init_urb(&rx_urb->urb);
7542 INIT_LIST_HEAD(&rx_urb->list);
7543 rx_urb->hw = hw;
7544
7545 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
7546 }
7547 exit:
7548 /*
7549 * Accept all data and mgmt frames
7550 */
7551 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
7552 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
7553
7554 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
7555
7556 return ret;
7557
7558 error_out:
7559 rtl8xxxu_free_tx_resources(priv);
7560 /*
7561 * Disable all data and mgmt frames
7562 */
7563 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
7564 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
7565
7566 return ret;
7567 }
7568
7569 static void rtl8xxxu_stop(struct ieee80211_hw *hw)
7570 {
7571 struct rtl8xxxu_priv *priv = hw->priv;
7572 unsigned long flags;
7573
7574 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
7575
7576 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
7577 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
7578
7579 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7580 priv->shutdown = true;
7581 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7582
7583 usb_kill_anchored_urbs(&priv->rx_anchor);
7584 usb_kill_anchored_urbs(&priv->tx_anchor);
7585 if (priv->usb_interrupts)
7586 usb_kill_anchored_urbs(&priv->int_anchor);
7587
7588 rtl8723a_disable_rf(priv);
7589
7590 /*
7591 * Disable interrupts
7592 */
7593 if (priv->usb_interrupts)
7594 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
7595
7596 rtl8xxxu_free_rx_resources(priv);
7597 rtl8xxxu_free_tx_resources(priv);
7598 }
7599
7600 static const struct ieee80211_ops rtl8xxxu_ops = {
7601 .tx = rtl8xxxu_tx,
7602 .add_interface = rtl8xxxu_add_interface,
7603 .remove_interface = rtl8xxxu_remove_interface,
7604 .config = rtl8xxxu_config,
7605 .conf_tx = rtl8xxxu_conf_tx,
7606 .bss_info_changed = rtl8xxxu_bss_info_changed,
7607 .configure_filter = rtl8xxxu_configure_filter,
7608 .set_rts_threshold = rtl8xxxu_set_rts_threshold,
7609 .start = rtl8xxxu_start,
7610 .stop = rtl8xxxu_stop,
7611 .sw_scan_start = rtl8xxxu_sw_scan_start,
7612 .sw_scan_complete = rtl8xxxu_sw_scan_complete,
7613 .set_key = rtl8xxxu_set_key,
7614 .ampdu_action = rtl8xxxu_ampdu_action,
7615 };
7616
7617 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
7618 struct usb_interface *interface)
7619 {
7620 struct usb_interface_descriptor *interface_desc;
7621 struct usb_host_interface *host_interface;
7622 struct usb_endpoint_descriptor *endpoint;
7623 struct device *dev = &priv->udev->dev;
7624 int i, j = 0, endpoints;
7625 u8 dir, xtype, num;
7626 int ret = 0;
7627
7628 host_interface = &interface->altsetting[0];
7629 interface_desc = &host_interface->desc;
7630 endpoints = interface_desc->bNumEndpoints;
7631
7632 for (i = 0; i < endpoints; i++) {
7633 endpoint = &host_interface->endpoint[i].desc;
7634
7635 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
7636 num = usb_endpoint_num(endpoint);
7637 xtype = usb_endpoint_type(endpoint);
7638 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7639 dev_dbg(dev,
7640 "%s: endpoint: dir %02x, # %02x, type %02x\n",
7641 __func__, dir, num, xtype);
7642 if (usb_endpoint_dir_in(endpoint) &&
7643 usb_endpoint_xfer_bulk(endpoint)) {
7644 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7645 dev_dbg(dev, "%s: in endpoint num %i\n",
7646 __func__, num);
7647
7648 if (priv->pipe_in) {
7649 dev_warn(dev,
7650 "%s: Too many IN pipes\n", __func__);
7651 ret = -EINVAL;
7652 goto exit;
7653 }
7654
7655 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
7656 }
7657
7658 if (usb_endpoint_dir_in(endpoint) &&
7659 usb_endpoint_xfer_int(endpoint)) {
7660 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7661 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
7662 __func__, num);
7663
7664 if (priv->pipe_interrupt) {
7665 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
7666 __func__);
7667 ret = -EINVAL;
7668 goto exit;
7669 }
7670
7671 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
7672 }
7673
7674 if (usb_endpoint_dir_out(endpoint) &&
7675 usb_endpoint_xfer_bulk(endpoint)) {
7676 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7677 dev_dbg(dev, "%s: out endpoint num %i\n",
7678 __func__, num);
7679 if (j >= RTL8XXXU_OUT_ENDPOINTS) {
7680 dev_warn(dev,
7681 "%s: Too many OUT pipes\n", __func__);
7682 ret = -EINVAL;
7683 goto exit;
7684 }
7685 priv->out_ep[j++] = num;
7686 }
7687 }
7688 exit:
7689 priv->nr_out_eps = j;
7690 return ret;
7691 }
7692
7693 static int rtl8xxxu_probe(struct usb_interface *interface,
7694 const struct usb_device_id *id)
7695 {
7696 struct rtl8xxxu_priv *priv;
7697 struct ieee80211_hw *hw;
7698 struct usb_device *udev;
7699 struct ieee80211_supported_band *sband;
7700 int ret = 0;
7701 int untested = 1;
7702
7703 udev = usb_get_dev(interface_to_usbdev(interface));
7704
7705 switch (id->idVendor) {
7706 case USB_VENDOR_ID_REALTEK:
7707 switch(id->idProduct) {
7708 case 0x1724:
7709 case 0x8176:
7710 case 0x8178:
7711 case 0x817f:
7712 untested = 0;
7713 break;
7714 }
7715 break;
7716 case 0x7392:
7717 if (id->idProduct == 0x7811)
7718 untested = 0;
7719 break;
7720 default:
7721 break;
7722 }
7723
7724 if (untested) {
7725 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE;
7726 dev_info(&udev->dev,
7727 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
7728 id->idVendor, id->idProduct);
7729 dev_info(&udev->dev,
7730 "Please report results to Jes.Sorensen@gmail.com\n");
7731 }
7732
7733 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
7734 if (!hw) {
7735 ret = -ENOMEM;
7736 goto exit;
7737 }
7738
7739 priv = hw->priv;
7740 priv->hw = hw;
7741 priv->udev = udev;
7742 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
7743 mutex_init(&priv->usb_buf_mutex);
7744 mutex_init(&priv->h2c_mutex);
7745 INIT_LIST_HEAD(&priv->tx_urb_free_list);
7746 spin_lock_init(&priv->tx_urb_lock);
7747 INIT_LIST_HEAD(&priv->rx_urb_pending_list);
7748 spin_lock_init(&priv->rx_urb_lock);
7749 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
7750
7751 usb_set_intfdata(interface, hw);
7752
7753 ret = rtl8xxxu_parse_usb(priv, interface);
7754 if (ret)
7755 goto exit;
7756
7757 ret = rtl8xxxu_identify_chip(priv);
7758 if (ret) {
7759 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
7760 goto exit;
7761 }
7762
7763 ret = rtl8xxxu_read_efuse(priv);
7764 if (ret) {
7765 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
7766 goto exit;
7767 }
7768
7769 ret = priv->fops->parse_efuse(priv);
7770 if (ret) {
7771 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
7772 goto exit;
7773 }
7774
7775 rtl8xxxu_print_chipinfo(priv);
7776
7777 ret = priv->fops->load_firmware(priv);
7778 if (ret) {
7779 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
7780 goto exit;
7781 }
7782
7783 ret = rtl8xxxu_init_device(hw);
7784
7785 hw->wiphy->max_scan_ssids = 1;
7786 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
7787 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
7788 hw->queues = 4;
7789
7790 sband = &rtl8xxxu_supported_band;
7791 sband->ht_cap.ht_supported = true;
7792 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
7793 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
7794 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
7795 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
7796 sband->ht_cap.mcs.rx_mask[0] = 0xff;
7797 sband->ht_cap.mcs.rx_mask[4] = 0x01;
7798 if (priv->rf_paths > 1) {
7799 sband->ht_cap.mcs.rx_mask[1] = 0xff;
7800 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
7801 }
7802 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
7803 /*
7804 * Some APs will negotiate HT20_40 in a noisy environment leading
7805 * to miserable performance. Rather than defaulting to this, only
7806 * enable it if explicitly requested at module load time.
7807 */
7808 if (rtl8xxxu_ht40_2g) {
7809 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
7810 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
7811 }
7812 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
7813
7814 hw->wiphy->rts_threshold = 2347;
7815
7816 SET_IEEE80211_DEV(priv->hw, &interface->dev);
7817 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
7818
7819 hw->extra_tx_headroom = sizeof(struct rtl8xxxu_tx_desc);
7820 ieee80211_hw_set(hw, SIGNAL_DBM);
7821 /*
7822 * The firmware handles rate control
7823 */
7824 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
7825 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
7826
7827 ret = ieee80211_register_hw(priv->hw);
7828 if (ret) {
7829 dev_err(&udev->dev, "%s: Failed to register: %i\n",
7830 __func__, ret);
7831 goto exit;
7832 }
7833
7834 exit:
7835 if (ret < 0)
7836 usb_put_dev(udev);
7837 return ret;
7838 }
7839
7840 static void rtl8xxxu_disconnect(struct usb_interface *interface)
7841 {
7842 struct rtl8xxxu_priv *priv;
7843 struct ieee80211_hw *hw;
7844
7845 hw = usb_get_intfdata(interface);
7846 priv = hw->priv;
7847
7848 rtl8xxxu_disable_device(hw);
7849 usb_set_intfdata(interface, NULL);
7850
7851 dev_info(&priv->udev->dev, "disconnecting\n");
7852
7853 ieee80211_unregister_hw(hw);
7854
7855 kfree(priv->fw_data);
7856 mutex_destroy(&priv->usb_buf_mutex);
7857 mutex_destroy(&priv->h2c_mutex);
7858
7859 usb_put_dev(priv->udev);
7860 ieee80211_free_hw(hw);
7861 }
7862
7863 static struct rtl8xxxu_fileops rtl8723au_fops = {
7864 .parse_efuse = rtl8723au_parse_efuse,
7865 .load_firmware = rtl8723au_load_firmware,
7866 .power_on = rtl8723au_power_on,
7867 .llt_init = rtl8xxxu_init_llt_table,
7868 .phy_iq_calibrate = rtl8723au_phy_iq_calibrate,
7869 .config_channel = rtl8723au_config_channel,
7870 .parse_rx_desc = rtl8723au_parse_rx_desc,
7871 .writeN_block_size = 1024,
7872 .mbox_ext_reg = REG_HMBOX_EXT_0,
7873 .mbox_ext_width = 2,
7874 .adda_1t_init = 0x0b1b25a0,
7875 .adda_1t_path_on = 0x0bdb25a0,
7876 .adda_2t_path_on_a = 0x04db25a4,
7877 .adda_2t_path_on_b = 0x0b1b25a4,
7878 };
7879
7880 static struct rtl8xxxu_fileops rtl8723bu_fops = {
7881 .parse_efuse = rtl8723bu_parse_efuse,
7882 .load_firmware = rtl8723bu_load_firmware,
7883 .power_on = rtl8723bu_power_on,
7884 .llt_init = rtl8xxxu_auto_llt_table,
7885 .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection,
7886 .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
7887 .config_channel = rtl8723bu_config_channel,
7888 .init_bt = rtl8723bu_init_bt,
7889 .parse_rx_desc = rtl8723bu_parse_rx_desc,
7890 .writeN_block_size = 1024,
7891 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
7892 .mbox_ext_width = 4,
7893 .has_s0s1 = 1,
7894 .adda_1t_init = 0x01c00014,
7895 .adda_1t_path_on = 0x01c00014,
7896 .adda_2t_path_on_a = 0x01c00014,
7897 .adda_2t_path_on_b = 0x01c00014,
7898 };
7899
7900 #ifdef CONFIG_RTL8XXXU_UNTESTED
7901
7902 static struct rtl8xxxu_fileops rtl8192cu_fops = {
7903 .parse_efuse = rtl8192cu_parse_efuse,
7904 .load_firmware = rtl8192cu_load_firmware,
7905 .power_on = rtl8192cu_power_on,
7906 .llt_init = rtl8xxxu_init_llt_table,
7907 .phy_iq_calibrate = rtl8723au_phy_iq_calibrate,
7908 .config_channel = rtl8723au_config_channel,
7909 .parse_rx_desc = rtl8723au_parse_rx_desc,
7910 .writeN_block_size = 128,
7911 .mbox_ext_reg = REG_HMBOX_EXT_0,
7912 .mbox_ext_width = 2,
7913 .adda_1t_init = 0x0b1b25a0,
7914 .adda_1t_path_on = 0x0bdb25a0,
7915 .adda_2t_path_on_a = 0x04db25a4,
7916 .adda_2t_path_on_b = 0x0b1b25a4,
7917 };
7918
7919 #endif
7920
7921 static struct rtl8xxxu_fileops rtl8192eu_fops = {
7922 .parse_efuse = rtl8192eu_parse_efuse,
7923 .load_firmware = rtl8192eu_load_firmware,
7924 .power_on = rtl8192eu_power_on,
7925 .llt_init = rtl8xxxu_auto_llt_table,
7926 .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
7927 .config_channel = rtl8723bu_config_channel,
7928 .parse_rx_desc = rtl8723bu_parse_rx_desc,
7929 .writeN_block_size = 128,
7930 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
7931 .mbox_ext_width = 4,
7932 .has_s0s1 = 1,
7933 .adda_1t_init = 0x0fc01616,
7934 .adda_1t_path_on = 0x0fc01616,
7935 .adda_2t_path_on_a = 0x0fc01616,
7936 .adda_2t_path_on_b = 0x0fc01616,
7937 };
7938
7939 static struct usb_device_id dev_table[] = {
7940 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
7941 .driver_info = (unsigned long)&rtl8723au_fops},
7942 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
7943 .driver_info = (unsigned long)&rtl8723au_fops},
7944 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
7945 .driver_info = (unsigned long)&rtl8723au_fops},
7946 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
7947 .driver_info = (unsigned long)&rtl8192eu_fops},
7948 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
7949 .driver_info = (unsigned long)&rtl8723bu_fops},
7950 #ifdef CONFIG_RTL8XXXU_UNTESTED
7951 /* Still supported by rtlwifi */
7952 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
7953 .driver_info = (unsigned long)&rtl8192cu_fops},
7954 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
7955 .driver_info = (unsigned long)&rtl8192cu_fops},
7956 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
7957 .driver_info = (unsigned long)&rtl8192cu_fops},
7958 /* Tested by Larry Finger */
7959 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
7960 .driver_info = (unsigned long)&rtl8192cu_fops},
7961 /* Currently untested 8188 series devices */
7962 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
7963 .driver_info = (unsigned long)&rtl8192cu_fops},
7964 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
7965 .driver_info = (unsigned long)&rtl8192cu_fops},
7966 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
7967 .driver_info = (unsigned long)&rtl8192cu_fops},
7968 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
7969 .driver_info = (unsigned long)&rtl8192cu_fops},
7970 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
7971 .driver_info = (unsigned long)&rtl8192cu_fops},
7972 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
7973 .driver_info = (unsigned long)&rtl8192cu_fops},
7974 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
7975 .driver_info = (unsigned long)&rtl8192cu_fops},
7976 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
7977 .driver_info = (unsigned long)&rtl8192cu_fops},
7978 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
7979 .driver_info = (unsigned long)&rtl8192cu_fops},
7980 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
7981 .driver_info = (unsigned long)&rtl8192cu_fops},
7982 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
7983 .driver_info = (unsigned long)&rtl8192cu_fops},
7984 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
7985 .driver_info = (unsigned long)&rtl8192cu_fops},
7986 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
7987 .driver_info = (unsigned long)&rtl8192cu_fops},
7988 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
7989 .driver_info = (unsigned long)&rtl8192cu_fops},
7990 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
7991 .driver_info = (unsigned long)&rtl8192cu_fops},
7992 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
7993 .driver_info = (unsigned long)&rtl8192cu_fops},
7994 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
7995 .driver_info = (unsigned long)&rtl8192cu_fops},
7996 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
7997 .driver_info = (unsigned long)&rtl8192cu_fops},
7998 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
7999 .driver_info = (unsigned long)&rtl8192cu_fops},
8000 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
8001 .driver_info = (unsigned long)&rtl8192cu_fops},
8002 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
8003 .driver_info = (unsigned long)&rtl8192cu_fops},
8004 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
8005 .driver_info = (unsigned long)&rtl8192cu_fops},
8006 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
8007 .driver_info = (unsigned long)&rtl8192cu_fops},
8008 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
8009 .driver_info = (unsigned long)&rtl8192cu_fops},
8010 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
8011 .driver_info = (unsigned long)&rtl8192cu_fops},
8012 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
8013 .driver_info = (unsigned long)&rtl8192cu_fops},
8014 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
8015 .driver_info = (unsigned long)&rtl8192cu_fops},
8016 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
8017 .driver_info = (unsigned long)&rtl8192cu_fops},
8018 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
8019 .driver_info = (unsigned long)&rtl8192cu_fops},
8020 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
8021 .driver_info = (unsigned long)&rtl8192cu_fops},
8022 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
8023 .driver_info = (unsigned long)&rtl8192cu_fops},
8024 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
8025 .driver_info = (unsigned long)&rtl8192cu_fops},
8026 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
8027 .driver_info = (unsigned long)&rtl8192cu_fops},
8028 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
8029 .driver_info = (unsigned long)&rtl8192cu_fops},
8030 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
8031 .driver_info = (unsigned long)&rtl8192cu_fops},
8032 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
8033 .driver_info = (unsigned long)&rtl8192cu_fops},
8034 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
8035 .driver_info = (unsigned long)&rtl8192cu_fops},
8036 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
8037 .driver_info = (unsigned long)&rtl8192cu_fops},
8038 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
8039 .driver_info = (unsigned long)&rtl8192cu_fops},
8040 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
8041 .driver_info = (unsigned long)&rtl8192cu_fops},
8042 /* Currently untested 8192 series devices */
8043 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
8044 .driver_info = (unsigned long)&rtl8192cu_fops},
8045 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
8046 .driver_info = (unsigned long)&rtl8192cu_fops},
8047 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
8048 .driver_info = (unsigned long)&rtl8192cu_fops},
8049 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
8050 .driver_info = (unsigned long)&rtl8192cu_fops},
8051 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
8052 .driver_info = (unsigned long)&rtl8192cu_fops},
8053 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
8054 .driver_info = (unsigned long)&rtl8192cu_fops},
8055 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
8056 .driver_info = (unsigned long)&rtl8192cu_fops},
8057 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
8058 .driver_info = (unsigned long)&rtl8192cu_fops},
8059 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
8060 .driver_info = (unsigned long)&rtl8192cu_fops},
8061 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
8062 .driver_info = (unsigned long)&rtl8192cu_fops},
8063 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
8064 .driver_info = (unsigned long)&rtl8192cu_fops},
8065 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
8066 .driver_info = (unsigned long)&rtl8192cu_fops},
8067 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
8068 .driver_info = (unsigned long)&rtl8192cu_fops},
8069 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
8070 .driver_info = (unsigned long)&rtl8192cu_fops},
8071 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
8072 .driver_info = (unsigned long)&rtl8192cu_fops},
8073 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
8074 .driver_info = (unsigned long)&rtl8192cu_fops},
8075 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
8076 .driver_info = (unsigned long)&rtl8192cu_fops},
8077 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
8078 .driver_info = (unsigned long)&rtl8192cu_fops},
8079 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
8080 .driver_info = (unsigned long)&rtl8192cu_fops},
8081 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
8082 .driver_info = (unsigned long)&rtl8192cu_fops},
8083 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
8084 .driver_info = (unsigned long)&rtl8192cu_fops},
8085 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
8086 .driver_info = (unsigned long)&rtl8192cu_fops},
8087 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
8088 .driver_info = (unsigned long)&rtl8192cu_fops},
8089 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
8090 .driver_info = (unsigned long)&rtl8192cu_fops},
8091 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
8092 .driver_info = (unsigned long)&rtl8192cu_fops},
8093 #endif
8094 { }
8095 };
8096
8097 static struct usb_driver rtl8xxxu_driver = {
8098 .name = DRIVER_NAME,
8099 .probe = rtl8xxxu_probe,
8100 .disconnect = rtl8xxxu_disconnect,
8101 .id_table = dev_table,
8102 .disable_hub_initiated_lpm = 1,
8103 };
8104
8105 static int __init rtl8xxxu_module_init(void)
8106 {
8107 int res;
8108
8109 res = usb_register(&rtl8xxxu_driver);
8110 if (res < 0)
8111 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
8112
8113 return res;
8114 }
8115
8116 static void __exit rtl8xxxu_module_exit(void)
8117 {
8118 usb_deregister(&rtl8xxxu_driver);
8119 }
8120
8121
8122 MODULE_DEVICE_TABLE(usb, dev_table);
8123
8124 module_init(rtl8xxxu_module_init);
8125 module_exit(rtl8xxxu_module_exit);
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