drivers/gpio/gpio-tc3589x.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2010
   3  *
   4  * License Terms: GNU General Public License, version 2
   5  * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson
   6  * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
   7  */
   8
   9 #include <linux/init.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/slab.h>
  12 #include <linux/gpio/driver.h>
  13 #include <linux/of.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/mfd/tc3589x.h>
  16 #include <linux/bitops.h>
  17
  18 /*
  19  * These registers are modified under the irq bus lock and cached to avoid
  20  * unnecessary writes in bus_sync_unlock.
  21  */
  22 enum { REG_IBE, REG_IEV, REG_IS, REG_IE };
  23
  24 #define CACHE_NR_REGS   4
  25 #define CACHE_NR_BANKS  3
  26
  27 struct tc3589x_gpio {
  28         struct gpio_chip chip;
  29         struct tc3589x *tc3589x;
  30         struct device *dev;
  31         struct mutex irq_lock;
  32         /* Caches of interrupt control registers for bus_lock */
  33         u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
  34         u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
  35 };
  36
  37 static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned offset)
  38 {
  39         struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
  40         struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  41         u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
  42         u8 mask = BIT(offset % 8);
  43         int ret;
  44
  45         ret = tc3589x_reg_read(tc3589x, reg);
  46         if (ret < 0)
  47                 return ret;
  48
  49         return !!(ret & mask);
  50 }
  51
  52 static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
  53 {
  54         struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
  55         struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  56         u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
  57         unsigned pos = offset % 8;
  58         u8 data[] = {val ? BIT(pos) : 0, BIT(pos)};
  59
  60         tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data);
  61 }
  62
  63 static int tc3589x_gpio_direction_output(struct gpio_chip *chip,
  64                                          unsigned offset, int val)
  65 {
  66         struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
  67         struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  68         u8 reg = TC3589x_GPIODIR0 + offset / 8;
  69         unsigned pos = offset % 8;
  70
  71         tc3589x_gpio_set(chip, offset, val);
  72
  73         return tc3589x_set_bits(tc3589x, reg, BIT(pos), BIT(pos));
  74 }
  75
  76 static int tc3589x_gpio_direction_input(struct gpio_chip *chip,
  77                                         unsigned offset)
  78 {
  79         struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
  80         struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  81         u8 reg = TC3589x_GPIODIR0 + offset / 8;
  82         unsigned pos = offset % 8;
  83
  84         return tc3589x_set_bits(tc3589x, reg, BIT(pos), 0);
  85 }
  86
  87 static int tc3589x_gpio_single_ended(struct gpio_chip *chip,
  88                                      unsigned offset,
  89                                      enum single_ended_mode mode)
  90 {
  91         struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
  92         struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  93         /*
  94          * These registers are alterated at each second address
  95          * ODM bit 0 = drive to GND or Hi-Z (open drain)
  96          * ODM bit 1 = drive to VDD or Hi-Z (open source)
  97          */
  98         u8 odmreg = TC3589x_GPIOODM0 + (offset / 8) * 2;
  99         u8 odereg = TC3589x_GPIOODE0 + (offset / 8) * 2;
 100         unsigned pos = offset % 8;
 101         int ret;
 102
 103         switch(mode) {
 104         case LINE_MODE_OPEN_DRAIN:
 105                 /* Set open drain mode */
 106                 ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), 0);
 107                 if (ret)
 108                         return ret;
 109                 /* Enable open drain/source mode */
 110                 return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
 111         case LINE_MODE_OPEN_SOURCE:
 112                 /* Set open source mode */
 113                 ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), BIT(pos));
 114                 if (ret)
 115                         return ret;
 116                 /* Enable open drain/source mode */
 117                 return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
 118         case LINE_MODE_PUSH_PULL:
 119                 /* Disable open drain/source mode */
 120                 return tc3589x_set_bits(tc3589x, odereg, BIT(pos), 0);
 121         default:
 122                 break;
 123         }
 124         return -ENOTSUPP;
 125 }
 126
 127 static struct gpio_chip template_chip = {
 128         .label                  = "tc3589x",
 129         .owner                  = THIS_MODULE,
 130         .direction_input        = tc3589x_gpio_direction_input,
 131         .get                    = tc3589x_gpio_get,
 132         .direction_output       = tc3589x_gpio_direction_output,
 133         .set                    = tc3589x_gpio_set,
 134         .set_single_ended       = tc3589x_gpio_single_ended,
 135         .can_sleep              = true,
 136 };
 137
 138 static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 139 {
 140         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 141         struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
 142         int offset = d->hwirq;
 143         int regoffset = offset / 8;
 144         int mask = BIT(offset % 8);
 145
 146         if (type == IRQ_TYPE_EDGE_BOTH) {
 147                 tc3589x_gpio->regs[REG_IBE][regoffset] |= mask;
 148                 return 0;
 149         }
 150
 151         tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask;
 152
 153         if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
 154                 tc3589x_gpio->regs[REG_IS][regoffset] |= mask;
 155         else
 156                 tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask;
 157
 158         if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
 159                 tc3589x_gpio->regs[REG_IEV][regoffset] |= mask;
 160         else
 161                 tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;
 162
 163         return 0;
 164 }
 165
 166 static void tc3589x_gpio_irq_lock(struct irq_data *d)
 167 {
 168         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 169         struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
 170
 171         mutex_lock(&tc3589x_gpio->irq_lock);
 172 }
 173
 174 static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
 175 {
 176         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 177         struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
 178         struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
 179         static const u8 regmap[] = {
 180                 [REG_IBE]       = TC3589x_GPIOIBE0,
 181                 [REG_IEV]       = TC3589x_GPIOIEV0,
 182                 [REG_IS]        = TC3589x_GPIOIS0,
 183                 [REG_IE]        = TC3589x_GPIOIE0,
 184         };
 185         int i, j;
 186
 187         for (i = 0; i < CACHE_NR_REGS; i++) {
 188                 for (j = 0; j < CACHE_NR_BANKS; j++) {
 189                         u8 old = tc3589x_gpio->oldregs[i][j];
 190                         u8 new = tc3589x_gpio->regs[i][j];
 191
 192                         if (new == old)
 193                                 continue;
 194
 195                         tc3589x_gpio->oldregs[i][j] = new;
 196                         tc3589x_reg_write(tc3589x, regmap[i] + j * 8, new);
 197                 }
 198         }
 199
 200         mutex_unlock(&tc3589x_gpio->irq_lock);
 201 }
 202
 203 static void tc3589x_gpio_irq_mask(struct irq_data *d)
 204 {
 205         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 206         struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
 207         int offset = d->hwirq;
 208         int regoffset = offset / 8;
 209         int mask = BIT(offset % 8);
 210
 211         tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
 212 }
 213
 214 static void tc3589x_gpio_irq_unmask(struct irq_data *d)
 215 {
 216         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 217         struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
 218         int offset = d->hwirq;
 219         int regoffset = offset / 8;
 220         int mask = BIT(offset % 8);
 221
 222         tc3589x_gpio->regs[REG_IE][regoffset] |= mask;
 223 }
 224
 225 static struct irq_chip tc3589x_gpio_irq_chip = {
 226         .name                   = "tc3589x-gpio",
 227         .irq_bus_lock           = tc3589x_gpio_irq_lock,
 228         .irq_bus_sync_unlock    = tc3589x_gpio_irq_sync_unlock,
 229         .irq_mask               = tc3589x_gpio_irq_mask,
 230         .irq_unmask             = tc3589x_gpio_irq_unmask,
 231         .irq_set_type           = tc3589x_gpio_irq_set_type,
 232 };
 233
 234 static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
 235 {
 236         struct tc3589x_gpio *tc3589x_gpio = dev;
 237         struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
 238         u8 status[CACHE_NR_BANKS];
 239         int ret;
 240         int i;
 241
 242         ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0,
 243                                  ARRAY_SIZE(status), status);
 244         if (ret < 0)
 245                 return IRQ_NONE;
 246
 247         for (i = 0; i < ARRAY_SIZE(status); i++) {
 248                 unsigned int stat = status[i];
 249                 if (!stat)
 250                         continue;
 251
 252                 while (stat) {
 253                         int bit = __ffs(stat);
 254                         int line = i * 8 + bit;
 255                         int irq = irq_find_mapping(tc3589x_gpio->chip.irqdomain,
 256                                                    line);
 257
 258                         handle_nested_irq(irq);
 259                         stat &= ~(1 << bit);
 260                 }
 261
 262                 tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]);
 263         }
 264
 265         return IRQ_HANDLED;
 266 }
 267
 268 static int tc3589x_gpio_probe(struct platform_device *pdev)
 269 {
 270         struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
 271         struct device_node *np = pdev->dev.of_node;
 272         struct tc3589x_gpio *tc3589x_gpio;
 273         int ret;
 274         int irq;
 275
 276         if (!np) {
 277                 dev_err(&pdev->dev, "No Device Tree node found\n");
 278                 return -EINVAL;
 279         }
 280
 281         irq = platform_get_irq(pdev, 0);
 282         if (irq < 0)
 283                 return irq;
 284
 285         tc3589x_gpio = devm_kzalloc(&pdev->dev, sizeof(struct tc3589x_gpio),
 286                                     GFP_KERNEL);
 287         if (!tc3589x_gpio)
 288                 return -ENOMEM;
 289
 290         mutex_init(&tc3589x_gpio->irq_lock);
 291
 292         tc3589x_gpio->dev = &pdev->dev;
 293         tc3589x_gpio->tc3589x = tc3589x;
 294
 295         tc3589x_gpio->chip = template_chip;
 296         tc3589x_gpio->chip.ngpio = tc3589x->num_gpio;
 297         tc3589x_gpio->chip.parent = &pdev->dev;
 298         tc3589x_gpio->chip.base = -1;
 299         tc3589x_gpio->chip.of_node = np;
 300
 301         /* Bring the GPIO module out of reset */
 302         ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
 303                                TC3589x_RSTCTRL_GPIRST, 0);
 304         if (ret < 0)
 305                 return ret;
 306
 307         ret = devm_request_threaded_irq(&pdev->dev,
 308                                         irq, NULL, tc3589x_gpio_irq,
 309                                         IRQF_ONESHOT, "tc3589x-gpio",
 310                                         tc3589x_gpio);
 311         if (ret) {
 312                 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
 313                 return ret;
 314         }
 315
 316         ret = devm_gpiochip_add_data(&pdev->dev, &tc3589x_gpio->chip,
 317                                      tc3589x_gpio);
 318         if (ret) {
 319                 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
 320                 return ret;
 321         }
 322
 323         ret =  gpiochip_irqchip_add(&tc3589x_gpio->chip,
 324                                     &tc3589x_gpio_irq_chip,
 325                                     0,
 326                                     handle_simple_irq,
 327                                     IRQ_TYPE_NONE);
 328         if (ret) {
 329                 dev_err(&pdev->dev,
 330                         "could not connect irqchip to gpiochip\n");
 331                 return ret;
 332         }
 333
 334         gpiochip_set_chained_irqchip(&tc3589x_gpio->chip,
 335                                      &tc3589x_gpio_irq_chip,
 336                                      irq,
 337                                      NULL);
 338
 339         platform_set_drvdata(pdev, tc3589x_gpio);
 340
 341         return 0;
 342 }
 343
 344 static struct platform_driver tc3589x_gpio_driver = {
 345         .driver.name    = "tc3589x-gpio",
 346         .driver.owner   = THIS_MODULE,
 347         .probe          = tc3589x_gpio_probe,
 348 };
 349
 350 static int __init tc3589x_gpio_init(void)
 351 {
 352         return platform_driver_register(&tc3589x_gpio_driver);
 353 }
 354 subsys_initcall(tc3589x_gpio_init);