drivers/irqchip/irq-vic.c

   1 /*
   2  *  linux/arch/arm/common/vic.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #include <linux/export.h>
  23 #include <linux/init.h>
  24 #include <linux/list.h>
  25 #include <linux/io.h>
  26 #include <linux/irqdomain.h>
  27 #include <linux/of.h>
  28 #include <linux/of_address.h>
  29 #include <linux/of_irq.h>
  30 #include <linux/syscore_ops.h>
  31 #include <linux/device.h>
  32 #include <linux/amba/bus.h>
  33 #include <linux/irqchip/arm-vic.h>
  34
  35 #include <asm/exception.h>
  36 #include <asm/mach/irq.h>
  37
  38 #include "irqchip.h"
  39
  40 #define VIC_IRQ_STATUS                  0x00
  41 #define VIC_FIQ_STATUS                  0x04
  42 #define VIC_INT_SELECT                  0x0c    /* 1 = FIQ, 0 = IRQ */
  43 #define VIC_INT_SOFT                    0x18
  44 #define VIC_INT_SOFT_CLEAR              0x1c
  45 #define VIC_PROTECT                     0x20
  46 #define VIC_PL190_VECT_ADDR             0x30    /* PL190 only */
  47 #define VIC_PL190_DEF_VECT_ADDR         0x34    /* PL190 only */
  48
  49 #define VIC_VECT_ADDR0                  0x100   /* 0 to 15 (0..31 PL192) */
  50 #define VIC_VECT_CNTL0                  0x200   /* 0 to 15 (0..31 PL192) */
  51 #define VIC_ITCR                        0x300   /* VIC test control register */
  52
  53 #define VIC_VECT_CNTL_ENABLE            (1 << 5)
  54
  55 #define VIC_PL192_VECT_ADDR             0xF00
  56
  57 /**
  58  * struct vic_device - VIC PM device
  59  * @irq: The IRQ number for the base of the VIC.
  60  * @base: The register base for the VIC.
  61  * @valid_sources: A bitmask of valid interrupts
  62  * @resume_sources: A bitmask of interrupts for resume.
  63  * @resume_irqs: The IRQs enabled for resume.
  64  * @int_select: Save for VIC_INT_SELECT.
  65  * @int_enable: Save for VIC_INT_ENABLE.
  66  * @soft_int: Save for VIC_INT_SOFT.
  67  * @protect: Save for VIC_PROTECT.
  68  * @domain: The IRQ domain for the VIC.
  69  */
  70 struct vic_device {
  71         void __iomem    *base;
  72         int             irq;
  73         u32             valid_sources;
  74         u32             resume_sources;
  75         u32             resume_irqs;
  76         u32             int_select;
  77         u32             int_enable;
  78         u32             soft_int;
  79         u32             protect;
  80         struct irq_domain *domain;
  81 };
  82
  83 /* we cannot allocate memory when VICs are initially registered */
  84 static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
  85
  86 static int vic_id;
  87
  88 static void vic_handle_irq(struct pt_regs *regs);
  89
  90 /**
  91  * vic_init2 - common initialisation code
  92  * @base: Base of the VIC.
  93  *
  94  * Common initialisation code for registration
  95  * and resume.
  96 */
  97 static void vic_init2(void __iomem *base)
  98 {
  99         int i;
 100
 101         for (i = 0; i < 16; i++) {
 102                 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
 103                 writel(VIC_VECT_CNTL_ENABLE | i, reg);
 104         }
 105
 106         writel(32, base + VIC_PL190_DEF_VECT_ADDR);
 107 }
 108
 109 #ifdef CONFIG_PM
 110 static void resume_one_vic(struct vic_device *vic)
 111 {
 112         void __iomem *base = vic->base;
 113
 114         printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
 115
 116         /* re-initialise static settings */
 117         vic_init2(base);
 118
 119         writel(vic->int_select, base + VIC_INT_SELECT);
 120         writel(vic->protect, base + VIC_PROTECT);
 121
 122         /* set the enabled ints and then clear the non-enabled */
 123         writel(vic->int_enable, base + VIC_INT_ENABLE);
 124         writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
 125
 126         /* and the same for the soft-int register */
 127
 128         writel(vic->soft_int, base + VIC_INT_SOFT);
 129         writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
 130 }
 131
 132 static void vic_resume(void)
 133 {
 134         int id;
 135
 136         for (id = vic_id - 1; id >= 0; id--)
 137                 resume_one_vic(vic_devices + id);
 138 }
 139
 140 static void suspend_one_vic(struct vic_device *vic)
 141 {
 142         void __iomem *base = vic->base;
 143
 144         printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
 145
 146         vic->int_select = readl(base + VIC_INT_SELECT);
 147         vic->int_enable = readl(base + VIC_INT_ENABLE);
 148         vic->soft_int = readl(base + VIC_INT_SOFT);
 149         vic->protect = readl(base + VIC_PROTECT);
 150
 151         /* set the interrupts (if any) that are used for
 152          * resuming the system */
 153
 154         writel(vic->resume_irqs, base + VIC_INT_ENABLE);
 155         writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
 156 }
 157
 158 static int vic_suspend(void)
 159 {
 160         int id;
 161
 162         for (id = 0; id < vic_id; id++)
 163                 suspend_one_vic(vic_devices + id);
 164
 165         return 0;
 166 }
 167
 168 struct syscore_ops vic_syscore_ops = {
 169         .suspend        = vic_suspend,
 170         .resume         = vic_resume,
 171 };
 172
 173 /**
 174  * vic_pm_init - initicall to register VIC pm
 175  *
 176  * This is called via late_initcall() to register
 177  * the resources for the VICs due to the early
 178  * nature of the VIC's registration.
 179 */
 180 static int __init vic_pm_init(void)
 181 {
 182         if (vic_id > 0)
 183                 register_syscore_ops(&vic_syscore_ops);
 184
 185         return 0;
 186 }
 187 late_initcall(vic_pm_init);
 188 #endif /* CONFIG_PM */
 189
 190 static struct irq_chip vic_chip;
 191
 192 static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq,
 193                              irq_hw_number_t hwirq)
 194 {
 195         struct vic_device *v = d->host_data;
 196
 197         /* Skip invalid IRQs, only register handlers for the real ones */
 198         if (!(v->valid_sources & (1 << hwirq)))
 199                 return -ENOTSUPP;
 200         irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq);
 201         irq_set_chip_data(irq, v->base);
 202         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 203         return 0;
 204 }
 205
 206 /*
 207  * Handle each interrupt in a single VIC.  Returns non-zero if we've
 208  * handled at least one interrupt.  This reads the status register
 209  * before handling each interrupt, which is necessary given that
 210  * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
 211  */
 212 static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
 213 {
 214         u32 stat, irq;
 215         int handled = 0;
 216
 217         while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
 218                 irq = ffs(stat) - 1;
 219                 handle_IRQ(irq_find_mapping(vic->domain, irq), regs);
 220                 handled = 1;
 221         }
 222
 223         return handled;
 224 }
 225
 226 /*
 227  * Keep iterating over all registered VIC's until there are no pending
 228  * interrupts.
 229  */
 230 static asmlinkage void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
 231 {
 232         int i, handled;
 233
 234         do {
 235                 for (i = 0, handled = 0; i < vic_id; ++i)
 236                         handled |= handle_one_vic(&vic_devices[i], regs);
 237         } while (handled);
 238 }
 239
 240 static struct irq_domain_ops vic_irqdomain_ops = {
 241         .map = vic_irqdomain_map,
 242         .xlate = irq_domain_xlate_onetwocell,
 243 };
 244
 245 /**
 246  * vic_register() - Register a VIC.
 247  * @base: The base address of the VIC.
 248  * @irq: The base IRQ for the VIC.
 249  * @valid_sources: bitmask of valid interrupts
 250  * @resume_sources: bitmask of interrupts allowed for resume sources.
 251  * @node: The device tree node associated with the VIC.
 252  *
 253  * Register the VIC with the system device tree so that it can be notified
 254  * of suspend and resume requests and ensure that the correct actions are
 255  * taken to re-instate the settings on resume.
 256  *
 257  * This also configures the IRQ domain for the VIC.
 258  */
 259 static void __init vic_register(void __iomem *base, unsigned int irq,
 260                                 u32 valid_sources, u32 resume_sources,
 261                                 struct device_node *node)
 262 {
 263         struct vic_device *v;
 264         int i;
 265
 266         if (vic_id >= ARRAY_SIZE(vic_devices)) {
 267                 printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
 268                 return;
 269         }
 270
 271         v = &vic_devices[vic_id];
 272         v->base = base;
 273         v->valid_sources = valid_sources;
 274         v->resume_sources = resume_sources;
 275         v->irq = irq;
 276         set_handle_irq(vic_handle_irq);
 277         vic_id++;
 278         v->domain = irq_domain_add_simple(node, fls(valid_sources), irq,
 279                                           &vic_irqdomain_ops, v);
 280         /* create an IRQ mapping for each valid IRQ */
 281         for (i = 0; i < fls(valid_sources); i++)
 282                 if (valid_sources & (1 << i))
 283                         irq_create_mapping(v->domain, i);
 284 }
 285
 286 static void vic_ack_irq(struct irq_data *d)
 287 {
 288         void __iomem *base = irq_data_get_irq_chip_data(d);
 289         unsigned int irq = d->hwirq;
 290         writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
 291         /* moreover, clear the soft-triggered, in case it was the reason */
 292         writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
 293 }
 294
 295 static void vic_mask_irq(struct irq_data *d)
 296 {
 297         void __iomem *base = irq_data_get_irq_chip_data(d);
 298         unsigned int irq = d->hwirq;
 299         writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
 300 }
 301
 302 static void vic_unmask_irq(struct irq_data *d)
 303 {
 304         void __iomem *base = irq_data_get_irq_chip_data(d);
 305         unsigned int irq = d->hwirq;
 306         writel(1 << irq, base + VIC_INT_ENABLE);
 307 }
 308
 309 #if defined(CONFIG_PM)
 310 static struct vic_device *vic_from_irq(unsigned int irq)
 311 {
 312         struct vic_device *v = vic_devices;
 313         unsigned int base_irq = irq & ~31;
 314         int id;
 315
 316         for (id = 0; id < vic_id; id++, v++) {
 317                 if (v->irq == base_irq)
 318                         return v;
 319         }
 320
 321         return NULL;
 322 }
 323
 324 static int vic_set_wake(struct irq_data *d, unsigned int on)
 325 {
 326         struct vic_device *v = vic_from_irq(d->irq);
 327         unsigned int off = d->hwirq;
 328         u32 bit = 1 << off;
 329
 330         if (!v)
 331                 return -EINVAL;
 332
 333         if (!(bit & v->resume_sources))
 334                 return -EINVAL;
 335
 336         if (on)
 337                 v->resume_irqs |= bit;
 338         else
 339                 v->resume_irqs &= ~bit;
 340
 341         return 0;
 342 }
 343 #else
 344 #define vic_set_wake NULL
 345 #endif /* CONFIG_PM */
 346
 347 static struct irq_chip vic_chip = {
 348         .name           = "VIC",
 349         .irq_ack        = vic_ack_irq,
 350         .irq_mask       = vic_mask_irq,
 351         .irq_unmask     = vic_unmask_irq,
 352         .irq_set_wake   = vic_set_wake,
 353 };
 354
 355 static void __init vic_disable(void __iomem *base)
 356 {
 357         writel(0, base + VIC_INT_SELECT);
 358         writel(0, base + VIC_INT_ENABLE);
 359         writel(~0, base + VIC_INT_ENABLE_CLEAR);
 360         writel(0, base + VIC_ITCR);
 361         writel(~0, base + VIC_INT_SOFT_CLEAR);
 362 }
 363
 364 static void __init vic_clear_interrupts(void __iomem *base)
 365 {
 366         unsigned int i;
 367
 368         writel(0, base + VIC_PL190_VECT_ADDR);
 369         for (i = 0; i < 19; i++) {
 370                 unsigned int value;
 371
 372                 value = readl(base + VIC_PL190_VECT_ADDR);
 373                 writel(value, base + VIC_PL190_VECT_ADDR);
 374         }
 375 }
 376
 377 /*
 378  * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
 379  * The original cell has 32 interrupts, while the modified one has 64,
 380  * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
 381  * the probe function is called twice, with base set to offset 000
 382  *  and 020 within the page. We call this "second block".
 383  */
 384 static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
 385                                u32 vic_sources, struct device_node *node)
 386 {
 387         unsigned int i;
 388         int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
 389
 390         /* Disable all interrupts initially. */
 391         vic_disable(base);
 392
 393         /*
 394          * Make sure we clear all existing interrupts. The vector registers
 395          * in this cell are after the second block of general registers,
 396          * so we can address them using standard offsets, but only from
 397          * the second base address, which is 0x20 in the page
 398          */
 399         if (vic_2nd_block) {
 400                 vic_clear_interrupts(base);
 401
 402                 /* ST has 16 vectors as well, but we don't enable them by now */
 403                 for (i = 0; i < 16; i++) {
 404                         void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
 405                         writel(0, reg);
 406                 }
 407
 408                 writel(32, base + VIC_PL190_DEF_VECT_ADDR);
 409         }
 410
 411         vic_register(base, irq_start, vic_sources, 0, node);
 412 }
 413
 414 void __init __vic_init(void __iomem *base, int irq_start,
 415                               u32 vic_sources, u32 resume_sources,
 416                               struct device_node *node)
 417 {
 418         unsigned int i;
 419         u32 cellid = 0;
 420         enum amba_vendor vendor;
 421
 422         /* Identify which VIC cell this one is, by reading the ID */
 423         for (i = 0; i < 4; i++) {
 424                 void __iomem *addr;
 425                 addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
 426                 cellid |= (readl(addr) & 0xff) << (8 * i);
 427         }
 428         vendor = (cellid >> 12) & 0xff;
 429         printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
 430                base, cellid, vendor);
 431
 432         switch(vendor) {
 433         case AMBA_VENDOR_ST:
 434                 vic_init_st(base, irq_start, vic_sources, node);
 435                 return;
 436         default:
 437                 printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
 438                 /* fall through */
 439         case AMBA_VENDOR_ARM:
 440                 break;
 441         }
 442
 443         /* Disable all interrupts initially. */
 444         vic_disable(base);
 445
 446         /* Make sure we clear all existing interrupts */
 447         vic_clear_interrupts(base);
 448
 449         vic_init2(base);
 450
 451         vic_register(base, irq_start, vic_sources, resume_sources, node);
 452 }
 453
 454 /**
 455  * vic_init() - initialise a vectored interrupt controller
 456  * @base: iomem base address
 457  * @irq_start: starting interrupt number, must be muliple of 32
 458  * @vic_sources: bitmask of interrupt sources to allow
 459  * @resume_sources: bitmask of interrupt sources to allow for resume
 460  */
 461 void __init vic_init(void __iomem *base, unsigned int irq_start,
 462                      u32 vic_sources, u32 resume_sources)
 463 {
 464         __vic_init(base, irq_start, vic_sources, resume_sources, NULL);
 465 }
 466
 467 #ifdef CONFIG_OF
 468 int __init vic_of_init(struct device_node *node, struct device_node *parent)
 469 {
 470         void __iomem *regs;
 471
 472         if (WARN(parent, "non-root VICs are not supported"))
 473                 return -EINVAL;
 474
 475         regs = of_iomap(node, 0);
 476         if (WARN_ON(!regs))
 477                 return -EIO;
 478
 479         /*
 480          * Passing 0 as first IRQ makes the simple domain allocate descriptors
 481          */
 482         __vic_init(regs, 0, ~0, ~0, node);
 483
 484         return 0;
 485 }
 486 IRQCHIP_DECLARE(arm_pl190_vic, "arm,pl190-vic", vic_of_init);
 487 IRQCHIP_DECLARE(arm_pl192_vic, "arm,pl192-vic", vic_of_init);
 488 IRQCHIP_DECLARE(arm_versatile_vic, "arm,versatile-vic", vic_of_init);
 489 #endif /* CONFIG OF */